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Table of Contents
- 1. Introduction
- 2. Header
- 3. File Organization
- 4. Libraries
- 5. Aesthetics and Maintainability
- 6. Entity
- 6.1 Generics
- 6.2 Port Declarations
- 7. Single-Bit Models
- 8. Architecture
- 8.1 Signal Declarations
- 8.2 Wire Delay Block
- 8.3 Concurrent Procedures Section
- 8.4 Process Section
- 8.4.1 Variable Declarations
- 8.4.2 Timing Check Section
- 8.4.3 Functionality Section
- 8.4.4 VITAL State Tables
- 8.4.5 Path Delay Section
- 9. Negative Timing Constraints
- APPENDIX 1
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