FMF Timing for s70fl01gs Parts version: | author: | mod date: | changes made: V1.0 M.Dinic 18 Aug 06 Initial release 1ns s70fl01gs S70FL01GSAGMFI010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 The values listed are for VIO=VCC=2.7V to 3.6V, CL=30pF ) (CELL (CELLTYPE "fl512s_1") (INSTANCE %LABEL%/SERIAL_FLASH_1) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg1 (IOPATH CSNeg1 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && dual (IOPATH CSNeg1 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg1 (COND sdr_rd SCK) (3)) (SETUP CSNeg1 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg1)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg1 (50)) (HOLD CSNeg1 (COND sdr_rd SCK) (3)) (HOLD CSNeg1 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg1)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg1 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg1)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg1)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )) (CELL (CELLTYPE "fl512s_2") (INSTANCE %LABEL%/SERIAL_FLASH_2) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (5.4:6.7:8) (5.4:6.7:8) (1) (5.4:6.7:8) (1) (5.4:6.7:8))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg2 (IOPATH CSNeg2 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && dual (IOPATH CSNeg2 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg2 (COND sdr_rd SCK) (3)) (SETUP CSNeg2 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg2)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg2 (50)) (HOLD CSNeg2 (COND sdr_rd SCK) (3)) (HOLD CSNeg2 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg2)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg2 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg2)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg2)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) ) S70FL01GSAGMFI010_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI011_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI013_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV010_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV011_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV013_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA010_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA011_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA013_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB010_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB011_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB013_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM010_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM011_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM013_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC10_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC13_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC10_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC13_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC10_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC13_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC10_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC13_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC10_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC13_R_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=30pF ) (CELL (CELLTYPE "fl512s_1") (INSTANCE dut/SERIAL_FLASH_1) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg1 (IOPATH CSNeg1 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && dual (IOPATH CSNeg1 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg1 (COND sdr_rd SCK) (3)) (SETUP CSNeg1 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg1)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg1 (50)) (HOLD CSNeg1 (COND sdr_rd SCK) (3)) (HOLD CSNeg1 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg1)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg1 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg1)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg1)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )) (CELL (CELLTYPE "fl512s_2") (INSTANCE dut/SERIAL_FLASH_2) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.3:6.0:7.65) (4.3:6.0:7.65) (1) (4.3:6.0:7.65) (1) (4.3:6.0:7.65))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg2 (IOPATH CSNeg2 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && dual (IOPATH CSNeg2 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg2 (COND sdr_rd SCK) (3)) (SETUP CSNeg2 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg2)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg2 (50)) (HOLD CSNeg2 (COND sdr_rd SCK) (3)) (HOLD CSNeg2 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg2)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg2 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg2)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg2)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) ) S70FL01GSAGMFI010_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI011_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFI013_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV010_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV011_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFV013_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA010_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA011_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFA013_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB010_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB011_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFB013_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM010_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM011_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGMFM013_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC10_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHAC13_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC10_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHBC13_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC10_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHMC13_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC10_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHIC13_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC10_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSAGBHVC13_R_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 The values listed are for regulated Vcc range VCC=3.0V to 3.6V, CL=15pF, Industrial Ta=-40 to +85 Celsius ) (CELL (CELLTYPE "fl512s_1") (INSTANCE dut/SERIAL_FLASH_1) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg1 (IOPATH CSNeg1 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && dual (IOPATH CSNeg1 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg1 (COND sdr_rd SCK) (3)) (SETUP CSNeg1 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg1)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg1 (50)) (HOLD CSNeg1 (COND sdr_rd SCK) (3)) (HOLD CSNeg1 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg1)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg1 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg1)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg1)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )) (CELL (CELLTYPE "fl512s_2") (INSTANCE dut/SERIAL_FLASH_2) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (4.5:5.5:6.5) (4.5:5.5:6.5) (1) (4.5:5.5:6.5) (1) (4.5:5.5:6.5))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg2 (IOPATH CSNeg2 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && dual (IOPATH CSNeg2 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg2 (COND sdr_rd SCK) (3)) (SETUP CSNeg2 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (3)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg2)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (3)) (SETUP RSTNeg CSNeg2 (50)) (HOLD CSNeg2 (COND sdr_rd SCK) (3)) (HOLD CSNeg2 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (2)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg2)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (3)) (HOLD CSNeg2 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (4.8)) (WIDTH (COND dual_rd (negedge SCK)) (4.8)) (WIDTH (COND fast_rd (negedge SCK)) (3.75)) (WIDTH (COND fast_rd (posedge SCK)) (3.75)) (WIDTH (COND quadpg (posedge SCK)) (6.25)) (WIDTH (COND quadpg (negedge SCK)) (6.25)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg2)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg2)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (7.52)) (PERIOD (COND dual_rd SCK) (9.6)) (PERIOD (COND quadpg SCK) (12.5)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) ) S70FL01GSDPMFI010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFI011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFI013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHIC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHIC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHVC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHVC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHIC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHIC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHVC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHVC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM010_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM011_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM013_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHAC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHAC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHBC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHBC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHMC10_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHMC13_F_30pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 The values listed are for Vcc range VCC=2.7V to 3.6V, CL=30pF, Industrial Ta=-40 to +85 Celsius ) (CELL (CELLTYPE "fl512s_1") (INSTANCE %LABEL%/SERIAL_FLASH_1) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg1 (IOPATH CSNeg1 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && dual (IOPATH CSNeg1 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg1 (COND sdr_rd SCK) (3)) (SETUP CSNeg1 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (5)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg1)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5)) (SETUP RSTNeg CSNeg1 (50)) (HOLD CSNeg1 (COND sdr_rd SCK) (3)) (HOLD CSNeg1 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (4)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg1)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5)) (HOLD CSNeg1 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (7.5)) (WIDTH (COND dual_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (posedge SCK)) (7.5)) (WIDTH (COND quadpg (posedge SCK)) (7.5)) (WIDTH (COND quadpg (negedge SCK)) (7.5)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg1)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg1)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (15)) (PERIOD (COND dual_rd SCK) (15)) (PERIOD (COND quadpg SCK) (15)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )) (CELL (CELLTYPE "fl512s_2") (INSTANCE %LABEL%/SERIAL_FLASH_2) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (1.5:8:14.5) (1.5:8:14.5) (1) (1.5:8:14.5) (1) (1.5:8:14.5))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg2 (IOPATH CSNeg2 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && dual (IOPATH CSNeg2 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg2 (COND sdr_rd SCK) (3)) (SETUP CSNeg2 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (5)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg2)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5)) (SETUP RSTNeg CSNeg2 (50)) (HOLD CSNeg2 (COND sdr_rd SCK) (3)) (HOLD CSNeg2 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (4)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg2)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5)) (HOLD CSNeg2 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (7.5)) (WIDTH (COND dual_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (posedge SCK)) (7.5)) (WIDTH (COND quadpg (posedge SCK)) (7.5)) (WIDTH (COND quadpg (negedge SCK)) (7.5)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg2)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg2)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (15)) (PERIOD (COND dual_rd SCK) (15)) (PERIOD (COND quadpg SCK) (15)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) ) S70FL01GSDPMFI010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFI011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFI013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPMFV013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFI013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFV013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHIC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHIC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHVC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDPBHVC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHIC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHIC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHVC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHVC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFA013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFB013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM010_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM011_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSMFM013_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHAC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHAC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHBC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHBC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHMC10_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 S70FL01GSDSBHMC13_F_15pFCypress Semiconductor Corporation, Document Number 001-98295 Rev. *N Revised April 03, 2018 The values listed are for Vcc range VCC=2.7V to 3.6V, CL=15pF, Industrial Ta=-40 to +85 Celsius ) (CELL (CELLTYPE "fl512s_1") (INSTANCE %LABEL%/SERIAL_FLASH_1) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg1 (IOPATH CSNeg1 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && dual (IOPATH CSNeg1 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg1 && QUAD (IOPATH CSNeg1 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg1 (COND sdr_rd SCK) (3)) (SETUP CSNeg1 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (5)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg1)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5)) (SETUP RSTNeg CSNeg1 (50)) (HOLD CSNeg1 (COND sdr_rd SCK) (3)) (HOLD CSNeg1 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (4)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg1)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5)) (HOLD CSNeg1 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (7.5)) (WIDTH (COND dual_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (posedge SCK)) (7.5)) (WIDTH (COND quadpg (posedge SCK)) (7.5)) (WIDTH (COND quadpg (negedge SCK)) (7.5)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg1)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg1)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (15)) (PERIOD (COND dual_rd SCK) (15)) (PERIOD (COND quadpg SCK) (15)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )) (CELL (CELLTYPE "fl512s_2") (INSTANCE %LABEL%/SERIAL_FLASH_2) (DELAY (ABSOLUTE (COND ~ddr (IOPATH SCK SO (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND (ddr || rd_fast) (IOPATH SCK SO (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && dual (IOPATH SCK SI (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && dual (IOPATH SCK SI (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK HOLDNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && QUAD (IOPATH SCK HOLDNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND ~ddr && QUAD (IOPATH SCK WPNeg (2:7:12) (2:7:12) (1) (2:7:12) (1) (2:7:12))) (COND ddr && QUAD (IOPATH SCK WPNeg (1.5:4:6.5) (1.5:4:6.5) (1) (1.5:4:6.5) (1) (1.5:4:6.5))) (COND CSNeg2 (IOPATH CSNeg2 SO () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && dual (IOPATH CSNeg2 SI () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 HOLDNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND CSNeg2 && QUAD (IOPATH CSNeg2 WPNeg () () (5.4:6.7:8) () (5.4:6.7:8) ())) (COND ~QUAD (IOPATH HOLDNeg SO () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (COND ~QUAD && dual (IOPATH HOLDNeg SI () () (7:10.5:14) (7:10.5:14) (7:10.5:14) (7:10.5:14))) (IOPATH RSTNeg SO () () (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8) (5.4:6.7:8)) )) (TIMINGCHECK (SETUP CSNeg2 (COND sdr_rd SCK) (3)) (SETUP CSNeg2 (COND ddr_rd SCK) (3)) (SETUP SI (COND deg_sin(posedge SCK)) (5)) (SETUP SI (COND ddro(posedge SCK)) (2)) (SETUP SI (COND ddro(negedge SCK)) (2)) (SETUP SI (COND ddro80(posedge SCK)) (1.5)) (SETUP SI (COND ddro80(negedge SCK)) (1.5)) (SETUP WPNeg (COND wr_prot(negedge CSNeg2)) (20)) (SETUP HOLDNeg (COND quad_rd (posedge SCK)) (5)) (SETUP RSTNeg CSNeg2 (50)) (HOLD CSNeg2 (COND sdr_rd SCK) (3)) (HOLD CSNeg2 (COND ddr_rd SCK) (3)) (HOLD SI (COND deg_sin (posedge SCK)) (4)) (HOLD SI (COND ddro (posedge SCK)) (2)) (HOLD SI (COND ddro (negedge SCK)) (2)) (HOLD SI (COND ddro80 (posedge SCK)) (1.5)) (HOLD SI (COND ddro80 (negedge SCK)) (1.5)) (HOLD WPNeg (COND wr_prot (posedge CSNeg2)) (100)) (HOLD HOLDNeg (COND quad_rd (posedge SCK)) (5)) (HOLD CSNeg2 RSTNeg (35000)) (WIDTH (COND rd (posedge SCK)) (10)) (WIDTH (COND rd (negedge SCK)) (10)) (WIDTH (COND dual_rd (posedge SCK)) (7.5)) (WIDTH (COND dual_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (negedge SCK)) (7.5)) (WIDTH (COND fast_rd (posedge SCK)) (7.5)) (WIDTH (COND quadpg (posedge SCK)) (7.5)) (WIDTH (COND quadpg (negedge SCK)) (7.5)) (WIDTH (COND ddrd (posedge SCK)) (7.5)) (WIDTH (COND ddrd (negedge SCK)) (7.5)) (WIDTH (COND ddrd80 (posedge SCK)) (6.25)) (WIDTH (COND ddrd80 (negedge SCK)) (6.25)) (WIDTH (COND RD_EQU_1 (posedge CSNeg2)) (10)) (WIDTH (COND RD_EQU_0 (posedge CSNeg2)) (50)) (WIDTH (negedge RSTNeg) (200)) (WIDTH (posedge RSTNeg) (50)) (PERIOD (COND rd SCK) (20)) (PERIOD (COND fast_rd SCK) (15)) (PERIOD (COND dual_rd SCK) (15)) (PERIOD (COND quadpg SCK) (15)) (PERIOD (COND ddrd SCK) (15)) (PERIOD (COND ddrd80 SCK) (12.5)) )