What's New at FMF for the week of 2010 January 31
New Files
- mt48lc16m16a2.vhd
Updated VHDL model of a 4M x 16 x 4Banks SDRAM.
Changes: Corrected memory addressing in part of column address.
Thank you to Michael Pagen for finding the bug and providing a fix.
Version 1.2
What's New at FMF for the week of 2010 January 24
New Files
- tlv1572.vhd
Updated VHDL model of a Serial Analog-to_Digital Converter.
Changes: Corrected operation in uC mode.
Thank you to Wojtek Powiertowski for finding the bug and providing the fix.
Version 1.1
What's New at FMF for the week of 2010 January 17
New Files
- s29jl064h.vhd
Updated VHDL model of a 64Megabit (8M x 8-bit/ 4M x 16-bit) Simultaneous
Read/Write Flash Memory.
Changes: First read after completion of embedded program/erase algorithm is
read valid data.
Version 1.5
- s29jl064h.v
Updated Verilog model of a 64Megabit (8M x 8-bit/ 4M x 16-bit) Simultaneous
Read/Write Flash Memory.
Changes: First read after completion of embedded program/erase algorithm is
read valid data.
Version 1.8
What's New at FMF for the week of 2009 December 06
New Files
- s25fl128r00m.vhd
VHDL model of a 128 Megabit Serial Flash Memory with 104 MHz SPI Bus Interface
Version 1.0
- s25fl128r00m.ftm
VHDL timing file for S25FL128R-00 parts from Spansion.
Version 1.0
- s25fl128r00m.v
Verilog model of a 128 Megabit Serial Flash Memory with 104 MHz SPI Bus Interface
Version 1.0
- s25fl128r00m.ftmv
Verilog timing file for S25FL128R-00 parts from Spansion.
Version 1.0
- s25fl128r01m.vhd
VHDL model of a 128 Megabit Serial Flash Memory with 104 MHz SPI Bus Interface
Version 1.0
- s25fl128r01m.ftm
VHDL timing file for S25FL128R-00 parts from Spansion.
Version 1.0
- s25fl128r01m.v
Verilog model of a 128 Megabit Serial Flash Memory with 104 MHz SPI Bus Interface
Version 1.0
- s25fl128r01m.ftmv
Verilog timing file for S25FL128R-00 parts from Spansion.
Version 1.0
Monthly summaries of new files are also posted in the FMF monthly news letter.
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