delay_file ::= ( DELAYFILE sdf_header cell+ )
sdf_header ::= sdf_version design_name? date? vendor? program_name?
program_version? hierarchy_divider? voltage? process?
temperature? time_scale?
sdf_version ::= ( SDFVERSION qstring )
design_name ::= ( DESIGN qstring )
date ::= ( DATE qstring )
vendor ::= ( VENDOR qstring )
program_name ::= ( PROGRAM qstring )
program_version ::= ( VERSION qstring )
hierarchy_divider ::= ( DIVIDER HCHAR )
HCHAR ::= . // a period character
||= / // a slash character
voltage ::= ( VOLTAGE rtriple )
||= ( VOLTAGE RNUMBER )
process ::= ( PROCESS qstring )
temperature ::= ( TEMPERATURE rtriple )
||= ( TEMPERATURE RNUMBER )
time_scale ::= ( TIMESCALE TSVALUE )
qstring ::= "{ascii character}"
cell ::= ( CELL celltype cell_instance correlation? timing_spec* )
celltype ::= ( CELLTYPE qstring )
cell_instance ::= instance+
||= ( INSTANCE WILDCARD )
WILDCARD ::= * // the asterisk character
instance ::= ( INSTANCE PATH? )
correlation ::= ( CORRELATION qstring corr_factor? )
corr_factor ::= NUMBER
||= NUMBER NUMBER NUMBER
timing_spec ::= del_spec
||= tc_spec
del_spec ::= ( DELAY deltype+ )
tc_spec ::= ( TIMINGCHECK tc_def+ )
deltype ::= ( PATHPULSE input_output_path? value value? )
||= ( GLOBALPATHPULSE input_output_path? value value? )
||= ( ABSOLUTE del_def+ )
||= ( INCREMENT del_def+ )
input_output_path ::= port_path port_path
del_def ::= ( IOPATH port_spec port_path rvalue_list )
||= ( COND conditional_port_expr ( IOPATH port_spec port_path rvalue_list ) )
||= ( PORT port_path rvalue_list )
||= ( INTERCONNECT port_instance port_instance rvalue_list )
||= ( NETDELAY net_spec rvalue_list )
||= ( DEVICE port_instance? rvalue_list )
net_spec ::= port_instance
||= net_instance
net_instance ::= net
||= instance net
net ::= IDENTIFIER
tc_def ::= tchk_def
||= cns_def
tchk_def ::= ( SETUP port_tchk port_tchk rvalue )
||= ( HOLD port_tchk port_tchk rvalue )
||= ( SETUPHOLD port_tchk port_tchk rvalue rvalue )
||= ( RECOVERY port_tchk port_tchk rvalue )
||= ( SKEW port_tchk port_tchk rvalue )
||= ( WIDTH port_tchk value )
||= ( PERIOD port_tchk value )
||= ( NOCHANGE port_tchk port_tchk rvalue rvalue )
cns_def ::= ( PATHCONSTRAINT port_instance port_instance+ rvalue rvalue )
||= ( SUM constraint_path constraint_path+ rvalue rvalue? )
||= ( DIFF constraint_path constraint_path value value? )
||= ( SKEWCONSTRAINT port_spec value )
port_tchk ::= port_spec
||= ( COND timing_check_condition port_spec )
constraint_path ::= ( port_instance port_instance )
port_spec ::= port_path
||= port_edge
port_edge ::= ( EDGE_IDENTIFIER port_path )
EDGE_IDENTIFIER ::= posedge
||= negedge
||= 01
||= 10
||= 0z
||= z1
||= 1z
||= z0
port_path ::= port
||= PATH HCHAR port
port ::= scalar_port
||= bus_port
scalar_port ::= IDENTIFIER
||= IDENTIFIER [ DNUMBER ]
bus_port ::= IDENTIFIER [ DNUMBER : DNUMBER ]
port_instance ::= port_path
||= instance port_path
value ::= ( NUMBER )
||= ( triple )
triple ::= NUMBER : NUMBER? : NUMBER?
||= NUMBER? : NUMBER : NUMBER?
||= NUMBER? : NUMBER? : NUMBER
A triple consists of one, two or three colon-separated NUMBERs. Each NUMBER corresponds to a data value in one of three data sets, commonly used (in order) as minimum, typical, and maximum values. If a NUMBER is omitted, then data is not included for that data set. At least one NUMBER is required. Both colons must always be present.
rvalue ::= ( RNUMBER )
||= ( rtriple )
rtriple ::= RNUMBER : RNUMBER? : RNUMBER?
||= RNUMBER? : RNUMBER : RNUMBER?
||= RNUMBER? : RNUMBER? : RNUMBER
Apart from allowing negative numbers (RNUMBER instead of NUMBER), an rtriple is essentially the same as a triple.
rvalue_list ::= ( rvalue )
||= ( rvalue? ) ( rvalue? )
||= ( rvalue? ) ( rvalue? ) ( rvalue? )
||= ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? )
||= ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? )
( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? ) ( rvalue? )
The number of rvalues you can specify is limited to one, two, three, six or twelve. A complete discussion of the use of rvalue_list is included in "Specifying Delay Values" on page 3-17.
conditional_port_expr ::= simple_expression
||= ( conditional_port_expr )
||= UNARY_OPERATOR ( conditional_port_expr )
||= conditional_port_expr BINARY_OPERATOR conditional_port_expr
simple_expression ::= ( simple_expression )
||= UNARY_OPERATOR ( simple_expression )
||= port
||= UNARY_OPERATOR port
||= SCALAR_CONSTANT
||= UNARY_OPERATOR SCALAR_CONSTANT
||= simple_expression ? simple_expression : simple_expression
||= { simple_expression concat_expression? }
||= { simple_expression { simple_expression concat_expression? } }
concat_expression ::= , simple_expression
timing_check_condition ::= scalar_port
||= INVERSION_OPERATOR scalar_port
||= scalar_port EQUALITY_OPERATOR SCALAR_CONSTANT
SCALAR_CONSTANT ::= 1`b0 // logical zero
||= 1`b1 // logical one
||= 1`B0 // logical zero
||= `B1 // logical one
||= `b0 // logical zero
||= `b1 // logical one
||= `B0 // logical zero
||= `B1 // logical one
||= 0 // logical zero
||= 1 // logical one
UNARY_OPERATOR ::= + // arithmetic identity
||= - // arithmetic negation
||= ! // logical negation
||= ~ // bit-wise unary negation
||= & // reduction unary AND
||= ~& // reduction unary NAND
||= | // reduction unary OR
||= ~| // reduction unary NOR
||= ^ // reduction unary XOR
||= ^~ // reduction unary XNOR
||= ~^ // reduction unary XNOR (alternative)
INVERSION_OPERATOR ::= ! // logical negation
||= ~ // bit-wise unary negation
BINARY_OPERATOR ::= + // arithmetic sum
||= - // arithmetic difference
||= * // arithmetic product
||= / // arithmetic quotient
||= % // modulus
||= == // logical equality
||= != // logical inequality
||= === // case equality
||= !== // case inequality
||= && // logical AND
||= || // logical OR
||= < // relational
||= <= // relational
||= > // relational
||= >= // relational
||= & // bit-wise binary AND
||= | // bit-wise binary inclusive OR
||= ^ // bit-wise binary exclusive OR
||= ^~ // bit-wise binary equivalence
||= ~^ // bit-wise binary equivalence (alternative)
||= >> // right shift
||= << // left shift
EQUALITY_OPERATOR ::= == // logical equality
||= != // logical inequality
||= === // case equality
||= !== // case inequality
a == b (logical equality) will be TRUE (1) only if a and b are of known logical state (0 or 1) and equal and FALSE (0) only if a and b are known and not equal. If either a or b is X or Z, then the result will be X.
a != b (logical inequality) will be TRUE (1) only if a and b are known and not equal and FALSE (0) only if a and b are known and equal. If either a or b is X or Z, then the result will be X.
a === b (case equality) will be TRUE (1) if a and b are of the exact same logical state, including the X and Z states, and FALSE (0) otherwise.
a !== b (case inequality) will be TRUE (1) if a and b are of different logical states, including the X and Z states, and FALSE (0) otherwise.
! ~ highest precedence * / % + - << >> < <= > >= == != === !== & ^ ^~ | && || lowest precedence