//////////////////////////////////////////////////////////////////////////////
//  File name : idt70t3509m.v
//////////////////////////////////////////////////////////////////////////////
//  Copyright (C) 2007 Free Model Foundry; http://www.freemodelfoundry.com
//
//  This program is free software; you can redistribute it and/or modify
//  it under the terms of the GNU General Public License version 2 as
//  published by the Free Software Foundation.
//
//  MODIFICATION HISTORY:
//
//  version: |  author:       |  mod date:  | changes made:
//    V1.0     V. Ljubisavljevic 07 Feb 23    Initial release
//
//////////////////////////////////////////////////////////////////////////////
//  PART DESCRIPTION:
//
//  Library:    RAM
//  Technology: 
//  Part:       IDT70T3509M
//
//  Description: 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
//
//////////////////////////////////////////////////////////////////////////////
//  Known Bugs:
//
//////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////
// NOTE!!!
// Simulation resolution must be 100 ps
/////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/100 ps
`define NULL 0
`define EOF 32'hFFFF_FFFF

module idt70t3509m (/*AUTOARG*/
    // Outputs
    INTLNeg, INTRNeg,
    // Inouts
    IOL35, IOL34, IOL33, IOL32, IOL31, IOL30, IOL29, IOL28, IOL27,
    IOL26, IOL25, IOL24, IOL23, IOL22, IOL21, IOL20, IOL19, IOL18,
    IOL17, IOL16, IOL15, IOL14, IOL13, IOL12, IOL11, IOL10, IOL9,
    IOL8, IOL7, IOL6, IOL5, IOL4, IOL3, IOL2, IOL1, IOL0, IOR35,
    IOR34, IOR33, IOR32, IOR31, IOR30, IOR29, IOR28, IOR27, IOR26,
    IOR25, IOR24, IOR23, IOR22, IOR21, IOR20, IOR19, IOR18, IOR17,
    IOR16, IOR15, IOR14, IOR13, IOR12, IOR11, IOR10, IOR9, IOR8,
    IOR7, IOR6, IOR5, IOR4, IOR3, IOR2, IOR1, IOR0,
    // Inputs
    CE0LNeg, CE1L, RWL, OELNeg, AL19, AL18, AL17, AL16, AL15, AL14,
    AL13, AL12, AL11, AL10, AL9, AL8, AL7, AL6, AL5, AL4, AL3, AL2,
    AL1, AL0, CLKL, PLFTL, ADSLNeg, CNTENLNeg, REPEATLNeg, BEL3Neg,
    BEL2Neg, BEL1Neg, BEL0Neg, ZZL, CE0RNeg, CE1R, RWR, OERNeg, AR19,
    AR18, AR17, AR16, AR15, AR14, AR13, AR12, AR11, AR10, AR9, AR8,
    AR7, AR6, AR5, AR4, AR3, AR2, AR1, AR0, CLKR, PLFTR, ADSRNeg,
    CNTENRNeg, REPEATRNeg, BER3Neg, BER2Neg, BER1Neg, BER0Neg, ZZR
    ) ;
    // Left side
    input  CE0LNeg;
    input  CE1L;
    input  RWL;
    input  OELNeg;
    input  AL19;
    input  AL18;
    input  AL17;
    input  AL16;
    input  AL15;
    input  AL14;
    input  AL13;
    input  AL12;
    input  AL11;
    input  AL10;
    input  AL9;
    input  AL8;
    input  AL7;
    input  AL6;
    input  AL5;
    input  AL4;
    input  AL3;
    input  AL2;
    input  AL1;
    input  AL0;
    inout  IOL35;
    inout  IOL34;
    inout  IOL33;
    inout  IOL32;
    inout  IOL31;
    inout  IOL30;
    inout  IOL29;
    inout  IOL28;
    inout  IOL27;
    inout  IOL26;
    inout  IOL25;
    inout  IOL24;
    inout  IOL23;
    inout  IOL22;
    inout  IOL21;
    inout  IOL20;
    inout  IOL19;
    inout  IOL18;
    inout  IOL17;
    inout  IOL16;
    inout  IOL15;
    inout  IOL14;
    inout  IOL13;
    inout  IOL12;
    inout  IOL11;
    inout  IOL10;
    inout  IOL9;
    inout  IOL8;
    inout  IOL7;
    inout  IOL6;
    inout  IOL5;
    inout  IOL4;
    inout  IOL3;
    inout  IOL2;
    inout  IOL1;
    inout  IOL0;
    input  CLKL;
    input  PLFTL;
    input  ADSLNeg;
    input  CNTENLNeg;
    input  REPEATLNeg;
    input  BEL3Neg;
    input  BEL2Neg;
    input  BEL1Neg;
    input  BEL0Neg;
    input  ZZL;
    output INTLNeg;
    // Right side
    input  CE0RNeg;
    input  CE1R;
    input  RWR;
    input  OERNeg;
    input  AR19;
    input  AR18;
    input  AR17;
    input  AR16;
    input  AR15;
    input  AR14;
    input  AR13;
    input  AR12;
    input  AR11;
    input  AR10;
    input  AR9;
    input  AR8;
    input  AR7;
    input  AR6;
    input  AR5;
    input  AR4;
    input  AR3;
    input  AR2;
    input  AR1;
    input  AR0;
    inout  IOR35;
    inout  IOR34;
    inout  IOR33;
    inout  IOR32;
    inout  IOR31;
    inout  IOR30;
    inout  IOR29;
    inout  IOR28;
    inout  IOR27;
    inout  IOR26;
    inout  IOR25;
    inout  IOR24;
    inout  IOR23;
    inout  IOR22;
    inout  IOR21;
    inout  IOR20;
    inout  IOR19;
    inout  IOR18;
    inout  IOR17;
    inout  IOR16;
    inout  IOR15;
    inout  IOR14;
    inout  IOR13;
    inout  IOR12;
    inout  IOR11;
    inout  IOR10;
    inout  IOR9;
    inout  IOR8;
    inout  IOR7;
    inout  IOR6;
    inout  IOR5;
    inout  IOR4;
    inout  IOR3;
    inout  IOR2;
    inout  IOR1;
    inout  IOR0;
    input  CLKR;
    input  PLFTR;
    input  ADSRNeg;
    input  CNTENRNeg;
    input  REPEATRNeg;
    input  BER3Neg;
    input  BER2Neg;
    input  BER1Neg;
    input  BER0Neg;
    input  ZZR;
    output INTRNeg;

    //////////////////////////////////////////////////////////////////////////
    // Interconnect path delay signals for left port
    //////////////////////////////////////////////////////////////////////////
    wire   AL19_ipd;
    wire   AL18_ipd;
    wire   AL17_ipd;
    wire   AL16_ipd;
    wire   AL15_ipd;
    wire   AL14_ipd;
    wire   AL13_ipd;
    wire   AL12_ipd;
    wire   AL11_ipd;
    wire   AL10_ipd;
    wire   AL9_ipd;
    wire   AL8_ipd;
    wire   AL7_ipd;
    wire   AL6_ipd;
    wire   AL5_ipd;
    wire   AL4_ipd;
    wire   AL3_ipd;
    wire   AL2_ipd;
    wire   AL1_ipd;
    wire   AL0_ipd;

    wire   [19:0] AL;
    assign AL =
           {AL19_ipd,
            AL18_ipd,
            AL17_ipd,
            AL16_ipd,
            AL15_ipd,
            AL14_ipd,
            AL13_ipd,
            AL12_ipd,
            AL11_ipd,
            AL10_ipd,
            AL9_ipd,
            AL8_ipd,
            AL7_ipd,
            AL6_ipd,
            AL5_ipd,
            AL4_ipd,
            AL3_ipd,
            AL2_ipd,
            AL1_ipd,
            AL0_ipd
            };
    wire   IOL35_ipd;
    wire   IOL34_ipd;
    wire   IOL33_ipd;
    wire   IOL32_ipd;
    wire   IOL31_ipd;
    wire   IOL30_ipd;
    wire   IOL29_ipd;
    wire   IOL28_ipd;
    wire   IOL27_ipd;
    wire   IOL26_ipd;
    wire   IOL25_ipd;
    wire   IOL24_ipd;
    wire   IOL23_ipd;
    wire   IOL22_ipd;
    wire   IOL21_ipd;
    wire   IOL20_ipd;
    wire   IOL19_ipd;
    wire   IOL18_ipd;
    wire   IOL17_ipd;
    wire   IOL16_ipd;
    wire   IOL15_ipd;
    wire   IOL14_ipd;
    wire   IOL13_ipd;
    wire   IOL12_ipd;
    wire   IOL11_ipd;
    wire   IOL10_ipd;
    wire   IOL9_ipd;
    wire   IOL8_ipd;
    wire   IOL7_ipd;
    wire   IOL6_ipd;
    wire   IOL5_ipd;
    wire   IOL4_ipd;
    wire   IOL3_ipd;
    wire   IOL2_ipd;
    wire   IOL1_ipd;
    wire   IOL0_ipd;

    wire   [35:0] DInL;
    assign DInL =
           {IOL35_ipd,
            IOL34_ipd,
            IOL33_ipd,
            IOL32_ipd,
            IOL31_ipd,
            IOL30_ipd,
            IOL29_ipd,
            IOL28_ipd,
            IOL27_ipd,
            IOL26_ipd,
            IOL25_ipd,
            IOL24_ipd,
            IOL23_ipd,
            IOL22_ipd,
            IOL21_ipd,
            IOL20_ipd,
            IOL19_ipd,
            IOL18_ipd,
            IOL17_ipd,
            IOL16_ipd,
            IOL15_ipd,
            IOL14_ipd,
            IOL13_ipd,
            IOL12_ipd,
            IOL11_ipd,
            IOL10_ipd,
            IOL9_ipd,
            IOL8_ipd,
            IOL7_ipd,
            IOL6_ipd,
            IOL5_ipd,
            IOL4_ipd,
            IOL3_ipd,
            IOL2_ipd,
            IOL1_ipd,
            IOL0_ipd
            };
    wire   BEL3Neg_ipd;
    wire   BEL2Neg_ipd;
    wire   BEL1Neg_ipd;
    wire   BEL0Neg_ipd;
    wire   [3:0] BELNeg;
    assign BELNeg = {BEL3Neg_ipd,
                     BEL2Neg_ipd,
                     BEL1Neg_ipd,
                     BEL0Neg_ipd
                     };
    wire   CE0LNeg_ipd;
    wire   CE1L_ipd;
    wire   RWL_ipd;
    wire   OELNeg_ipd;
    wire   CLKL_ipd;
    wire   PLFTL_ipd;
    wire   ADSLNeg_ipd;
    wire   CNTENLNeg_ipd;
    wire   REPEATLNeg_ipd;
    wire   ZZL_ipd;

    // Interconnect delays for Right port
    wire   AR19_ipd;
    wire   AR18_ipd;
    wire   AR17_ipd;
    wire   AR16_ipd;
    wire   AR15_ipd;
    wire   AR14_ipd;
    wire   AR13_ipd;
    wire   AR12_ipd;
    wire   AR11_ipd;
    wire   AR10_ipd;
    wire   AR9_ipd;
    wire   AR8_ipd;
    wire   AR7_ipd;
    wire   AR6_ipd;
    wire   AR5_ipd;
    wire   AR4_ipd;
    wire   AR3_ipd;
    wire   AR2_ipd;
    wire   AR1_ipd;
    wire   AR0_ipd;

    wire   [19:0] AR;
    assign AR =
           {AR19_ipd,
            AR18_ipd,
            AR17_ipd,
            AR16_ipd,
            AR15_ipd,
            AR14_ipd,
            AR13_ipd,
            AR12_ipd,
            AR11_ipd,
            AR10_ipd,
            AR9_ipd,
            AR8_ipd,
            AR7_ipd,
            AR6_ipd,
            AR5_ipd,
            AR4_ipd,
            AR3_ipd,
            AR2_ipd,
            AR1_ipd,
            AR0_ipd
            };
    wire   IOR35_ipd;
    wire   IOR34_ipd;
    wire   IOR33_ipd;
    wire   IOR32_ipd;
    wire   IOR31_ipd;
    wire   IOR30_ipd;
    wire   IOR29_ipd;
    wire   IOR28_ipd;
    wire   IOR27_ipd;
    wire   IOR26_ipd;
    wire   IOR25_ipd;
    wire   IOR24_ipd;
    wire   IOR23_ipd;
    wire   IOR22_ipd;
    wire   IOR21_ipd;
    wire   IOR20_ipd;
    wire   IOR19_ipd;
    wire   IOR18_ipd;
    wire   IOR17_ipd;
    wire   IOR16_ipd;
    wire   IOR15_ipd;
    wire   IOR14_ipd;
    wire   IOR13_ipd;
    wire   IOR12_ipd;
    wire   IOR11_ipd;
    wire   IOR10_ipd;
    wire   IOR9_ipd;
    wire   IOR8_ipd;
    wire   IOR7_ipd;
    wire   IOR6_ipd;
    wire   IOR5_ipd;
    wire   IOR4_ipd;
    wire   IOR3_ipd;
    wire   IOR2_ipd;
    wire   IOR1_ipd;
    wire   IOR0_ipd;

    wire   [35:0] DInR;
    assign DInR =
           {IOR35_ipd,
            IOR34_ipd,
            IOR33_ipd,
            IOR32_ipd,
            IOR31_ipd,
            IOR30_ipd,
            IOR29_ipd,
            IOR28_ipd,
            IOR27_ipd,
            IOR26_ipd,
            IOR25_ipd,
            IOR24_ipd,
            IOR23_ipd,
            IOR22_ipd,
            IOR21_ipd,
            IOR20_ipd,
            IOR19_ipd,
            IOR18_ipd,
            IOR17_ipd,
            IOR16_ipd,
            IOR15_ipd,
            IOR14_ipd,
            IOR13_ipd,
            IOR12_ipd,
            IOR11_ipd,
            IOR10_ipd,
            IOR9_ipd,
            IOR8_ipd,
            IOR7_ipd,
            IOR6_ipd,
            IOR5_ipd,
            IOR4_ipd,
            IOR3_ipd,
            IOR2_ipd,
            IOR1_ipd,
            IOR0_ipd
            };
    wire   BER3Neg_ipd;
    wire   BER2Neg_ipd;
    wire   BER1Neg_ipd;
    wire   BER0Neg_ipd;
    wire   [3:0] BERNeg;
    assign BERNeg = {BER3Neg_ipd,
                     BER2Neg_ipd,
                     BER1Neg_ipd,
                     BER0Neg_ipd
                     };
    wire   CE0RNeg_ipd;
    wire   CE1R_ipd;
    wire   RWR_ipd;
    wire   OERNeg_ipd;
    wire   CLKR_ipd;
    wire   PLFTR_ipd;
    wire   ADSRNeg_ipd;
    wire   CNTENRNeg_ipd;
    wire   REPEATRNeg_ipd;
    wire   ZZR_ipd;

    /* Internal dealys*/
    reg    CLKL_out;
    reg    CLKL_in;
    reg    CLKR_out;
    reg    CLKR_in;

    reg    [35:0] DOutL_zd;
    reg    [35:0] DOutR_zd;

    wire   DOutL0_zd;
    wire   DOutL1_zd;
    wire   DOutL2_zd;
    wire   DOutL3_zd;
    wire   DOutL4_zd;
    wire   DOutL5_zd;
    wire   DOutL6_zd;
    wire   DOutL7_zd;
    wire   DOutL8_zd;
    wire   DOutL9_zd;
    wire   DOutL10_zd;
    wire   DOutL11_zd;
    wire   DOutL12_zd;
    wire   DOutL13_zd;
    wire   DOutL14_zd;
    wire   DOutL15_zd;
    wire   DOutL16_zd;
    wire   DOutL17_zd;
    wire   DOutL18_zd;
    wire   DOutL19_zd;
    wire   DOutL20_zd;
    wire   DOutL21_zd;
    wire   DOutL22_zd;
    wire   DOutL23_zd;
    wire   DOutL24_zd;
    wire   DOutL25_zd;
    wire   DOutL26_zd;
    wire   DOutL27_zd;
    wire   DOutL28_zd;
    wire   DOutL29_zd;
    wire   DOutL30_zd;
    wire   DOutL31_zd;
    wire   DOutL32_zd;
    wire   DOutL33_zd;
    wire   DOutL34_zd;
    wire   DOutL35_zd;
    assign {DOutL35_zd,
            DOutL34_zd,
            DOutL33_zd,
            DOutL32_zd,
            DOutL31_zd,
            DOutL30_zd,
            DOutL29_zd,
            DOutL28_zd,
            DOutL27_zd,
            DOutL26_zd,
            DOutL25_zd,
            DOutL24_zd,
            DOutL23_zd,
            DOutL22_zd,
            DOutL21_zd,
            DOutL20_zd,
            DOutL19_zd,
            DOutL18_zd,
            DOutL17_zd,
            DOutL16_zd,
            DOutL15_zd,
            DOutL14_zd,
            DOutL13_zd,
            DOutL12_zd,
            DOutL11_zd,
            DOutL10_zd,
            DOutL9_zd,
            DOutL8_zd,
            DOutL7_zd,
            DOutL6_zd,
            DOutL5_zd,
            DOutL4_zd,
            DOutL3_zd,
            DOutL2_zd,
            DOutL1_zd,
            DOutL0_zd} = DOutL_zd;

    wire   DOutR0_zd;
    wire   DOutR1_zd;
    wire   DOutR2_zd;
    wire   DOutR3_zd;
    wire   DOutR4_zd;
    wire   DOutR5_zd;
    wire   DOutR6_zd;
    wire   DOutR7_zd;
    wire   DOutR8_zd;
    wire   DOutR9_zd;
    wire   DOutR10_zd;
    wire   DOutR11_zd;
    wire   DOutR12_zd;
    wire   DOutR13_zd;
    wire   DOutR14_zd;
    wire   DOutR15_zd;
    wire   DOutR16_zd;
    wire   DOutR17_zd;
    wire   DOutR18_zd;
    wire   DOutR19_zd;
    wire   DOutR20_zd;
    wire   DOutR21_zd;
    wire   DOutR22_zd;
    wire   DOutR23_zd;
    wire   DOutR24_zd;
    wire   DOutR25_zd;
    wire   DOutR26_zd;
    wire   DOutR27_zd;
    wire   DOutR28_zd;
    wire   DOutR29_zd;
    wire   DOutR30_zd;
    wire   DOutR31_zd;
    wire   DOutR32_zd;
    wire   DOutR33_zd;
    wire   DOutR34_zd;
    wire   DOutR35_zd;
    assign {DOutR35_zd,
            DOutR34_zd,
            DOutR33_zd,
            DOutR32_zd,
            DOutR31_zd,
            DOutR30_zd,
            DOutR29_zd,
            DOutR28_zd,
            DOutR27_zd,
            DOutR26_zd,
            DOutR25_zd,
            DOutR24_zd,
            DOutR23_zd,
            DOutR22_zd,
            DOutR21_zd,
            DOutR20_zd,
            DOutR19_zd,
            DOutR18_zd,
            DOutR17_zd,
            DOutR16_zd,
            DOutR15_zd,
            DOutR14_zd,
            DOutR13_zd,
            DOutR12_zd,
            DOutR11_zd,
            DOutR10_zd,
            DOutR9_zd,
            DOutR8_zd,
            DOutR7_zd,
            DOutR6_zd,
            DOutR5_zd,
            DOutR4_zd,
            DOutR3_zd,
            DOutR2_zd,
            DOutR1_zd,
            DOutR0_zd} = DOutR_zd;
    reg    INTRNeg_zd;
    reg    INTLNeg_zd;

    parameter     UserPreload = 1'b0;
    parameter     mem_file_name = "none";
    parameter     TimingModel = "DefaultTimingModel";
    parameter     PartId = "idt70t3509m";
    parameter     MaxData = 9'h1FF;
    parameter     HiAddrBit = 19;
    parameter     HiDataBit = 35;
    parameter     MemSize = 1048576;

    localparam desel = 2'b00;
    localparam read = 2'b01;
    localparam write = 2'b10;
    localparam collision = 2'b11;

    // Memory definition
    integer       MemA[0:MemSize-1];
    integer       MemB[0:MemSize-1];
    integer       MemC[0:MemSize-1];
    integer       MemD[0:MemSize-1];

    reg           SKEW_In;
    reg           SKEW_out;
    reg           SKEW1_In;
    reg           SKEW1_out;
    reg           SKEW2_In;
    wire          SKEW2_out;
    reg           SKEW3_In;
    wire          SKEW3_out;
    // Internaly delayed sleep pins
    reg           ZZL_int = 1'b0;
    reg           ZZR_int = 1'b0;

    // States on left and right ports
    reg [1:0]     stateL;
    reg [1:0]     stateR;

    reg           CELReg, CERReg;
    reg           RWLReg, RWRReg;
    reg [HiDataBit:0] MemOutLReg, MemOutRReg;
    reg [HiDataBit:0] MemOutL, MemOutR;
    reg [HiDataBit:0] MemInRegL, MemInRegR;
    reg [HiDataBit:0] OutMuxL, OutMuxR;
    reg [3:0]         BELNegReg, BERNegReg;
    reg [3:0]         BELNegPipe, BERNegPipe;
    reg [3:0]         MemBEL, MemBER;
    wire [3:0]        DoutLSel, DoutRSel;

    //////////////////////////////////////////////////////////////////////////
    // Interconnect Path Delay Section
    //////////////////////////////////////////////////////////////////////////
    // Left port
    buf(AL19_ipd,AL19);
    buf(AL18_ipd,AL18);
    buf(AL17_ipd,AL17);
    buf(AL16_ipd,AL16);
    buf(AL15_ipd,AL15);
    buf(AL14_ipd,AL14);
    buf(AL13_ipd,AL13);
    buf(AL12_ipd,AL12);
    buf(AL11_ipd,AL11);
    buf(AL10_ipd,AL10);
    buf(AL9_ipd,AL9);
    buf(AL8_ipd,AL8);
    buf(AL7_ipd,AL7);
    buf(AL6_ipd,AL6);
    buf(AL5_ipd,AL5);
    buf(AL4_ipd,AL4);
    buf(AL3_ipd,AL3);
    buf(AL2_ipd,AL2);
    buf(AL1_ipd,AL1);
    buf(AL0_ipd,AL0);

    buf(IOL35_ipd,IOL35);
    buf(IOL34_ipd,IOL34);
    buf(IOL33_ipd,IOL33);
    buf(IOL32_ipd,IOL32);
    buf(IOL31_ipd,IOL31);
    buf(IOL30_ipd,IOL30);
    buf(IOL29_ipd,IOL29);
    buf(IOL28_ipd,IOL28);
    buf(IOL27_ipd,IOL27);
    buf(IOL26_ipd,IOL26);
    buf(IOL25_ipd,IOL25);
    buf(IOL24_ipd,IOL24);
    buf(IOL23_ipd,IOL23);
    buf(IOL22_ipd,IOL22);
    buf(IOL21_ipd,IOL21);
    buf(IOL20_ipd,IOL20);
    buf(IOL19_ipd,IOL19);
    buf(IOL18_ipd,IOL18);
    buf(IOL17_ipd,IOL17);
    buf(IOL16_ipd,IOL16);
    buf(IOL15_ipd,IOL15);
    buf(IOL14_ipd,IOL14);
    buf(IOL13_ipd,IOL13);
    buf(IOL12_ipd,IOL12);
    buf(IOL11_ipd,IOL11);
    buf(IOL10_ipd,IOL10);
    buf(IOL9_ipd,IOL9);
    buf(IOL8_ipd,IOL8);
    buf(IOL7_ipd,IOL7);
    buf(IOL6_ipd,IOL6);
    buf(IOL5_ipd,IOL5);
    buf(IOL4_ipd,IOL4);
    buf(IOL3_ipd,IOL3);
    buf(IOL2_ipd,IOL2);
    buf(IOL1_ipd,IOL1);
    buf(IOL0_ipd,IOL0);

    buf(CE0LNeg_ipd,CE0LNeg);
    buf(CE1L_ipd,CE1L);
    buf(RWL_ipd, RWL);
    buf(OELNeg_ipd,OELNeg);
    buf(CLKL_ipd, CLKL);
    buf(PLFTL_ipd, PLFTL);
    buf(ADSLNeg_ipd, ADSLNeg);
    buf(CNTENLNeg_ipd, CNTENLNeg);
    buf(REPEATLNeg_ipd, REPEATLNeg);
    buf(BEL3Neg_ipd, BEL3Neg);
    buf(BEL2Neg_ipd, BEL2Neg);
    buf(BEL1Neg_ipd, BEL1Neg);
    buf(BEL0Neg_ipd, BEL0Neg);
    buf(ZZL_ipd,ZZL);

    // Right port Inerconnect path delays
    buf(AR19_ipd,AR19);
    buf(AR18_ipd,AR18);
    buf(AR17_ipd,AR17);
    buf(AR16_ipd,AR16);
    buf(AR15_ipd,AR15);
    buf(AR14_ipd,AR14);
    buf(AR13_ipd,AR13);
    buf(AR12_ipd,AR12);
    buf(AR11_ipd,AR11);
    buf(AR10_ipd,AR10);
    buf(AR9_ipd,AR9);
    buf(AR8_ipd,AR8);
    buf(AR7_ipd,AR7);
    buf(AR6_ipd,AR6);
    buf(AR5_ipd,AR5);
    buf(AR4_ipd,AR4);
    buf(AR3_ipd,AR3);
    buf(AR2_ipd,AR2);
    buf(AR1_ipd,AR1);
    buf(AR0_ipd,AR0);

    buf(IOR35_ipd,IOR35);
    buf(IOR34_ipd,IOR34);
    buf(IOR33_ipd,IOR33);
    buf(IOR32_ipd,IOR32);
    buf(IOR31_ipd,IOR31);
    buf(IOR30_ipd,IOR30);
    buf(IOR29_ipd,IOR29);
    buf(IOR28_ipd,IOR28);
    buf(IOR27_ipd,IOR27);
    buf(IOR26_ipd,IOR26);
    buf(IOR25_ipd,IOR25);
    buf(IOR24_ipd,IOR24);
    buf(IOR23_ipd,IOR23);
    buf(IOR22_ipd,IOR22);
    buf(IOR21_ipd,IOR21);
    buf(IOR20_ipd,IOR20);
    buf(IOR19_ipd,IOR19);
    buf(IOR18_ipd,IOR18);
    buf(IOR17_ipd,IOR17);
    buf(IOR16_ipd,IOR16);
    buf(IOR15_ipd,IOR15);
    buf(IOR14_ipd,IOR14);
    buf(IOR13_ipd,IOR13);
    buf(IOR12_ipd,IOR12);
    buf(IOR11_ipd,IOR11);
    buf(IOR10_ipd,IOR10);
    buf(IOR9_ipd,IOR9);
    buf(IOR8_ipd,IOR8);
    buf(IOR7_ipd,IOR7);
    buf(IOR6_ipd,IOR6);
    buf(IOR5_ipd,IOR5);
    buf(IOR4_ipd,IOR4);
    buf(IOR3_ipd,IOR3);
    buf(IOR2_ipd,IOR2);
    buf(IOR1_ipd,IOR1);
    buf(IOR0_ipd,IOR0);

    buf(CE0RNeg_ipd,CE0RNeg);
    buf(CE1R_ipd,CE1R);
    buf(RWR_ipd, RWR);
    buf(OERNeg_ipd,OERNeg);
    buf(CLKR_ipd, CLKR);
    buf(PLFTR_ipd, PLFTR);
    buf(ADSRNeg_ipd, ADSRNeg);
    buf(CNTENRNeg_ipd, CNTENRNeg);
    buf(REPEATRNeg_ipd, REPEATRNeg);
    buf(BER3Neg_ipd, BER3Neg);
    buf(BER2Neg_ipd, BER2Neg);
    buf(BER1Neg_ipd, BER1Neg);
    buf(BER0Neg_ipd, BER0Neg);
    buf(ZZR_ipd,ZZR);

    //////////////////////////////////////////////////////////////////////////
    // Propagation delay section
    //////////////////////////////////////////////////////////////////////////
    nmos(IOL35, DOutL35_zd, 1);
    nmos(IOL34, DOutL34_zd, 1);
    nmos(IOL33, DOutL33_zd, 1);
    nmos(IOL32, DOutL32_zd, 1);
    nmos(IOL31, DOutL31_zd, 1);
    nmos(IOL30, DOutL30_zd, 1);
    nmos(IOL29, DOutL29_zd, 1);
    nmos(IOL28, DOutL28_zd, 1);
    nmos(IOL27, DOutL27_zd, 1);
    nmos(IOL26, DOutL26_zd, 1);
    nmos(IOL25, DOutL25_zd, 1);
    nmos(IOL24, DOutL24_zd, 1);
    nmos(IOL23, DOutL23_zd, 1);
    nmos(IOL22, DOutL22_zd, 1);
    nmos(IOL21, DOutL21_zd, 1);
    nmos(IOL20, DOutL20_zd, 1);
    nmos(IOL19, DOutL19_zd, 1);
    nmos(IOL18, DOutL18_zd, 1);
    nmos(IOL17, DOutL17_zd, 1);
    nmos(IOL16, DOutL16_zd, 1);
    nmos(IOL15, DOutL15_zd, 1);
    nmos(IOL14, DOutL14_zd, 1);
    nmos(IOL13, DOutL13_zd, 1);
    nmos(IOL12, DOutL12_zd, 1);
    nmos(IOL11, DOutL11_zd, 1);
    nmos(IOL10, DOutL10_zd, 1);
    nmos(IOL9, DOutL9_zd, 1);
    nmos(IOL8, DOutL8_zd, 1);
    nmos(IOL7, DOutL7_zd, 1);
    nmos(IOL6, DOutL6_zd, 1);
    nmos(IOL5, DOutL5_zd, 1);
    nmos(IOL4, DOutL4_zd, 1);
    nmos(IOL3, DOutL3_zd, 1);
    nmos(IOL2, DOutL2_zd, 1);
    nmos(IOL1, DOutL1_zd, 1);
    nmos(IOL0, DOutL0_zd, 1);

    nmos(IOR35, DOutR35_zd, 1);
    nmos(IOR34, DOutR34_zd, 1);
    nmos(IOR33, DOutR33_zd, 1);
    nmos(IOR32, DOutR32_zd, 1);
    nmos(IOR31, DOutR31_zd, 1);
    nmos(IOR30, DOutR30_zd, 1);
    nmos(IOR29, DOutR29_zd, 1);
    nmos(IOR28, DOutR28_zd, 1);
    nmos(IOR27, DOutR27_zd, 1);
    nmos(IOR26, DOutR26_zd, 1);
    nmos(IOR25, DOutR25_zd, 1);
    nmos(IOR24, DOutR24_zd, 1);
    nmos(IOR23, DOutR23_zd, 1);
    nmos(IOR22, DOutR22_zd, 1);
    nmos(IOR21, DOutR21_zd, 1);
    nmos(IOR20, DOutR20_zd, 1);
    nmos(IOR19, DOutR19_zd, 1);
    nmos(IOR18, DOutR18_zd, 1);
    nmos(IOR17, DOutR17_zd, 1);
    nmos(IOR16, DOutR16_zd, 1);
    nmos(IOR15, DOutR15_zd, 1);
    nmos(IOR14, DOutR14_zd, 1);
    nmos(IOR13, DOutR13_zd, 1);
    nmos(IOR12, DOutR12_zd, 1);
    nmos(IOR11, DOutR11_zd, 1);
    nmos(IOR10, DOutR10_zd, 1);
    nmos(IOR9 , DOutR9_zd, 1);
    nmos(IOR8 , DOutR8_zd, 1);
    nmos(IOR7 , DOutR7_zd, 1);
    nmos(IOR6 , DOutR6_zd, 1);
    nmos(IOR5 , DOutR5_zd, 1);
    nmos(IOR4 , DOutR4_zd, 1);
    nmos(IOR3, DOutR3_zd, 1);
    nmos(IOR2, DOutR2_zd, 1);
    nmos(IOR1, DOutR1_zd, 1);
    nmos(IOR0, DOutR0_zd, 1);
    // Interrupt output flags
    nmos(INTRNeg, INTRNeg_zd, 1);
    nmos(INTLNeg, INTLNeg_zd, 1);

    // needed for timing checks
    wire   pipelineL;
    assign pipelineL = PLFTL;
    wire   nopipelineL;
    assign nopipelineL = ~PLFTL;
    wire   pipelineR;
    assign pipelineR = PLFTR;
    wire   nopipelineR;
    assign nopipelineR = ~PLFTR;

    specify
        // tipd delays: interconnect path delays ,
        // mapped to input port delays.
        // In Verilog is not necessary to declare any tipd_ delay variables,
        // they can be taken from SDF file
        // With all the other delays real delays would be taken from SDF file
        // tpd delays
        specparam tpd_CLKL_INTLNeg = 1;
        specparam tpd_CLKR_INTLNeg = 1;
        specparam tpd_CLKL_INTRNeg = 1;
        specparam tpd_CLKR_INTRNeg = 1;
        specparam tpd_CLKL_IOL0_pipelineL_EQ_0 =1;
        specparam tpd_CLKL_IOL0_pipelineL_EQ_1 =1;
        specparam tpd_CLKR_IOR0_pipelineR_EQ_0 =1;
        specparam tpd_CLKR_IOR0_pipelineR_EQ_1 =1;
        specparam tpd_OELNeg_IOL0 = 1;
        specparam tpd_OERNeg_IOR0 =1;

        // Setup parameters
        specparam tsetup_AL0_CLKL = 1;
        specparam tsetup_AR0_CLKR = 1;
        specparam tsetup_CE0LNeg_CLKL = 1;
        specparam tsetup_CE1L_CLKL = 1;
        specparam tsetup_CE0RNeg_CLKR = 1;
        specparam tsetup_CE1R_CLKR = 1;
        specparam tsetup_BEL0Neg_CLKL = 1;
        specparam tsetup_BER0Neg_CLKR = 1;
        specparam tsetup_RWL_CLKL = 1;
        specparam tsetup_RWR_CLKR = 1;
        specparam tsetup_IOL0_CLKL = 1;
        specparam tsetup_IOR0_CLKR = 1;
        specparam tsetup_ADSLNeg_CLKL = 1;
        specparam tsetup_ADSRNeg_CLKR = 1;
        specparam tsetup_CNTENLNeg_CLKL = 1;
        specparam tsetup_CNTENRNeg_CLKR = 1;
        specparam tsetup_REPEATLNeg_CLKL = 1;
        specparam tsetup_REPEATRNeg_CLKR = 1;
        // Hold times
        specparam thold_AL0_CLKL = 1;
        specparam thold_AR0_CLKR = 1;
        specparam thold_CE0LNeg_CLKL = 1;
        specparam thold_CE1L_CLKL = 1;
        specparam thold_CE0RNeg_CLKR = 1;
        specparam thold_CE1R_CLKR = 1;
        specparam thold_BEL0Neg_CLKL = 1;
        specparam thold_BER0Neg_CLKR = 1;
        specparam thold_RWL_CLKL = 1;
        specparam thold_RWR_CLKR = 1;
        specparam thold_IOL0_CLKL = 1;
        specparam thold_IOR0_CLKR = 1;
        specparam thold_ADSLNeg_CLKL = 1;
        specparam thold_ADSRNeg_CLKR = 1;
        specparam thold_CNTENLNeg_CLKL = 1;
        specparam thold_CNTENRNeg_CLKR = 1;
        specparam thold_REPEATLNeg_CLKL = 1;
        specparam thold_REPEATRNeg_CLKR = 1;
        // tpw values: puls width
        specparam tpw_CLKL_pipelineL_EQ_1_posedge = 1;
        specparam tpw_CLKL_pipelineL_EQ_1_negedge = 1;
        specparam tpw_CLKL_pipelineL_EQ_0_posedge = 1;
        specparam tpw_CLKL_pipelineL_EQ_0_negedge = 1;
        specparam tpw_CLKR_pipelineR_EQ_1_posedge = 1;
        specparam tpw_CLKR_pipelineR_EQ_1_negedge = 1;
        specparam tpw_CLKR_pipelineR_EQ_0_posedge = 1;
        specparam tpw_CLKR_pipelineR_EQ_0_negedge = 1;
        // tperiod values: period
        specparam tperiod_CLKL_pipelineL_EQ_1 = 1;
        specparam tperiod_CLKL_pipelineL_EQ_0 = 1;
        specparam tperiod_CLKR_pipelineR_EQ_1 = 1;
        specparam tperiod_CLKR_pipelineR_EQ_0 = 1;
        // tdevice values: internal delays...
        specparam tdevice_SKEW = 6;
        //////////////////////////////////////////////////////////////////////
        // Input Port  Delays  don't require Verilog description
        //////////////////////////////////////////////////////////////////////
        // Path delays
        //////////////////////////////////////////////////////////////////////
        // for IO signals
        if(pipelineL)
          (CLKL=>IOL35)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL34)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL33)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL32)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL31)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL30)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL29)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL28)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL27)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL26)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL25)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL24)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL23)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL22)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL21)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL20)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL19)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL18)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL17)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL16)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL15)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL14)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL13)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL12)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL11)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL10)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL9)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL8)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL7)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL6)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL5)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL4)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL3)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL2)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL1)= tpd_CLKL_IOL0_pipelineL_EQ_1;
        if(pipelineL)
          (CLKL=>IOL0)= tpd_CLKL_IOL0_pipelineL_EQ_1;

        if(pipelineR)
          (CLKR=>IOR35)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR34)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR33)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR32)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR31)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR30)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR29)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR28)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR27)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR26)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR25)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR24)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR23)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR22)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR21)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR20)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR19)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR18)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR17)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR16)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR15)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR14)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR13)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR12)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR11)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR10)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR9)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR8)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR7)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR6)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR5)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR4)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR3)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR2)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR1)= tpd_CLKR_IOR0_pipelineR_EQ_1;
        if(pipelineR)
          (CLKR=>IOR0)= tpd_CLKR_IOR0_pipelineR_EQ_1;

        if(~pipelineL)
          (CLKL=>IOL35)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL34)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL33)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL32)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL31)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL30)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL29)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL28)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL27)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL26)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL25)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL24)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL23)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL22)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL21)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL20)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL19)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL18)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL17)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL16)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL15)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL14)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL13)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL12)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL11)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL10)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL9)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL8)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL7)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL6)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL5)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL4)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL3)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL2)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL1)= tpd_CLKL_IOL0_pipelineL_EQ_0;
        if(~pipelineL)
          (CLKL=>IOL0)= tpd_CLKL_IOL0_pipelineL_EQ_0;

        if(~pipelineR)
          (CLKR=>IOR35)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR34)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR33)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR32)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR31)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR30)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR29)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR28)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR27)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR26)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR25)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR24)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR23)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR22)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR21)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR20)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR19)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR18)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR17)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR16)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR15)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR14)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR13)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR12)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR11)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR10)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR9)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR8)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR7)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR6)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR5)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR4)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR3)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR2)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR1)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        if(~pipelineR)
          (CLKR=>IOR0)= tpd_CLKR_IOR0_pipelineR_EQ_0;
        // From output enable pin...
        (OELNeg => IOL35) = tpd_OELNeg_IOL0;
        (OELNeg => IOL34) = tpd_OELNeg_IOL0;
        (OELNeg => IOL33) = tpd_OELNeg_IOL0;
        (OELNeg => IOL32) = tpd_OELNeg_IOL0;
        (OELNeg => IOL31) = tpd_OELNeg_IOL0;
        (OELNeg => IOL30) = tpd_OELNeg_IOL0;
        (OELNeg => IOL29) = tpd_OELNeg_IOL0;
        (OELNeg => IOL28) = tpd_OELNeg_IOL0;
        (OELNeg => IOL27) = tpd_OELNeg_IOL0;
        (OELNeg => IOL26) = tpd_OELNeg_IOL0;
        (OELNeg => IOL25) = tpd_OELNeg_IOL0;
        (OELNeg => IOL24) = tpd_OELNeg_IOL0;
        (OELNeg => IOL23) = tpd_OELNeg_IOL0;
        (OELNeg => IOL22) = tpd_OELNeg_IOL0;
        (OELNeg => IOL21) = tpd_OELNeg_IOL0;
        (OELNeg => IOL20) = tpd_OELNeg_IOL0;
        (OELNeg => IOL19) = tpd_OELNeg_IOL0;
        (OELNeg => IOL18) = tpd_OELNeg_IOL0;
        (OELNeg => IOL17) = tpd_OELNeg_IOL0;
        (OELNeg => IOL16) = tpd_OELNeg_IOL0;
        (OELNeg => IOL15) = tpd_OELNeg_IOL0;
        (OELNeg => IOL14) = tpd_OELNeg_IOL0;
        (OELNeg => IOL13) = tpd_OELNeg_IOL0;
        (OELNeg => IOL12) = tpd_OELNeg_IOL0;
        (OELNeg => IOL11) = tpd_OELNeg_IOL0;
        (OELNeg => IOL10) = tpd_OELNeg_IOL0;
        (OELNeg => IOL9) = tpd_OELNeg_IOL0;
        (OELNeg => IOL8) = tpd_OELNeg_IOL0;
        (OELNeg => IOL7) = tpd_OELNeg_IOL0;
        (OELNeg => IOL6) = tpd_OELNeg_IOL0;
        (OELNeg => IOL5) = tpd_OELNeg_IOL0;
        (OELNeg => IOL4) = tpd_OELNeg_IOL0;
        (OELNeg => IOL3) = tpd_OELNeg_IOL0;
        (OELNeg => IOL2) = tpd_OELNeg_IOL0;
        (OELNeg => IOL1) = tpd_OELNeg_IOL0;
        (OELNeg => IOL0) = tpd_OELNeg_IOL0;

        (OERNeg => IOR35) = tpd_OERNeg_IOR0;
        (OERNeg => IOR34) = tpd_OERNeg_IOR0;
        (OERNeg => IOR33) = tpd_OERNeg_IOR0;
        (OERNeg => IOR32) = tpd_OERNeg_IOR0;
        (OERNeg => IOR31) = tpd_OERNeg_IOR0;
        (OERNeg => IOR30) = tpd_OERNeg_IOR0;
        (OERNeg => IOR29) = tpd_OERNeg_IOR0;
        (OERNeg => IOR28) = tpd_OERNeg_IOR0;
        (OERNeg => IOR27) = tpd_OERNeg_IOR0;
        (OERNeg => IOR26) = tpd_OERNeg_IOR0;
        (OERNeg => IOR25) = tpd_OERNeg_IOR0;
        (OERNeg => IOR24) = tpd_OERNeg_IOR0;
        (OERNeg => IOR23) = tpd_OERNeg_IOR0;
        (OERNeg => IOR22) = tpd_OERNeg_IOR0;
        (OERNeg => IOR21) = tpd_OERNeg_IOR0;
        (OERNeg => IOR20) = tpd_OERNeg_IOR0;
        (OERNeg => IOR19) = tpd_OERNeg_IOR0;
        (OERNeg => IOR18) = tpd_OERNeg_IOR0;
        (OERNeg => IOR17) = tpd_OERNeg_IOR0;
        (OERNeg => IOR16) = tpd_OERNeg_IOR0;
        (OERNeg => IOR15) = tpd_OERNeg_IOR0;
        (OERNeg => IOR14) = tpd_OERNeg_IOR0;
        (OERNeg => IOR13) = tpd_OERNeg_IOR0;
        (OERNeg => IOR12) = tpd_OERNeg_IOR0;
        (OERNeg => IOR11) = tpd_OERNeg_IOR0;
        (OERNeg => IOR10) = tpd_OERNeg_IOR0;
        (OERNeg => IOR9) = tpd_OERNeg_IOR0;
        (OERNeg => IOR8) = tpd_OERNeg_IOR0;
        (OERNeg => IOR7) = tpd_OERNeg_IOR0;
        (OERNeg => IOR6) = tpd_OERNeg_IOR0;
        (OERNeg => IOR5) = tpd_OERNeg_IOR0;
        (OERNeg => IOR4) = tpd_OERNeg_IOR0;
        (OERNeg => IOR3) = tpd_OERNeg_IOR0;
        (OERNeg => IOR2) = tpd_OERNeg_IOR0;
        (OERNeg => IOR1) = tpd_OERNeg_IOR0;
        (OERNeg => IOR0) = tpd_OERNeg_IOR0;
        // Interrupt pins
        if(INTLNeg_zd)
          (CLKL => INTLNeg) = tpd_CLKL_INTLNeg;
        if(~INTLNeg_zd)
          (CLKR => INTLNeg) = tpd_CLKR_INTLNeg;
        if(INTRNeg_zd)
          (CLKR => INTRNeg) = tpd_CLKR_INTRNeg;
        if(~INTRNeg_zd)
          (CLKL => INTRNeg) = tpd_CLKL_INTRNeg;
        // Timing checks
        // Setup checks
        // Address setup check...
        $setup(AL19,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL18,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL17,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL16,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL15,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL14,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL13,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL12,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL11,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL10,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL9,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL8,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL7,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL6,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL5,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL4,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL3,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL2,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL1,posedge CLKL, tsetup_AL0_CLKL);
        $setup(AL0,posedge CLKL, tsetup_AL0_CLKL);

        $setup(AR19,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR18,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR17,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR16,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR15,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR14,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR13,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR12,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR11,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR10,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR9,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR8,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR7,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR6,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR5,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR4,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR3,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR2,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR1,posedge CLKR, tsetup_AR0_CLKR);
        $setup(AR0,posedge CLKR, tsetup_AR0_CLKR);
        // Chip enable
        $setup(CE0LNeg,posedge CLKL, tsetup_CE0LNeg_CLKL);
        $setup(CE1L, posedge CLKL, tsetup_CE1L_CLKL);
        $setup(CE0RNeg, posedge CLKR, tsetup_CE0RNeg_CLKR);
        $setup(CE1R,posedge CLKR, tsetup_CE1R_CLKR);
        // Byte ebable
        $setup(BEL0Neg, posedge CLKL, tsetup_BEL0Neg_CLKL);
        $setup(BEL1Neg, posedge CLKL, tsetup_BEL0Neg_CLKL);
        $setup(BEL2Neg, posedge CLKL, tsetup_BEL0Neg_CLKL);
        $setup(BEL3Neg, posedge CLKL, tsetup_BEL0Neg_CLKL);

        $setup(BER0Neg, posedge CLKR, tsetup_BER0Neg_CLKR);
        $setup(BER1Neg, posedge CLKR, tsetup_BER0Neg_CLKR);
        $setup(BER2Neg, posedge CLKR, tsetup_BER0Neg_CLKR);
        $setup(BER3Neg, posedge CLKR, tsetup_BER0Neg_CLKR);
        // RWL read write setup time
        $setup(RWL,posedge CLKL, tsetup_RWL_CLKL);
        $setup(RWR, posedge CLKR, tsetup_RWR_CLKR);
        // Input signal setup time
        $setup(IOL35,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL34,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL33,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL32,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL31,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL30,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL29,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL28,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL27,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL26,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL25,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL24,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL23,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL22,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL21,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL20,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL19,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL18,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL17,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL16,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL15,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL14,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL13,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL12,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL11,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL10,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL9,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL8,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL7,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL6,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL5,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL4,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL3,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL2,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL1,posedge CLKL, tsetup_IOL0_CLKL);
        $setup(IOL0,posedge CLKL, tsetup_IOL0_CLKL);

        $setup(IOR35,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR34,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR33,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR32,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR31,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR30,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR29,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR28,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR27,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR26,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR25,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR24,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR23,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR22,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR21,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR20,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR19,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR18,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR17,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR16,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR15,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR14,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR13,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR12,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR11,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR10,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR9,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR8,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR7,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR6,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR5,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR4,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR3,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR2,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR1,posedge CLKR, tsetup_IOR0_CLKR);
        $setup(IOR0,posedge CLKR, tsetup_IOR0_CLKR);
        // Address strobe setup check
        $setup(ADSRNeg, posedge CLKR, tsetup_ADSRNeg_CLKR);
        $setup(ADSLNeg, posedge CLKL, tsetup_ADSLNeg_CLKL);
        $setup(REPEATRNeg, posedge CLKR, tsetup_REPEATRNeg_CLKR);
        $setup(REPEATLNeg, posedge CLKL, tsetup_REPEATLNeg_CLKL);
        $setup(CNTENRNeg, posedge CLKR, tsetup_CNTENRNeg_CLKR);
        $setup(CNTENLNeg, posedge CLKL, tsetup_CNTENLNeg_CLKL);
        // Hold checks
        $hold(posedge CLKL, AL19, thold_AL0_CLKL);
        $hold(posedge CLKL, AL18, thold_AL0_CLKL);
        $hold(posedge CLKL, AL17, thold_AL0_CLKL);
        $hold(posedge CLKL, AL16, thold_AL0_CLKL);
        $hold(posedge CLKL, AL15, thold_AL0_CLKL);
        $hold(posedge CLKL, AL14, thold_AL0_CLKL);
        $hold(posedge CLKL, AL13, thold_AL0_CLKL);
        $hold(posedge CLKL, AL12, thold_AL0_CLKL);
        $hold(posedge CLKL, AL11, thold_AL0_CLKL);
        $hold(posedge CLKL, AL10, thold_AL0_CLKL);
        $hold(posedge CLKL, AL9, thold_AL0_CLKL);
        $hold(posedge CLKL, AL8, thold_AL0_CLKL);
        $hold(posedge CLKL, AL7, thold_AL0_CLKL);
        $hold(posedge CLKL, AL6, thold_AL0_CLKL);
        $hold(posedge CLKL, AL5, thold_AL0_CLKL);
        $hold(posedge CLKL, AL4, thold_AL0_CLKL);
        $hold(posedge CLKL, AL3, thold_AL0_CLKL);
        $hold(posedge CLKL, AL2, thold_AL0_CLKL);
        $hold(posedge CLKL, AL1, thold_AL0_CLKL);
        $hold(posedge CLKL, AL0, thold_AL0_CLKL);

        $hold(posedge CLKR, AR19, thold_AR0_CLKR);
        $hold(posedge CLKR, AR18, thold_AR0_CLKR);
        $hold(posedge CLKR, AR17, thold_AR0_CLKR);
        $hold(posedge CLKR, AR16, thold_AR0_CLKR);
        $hold(posedge CLKR, AR15, thold_AR0_CLKR);
        $hold(posedge CLKR, AR14, thold_AR0_CLKR);
        $hold(posedge CLKR, AR13, thold_AR0_CLKR);
        $hold(posedge CLKR, AR12, thold_AR0_CLKR);
        $hold(posedge CLKR, AR11, thold_AR0_CLKR);
        $hold(posedge CLKR, AR10, thold_AR0_CLKR);
        $hold(posedge CLKR, AR9, thold_AR0_CLKR);
        $hold(posedge CLKR, AR8, thold_AR0_CLKR);
        $hold(posedge CLKR, AR7, thold_AR0_CLKR);
        $hold(posedge CLKR, AR6, thold_AR0_CLKR);
        $hold(posedge CLKR, AR5, thold_AR0_CLKR);
        $hold(posedge CLKR, AR4, thold_AR0_CLKR);
        $hold(posedge CLKR, AR3, thold_AR0_CLKR);
        $hold(posedge CLKR, AR2, thold_AR0_CLKR);
        $hold(posedge CLKR, AR1, thold_AR0_CLKR);
        $hold(posedge CLKR, AR0, thold_AR0_CLKR);

        $hold(posedge CLKL, CE0LNeg, thold_CE0LNeg_CLKL);
        $hold(posedge CLKL, CE1L, thold_CE1L_CLKL);
        $hold(posedge CLKR, CE0RNeg, thold_CE0RNeg_CLKR);
        $hold(posedge CLKR, CE1R, thold_CE1R_CLKR);

        $hold(posedge CLKL, BEL3Neg, thold_BEL0Neg_CLKL);
        $hold(posedge CLKL, BEL2Neg, thold_BEL0Neg_CLKL);
        $hold(posedge CLKL, BEL1Neg, thold_BEL0Neg_CLKL);
        $hold(posedge CLKL, BEL0Neg, thold_BEL0Neg_CLKL);

        $hold(posedge CLKR, BER3Neg, thold_BER0Neg_CLKR);
        $hold(posedge CLKR, BER2Neg, thold_BER0Neg_CLKR);
        $hold(posedge CLKR, BER1Neg, thold_BER0Neg_CLKR);
        $hold(posedge CLKR, BER0Neg, thold_BER0Neg_CLKR);

        $hold(posedge CLKL, RWL, thold_RWL_CLKL);
        $hold(posedge CLKR, RWR, thold_RWR_CLKR);

        $hold(posedge CLKL, IOL35, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL34, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL33, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL32, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL31, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL30, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL29, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL28, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL27, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL26, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL25, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL24, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL23, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL22, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL21, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL20, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL19, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL18, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL17, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL16, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL15, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL14, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL13, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL12, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL11, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL10, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL9, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL8, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL7, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL6, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL5, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL4, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL3, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL2, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL1, thold_IOL0_CLKL);
        $hold(posedge CLKL, IOL0, thold_IOL0_CLKL);

        $hold(posedge CLKR, IOR35, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR34, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR33, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR32, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR31, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR30, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR29, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR28, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR27, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR26, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR25, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR24, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR23, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR22, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR21, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR20, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR19, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR18, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR17, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR16, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR15, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR14, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR13, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR12, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR11, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR10, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR9, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR8, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR7, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR6, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR5, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR4, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR3, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR2, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR1, thold_IOR0_CLKR);
        $hold(posedge CLKR, IOR0, thold_IOR0_CLKR);

        $hold(posedge CLKL,ADSLNeg,thold_ADSLNeg_CLKL);
        $hold(posedge CLKR,ADSRNeg,thold_ADSRNeg_CLKR);

        $hold(posedge CLKL,CNTENLNeg, thold_CNTENLNeg_CLKL);
        $hold(posedge CLKR,CNTENRNeg, thold_CNTENRNeg_CLKR);

        $hold(posedge CLKL, REPEATLNeg, thold_REPEATLNeg_CLKL);
        $hold(posedge CLKR, REPEATRNeg, thold_REPEATRNeg_CLKR);
        // Puls width check
        $width(posedge CLKL &&& pipelineL,tpw_CLKL_pipelineL_EQ_1_posedge);
        $width(negedge CLKL &&& pipelineL, tpw_CLKL_pipelineL_EQ_1_negedge);
        $width(posedge CLKL &&& ~pipelineL, tpw_CLKL_pipelineL_EQ_0_posedge);
        $width(negedge CLKL &&& ~pipelineL, tpw_CLKL_pipelineL_EQ_0_negedge);

        $width(posedge CLKR &&& pipelineR,tpw_CLKR_pipelineR_EQ_1_posedge);
        $width(negedge CLKR &&& pipelineR, tpw_CLKR_pipelineR_EQ_1_negedge);
        $width(posedge CLKR &&& ~pipelineR, tpw_CLKR_pipelineR_EQ_0_posedge);
        $width(negedge CLKR &&& ~pipelineR, tpw_CLKR_pipelineR_EQ_0_negedge);
        // Period check
        $period(posedge CLKL &&& pipelineL,tperiod_CLKL_pipelineL_EQ_1);
        $period(posedge CLKL &&& ~pipelineL,tperiod_CLKL_pipelineL_EQ_0);
        $period(posedge CLKR &&& pipelineR,tperiod_CLKR_pipelineR_EQ_1);
        $period(posedge CLKR &&& ~pipelineR,tperiod_CLKR_pipelineR_EQ_0);
    endspecify

    reg [1:0] sleep_cntL = 2'b00;
    reg [1:0] wake_cntL = 2'b00;
    reg [1:0] no_zz_cntL = 2'b00;
    reg       allowZZL = 1'b1;
    reg [HiAddrBit:0] AddrL, AddrRegL;
    reg               CELPipe;

    always @ (posedge CLKL_ipd)
    begin: LPipeline_p
        reg tmp;
        MemOutLReg <= MemOutL;
        CELPipe <= CELReg;
        BELNegPipe <= BELNegReg;
        // AddrLess counter
        if(~REPEATLNeg_ipd)
          AddrL = AddrRegL;
        else if(~ADSLNeg_ipd)
        begin
            AddrL = AL;
            AddrRegL = AL;
        end
             else if(~CNTENLNeg_ipd)
               AddrL = AddrL + 1;

        if (ZZL_ipd)
        begin
            if (sleep_cntL < 3) begin
                sleep_cntL = sleep_cntL + 1;
                wake_cntL = 0;
            end
            else
              ZZL_int = 1'b1;
        end
        else
        begin
            if(wake_cntL < 3)
            begin
                wake_cntL= wake_cntL + 1;
                sleep_cntL = 2'b00;
            end
            else
            begin
                ZZL_int = 1'b0;
                stateL = read;
            end
        end // else: !if(ZZL_ipd)
        tmp = CE1L_ipd | (~CE1L_ipd & ~CE0LNeg);
        if(~tmp)
        begin
            if(no_zz_cntL < 3)
              begin
                  no_zz_cntL = no_zz_cntL + 1;
                  allowZZL = 1'b0;
              end
            else
              begin
                  allowZZL = 1'b1;
                  no_zz_cntL = 1'b0;
              end
        end // if (~tmp)
        else
        begin
            allowZZL = 1'b0;
            no_zz_cntL = 1'b0;
        end // else: !if(~tmp)

        if (tmp && ~RWL_ipd) begin
            SKEW_In = 1'b1;
            SKEW_In <= #1 1'b0;
            stateL = write;
            if (stateR == write && SKEW1_out)
              stateL = collision;
        end

        case (PLFTL_ipd)
          1'b0: begin
              if ((tmp && ~OELNeg_ipd) && RWL_ipd) begin
                  stateL = read;
                  if((SKEW1_out && (stateR == write)) ||
                     (ZZL_ipd && ~allowZZL))
                    stateL = collision;
              end
          end
          1'b1: begin
              if((CELReg && ~OELNeg_ipd)&& RWL_ipd)
              begin
                  stateL = read;
                  if((SKEW1_out && (stateR == write)) ||
                     (ZZL_ipd && ~allowZZL))
                    stateL = collision;
              end
          end
          default: begin
          end
        endcase // case(PLFTL_ipd)

        MemOutL[8:0] = MemD[AddrL];
        MemOutL[17:9] = MemC[AddrL];
        MemOutL[26:18] = MemB[AddrL];
        MemOutL[35:27] = MemA[AddrL];
        if(~ZZL_ipd)
        begin
            if((MemA[AddrL] == -1) || (stateL == collision))
              MemOutL[35:27] = 9'bx;
            else
              MemOutL[35:27] = MemA[AddrL];
            if((MemB[AddrL] == -1) || (stateL == collision))
              MemOutL[26:18] = 9'bx;
            else
              MemOutL[26:18] = MemB[AddrL];
            if((MemC[AddrL] == -1) || (stateL == collision))
              MemOutL[17:9] = 9'bx;
            else
              MemOutL[17:9] = MemC[AddrL];
            if((MemD[AddrL] == -1) || (stateL == collision))
              MemOutL[8:0] = 9'bx;
            else
              MemOutL[8:0] = MemD[AddrL];
        end // if ((AddrL != 20'hFFFFE) && ~ZZL_ipd)
        else
          MemOutL = 'bz;

        CELReg = tmp;
        RWLReg = RWL_ipd;
        // Internal pipeline registers
        BELNegReg = BELNeg;
        // BE selection for write
        MemBEL[0] = ~BELNeg[0] & ~RWL_ipd & tmp;
        MemBEL[1] = ~BELNeg[1] & ~RWL_ipd & tmp;
        MemBEL[2] = ~BELNeg[2] & ~RWL_ipd & tmp;
        MemBEL[3] = ~BELNeg[3] & ~RWL_ipd & tmp;
        // Memory write
        if(MemBEL[0])
        begin
            if(stateL == collision)
              MemD[AddrL] = -1;
            else
              MemD[AddrL] = DInL[8:0];
        end
        if(MemBEL[1])
        begin
            if(stateL == collision)
              MemC[AddrL] = -1;
            else
              MemC[AddrL] = DInL[17:9];
        end
        if(MemBEL[2])
        begin
            if(stateL == collision)
              MemB[AddrL] = -1;
            else
              MemB[AddrL] = DInL[26:18];
        end
        if(MemBEL[3])
        begin
            if(stateL == collision)
              MemA[AddrL] = -1;
            else
              MemA[AddrL] = DInL[35:27];
        end

        // Interrupt flag set...
        if(CE1L_ipd && ~CE0LNeg)
        begin
            if((AddrL == 20'hFFFFF) && ~RWL_ipd)
              INTRNeg_zd = 1'b0;
            if ((AddrL == 20'hFFFFE) && RWL_ipd)
              INTLNeg_zd = 1'b1;
        end
    end

    reg CELMux;
    // CEL Multiplexer
    always @(PLFTL_ipd, CELReg, CELPipe)
    begin
        case (PLFTL_ipd)
          1'b0: begin
              CELMux = CELReg;
          end
          1'b1: begin
              CELMux = CELPipe;
          end
          default: begin
              CELMux = 1'bz;
          end
        endcase // case(PLFTL_ipd)
    end // always @ (PLFTL_ipd, CELReg, CELPipe)

    reg [3:0] BELMux;
    always @(PLFTL_ipd, BELNegReg, BELNegPipe)
    begin
        case (PLFTL_ipd)
          1'b0: begin
              BELMux = BELNegReg;
          end
          1'b1: begin
              BELMux = BELNegPipe;
          end
          default: begin
              BELMux = 'bz;
          end
        endcase // case(PLFTL_ipd)
    end // always @ (PLFTL_ipd, BELNegReg, BELNegPipe)

    // Memory output multiplexer
    always @(PLFTL_ipd, MemOutL, MemOutLReg)
    begin
        case (PLFTL_ipd)
          1'b0: begin
              OutMuxL = MemOutL;
          end
          1'b1: begin
              OutMuxL = MemOutLReg;
          end
          default: begin
              OutMuxL = 'hz;
          end
        endcase // case(PLFTL_ipd)
    end // always @ (PLFTL_ipd, MemOutL, MemOutLReg)

    // Selection signals for output buffer
    assign DoutLSel[0] = ~OELNeg_ipd & CELMux & ~BELMux[0] & RWLReg;
    assign DoutLSel[1] = ~OELNeg_ipd & CELMux & ~BELMux[1] & RWLReg;
    assign DoutLSel[2] = ~OELNeg_ipd & CELMux & ~BELMux[2] & RWLReg;
    assign DoutLSel[3] = ~OELNeg_ipd & CELMux & ~BELMux[3] & RWLReg;

    // Left Output BUFFER
    always @(DoutLSel, OutMuxL)
    begin
        // Output zero delayed
        DOutL_zd = 'bz;
        if(DoutLSel[0])
          DOutL_zd[8:0] = OutMuxL[8:0];
        if(DoutLSel[1])
          DOutL_zd[17:9] = OutMuxL[17:9];
        if(DoutLSel[2])
          DOutL_zd[26:18] = OutMuxL[26:18];
        if(DoutLSel[3])
          DOutL_zd[35:17] = OutMuxL[35:17];
    end // always @ (DoutLSel, OutMuxL)

    reg [1:0] sleep_cntR = 2'b00;
    reg [1:0] wake_cntR = 2'b00;
    reg [1:0] no_zz_cntR = 2'b00;
    reg       allowZZR = 1'b1;
    reg [HiAddrBit:0] AddrR, AddrRegR;
    reg               CERPipe;

    always @ (posedge CLKR_ipd)
    begin: RPipeline_p
        reg tmp;
        CERPipe <= CERReg;
        MemOutRReg <= MemOutR;
        BERNegPipe <= BERNegReg;
        // Address counter
        if(~REPEATRNeg_ipd)
          AddrR = AddrRegR;
        else if(~ADSRNeg_ipd)
        begin
            AddrR = AR;
            AddrRegR = AR;
        end
             else if(~CNTENRNeg_ipd)
               AddrR = AddrR + 1;

        if (ZZR_ipd)
        begin
            if (sleep_cntR < 3) begin
                sleep_cntR = sleep_cntR + 1;
                wake_cntR = 0;
            end
            else
              ZZR_int = 1'b1;
        end
        else
        begin
            if(wake_cntR < 3)
            begin
                wake_cntR= wake_cntR + 1;
                sleep_cntR = 2'b00;
            end
            else
            begin
                ZZL_int = 1'b0;
                stateR = read;
            end
        end // else: !if(ZZL_ipd)

        tmp = CE1R_ipd | (~CE1R_ipd & ~CE0RNeg);
        if(~tmp)
        begin
            if(no_zz_cntR < 3)
              begin
                  no_zz_cntR = no_zz_cntR + 1;
                  allowZZR = 1'b0;
              end
            else
              begin
                  allowZZR = 1'b1;
                  no_zz_cntR = 1'b0;
              end
        end // if (~tmp)
        else
        begin
            allowZZR = 1'b0;
            no_zz_cntR = 1'b0;
        end // else: !if(~tmp)

        if (tmp && ~RWR_ipd) begin
            SKEW1_In = 1'b1;
            SKEW1_In <= #1 1'b0;
            stateR = write;
            if (stateL == write && SKEW_out)
              stateR = collision;
        end

        case (PLFTR_ipd)
          1'b0: begin
              if ((tmp && ~OERNeg_ipd) && RWR_ipd) begin
                  stateR = read;
                  if((SKEW_out && (stateL == write)) ||
                     (ZZR_ipd && ~allowZZR))
                    stateR = collision;
              end
          end
          1'b1: begin
              if((CERReg && ~OERNeg_ipd)&& RWR_ipd)
              begin
                  stateR = read;
                  if((SKEW_out && (stateL == write)) ||
                     (ZZR_ipd && ~allowZZR))
                    stateR = collision;
              end
          end
          default: begin
          end
        endcase // case(PLFTL_ipd)

        MemOutR[8:0] = MemD[AddrR];
        MemOutR[17:9] = MemC[AddrR];
        MemOutR[26:18] = MemB[AddrR];
        MemOutR[35:27] = MemA[AddrR];
        if(~ZZR_ipd)
        begin
            if((MemA[AddrR] == -1) || (stateR == collision))
              MemOutR[35:27] = 9'bx;
            else
              MemOutR[35:27] = MemA[AddrR];
            if((MemB[AddrR] == -1) || (stateR == collision))
              MemOutR[26:18] = 9'bx;
            else
              MemOutR[26:18] = MemB[AddrR];
            if((MemC[AddrR] == -1) || (stateR == collision))
              MemOutR[17:9] = 9'bx;
            else
              MemOutR[17:9] = MemC[AddrR];
            if((MemD[AddrR] == -1) || (stateR == collision))
              MemOutR[8:0] = 9'bx;
            else
              MemOutR[8:0] = MemD[AddrR];
        end // if ((AddrR != 20'hFFFFE) && ~ZZL_ipd)
        else
          MemOutR = 'bz;

        CERReg = tmp;
        RWRReg = RWR_ipd;
        // Internal pipeline registers
        BERNegReg = BERNeg;
        // BE selection for write
        MemBER[0] = ~BERNeg[0] & ~RWR_ipd & tmp;
        MemBER[1] = ~BERNeg[1] & ~RWR_ipd & tmp;
        MemBER[2] = ~BERNeg[2] & ~RWR_ipd & tmp;
        MemBER[3] = ~BERNeg[3] & ~RWR_ipd & tmp;
        // Memory write
        if(MemBER[0])
        begin
            if(stateR == collision)
              MemD[AddrR] = -1;
            else
              MemD[AddrR] = DInR[8:0];
        end
        if(MemBER[1])
        begin
            if(stateR == collision)
              MemC[AddrR] = -1;
            else
              MemC[AddrR] = DInR[17:9];
        end
        if(MemBER[2])
        begin
            if(stateR == collision)
              MemB[AddrR] = -1;
            else
              MemB[AddrR] = DInR[26:18];
        end
        if(MemBER[3])
        begin
            if(stateR == collision)
              MemA[AddrR] = -1;
            else
              MemA[AddrR] = DInR[35:27];
        end

        // Interrupt flag set...
        if(CE1R_ipd && ~CE0RNeg)
        begin
            if((AddrR == 20'hFFFFE) && ~RWR_ipd)
              INTLNeg_zd = 1'b0;
            if ((AddrR == 20'hFFFFF) && RWR_ipd)
              INTRNeg_zd = 1'b1;
        end
    end // block: RPipeline_p

    reg CERMux;
    // CER Multiplexer
    always @(PLFTR_ipd, CERReg, CERPipe)
    begin
        case (PLFTR_ipd)
          1'b0: begin
              CERMux = CERReg;
          end
          1'b1: begin
              CERMux = CERPipe;
          end
          default: begin
              CERMux = 1'bz;
          end
        endcase // case(PLFTL_ipd)
    end // always @ (PLFTR_ipd, CERReg, CERPipe)

    reg [3:0] BERMux;
    always @(PLFTR_ipd, BERNegReg, BERNegPipe)
    begin
        case (PLFTR_ipd)
          1'b0: begin
              BERMux = BERNegReg;
          end
          1'b1: begin
              BERMux = BERNegPipe;
          end
          default: begin
              BERMux = 3'bz;
          end
        endcase // case(PLFTR_ipd)
    end // always @ (PLFTR_ipd, BERNegReg, BERNegPipe)

    // Memory output multiplexer
    always @(PLFTR_ipd, MemOutR, MemOutRReg)
    begin
        case (PLFTR_ipd)
          1'b1: begin
              OutMuxR = MemOutRReg;
          end
          1'b0: begin
              OutMuxR = MemOutR;
          end
          default: begin
              OutMuxR = 'hz;
          end
        endcase // case(PLFTR_ipd)
    end // always @ (PLFTR_ipd, MemOutR, MemOutRReg)

    // Selection signals for output buffer
    assign DoutRSel[0] = ~OERNeg_ipd & CERMux & ~BERMux[0] & RWRReg;
    assign DoutRSel[1] = ~OERNeg_ipd & CERMux & ~BERMux[1] & RWRReg;
    assign DoutRSel[2] = ~OERNeg_ipd & CERMux & ~BERMux[2] & RWRReg;
    assign DoutRSel[3] = ~OERNeg_ipd & CERMux & ~BERMux[3] & RWRReg;

    // Right Output BUFFER
    always @(DoutRSel, OutMuxR)
    begin
        // Output zero delayed
        DOutR_zd = 'bz;
        if(DoutRSel[0])
          DOutR_zd[8:0] = OutMuxR[8:0];
        if(DoutRSel[1])
          DOutR_zd[17:9] = OutMuxR[17:9];
        if(DoutRSel[2])
          DOutR_zd[26:18] = OutMuxR[26:18];
        if(DoutRSel[3])
          DOutR_zd[35:27] = OutMuxR[35:27];
    end // always @ (DoutRSel, OutMuxR)

    // Memory preload block
    initial
      begin: file_preload_block
          ////////////////////////////////////////////////////////////////////
          // idt70t3509m memory preload file
          // /                - comment must begin with this character
          // @aaaaa           - <aaaaa> stands for 20 bit address
          // ddd ddd ddd ddd  - <ddd> stands for 9 bit hex represation of data
          //                    First <ddd> goes on highest 9 bits of memory..
          // <aaaaa> is incremented on every data row load
          ////////////////////////////////////////////////////////////////////
          integer file_handle;
          // Character is 32 bit because it can be EOF...
          integer ch, r;
          // Temporally variables for storing data
          reg [8:0] dp0, dp1, dp2, dp3;
          // Temporal variable for address storing
          reg [HiAddrBit+1:0] address;
          // Line
          reg [8*80 - 1:0]  line;
          // Loop variable
          integer           i;

          for(i = 0;i<MemSize;i=i+1)
            begin
                MemA[i]=-2;
                MemB[i]=-2;
                MemC[i]=-2;
                MemD[i]=-2;
            end

          if (UserPreload && !(mem_file_name == "none")) begin
              file_handle = $fopen(mem_file_name,"r");
              if(file_handle == `NULL)
                begin
                    $display("There is no such file: ", mem_file_name);
                    disable file_preload_block;
                end
              ch = $fgetc(file_handle);
              while (ch != `EOF)
                begin : looping
                    if(ch == "/")
                      r = $fgets(line,file_handle);
                    else if(ch == "@")
                      begin
                          r= $fscanf(file_handle,"%20h\n",address);
                      end
                         else
                         begin
                             if(~address[HiAddrBit+1])
                             begin
                                 r = $ungetc(ch,file_handle);
                                 r = $fscanf(file_handle,"%9h %9h %9h %9h\n",
                                             dp3,dp2,dp1,dp0);
                                 if(r != 4)
                                 begin
                                     $display("Wrong num of data inputs",
                                              "\n must be 4");
                                     disable looping;
                                 end
                                 MemA[address] = dp3;
                                 MemB[address] = dp2;
                                 MemC[address] = dp1;
                                 MemD[address] = dp0;
                                 address=address+1;
                             end // if (~address[HiAddrBit+1])
                             else
                               $display("Memory address out of range");
                           end
                    ch = $fgetc(file_handle);
                end // block: looping
              $fclose(file_handle);
              $display("NOTE: Finished preload proces\n");
          end // if (UserPreload && !(mem_file_name == "none"))
      end // block: file_preload_block
    always @(posedge SKEW_In)
    begin: skew_start_p
        SKEW_out = SKEW_In;
        #tdevice_SKEW SKEW_out = 1'b0;
    end

    always @(posedge SKEW1_In)
    begin: skew1_start_p
        SKEW1_out = SKEW1_In;
        #tdevice_SKEW SKEW1_out = 1'b0;
    end

    BUFFER SKEW(SKEW2_out, SKEW2_In);
    BUFFER SKEW1(SKEW3_out, SKEW3_In);
endmodule // idt70t3509m
module BUFFER (OUT,IN);
    input IN;
    output OUT;
    buf   ( OUT, IN);
endmodule