////////////////////////////////////////////////////////////////////////////// // File name : hyb18t1g160af_120.v ////////////////////////////////////////////////////////////////////////////// // Developed by HDL-Design House, www.hdl-dh.com // Copyright (C) 2006 Free Model Foundry; http://www.freemodelfoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY: // // version: | author: | mod date: | changes made: // V1.0 S.Stojanovic 06 Feb 21 Initial release // ////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // // Library: RAM // Technology: CMOS // Part: hyb18t1g160af_120 // // Description: 1-Gbit DDR2 SDRAM ////////////////////////////////////////////////////////////////////////////// // NOTES : // // Simulator resolution : 1 ps ////////////////////////////////////////////////////////////////////////////// // ////////////////////////////////////////////////////////////////////////////// // Known Bugs: // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1ps module hyb18t1g160af_120 ( CK , CKNeg , CKE , RASNeg , CASNeg , WENeg , CSNeg , BA0 , BA1 , BA2 , A0 , A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 , A9 , A10 , A11 , A12 , DQ0 , DQ1 , DQ2 , DQ3 , DQ4 , DQ5 , DQ6 , DQ7 , DQ8 , DQ9 , DQ10 , DQ11 , DQ12 , DQ13 , DQ14 , DQ15 , UDQS , UDQSNeg , LDQS , LDQSNeg , UDM , LDM ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input CK ; input CKNeg ; input CKE ; input RASNeg ; input CASNeg ; input WENeg ; input CSNeg ; input BA0 ; input BA1 ; input BA2 ; input A0 ; input A1 ; input A2 ; input A3 ; input A4 ; input A5 ; input A6 ; input A7 ; input A8 ; input A9 ; input A10 ; input A11 ; input A12 ; inout DQ0 ; inout DQ1 ; inout DQ2 ; inout DQ3 ; inout DQ4 ; inout DQ5 ; inout DQ6 ; inout DQ7 ; inout DQ8 ; inout DQ9 ; inout DQ10 ; inout DQ11 ; inout DQ12 ; inout DQ13 ; inout DQ14 ; inout DQ15 ; inout UDQS ; inout UDQSNeg ; inout LDQS ; inout LDQSNeg ; input UDM ; input LDM ; // interconnect path delay signals wire CK_ipd ; wire CKNeg_ipd ; wire CKE_ipd ; wire RASNeg_ipd ; wire CASNeg_ipd ; wire WENeg_ipd ; wire CSNeg_ipd ; wire BA0_ipd ; wire BA1_ipd ; wire BA2_ipd ; wire A0_ipd ; wire A1_ipd ; wire A2_ipd ; wire A3_ipd ; wire A4_ipd ; wire A5_ipd ; wire A6_ipd ; wire A7_ipd ; wire A8_ipd ; wire A9_ipd ; wire A10_ipd ; wire A11_ipd ; wire A12_ipd ; wire DQ0_ipd ; wire DQ1_ipd ; wire DQ2_ipd ; wire DQ3_ipd ; wire DQ4_ipd ; wire DQ5_ipd ; wire DQ6_ipd ; wire DQ7_ipd ; wire DQ8_ipd ; wire DQ9_ipd ; wire DQ10_ipd ; wire DQ11_ipd ; wire DQ12_ipd ; wire DQ13_ipd ; wire DQ14_ipd ; wire DQ15_ipd ; wire UDQS_ipd ; wire UDQSNeg_ipd ; wire LDQS_ipd ; wire LDQSNeg_ipd ; wire UDM_ipd ; wire LDM_ipd ; wire CKIn; assign CKIn = CK_ipd; wire CKNegIn; assign CKNegIn = CKNeg_ipd; wire CKEIn; assign CKEIn = CKE_ipd; wire RASNegIn; assign RASNegIn = RASNeg_ipd; wire CASNegIn; assign CASNegIn = CASNeg_ipd; wire WENegIn; assign WENegIn = WENeg_ipd; wire CSNegIn; assign CSNegIn = CSNeg_ipd; wire [12 : 0] AIn; assign AIn = {A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire [2 : 0] BAIn; assign BAIn = {BA2_ipd, BA1_ipd, BA0_ipd }; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire UDQSIn; assign UDQSIn = UDQS_ipd; wire UDQSNegIn; assign UDQSNegIn = UDQSNeg_ipd; wire LDQSIn; assign LDQSIn = LDQS_ipd; wire LDQSNegIn; assign LDQSNegIn = LDQSNeg_ipd; wire UDMIn; assign UDMIn = UDM_ipd; wire LDMIn; assign LDMIn = LDM_ipd; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire UDQSOut; assign UDQS = UDQSOut; wire UDQSNegOut; assign UDQSNeg = UDQSNegOut; wire LDQSOut; assign LDQS = LDQSOut; wire LDQSNegOut; assign LDQSNeg = LDQSNegOut; // internal delays wire DOut15_zd; wire DOut14_zd; wire DOut13_zd; wire DOut12_zd; wire DOut11_zd; wire DOut10_zd; wire DOut9_zd; wire DOut8_zd; wire DOut7_zd; wire DOut6_zd; wire DOut5_zd; wire DOut4_zd; wire DOut3_zd; wire DOut2_zd; wire DOut1_zd; wire DOut0_zd; reg [15 : 0] DOut_zd; assign { DOut15_zd, DOut14_zd, DOut13_zd, DOut12_zd, DOut11_zd, DOut10_zd, DOut9_zd, DOut8_zd, DOut7_zd, DOut6_zd, DOut5_zd, DOut4_zd, DOut3_zd, DOut2_zd, DOut1_zd, DOut0_zd } = DOut_zd; reg [15 : 0] DataOut_temp; reg UDQSOut_zd; reg UDQSNegOut_zd; reg LDQSOut_zd; reg LDQSNegOut_zd; parameter UserPreload = 1'b1; parameter mem_file_name = "hyb18t1g160af_120.mem"; parameter prot_file_name = "none"; parameter TimingModel = "DefaultTimingModel"; parameter partID = "hyb18t1g160af_120"; parameter HiBankBit = 2; parameter HiAddrBit = 12; parameter HiRowBit = 12; parameter HiColBit = 9; parameter HiDataBit = 15; parameter MaxBank = 8; parameter MaxRow = 8192; parameter MaxColumn = 1024; parameter MaxData = 65535; parameter NoneBank = 8; parameter FALSE = 1'b0; parameter TRUE = 1'b1; //global signals : // actual clock frequency time t_CK; reg PoweredUp = FALSE; // timing check violation reg Viol = 1'b0; reg CKEPrev; reg CKENew; reg command_changed; reg new_rw [(MaxBank-1):0]; reg rc_in [(MaxBank-1):0]; reg rc_out [(MaxBank-1):0]; reg rcd_in [(MaxBank-1):0]; reg rcd_out[(MaxBank-1):0]; reg ras_in [(MaxBank-1):0]; reg ras_out[(MaxBank-1):0]; reg rp_in [(MaxBank-1):0]; reg rp_out [(MaxBank-1):0]; reg rtp_in [(MaxBank-1):0]; reg rtp_out[(MaxBank-1):0]; reg refi_in ; reg refi_out; reg rfc_in ; reg rfc_out ; reg rrd_in ; reg rrd_out ; reg wr_in ; reg wr_out ; reg wtr_in ; reg wtr_out ; reg xsnr_in ; reg xsnr_out; // TYPES, SIGNALS AND VARIABLES FROM MAIN BEHAVIOR BLOCK : // MRS : // Burst length integer BL;// : INTEGER RANGE 0 TO 8;-- burst_length // Burst type reg BT;// : burst_addr_seq_type; // CAS latency integer CL;// : INTEGER RANGE 0 TO 7;-- number of CKIn cycles // Test mode reg TM;// : std_logic; // Dll reset reg DLLreset;// : std_logic; // write recovery (for write with auto precharge) integer WR;// : INTEGER RANGE 0 TO 7; -- number of CKIn cycles // power down mode reg PD;// : power_down_mode_type; // EMRS(1) : // Dll enable reg DLLenable;// : std_logic; // Odd-chip driver impedance control reg DIC;// : std_logic; // additive latency integer AL;// : INTEGER RANGE 0 TO 4;-- number of CKIn cycles // disables DQSNeg signal (0-differential , 1-single) reg DQSNegDis;// : BOOLEAN; // disables output (1-outputs HiZ, 0-regular outputs) reg QoffHIz;// : std_logic; // EMRS(2) : future use // EMRS(3) : future use integer RL;// :INTEGER RANGE 0 TO 10 := 0;-- number of CKIn cycles integer WL;// :INTEGER RANGE 0 TO 9 := 0;-- number of CKIn cycles reg [3:0] command; reg [8*17:0] command_string; // Commands parameter nop =4'd0; parameter deselect =4'd1; parameter mrs =4'd2; parameter autoref =4'd3; parameter bankact =4'd4; parameter presingle =4'd5; parameter preall =4'd6; parameter write =4'd7; parameter writeapre =4'd8; parameter read =4'd9; parameter readapre =4'd10; parameter selfrefentry =4'd11; parameter pwrdwnentry =4'd12; parameter selfrefpwrdwnexit =4'd13; parameter unknown_c =4'd14; // FSM states (for state machine) parameter init_state =4'd0; parameter idle_state =4'd1; parameter mrs_set_state =4'd2; parameter self_refresh_state =4'd3; parameter auto_refresh_state =4'd4; parameter pwrdown_precharge_state =4'd5; parameter pwrdown_active_state =4'd6; parameter activating_state =4'd7; parameter bank_active_state =4'd8; parameter write_state =4'd9; parameter write_auto_precharge_state =4'd10; parameter read_state =4'd11; parameter read_auto_precharge_state =4'd12; parameter precharge_state =4'd13; //burst sequence type parameter sequential = 1'b0; parameter interleaved = 1'b1; //power down mode type parameter standard = 1'b0; parameter lowpower = 1'b1; reg [3:0] current_state [(MaxBank-1):0]; reg [3:0] next_state [(MaxBank-1):0]; reg command_update = 1'b0; reg mrs_finished [(MaxBank-1):0]; reg aref_finished [(MaxBank-1):0]; reg write_finished [(MaxBank-1):0]; reg read_finished [(MaxBank-1):0]; reg wap_finished [(MaxBank-1):0]; reg rap_finished [(MaxBank-1):0]; reg prech_finished [(MaxBank-1):0]; integer current_row [(MaxBank-1):0]; integer current_column; integer current_bank; integer columnFIFObuffer [7:0]; integer in_index = 0; integer out_index = 0; wire read_dqs_enabled_g; wire read_data_enabled_g; wire write_data_enabled_g; reg read_finished_interrupted; wire w_burst_n_interrupted_g; wire r_burst_n_interrupted_g; integer burst_index; integer burst_offset; reg read_dqs_enabled_0 [(MaxBank-1) : 0]; reg read_data_enabled_0 [(MaxBank-1) : 0]; reg read_dqs_enabled_1 [(MaxBank-1) : 0]; reg read_data_enabled_1 [(MaxBank-1) : 0]; reg read_dqs_enabled_2 [(MaxBank-1) : 0]; reg read_data_enabled_2 [(MaxBank-1) : 0]; reg read_dqs_enabled_3 [(MaxBank-1) : 0]; reg read_data_enabled_3 [(MaxBank-1) : 0]; reg read_dqs_enabled_4 [(MaxBank-1) : 0]; reg read_data_enabled_4 [(MaxBank-1) : 0]; reg read_dqs_enabled_5 [(MaxBank-1) : 0]; reg read_data_enabled_5 [(MaxBank-1) : 0]; reg read_dqs_enabled_6 [(MaxBank-1) : 0]; reg read_data_enabled_6 [(MaxBank-1) : 0]; reg read_dqs_enabled_7 [(MaxBank-1) : 0]; reg read_data_enabled_7 [(MaxBank-1) : 0]; reg write_data_enabled_0 [(MaxBank-1) : 0]; reg write_data_enabled_1 [(MaxBank-1) : 0]; reg write_data_enabled_2 [(MaxBank-1) : 0]; reg write_data_enabled_3 [(MaxBank-1) : 0]; reg write_data_enabled_4 [(MaxBank-1) : 0]; reg write_data_enabled_5 [(MaxBank-1) : 0]; reg write_data_enabled_6 [(MaxBank-1) : 0]; reg write_data_enabled_7 [(MaxBank-1) : 0]; reg w_burst_n_interrupted_0[(MaxBank-1) : 0]; reg r_burst_n_interrupted_0[(MaxBank-1) : 0]; assign read_dqs_enabled_g = read_dqs_enabled_0[0] || read_dqs_enabled_0[1] || read_dqs_enabled_0[2] || read_dqs_enabled_0[3] || read_dqs_enabled_0[4] || read_dqs_enabled_0[5] || read_dqs_enabled_0[6] || read_dqs_enabled_0[7] || read_dqs_enabled_1[0] || read_dqs_enabled_1[1] || read_dqs_enabled_1[2] || read_dqs_enabled_1[3] || read_dqs_enabled_1[4] || read_dqs_enabled_1[5] || read_dqs_enabled_1[6] || read_dqs_enabled_1[7] || read_dqs_enabled_2[0] || read_dqs_enabled_2[1] || read_dqs_enabled_2[2] || read_dqs_enabled_2[3] || read_dqs_enabled_2[4] || read_dqs_enabled_2[5] || read_dqs_enabled_2[6] || read_dqs_enabled_2[7] || read_dqs_enabled_3[0] || read_dqs_enabled_3[1] || read_dqs_enabled_3[2] || read_dqs_enabled_3[3] || read_dqs_enabled_3[4] || read_dqs_enabled_3[5] || read_dqs_enabled_3[6] || read_dqs_enabled_3[7] || read_dqs_enabled_4[0] || read_dqs_enabled_4[1] || read_dqs_enabled_4[2] || read_dqs_enabled_4[3] || read_dqs_enabled_4[4] || read_dqs_enabled_4[5] || read_dqs_enabled_4[6] || read_dqs_enabled_4[7] || read_dqs_enabled_5[0] || read_dqs_enabled_5[1] || read_dqs_enabled_5[2] || read_dqs_enabled_5[3] || read_dqs_enabled_5[4] || read_dqs_enabled_5[5] || read_dqs_enabled_5[6] || read_dqs_enabled_5[7] || read_dqs_enabled_6[0] || read_dqs_enabled_6[1] || read_dqs_enabled_6[2] || read_dqs_enabled_6[3] || read_dqs_enabled_6[4] || read_dqs_enabled_6[5] || read_dqs_enabled_6[6] || read_dqs_enabled_6[7] || read_dqs_enabled_7[0] || read_dqs_enabled_7[1] || read_dqs_enabled_7[2] || read_dqs_enabled_7[3] || read_dqs_enabled_7[4] || read_dqs_enabled_7[5] || read_dqs_enabled_7[6] || read_dqs_enabled_7[7]; assign read_data_enabled_g =(read_data_enabled_0[0] || read_data_enabled_0[1] || read_data_enabled_0[2] || read_data_enabled_0[3] || read_data_enabled_0[4] || read_data_enabled_0[5] || read_data_enabled_0[6] || read_data_enabled_0[7] || read_data_enabled_1[0] || read_data_enabled_1[1] || read_data_enabled_1[2] || read_data_enabled_1[3] || read_data_enabled_1[4] || read_data_enabled_1[5] || read_data_enabled_1[6] || read_data_enabled_1[7] || read_data_enabled_2[0] || read_data_enabled_2[1] || read_data_enabled_2[2] || read_data_enabled_2[3] || read_data_enabled_2[4] || read_data_enabled_2[5] || read_data_enabled_2[6] || read_data_enabled_2[7] || read_data_enabled_3[0] || read_data_enabled_3[1] || read_data_enabled_3[2] || read_data_enabled_3[3] || read_data_enabled_3[4] || read_data_enabled_3[5] || read_data_enabled_3[6] || read_data_enabled_3[7] || read_data_enabled_4[0] || read_data_enabled_4[1] || read_data_enabled_4[2] || read_data_enabled_4[3] || read_data_enabled_4[4] || read_data_enabled_4[5] || read_data_enabled_4[6] || read_data_enabled_4[7] || read_data_enabled_5[0] || read_data_enabled_5[1] || read_data_enabled_5[2] || read_data_enabled_5[3] || read_data_enabled_5[4] || read_data_enabled_5[5] || read_data_enabled_5[6] || read_data_enabled_5[7] || read_data_enabled_6[0] || read_data_enabled_6[1] || read_data_enabled_6[2] || read_data_enabled_6[3] || read_data_enabled_6[4] || read_data_enabled_6[5] || read_data_enabled_6[6] || read_data_enabled_6[7] || read_data_enabled_7[0] || read_data_enabled_7[1] || read_data_enabled_7[2] || read_data_enabled_7[3] || read_data_enabled_7[4] || read_data_enabled_7[5] || read_data_enabled_7[6] || read_data_enabled_7[7]) && r_burst_n_interrupted_g; assign write_data_enabled_g=(write_data_enabled_0[0] || write_data_enabled_0[1] || write_data_enabled_0[2] || write_data_enabled_0[3] || write_data_enabled_0[4] || write_data_enabled_0[5] || write_data_enabled_0[6] || write_data_enabled_0[7] || write_data_enabled_1[0] || write_data_enabled_1[1] || write_data_enabled_1[2] || write_data_enabled_1[3] || write_data_enabled_1[4] || write_data_enabled_1[5] || write_data_enabled_1[6] || write_data_enabled_1[7] || write_data_enabled_2[0] || write_data_enabled_2[1] || write_data_enabled_2[2] || write_data_enabled_2[3] || write_data_enabled_2[4] || write_data_enabled_2[5] || write_data_enabled_2[6] || write_data_enabled_2[7] || write_data_enabled_3[0] || write_data_enabled_3[1] || write_data_enabled_3[2] || write_data_enabled_3[3] || write_data_enabled_3[4] || write_data_enabled_3[5] || write_data_enabled_3[6] || write_data_enabled_3[7] || write_data_enabled_4[0] || write_data_enabled_4[1] || write_data_enabled_4[2] || write_data_enabled_4[3] || write_data_enabled_4[4] || write_data_enabled_4[5] || write_data_enabled_4[6] || write_data_enabled_4[7] || write_data_enabled_5[0] || write_data_enabled_5[1] || write_data_enabled_5[2] || write_data_enabled_5[3] || write_data_enabled_5[4] || write_data_enabled_5[5] || write_data_enabled_5[6] || write_data_enabled_5[7] || write_data_enabled_6[0] || write_data_enabled_6[1] || write_data_enabled_6[2] || write_data_enabled_6[3] || write_data_enabled_6[4] || write_data_enabled_6[5] || write_data_enabled_6[6] || write_data_enabled_6[7] || write_data_enabled_7[0] || write_data_enabled_7[1] || write_data_enabled_7[2] || write_data_enabled_7[3] || write_data_enabled_7[4] || write_data_enabled_7[5] || write_data_enabled_7[6] || write_data_enabled_7[7]) && w_burst_n_interrupted_g; assign r_burst_n_interrupted_g=r_burst_n_interrupted_0[0] && r_burst_n_interrupted_0[1] && r_burst_n_interrupted_0[2] && r_burst_n_interrupted_0[3] && r_burst_n_interrupted_0[4] && r_burst_n_interrupted_0[5] && r_burst_n_interrupted_0[6] && r_burst_n_interrupted_0[7]; assign w_burst_n_interrupted_g=w_burst_n_interrupted_0[0] && w_burst_n_interrupted_0[1] && w_burst_n_interrupted_0[2] && w_burst_n_interrupted_0[3] && w_burst_n_interrupted_0[4] && w_burst_n_interrupted_0[5] && w_burst_n_interrupted_0[6] && w_burst_n_interrupted_0[7]; integer burst_sequence [0:7]; task sa_4; input integer b_index; begin case (b_index) 0 : begin burst_sequence[0]= 4; burst_sequence[1]= 5; burst_sequence[2]= 6; burst_sequence[3]= 7; end 1 : begin burst_sequence[0]= 4; burst_sequence[1]= 5; burst_sequence[2]= 6; burst_sequence[3]= 3; end 2 : begin burst_sequence[0]= 4; burst_sequence[1]= 5; burst_sequence[2]= 2; burst_sequence[3]= 3; end default : begin burst_sequence[0]= 4; burst_sequence[1]= 1; burst_sequence[2]= 2; burst_sequence[3]= 3; end endcase end endtask task ia_4; input integer b_index; begin case (b_index) 0 : begin burst_sequence[0]= 4; burst_sequence[1]= 5; burst_sequence[2]= 6; burst_sequence[3]= 7; end 1 : begin burst_sequence[0]= 4; burst_sequence[1]= 3; burst_sequence[2]= 6; burst_sequence[3]= 5; end 2 : begin burst_sequence[0]= 4; burst_sequence[1]= 5; burst_sequence[2]= 2; burst_sequence[3]= 3; end default : begin burst_sequence[0]= 4; burst_sequence[1]= 3; burst_sequence[2]= 2; burst_sequence[3]= 1; end endcase end endtask task sa_8; input integer b_index; begin case (b_index) 0 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 11; burst_sequence[4]= 12; burst_sequence[5]= 13; burst_sequence[6]= 14; burst_sequence[7]= 15; end 1 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 7; burst_sequence[4]= 12; burst_sequence[5]= 13; burst_sequence[6]= 14; burst_sequence[7]= 11; end 2 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 12; burst_sequence[5]= 13; burst_sequence[6]= 10; burst_sequence[7]= 11; end 3 : begin burst_sequence[0]= 8; burst_sequence[1]= 5; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 12; burst_sequence[5]= 9; burst_sequence[6]= 10; burst_sequence[7]= 11; end 4 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 11; burst_sequence[4]= 4; burst_sequence[5]= 5; burst_sequence[6]= 6; burst_sequence[7]= 7; end 5 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 7; burst_sequence[4]= 4; burst_sequence[5]= 5; burst_sequence[6]= 6; burst_sequence[7]= 3; end 6 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 4; burst_sequence[5]= 5; burst_sequence[6]= 2; burst_sequence[7]= 3; end default : begin burst_sequence[0]= 8; burst_sequence[1]= 5; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 4; burst_sequence[5]= 1; burst_sequence[6]= 2; burst_sequence[7]= 3; end endcase end endtask task ia_8; input integer b_index; begin case (b_index) 0 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 11; burst_sequence[4]= 12; burst_sequence[5]= 13; burst_sequence[6]= 14; burst_sequence[7]= 15; end 1 : begin burst_sequence[0]= 8; burst_sequence[1]= 7; burst_sequence[2]= 10; burst_sequence[3]= 9; burst_sequence[4]= 12; burst_sequence[5]= 11; burst_sequence[6]= 14; burst_sequence[7]= 13; end 2 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 12; burst_sequence[5]= 13; burst_sequence[6]= 10; burst_sequence[7]= 11; end 3 : begin burst_sequence[0]= 8; burst_sequence[1]= 7; burst_sequence[2]= 6; burst_sequence[3]= 5; burst_sequence[4]= 12; burst_sequence[5]= 11; burst_sequence[6]= 10; burst_sequence[7]= 9; end 4 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 10; burst_sequence[3]= 11; burst_sequence[4]= 4; burst_sequence[5]= 5; burst_sequence[6]= 6; burst_sequence[7]= 7; end 5 : begin burst_sequence[0]= 8; burst_sequence[1]= 7; burst_sequence[2]= 10; burst_sequence[3]= 9; burst_sequence[4]= 4; burst_sequence[5]= 3; burst_sequence[6]= 6; burst_sequence[7]= 5; end 6 : begin burst_sequence[0]= 8; burst_sequence[1]= 9; burst_sequence[2]= 6; burst_sequence[3]= 7; burst_sequence[4]= 4; burst_sequence[5]= 5; burst_sequence[6]= 2; burst_sequence[7]= 3; end default : begin burst_sequence[0]= 8; burst_sequence[1]= 7; burst_sequence[2]= 6; burst_sequence[3]= 5; burst_sequence[4]= 4; burst_sequence[5]= 3; burst_sequence[6]= 2; burst_sequence[7]= 1; end endcase end endtask integer Memory [(MaxBank*MaxRow*MaxColumn - 1) : 0]; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (CK_ipd ,CK ); buf (CKNeg_ipd ,CKNeg ); buf (CKE_ipd ,CKE ); buf (RASNeg_ipd ,RASNeg ); buf (CASNeg_ipd ,CASNeg ); buf (WENeg_ipd ,WENeg ); buf (CSNeg_ipd ,CSNeg ); buf (BA0_ipd ,BA0 ); buf (BA1_ipd ,BA1 ); buf (BA2_ipd ,BA2 ); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (UDQS_ipd ,UDQS ); buf (UDQSNeg_ipd ,UDQSNeg ); buf (LDQS_ipd ,LDQS ); buf (LDQSNeg_ipd ,LDQSNeg ); buf (UDM_ipd ,UDM ); buf (LDM_ipd ,LDM ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DOut15_zd , 1); nmos (DQ14, DOut14_zd , 1); nmos (DQ13, DOut13_zd , 1); nmos (DQ12, DOut12_zd , 1); nmos (DQ11, DOut11_zd , 1); nmos (DQ10, DOut10_zd , 1); nmos (DQ9 , DOut9_zd , 1); nmos (DQ8 , DOut8_zd , 1); nmos (DQ7 , DOut7_zd , 1); nmos (DQ6 , DOut6_zd , 1); nmos (DQ5 , DOut5_zd , 1); nmos (DQ4 , DOut4_zd , 1); nmos (DQ3 , DOut3_zd , 1); nmos (DQ2 , DOut2_zd , 1); nmos (DQ1 , DOut1_zd , 1); nmos (DQ0 , DOut0_zd , 1); nmos (UDQS , UDQSOut_zd , 1); nmos (UDQSNeg , UDQSNegOut_zd , 1); nmos (LDQS , LDQSOut_zd , 1); nmos (LDQSNeg , LDQSNegOut_zd , 1); // all values are for t_CK = 8 ns // must be changed if other value for t_CK is used parameter t_CK_period = 8; // t_CK parameter tsetup_UDQS_CK = 1.6; // (0.2*t_CK) -- tDSS parameter thold_UDQS_CK = 1.6; // (0.2*t_CK) -- tDSH parameter tpwCKEnegedge = 24; // (3*t_CK) -- tCKE parameter tpwDQ0posedge = 2.8; // (0.35*t_CK) -- tDIPW (DQ and DM) parameter tpwDQSposedge = 2.8; // (0.35*t_CK) -- tDQSL,H parameter tpwA0posedge = 4.8; // (0.6*t_CK) -- tIPW parameter tpwCKnegedge = 3.6; // (0.45*t_CK) parameter tpwCKposedge = 3.6; // (0.45*t_CK) time tdevice_MRD; time tdevic_RPRE; time tdevic_RPST; time tdevic_WPRE; time tdevic_WPST; time tdevice_XARD; time tdevice_XARDS; time tdevice_XP; time tdevice_XSRD; wire Check_DQ0_UDQSNeg; assign Check_DQ0_UDQSNeg = ((DQSNegDis == FALSE) && (write_data_enabled_g == 1'b1)); wire Check_DQ0_UDQS; assign Check_DQ0_UDQS = ((DQSNegDis == TRUE) && (write_data_enabled_g == 1'b1)); wire Check_UDQS_CK; wire Check_UDM_UDQSf; assign Check_UDM_UDQSf = ~DQSNegDis; wire Check_UDM_UDQSt; assign Check_UDM_UDQSf = DQSNegDis; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd: path delays specparam tpd_CK_DQ0 =1; specparam tpd_CK_DQ1 =1; specparam tpd_CK_DQ2 =1; specparam tpd_CK_DQ3 =1; specparam tpd_CK_DQ4 =1; specparam tpd_CK_DQ5 =1; specparam tpd_CK_DQ6 =1; specparam tpd_CK_DQ7 =1; specparam tpd_CK_DQ8 =1; specparam tpd_CK_DQ9 =1; specparam tpd_CK_DQ10 =1; specparam tpd_CK_DQ11 =1; specparam tpd_CK_DQ12 =1; specparam tpd_CK_DQ13 =1; specparam tpd_CK_DQ14 =1; specparam tpd_CK_DQ15 =1; specparam tpd_CK_UDQS =1; specparam tpd_CK_UDQSNeg =1; specparam tpd_CK_LDQS =1; specparam tpd_CK_LDQSNeg =1; // tperiod values: signal period specparam tperiod_CK =1; // tsetup values: setup time specparam tsetup_DQ0_UDQSNeg =1; specparam tsetup_DQ0_UDQS =1; specparam tsetup_A0_CK =1; // thold values: hold times specparam thold_DQ0_UDQSNeg =1; specparam thold_DQ0_UDQS =1; specparam thold_A0_CK =1; // tdevice values: values for internal delays specparam tdevice_RAS = 45; //1; extract specparam tdevice_RC = 60; //1; extract specparam tdevice_RCD = 15; specparam tdevice_RP = 15; specparam tdevice_REFI = 7800; specparam tdevice_RFC = 127.5; specparam tdevice_RRD = 10; specparam tdevice_RTP = 7.5; specparam tdevice_WR = 15; specparam tdevice_WTR = 1; // extract specparam tdevice_XSNR = 137.5; /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// (CK => DQ0) = tpd_CK_DQ0; (CK => DQ1) = tpd_CK_DQ1; (CK => DQ2) = tpd_CK_DQ2; (CK => DQ3) = tpd_CK_DQ3; (CK => DQ4) = tpd_CK_DQ4; (CK => DQ5) = tpd_CK_DQ5; (CK => DQ6) = tpd_CK_DQ6; (CK => DQ7) = tpd_CK_DQ7; (CK => DQ8) = tpd_CK_DQ8; (CK => DQ9) = tpd_CK_DQ9; (CK => DQ10) = tpd_CK_DQ10; (CK => DQ11) = tpd_CK_DQ11; (CK => DQ12) = tpd_CK_DQ12; (CK => DQ13) = tpd_CK_DQ13; (CK => DQ14) = tpd_CK_DQ14; (CK => DQ15) = tpd_CK_DQ15; (CK => UDQS) = tpd_CK_UDQS; (CK => UDQSNeg) = tpd_CK_UDQSNeg; (CK => LDQS) = tpd_CK_LDQS; (CK => LDQSNeg) = tpd_CK_LDQSNeg; /////////////////////////////////////////////////////////////////////////////// // Timing Violation // /////////////////////////////////////////////////////////////////////////////// $setup ( DQ0 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ1 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ2 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ3 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ4 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ5 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ6 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ7 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ8 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ9 , negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ10, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ11, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ12, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ13, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ14, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ15, negedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ0 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ1 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ2 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ3 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ4 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ5 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ6 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ7 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ8 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ9 , posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ10, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ11, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ12, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ13, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ14, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ15, posedge UDQSNeg &&& Check_DQ0_UDQSNeg,tsetup_DQ0_UDQSNeg,Viol); $setup ( DQ0 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ1 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ2 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ3 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ4 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ5 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ6 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ7 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ8 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ9 , negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ10, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ11, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ12, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ13, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ14, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ15, negedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ0 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ1 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ2 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ3 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ4 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ5 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ6 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ7 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ8 , posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ9 ,posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ10 ,posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ11, posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ12, posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ13, posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ14, posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $setup ( DQ15, posedge UDQS &&& Check_DQ0_UDQS,tsetup_DQ0_UDQS , Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ0 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ1 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ2 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ3 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ4 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ5 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ6 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ7 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ8 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ0 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ10 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ11 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ12 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ13 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ14 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ15 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ0 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ1 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ2 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ3 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ4 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ5 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ6 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ7 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ8 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ9 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ10 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ11 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ12 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ13 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ14 ,thold_DQ0_UDQSNeg,Viol); $hold ( posedge UDQSNeg &&& Check_DQ0_UDQSNeg, DQ15 ,thold_DQ0_UDQSNeg,Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ0 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ1 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ2 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ3 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ4 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ5 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ6 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ7 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ8 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ9 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ10 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ11 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ12 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ13 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ14 ,thold_DQ0_UDQS , Viol); $hold ( negedge UDQS &&& Check_DQ0_UDQS, DQ15 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ0 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ1 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ2 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ3 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ4 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ5 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ6 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ7 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ8 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ9 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ10 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ11 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ12 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ13 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ14 ,thold_DQ0_UDQS , Viol); $hold ( posedge UDQS &&& Check_DQ0_UDQS, DQ15 ,thold_DQ0_UDQS , Viol); $setup ( UDM, posedge UDQS &&& Check_UDM_UDQSf,tsetup_DQ0_UDQSNeg, Viol); $setup ( UDM, negedge UDQS &&& Check_UDM_UDQSf,tsetup_DQ0_UDQSNeg, Viol); $setup ( UDM, posedge UDQS &&& Check_UDM_UDQSt,tsetup_DQ0_UDQS, Viol); $setup ( UDM, negedge UDQS &&& Check_UDM_UDQSt,tsetup_DQ0_UDQS, Viol); $hold (posedge UDQS &&& Check_UDM_UDQSf, UDM ,thold_DQ0_UDQSNeg, Viol); $hold (negedge UDQS &&& Check_UDM_UDQSf, UDM ,thold_DQ0_UDQSNeg, Viol); $hold (posedge UDQS &&& Check_UDM_UDQSt, UDM ,thold_DQ0_UDQS , Viol); $hold (negedge UDQS &&& Check_UDM_UDQSt, UDM ,thold_DQ0_UDQS , Viol); $setup ( A0 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A1 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A2 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A3 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A4 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A5 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A6 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A7 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A8 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A9 , posedge CK ,tsetup_A0_CK , Viol); $setup ( A10, posedge CK ,tsetup_A0_CK , Viol); $setup ( A11, posedge CK ,tsetup_A0_CK , Viol); $setup ( A12, posedge CK ,tsetup_A0_CK , Viol); $hold ( posedge CK , A0 ,thold_A0_CK , Viol); $hold ( posedge CK , A1 ,thold_A0_CK , Viol); $hold ( posedge CK , A2 ,thold_A0_CK , Viol); $hold ( posedge CK , A3 ,thold_A0_CK , Viol); $hold ( posedge CK , A4 ,thold_A0_CK , Viol); $hold ( posedge CK , A5 ,thold_A0_CK , Viol); $hold ( posedge CK , A6 ,thold_A0_CK , Viol); $hold ( posedge CK , A7 ,thold_A0_CK , Viol); $hold ( posedge CK , A8 ,thold_A0_CK , Viol); $hold ( posedge CK , A9 ,thold_A0_CK , Viol); $hold ( posedge CK , A10,thold_A0_CK , Viol); $hold ( posedge CK , A11,thold_A0_CK , Viol); $hold ( posedge CK , A12,thold_A0_CK , Viol); $setup ( CSNeg, posedge CK, tsetup_A0_CK , Viol); $hold (posedge CK, CSNeg, thold_A0_CK , Viol); $setup ( RASNeg, posedge CK, tsetup_A0_CK , Viol); $hold ( posedge CK, RASNeg, thold_A0_CK , Viol); $setup ( CASNeg, posedge CK, tsetup_A0_CK , Viol); $hold ( CASNeg, posedge CK, thold_A0_CK , Viol); $setup ( WENeg, posedge CK, tsetup_A0_CK , Viol); $hold (posedge CK, WENeg, thold_A0_CK , Viol); $setup ( WENeg, posedge CK, tsetup_A0_CK , Viol); $hold ( WENeg, posedge CK, thold_A0_CK , Viol); $setup ( UDQS, posedge CK &&& Check_UDQS_CK, tsetup_UDQS_CK , Viol); $hold (posedge CK &&& Check_UDQS_CK, UDQS, thold_UDQS_CK , Viol); $period (posedge CK, t_CK_period); $width (posedge CK, tpwCKposedge); $width (negedge CK, tpwCKnegedge); $width (posedge DQ0 &&& DQ0 === 1'b1, tpwDQ0posedge); $width (negedge DQ0 &&& DQ0 === 1'b0, tpwDQ0posedge); $width (posedge DQ1 &&& DQ1 === 1'b1, tpwDQ0posedge); $width (negedge DQ1 &&& DQ1 === 1'b0, tpwDQ0posedge); $width (posedge DQ2 &&& DQ2 === 1'b1, tpwDQ0posedge); $width (negedge DQ2 &&& DQ2 === 1'b0, tpwDQ0posedge); $width (posedge DQ3 &&& DQ3 === 1'b1, tpwDQ0posedge); $width (negedge DQ3 &&& DQ3 === 1'b0, tpwDQ0posedge); $width (posedge DQ4 &&& DQ4 === 1'b1, tpwDQ0posedge); $width (negedge DQ4 &&& DQ4 === 1'b0, tpwDQ0posedge); $width (posedge DQ5 &&& DQ5 === 1'b1, tpwDQ0posedge); $width (negedge DQ5 &&& DQ5 === 1'b0, tpwDQ0posedge); $width (posedge DQ6 &&& DQ6 === 1'b1, tpwDQ0posedge); $width (negedge DQ6 &&& DQ6 === 1'b0, tpwDQ0posedge); $width (posedge DQ7 &&& DQ7 === 1'b1, tpwDQ0posedge); $width (negedge DQ7 &&& DQ7 === 1'b0, tpwDQ0posedge); $width (posedge DQ8 &&& DQ8 === 1'b1, tpwDQ0posedge); $width (negedge DQ8 &&& DQ8 === 1'b0, tpwDQ0posedge); $width (posedge DQ9 &&& DQ9 === 1'b1, tpwDQ0posedge); $width (negedge DQ9 &&& DQ9 === 1'b0, tpwDQ0posedge); $width (posedge DQ10 &&& DQ10 === 1'b1, tpwDQ0posedge); $width (negedge DQ10 &&& DQ10 === 1'b0, tpwDQ0posedge); $width (posedge DQ11 &&& DQ11 === 1'b1, tpwDQ0posedge); $width (negedge DQ11 &&& DQ11 === 1'b0, tpwDQ0posedge); $width (posedge DQ12 &&& DQ12 === 1'b1, tpwDQ0posedge); $width (negedge DQ12 &&& DQ12 === 1'b0, tpwDQ0posedge); $width (posedge DQ13 &&& DQ13 === 1'b1, tpwDQ0posedge); $width (negedge DQ13 &&& DQ13 === 1'b0, tpwDQ0posedge); $width (posedge DQ14 &&& DQ14 === 1'b1, tpwDQ0posedge); $width (negedge DQ14 &&& DQ14 === 1'b0, tpwDQ0posedge); $width (posedge DQ15 &&& DQ15 === 1'b1, tpwDQ0posedge); $width (negedge DQ15 &&& DQ15 === 1'b0, tpwDQ0posedge); $width (posedge UDM &&& UDM === 1'b1, tpwDQ0posedge); $width (negedge UDM &&& UDM === 1'b0, tpwDQ0posedge); $width (posedge UDQS &&& UDQS === 1'b1, tpwDQSposedge); $width (negedge UDQS &&& UDQS === 1'b0, tpwDQSposedge); $width (posedge A0 &&& A0 === 1'b1, tpwA0posedge); $width (negedge A0 &&& A0 === 1'b0, tpwA0posedge); $width (posedge A1 &&& A1 === 1'b1, tpwA0posedge); $width (negedge A1 &&& A1 === 1'b0, tpwA0posedge); $width (posedge A2 &&& A2 === 1'b1, tpwA0posedge); $width (negedge A2 &&& A2 === 1'b0, tpwA0posedge); $width (posedge A3 &&& A3 === 1'b1, tpwA0posedge); $width (negedge A3 &&& A3 === 1'b0, tpwA0posedge); $width (posedge A4 &&& A4 === 1'b1, tpwA0posedge); $width (negedge A4 &&& A4 === 1'b0, tpwA0posedge); $width (posedge A5 &&& A5 === 1'b1, tpwA0posedge); $width (negedge A5 &&& A5 === 1'b0, tpwA0posedge); $width (posedge A6 &&& A6 === 1'b1, tpwA0posedge); $width (negedge A6 &&& A6 === 1'b0, tpwA0posedge); $width (posedge A7 &&& A7 === 1'b1, tpwA0posedge); $width (negedge A7 &&& A7 === 1'b0, tpwA0posedge); $width (posedge A8 &&& A8 === 1'b1, tpwA0posedge); $width (negedge A8 &&& A8 === 1'b0, tpwA0posedge); $width (posedge A9 &&& A9 === 1'b1, tpwA0posedge); $width (negedge A9 &&& A9 === 1'b0, tpwA0posedge); $width (posedge A10 &&& A10 === 1'b1, tpwA0posedge); $width (negedge A10 &&& A10 === 1'b0, tpwA0posedge); $width (posedge A11 &&& A11 === 1'b1, tpwA0posedge); $width (negedge A11 &&& A11 === 1'b0, tpwA0posedge); $width (posedge A12 &&& A12 === 1'b1, tpwA0posedge); $width (negedge A12 &&& A12 === 1'b0, tpwA0posedge); $width (posedge CSNeg, tpwA0posedge); $width (negedge CSNeg, tpwA0posedge); $width (posedge CASNeg, tpwA0posedge); $width (negedge CASNeg, tpwA0posedge); $width (posedge RASNeg, tpwA0posedge); $width (negedge RASNeg, tpwA0posedge); $width (posedge WENeg, tpwA0posedge); $width (negedge WENeg, tpwA0posedge); $width (posedge CKE, tpwCKEnegedge); $width (negedge CKE, tpwCKEnegedge); endspecify /////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // /////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// // Functionality Section /////////////////////////////////////////////////////////////////////////////// reg rising_edge_CK; reg CKE_event; reg falling_edge_CK; reg edge_CK; reg rising_edge_read_data_enabled_g; integer state_changed [0:7]; reg new_rw_event [(MaxBank-1):0]; /////////////////////////////////////////////////////////////////////////////// // Initial process (regs gets its default values) /////////////////////////////////////////////////////////////////////////////// initial begin : InitProc integer itemp; CKEPrev = 1'b0; CKENew = 1'b0; command_changed= 1'b0; command = unknown_c; command_string = "UNKNOWN"; DataOut_temp = 16'hz; UDQSOut_zd = 1'hz; UDQSNegOut_zd = 1'hz; LDQSOut_zd = 1'hz; LDQSNegOut_zd = 1'hz; rising_edge_CK = 1'b0; CKE_event = 1'b0; falling_edge_CK = 1'b0; edge_CK = 1'b0; rising_edge_read_data_enabled_g = 1'b0; for (itemp = 0; itemp <= (MaxBank - 1); itemp = itemp + 1) begin new_rw [itemp] = 1'b0; current_state[itemp] = init_state; next_state[itemp] = init_state; rc_in[itemp] = 1'b0; rc_out[itemp] = 1'b0; rcd_in[itemp] = 1'b0; rcd_out[itemp] = 1'b0; ras_in[itemp] = 1'b0; ras_out[itemp] = 1'b0; rp_in[itemp] = 1'b0; rp_out[itemp] = 1'b0; rtp_in[itemp] = 1'b0; rtp_out[itemp] = 1'b0; mrs_finished[itemp] = 1'b1; aref_finished[itemp] = 1'b1; write_finished[itemp] = 1'b1; read_finished[itemp] = 1'b1; wap_finished[itemp] = 1'b1; rap_finished[itemp] = 1'b1; prech_finished[itemp] = 1'b1; read_dqs_enabled_0 [itemp] = 1'b0; read_data_enabled_0 [itemp] = 1'b0; read_dqs_enabled_1 [itemp] = 1'b0; read_data_enabled_1 [itemp] = 1'b0; read_dqs_enabled_2 [itemp] = 1'b0; read_data_enabled_2 [itemp] = 1'b0; read_dqs_enabled_3 [itemp] = 1'b0; read_data_enabled_3 [itemp] = 1'b0; read_dqs_enabled_4 [itemp] = 1'b0; read_data_enabled_4 [itemp] = 1'b0; read_dqs_enabled_5 [itemp] = 1'b0; read_data_enabled_5 [itemp] = 1'b0; read_dqs_enabled_6 [itemp] = 1'b0; read_data_enabled_6 [itemp] = 1'b0; read_dqs_enabled_7 [itemp] = 1'b0; read_data_enabled_7 [itemp] = 1'b0; write_data_enabled_0 [itemp] = 1'b0; write_data_enabled_1 [itemp] = 1'b0; write_data_enabled_2 [itemp] = 1'b0; write_data_enabled_3 [itemp] = 1'b0; write_data_enabled_4 [itemp] = 1'b0; write_data_enabled_5 [itemp] = 1'b0; write_data_enabled_6 [itemp] = 1'b0; write_data_enabled_7 [itemp] = 1'b0; w_burst_n_interrupted_0[itemp] = 1'b1; r_burst_n_interrupted_0[itemp] = 1'b1; end refi_in = 1'b0; refi_out= 1'b0; rfc_in = 1'b0; rfc_out = 1'b0; rrd_in = 1'b0; rrd_out = 1'b0; wr_in = 1'b0; wr_out = 1'b0; wtr_in = 1'b0; wtr_out = 1'b0; xsnr_in = 1'b0; xsnr_out= 1'b0; read_finished_interrupted = 1'b0; burst_index = 0; burst_offset= 0; end /////////////////////////////////////////////////////////////////////////////// // Process that reads actual clock frequency /////////////////////////////////////////////////////////////////////////////// always @(CKIn) begin : CK_period_read time tprev; time tnow; tprev = tnow; tnow = $time; t_CK = 2 *(tnow - tprev); tdevice_MRD = (2*t_CK); tdevic_RPRE = (1.1*t_CK); tdevic_RPST = (0.6*t_CK); tdevic_WPRE = (0.35 * t_CK); tdevic_WPST = (0.35 * t_CK); tdevice_XARD = 2*t_CK; tdevice_XARDS = (6-AL)*t_CK; tdevice_XP = 2*t_CK; tdevice_XSRD = 200*t_CK; end /////////////////////////////////////////////////////////////////////////////// // Command decode process : // -- reads control signals and generates commands // -- stores information of previous CKEIn value on CKEIn change /////////////////////////////////////////////////////////////////////////////// reg entered_pwr_down; initial begin : InitCommandDecode entered_pwr_down = FALSE; end always @(CKEIn or rising_edge_CK) begin : CommandDecode // commands entered on each CK rising edge // command_changed is used in FSM sensitivity list // Read new command every CK or CKNeg rise CKEPrev = CKENew; CKENew = CKE; if (!CKE_event) begin if (command_update == 1'b1) command_update <= 1'b0; else command_update <= 1'b1; if (CKEPrev == 1'b1 || PoweredUp == FALSE) begin if (CKENew == 1'b1) begin // deselect if (CSNegIn == 1'b1) begin command = deselect; command_string = "DESELECT"; end // nop else if((CSNegIn==1'b0)&&(RASNegIn==1'b1)&&(CASNegIn==1'b1) && (WENegIn == 1'b1)) begin command = nop; command_string = "NOP"; end // (extended) mode register set else if ((CSNegIn==1'b0)&&(RASNegIn==1'b0)&&(CASNegIn==1'b0) && (WENegIn == 1'b0)) begin command = mrs; // + BA[2:0], A[12:0] loaded command_string = "MRS"; end // auto refresh else if ((CSNegIn==1'b0)&&(RASNegIn==1'b0)&&(CASNegIn==1'b0) && (WENegIn == 1'b1)) begin command = autoref; command_string = "AUTOREF"; end // bank activate else if ((CSNegIn==1'b0)&&(RASNegIn==1'b0)&&(CASNegIn==1'b1) && (WENegIn == 1'b1)) begin command = bankact; command_string = "BANKACT"; end // precharge single bank // precharge all banks else if ((CSNegIn==1'b0)&&(RASNegIn==1'b0)&&(CASNegIn==1'b1) && (WENegIn == 1'b0)) begin if (AIn[10] == 1'b0) begin command = presingle; command_string = "PRESINGLE"; end else begin command = preall; command_string = "PREALL"; end end // write // write with auto precharge else if ((CSNegIn==1'b0)&&(RASNegIn==1'b1)&&(CASNegIn==1'b0) && (WENegIn == 1'b0)) begin if (AIn[10] == 1'b0) begin command = write; command_string = "WRITE"; end else begin command = writeapre; command_string = "WRITEAPRE"; end end // read // read with auto precharge else if ((CSNegIn==1'b0)&&(RASNegIn==1'b1)&&(CASNegIn==1'b0) && (WENegIn == 1'b1)) begin if (AIn[10] == 1'b0) begin command = read; command_string = "READ"; end else begin command = readapre; command_string = "READAPRE"; end end end else //( CKENew = '0') begin // self refresh entry if ((CSNegIn==1'b0)&&(RASNegIn==1'b0)&&(CASNegIn==1'b0) && (WENegIn == 1'b1)) begin command = selfrefentry; // CKE : H -> L (entry) command_string = "SELFREFENTRY"; end // power down entry if ( (CSNegIn == 1'b1) || ((CSNegIn==1'b0)&&(RASNegIn==1'b1)&&(CASNegIn==1'b1) && (WENegIn == 1'b1)) ) begin command = pwrdwnentry; // CKE : H -> L (entry) command_string = "PWRDWNENTRY"; entered_pwr_down = TRUE; end end end else begin if (CKEPrev == 1'b0 && CKENew == 1'b1) begin // self refresh exit // power down exit if ( (CSNegIn == 1'b1) || ((CSNegIn==1'b0)&&(RASNegIn==1'b1)&&(CASNegIn==1'b1) && (WENegIn == 1'b1)) ) begin command = selfrefpwrdwnexit; // CKE : L -> H (exit) command_string = "SELFREFPWRDWNEXIT"; entered_pwr_down = FALSE; end end else // (CKEPrev = '0' AND CKENew = '0') if (entered_pwr_down == TRUE) begin command = nop; command_string = "NOP"; end end end //if end //CommandDecode /////////////////////////////////////////////////////////////////////////////// // State Generation process // combinational process for next state generation // and FSM state transition /////////////////////////////////////////////////////////////////////////////// reg all_banks_precharged; reg enable_precharge_all; integer init_counter; reg timing_ok; integer i; initial begin : InitStateGen init_counter = 0; timing_ok = 1'b1; end always @(command_update) begin : StateGen // Initialization sequence if (PoweredUp == FALSE) begin // 'Power Up - Initialization' STATE MACHINE if (current_state[0] == init_state) begin if ((command == nop) || (command == deselect)) init_counter = 1; else if ((command == preall) && (init_counter == 1)) begin for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = precharge_state; init_counter = 2; end else if (command != unknown_c) $display ("WARNING : Illegal command during initialization!"); end else if (current_state[0] == mrs_set_state) begin // automatic transition of all banks to idle_state after finish if (mrs_finished[0] == TRUE) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = idle_state; if (init_counter >= 11) PoweredUp <= TRUE; end else if (current_state[0] == idle_state) begin if (command == mrs) begin init_counter = init_counter +1; for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = mrs_set_state; end if ((command == preall) && (init_counter >= 6)) begin for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = precharge_state; init_counter = 7; end if ((command == autoref) && (init_counter >= 7 )) begin for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = auto_refresh_state; init_counter = 8; end end else if (current_state[0] == auto_refresh_state) begin // auto_refresh_state : // automatic transition of all banks to idle_state after finish if (aref_finished[0] == TRUE) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = idle_state; end else if (current_state[0] == precharge_state) begin // automatic transition of all banks to idle_state after finish if (prech_finished[0] == TRUE) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = idle_state; end end else // PoweredUp = TRUE begin // 'Powered Up' STATE MACHINE // current bank (0..7) if ((command == presingle) || (command == bankact) || (command == write) || (command == writeapre) || (command == read) || (command == readapre)) begin current_bank = BAIn[2:0]; end else if ((command != nop) && (command != deselect)) begin current_bank = NoneBank; // none bank selected end // current row (0..8191) if (command == bankact) current_row[current_bank] = AIn[12:0]; // current column (0..1023) if ((command == write) || (command == writeapre) || (command == read) || (command == readapre)) begin columnFIFObuffer[in_index] = AIn[9:0]; if (in_index == 7) in_index = 0; else in_index = in_index + 1; end enable_precharge_all = FALSE; if (command == preall) begin for (i=0; i<= MaxBank-1; i=i+1) if ((current_state[i] == bank_active_state) || (current_state[i] == write_state) || (current_state[i] == read_state)) enable_precharge_all = TRUE; end all_banks_precharged = TRUE; for (i=0; i<= MaxBank-1; i=i+1) if (current_state[i] != idle_state) all_banks_precharged = FALSE; //PROTOCOL CHECKING timing_ok = 1'b1; if (command == presingle) begin if (ras_out[current_bank] != ras_in[current_bank]) begin $display ("WARNING : Precharge cannot be executed ..."); $display ("... due to tRAS time is not met!"); timing_ok = 1'b0; end end else if (command == bankact) begin begin if (rp_out[current_bank] != rp_in[current_bank]) begin $display("WARNING : Bank Activation cannot be executed ..."); $display("... due to tRP time is not met!"); timing_ok = 1'b0; end end end else if ((command == write) || (command == writeapre) || (command == read) || (command == readapre)) begin if (rcd_out[current_bank] != rcd_in[current_bank]) begin $display("WARNING : Memory access (read or write) cannot..."); $display("... be executed due to tRCD time is not met!"); timing_ok = 1'b0; end end // STATE MACHINE : if (timing_ok == 1'b1) // STATE MACHINE : begin // bank_act , write , read -> precharge (all) if (enable_precharge_all == TRUE) begin for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = precharge_state; end // idle -> mrs, self_refresh, auto_refresh, pwrdwn_precharge if (all_banks_precharged == TRUE) begin if (command == mrs) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = mrs_set_state; if (command == autoref) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = auto_refresh_state; if (command == selfrefentry) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = self_refresh_state; if (command == pwrdwnentry) for (i=0; i<= MaxBank-1; i=i+1) next_state[i] = pwrdown_precharge_state; end else begin if ((command == mrs) || (command == autoref) || ((current_state[0] != self_refresh_state) && (command == selfrefentry))) begin $display ("WARNING : Illegal command !"); $display ("All banks must be precharged !"); end end for (i=0; i<= (MaxBank-1); i=i+1) begin case (current_state[i]) // mrs -> idle mrs_set_state : if (mrs_finished[0] == TRUE) next_state[i] = idle_state; // pwrdown_active -> bank_active pwrdown_active_state : if (command == selfrefpwrdwnexit) next_state[i] = bank_active_state; // pwrdwn_precharge -> idle pwrdown_precharge_state : if (command == selfrefpwrdwnexit) next_state[i] = idle_state; // bank_active -> pwrdown_active bank_active_state : if (command == pwrdwnentry) next_state[i] = pwrdown_active_state; // precharge -> idle precharge_state : if (prech_finished[i] == TRUE) // automatic transition to idle_state after finish next_state[i] = idle_state; // write -> bank_active write_state : if (write_finished[i]) // automatic transition to bank_active_state after finish next_state[i] = bank_active_state; // read -> bank_active read_state : if (read_finished[i]) // automatic transition to bank_active_state after finish next_state[i] = bank_active_state; // write_auto_precharge -> idle write_auto_precharge_state : if (wap_finished[i]) // automatic transition to idle_state after finish next_state[i] = idle_state; // read_auto_precharge -> idle read_auto_precharge_state : if (rap_finished[i]) // automatic transition to idle_state after finish next_state[i] = idle_state; // self_refresh -> idle self_refresh_state : if (command == selfrefpwrdwnexit) next_state[i] = idle_state; auto_refresh_state : // auto_refresh -> pwrdown_precharge , idle begin if (command == pwrdwnentry) next_state[i] = pwrdown_precharge_state; else if (aref_finished[0] == TRUE) next_state[i] = idle_state; end activating_state : begin if (command == pwrdwnentry) next_state[i] = pwrdown_active_state; else next_state[i] = bank_active_state; end endcase; end // for (i=0; i<= MaxBank-1; i=i+1) if (current_bank != NoneBank) begin case (current_state[current_bank]) // idle -> activating -> bank_active_state idle_state : begin if (command == bankact) // automatic transition to bank_active_state t_CK from // entering activating_state next_state[current_bank] = activating_state; else if ((command != nop) && (command != deselect)) begin $display ("WARNING : Illegal command !"); $display ("Expecting bank activating command !"); end end // bank_active -> write , write_auto_precharge // read , read_auto_precharge, precharge bank_active_state : begin if (command == write) next_state[current_bank] = write_state; else if (command == writeapre) next_state[current_bank] = write_auto_precharge_state; else if (command == read) next_state[current_bank] = read_state; else if (command == readapre) next_state[current_bank] = read_auto_precharge_state; else if (command == presingle) next_state[current_bank] = precharge_state; else if ((command != nop) && (command != deselect)) begin $display ("WARNING : Illegal command !"); $display ("Bank is already ACTIV !"); end end // write -> write_auto_precharge, read, read_auto_precharge, // precharge, bank_active write_state : begin if (command == write) new_rw[current_bank] <= ~new_rw[current_bank]; else if (command == writeapre) next_state[current_bank] = write_auto_precharge_state; else if (command == read) next_state[current_bank] = read_state; else if (command == readapre) next_state[current_bank] = read_auto_precharge_state; else if (command == presingle) next_state[current_bank] = precharge_state; end // read -> read_auto_precharge, write, write_auto_precharge, // precharge, bank_active read_state : begin if (command == read) new_rw[current_bank] <= ~new_rw[current_bank]; else if (command == readapre) next_state[current_bank] = read_auto_precharge_state; else if (command == write) next_state[current_bank] = write_state; else if (command == writeapre) next_state[current_bank] = write_auto_precharge_state; else if (command == presingle) next_state[current_bank] = precharge_state; end endcase; end //(current_bank != NoneBank) end // (timing_ok = 1'b1) end // (PoweredUp = TRUE) for (i=0; i<= (MaxBank-1); i=i+1) current_state[i] <= next_state[i]; end // StateGen ////////////////////////////////////////////////////////////////////////// //FSM Output generation and general funcionality ////////////////////////////////////////////////////////////////////////// time idle_entry; time mrs_set_entry; time self_refresh_entry; time auto_refresh_entry; time pwrdown_precharge_entry; time pwrdown_active_entry; time activating_entry; time bank_active_entry; time write_entry; time write_auto_precharge_entry; time read_entry; time read_auto_precharge_entry; time precharge_entry; integer j; integer k; integer m; integer n; integer s; initial begin : Functional_Gen idle_entry = 0; mrs_set_entry = 0; self_refresh_entry = 0; auto_refresh_entry = 0; pwrdown_precharge_entry = 0; pwrdown_active_entry = 0; activating_entry = 0; bank_active_entry = 0; write_entry = 0; write_auto_precharge_entry = 0; read_entry = 0; read_auto_precharge_entry = 0; precharge_entry = 0; j = 0; k = 0; m = 0; n = 0; end always @(posedge state_changed[0] or posedge new_rw_event[0] or posedge state_changed[1] or posedge new_rw_event[1] or posedge state_changed[2] or posedge new_rw_event[2] or posedge state_changed[3] or posedge new_rw_event[3] or posedge state_changed[4] or posedge new_rw_event[4] or posedge state_changed[5] or posedge new_rw_event[5] or posedge state_changed[6] or posedge new_rw_event[6] or posedge state_changed[7] or posedge new_rw_event[7]) begin : Functional for (s=0; s<=(MaxBank-1); s=s+1) if (state_changed[s] == 1'b1 || new_rw_event[s] == 1'b1) case (current_state[s]) init_state : #1000; idle_state : idle_entry = $time; mrs_set_state : if (s == 0) begin mrs_set_entry = $time; begin mrs_finished[s] <= FALSE; mrs_finished[s] <= #(tdevice_MRD) TRUE; end case (BAIn[2:0]) //MRS 3'b000 : begin case (AIn[2:0]) 3'b010 : BL = 4; 3'b011 : BL = 8; default : begin BL = 0; $display ("WARNING : Illegal Address[2..0]"); $display ("BL cannot be adjusted!"); end endcase case (AIn[3]) 1'b0 : BT = sequential; default : // WHEN '1' BT = interleaved; endcase case (AIn[6:4]) 3'b010 : CL = 2; 3'b011 : CL = 3; 3'b100 : CL = 4; 3'b101 : CL = 5; 3'b110 : CL = 6; default : begin CL = 1; $display ("WARNING : Illegal Address[6..4]"); $display ("CL cannot be adjusted!"); end endcase RL = AL + CL; WL = RL -1; TM = AIn[7]; DLLreset = AIn[8]; case (AIn[11:9]) 3'b001 : WR = 2; 3'b010 : WR = 3; 3'b011 : WR = 4; 3'b100 : WR = 5; 3'b101 : WR = 6; default : begin WR = 1; $display ("WARNING : Illegal Address[11..9]"); $display ("WR cannot be adjusted!"); end endcase case (AIn[12]) 1'b0 : PD = standard; default // WHEN '1' PD = lowpower; endcase end // 3'b000 : // EMRS(1) 3'b001 : begin DLLenable = AIn[0]; DIC = AIn[1]; case (AIn[5:3]) 3'b000 : AL = 0; 3'b001 : AL = 1; 3'b010 : AL = 2; 3'b011 : AL = 3; 3'b100 : AL = 4; default : begin AL = 0; $display ("WARNING : Illegal Address[5..3]]"); $display ("AL cannot be adjusted!"); end endcase RL = AL + CL; WL = RL -1; if (AIn[10] === 1'b1) begin DQSNegDis = TRUE; end else begin DQSNegDis = FALSE; end QoffHIz = AIn[12]; end // 3'b001 // EMRS(2) 3'b010 : begin if ((AIn[12:8] !== 5'b0) || (AIn[6:0] !== 7'b0)) begin $display ("WARNING : Illegal command"); $display ("EMRS(2) cannot be adjusted!"); end end //3'b010 // EMRS(3) 3'b011 : begin if (AIn[12:0] !== 13'b0) begin $display ("WARNING : Illegal command"); $display ("EMRS(3) cannot be adjusted!"); end end //3'b011 default : begin //BAIn[2] is '1' $display ("WARNING : Illegal command"); $display ("BA[2] = '1' is NOT allowed !"); end endcase // BAIn end // if (s==0) self_refresh_state : if (s == 0) self_refresh_entry = $time; auto_refresh_state : if (s == 0) begin auto_refresh_entry = $time; aref_finished[s] <= FALSE; aref_finished[s] <= #(1000*tdevice_RFC) TRUE; end pwrdown_precharge_state : if (s == 0) pwrdown_precharge_entry = $time; pwrdown_active_state : pwrdown_active_entry = $time; activating_state : begin activating_entry = $time; ras_in[s] <= ~ras_in[s]; ras_out[s] <= #(1000*tdevice_RAS) ~ras_in[s]; rc_in[s] <= ~rc_in[s]; rc_out[s] <= #(1000*tdevice_RC) ~rc_in[s]; rcd_in[s] <= ~rcd_in[s]; rcd_out[s] <= #(1000*tdevice_RCD) ~rcd_in[s]; end bank_active_state : bank_active_entry = $time; write_state , write_auto_precharge_state : begin if ((BL == 8) && (($time - write_entry) == (2*t_CK))) begin w_burst_n_interrupted_0[s] <= #(WL*t_CK - t_CK/4 - t_CK/128) 1'b0; w_burst_n_interrupted_0[s] <= #(WL*t_CK - t_CK/4 + t_CK/128) 1'b1; end write_entry <= #1000 $time; if (current_state[s] == write_state) begin if (write_finished[s] == TRUE) write_finished[s] = FALSE; end else begin if (wap_finished[s] == TRUE) wap_finished[s] = FALSE; end if (k == 0) begin write_data_enabled_0[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_0[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 1) begin write_data_enabled_1[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_1[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 2) begin write_data_enabled_2[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_2[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 3) begin write_data_enabled_3[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_3[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 4) begin write_data_enabled_4[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_4[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 5) begin write_data_enabled_5[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_5[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else if (k == 6) begin write_data_enabled_6[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_6[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end else begin write_data_enabled_7[s] <= #((WL)*t_CK - t_CK/4 + t_CK/128) 1'b1; write_data_enabled_7[s] <= #((WL+(BL/2))*t_CK - t_CK/4 - t_CK/128) 1'b0; end if (k == 7) k <= #1000 0; else k <= #1000 (k + 1); end read_state , read_auto_precharge_state : begin if ((BL == 8) && (($time - read_entry) == (2*t_CK))) begin r_burst_n_interrupted_0[s] <= #(RL*t_CK - 3*t_CK/8) 1'b0; r_burst_n_interrupted_0[s] <= #(RL*t_CK - t_CK/8) 1'b1; end read_entry = $time; if (current_state[s] == read_state) begin rtp_in[s] <= ~ rtp_in[s]; rtp_out[s] <= #(1000*tdevice_RTP) ~rtp_in[s]; if (read_finished[s] == TRUE) read_finished[s] = FALSE; end else begin if (rap_finished[s] == TRUE) rap_finished[s] = FALSE; end if (j == 0) begin read_dqs_enabled_0[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_0[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_0[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_0[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 1) begin read_dqs_enabled_1[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_1[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_1[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_1[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 2) begin read_dqs_enabled_2[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_2[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_2[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_2[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 3) begin read_dqs_enabled_3[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_3[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_3[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_3[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 4) begin read_dqs_enabled_4[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_4[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_4[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_4[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 5) begin read_dqs_enabled_5[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_5[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_5[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_5[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else if (j == 6) begin read_dqs_enabled_6[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_6[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_6[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_6[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end else begin read_dqs_enabled_7[s] <= #((RL-1)*t_CK) 1'b1; read_dqs_enabled_7[s] <= #((RL)*t_CK) 1'b0; read_data_enabled_7[s] <= #((RL)*t_CK) 1'b1; read_data_enabled_7[s] <= #((RL + (BL/2))*t_CK - t_CK/2 + t_CK/8) 1'b0; end begin if (j == 7) j <= #1000 0; else j <= #1000 (j + 1); end end precharge_state : begin rp_in[s] <= ~ rp_in[s]; rp_out[s] <= #(1000*tdevice_RP) ~rp_in[s]; precharge_entry = $time; prech_finished[s] <= FALSE; prech_finished[s] <= #(1000*tdevice_RP) TRUE; end endcase end // Functional ////////////////////////////////////////////////////////////////////////// // Process that generates DQS ////////////////////////////////////////////////////////////////////////// always @(CKIn) begin : DQS_drive_Gen #1; if (PoweredUp == TRUE) begin if (read_data_enabled_g == 1'b1) begin UDQSOut_zd <= CKIn; // transport delay LDQSOut_zd <= CKIn; // transport delay if (DQSNegDis == FALSE) begin UDQSNegOut_zd <= CKNegIn; // transport delay LDQSNegOut_zd <= CKNegIn; // transport delay end else begin UDQSNegOut_zd <= 1'bz; LDQSNegOut_zd <= 1'bz; end end else if (read_dqs_enabled_g == 1'b1) begin UDQSOut_zd <= 1'b0; LDQSOut_zd <= 1'b0; if (DQSNegDis == FALSE) begin UDQSNegOut_zd <= 1'b1; LDQSNegOut_zd <= 1'b1; end else begin UDQSNegOut_zd <= 1'bz; LDQSNegOut_zd <= 1'bz; end end else begin UDQSOut_zd <= 1'bz; LDQSOut_zd <= 1'bz; UDQSNegOut_zd <= 1'bz; LDQSNegOut_zd <= 1'bz; DataOut_temp <= 16'bz; end end // OUTPUTS : Check if outputs are disabled if (QoffHIz == 1'b1 && write_data_enabled_g == 1'b0) begin UDQSOut_zd <= 1'bz; LDQSOut_zd <= 1'bz; DataOut_temp <= 16'bz; if (DQSNegDis == FALSE) begin UDQSNegOut_zd <= 1'bz; LDQSNegOut_zd <= 1'bz; end end end integer read_counter; // counts burst_length integer read_column; integer mem_index; ////////////////////////////////////////////////////////////////////////// // Process that executes burst read operation ////////////////////////////////////////////////////////////////////////// always @(rising_edge_read_data_enabled_g) begin : Data_read_gen if (PoweredUp == TRUE) begin current_column = columnFIFObuffer[out_index]; if (out_index == 7) out_index = 0; else out_index = out_index + 1; if (BL == 4) burst_index = current_column % 4; else // (BL = 8) burst_index = current_column % 8; burst_offset = 0; if (BL == 4) if (BT == sequential) sa_4(burst_index); else //(BT = interleaved) ia_4(burst_index); else // (BL = 8) if (BT == sequential) sa_8(burst_index); else //(BT = interleaved) ia_8(burst_index); read_counter = 0; read_finished_interrupted = 1'b0; while (read_finished_interrupted == 1'b0) begin read_column = current_column+(burst_sequence[burst_offset]- BL); mem_index = current_bank*MaxRow*MaxColumn + current_row[current_bank]*MaxColumn + read_column; while (edge_CK != 1'b1) begin #1; end; if (Memory[mem_index] >= 0) begin DataOut_temp = Memory[mem_index]; end else begin if (Memory[mem_index] == -1) DataOut_temp = 16'hzzzz; else DataOut_temp = 16'hxxxx; end burst_offset = burst_offset + 1; read_counter = read_counter + 1; if (read_counter == BL) begin read_finished_interrupted = 1'b1; end else #(t_CK/4); //wait to see if interrupted end //while (read_finished_interrupted = 1'b0) end end ///////////////////////////////////////////////////////////////////////// // Process that interrupts burst read operation ///////////////////////////////////////////////////////////////////////// always @(r_burst_n_interrupted_g) begin : Interrupt_burst_read if (r_burst_n_interrupted_g == 1'b0) read_finished_interrupted = 1'b1; end ///////////////////////////////////////////////////////////////////////// // Process that adjusts current_column for burst write ///////////////////////////////////////////////////////////////////////// always @(write_data_enabled_g) begin : Write_process_column_choose if (PoweredUp == TRUE) begin if (write_data_enabled_g == 1'b1) begin current_column = columnFIFObuffer[out_index]; if (out_index == 7) out_index = 0; else out_index = out_index + 1; if (BL == 4) burst_index = current_column % 4; else // (BL = 8) burst_index = current_column % 8; burst_offset = 0; if (BL == 4) if (BT == sequential) sa_4(burst_index); else //(BT = interleaved) ia_4(burst_index); else // (BL = 8) if (BT == sequential) sa_8(burst_index); else //(BT = interleaved) ia_8(burst_index); end end end integer write_column; ///////////////////////////////////////////////////////////////////////// // Process that executes burst write operation ///////////////////////////////////////////////////////////////////////// always @(UDQSIn) begin : WriteProcess if (PoweredUp == TRUE) begin if (write_data_enabled_g == 1'b1) begin write_column=current_column+(burst_sequence[burst_offset]-BL); mem_index = current_bank*MaxRow*MaxColumn + current_row[current_bank]*MaxColumn + write_column; if ((UDMIn === 1'b0) && (LDMIn === 1'b0)) begin if ((DIn[15:0] !== 16'bzzzz) && (DIn[15:0] !== 16'bxxxx)) Memory[mem_index] = DIn; else Memory[mem_index] = -1; end else Memory[mem_index] = -1; burst_offset = burst_offset + 1; end end end ///////////////////////////////////////////////////////////////////////// //// Output section - DataOut assign control ///////////////////////////////////////////////////////////////////////// always @(rising_edge_CK or falling_edge_CK) begin : DataOutAssign #2; DOut_zd <= DataOut_temp; end ///////////////////////////////////////////////////////////////////////// //// File Read Section - Preload Control ///////////////////////////////////////////////////////////////////////// initial begin: InitMemory integer i_pr; reg [15:0] mem_tmp; if (UserPreload && !(mem_file_name == "none")) begin // hyb18t1g160af_120.memory file // / - comment // @aaaaaaa - is mem_index (address) : // dd -
is data (1 byte) to be written in Memory // After write : address increments // No empty lines. $readmemh(mem_file_name,Memory); end for (i_pr=0; i_pr< MaxBank*MaxRow*MaxColumn; i_pr= i_pr+1) begin mem_tmp = Memory[i_pr]; mem_tmp[15:8] = 8'b0; Memory[i_pr] = mem_tmp; end; end ////////////////////////////////////////////////////////////////////////// // // Detection and generation of edge sensitive signals // ////////////////////////////////////////////////////////////////////////// always @(posedge CKIn) begin rising_edge_CK = ~rising_edge_CK; end always @(negedge CKIn) begin falling_edge_CK = ~falling_edge_CK; end always @(rising_edge_CK or falling_edge_CK) begin edge_CK = 1'b1; # 10; // 10 ps edge_CK = 1'b0; end always @(CKEIn) begin CKE_event <= 1'b1; CKE_event <= #1000 1'b0; end always @(posedge read_data_enabled_g) begin rising_edge_read_data_enabled_g = ~rising_edge_read_data_enabled_g; end always @(current_state[0]) begin state_changed[0] <= 1'b1; #1000 state_changed[0] <= 1'b0; end always @(current_state[1]) begin state_changed[1] <= 1'b1; #1000 state_changed[1] <= 1'b0; end always @(current_state[2]) begin state_changed[2] <= 1'b1; #1000 state_changed[2] <= 1'b0; end always @(current_state[3]) begin state_changed[3] <= 1'b1; #1000 state_changed[3] <= 1'b0; end always @(current_state[4]) begin state_changed[4] <= 1'b1; #1000 state_changed[4] <= 1'b0; end always @(current_state[5]) begin state_changed[5] <= 1'b1; #1000 state_changed[5] <= 1'b0; end always @(current_state[6]) begin state_changed[6] <= 1'b1; #1000 state_changed[6] <= 1'b0; end always @(current_state[7]) begin state_changed[7] <= 1'b1; #1000 state_changed[7] <= 1'b0; end //----------------------------------------- always @(new_rw[0]) begin new_rw_event[0] <= 1'b1; #1000 new_rw_event[0] <= 1'b0; end always @(new_rw[1]) begin new_rw_event[1] <= 1'b1; #1000 new_rw_event[1] <= 1'b0; end always @(new_rw[2]) begin new_rw_event[2] <= 1'b1; #1000 new_rw_event[2] <= 1'b0; end always @(new_rw[3]) begin new_rw_event[3] <= 1'b1; #1000 new_rw_event[3] <= 1'b0; end always @(new_rw[4]) begin new_rw_event[4] <= 1'b1; #1000 new_rw_event[4] <= 1'b0; end always @(new_rw[5]) begin new_rw_event[5] <= 1'b1; #1000 new_rw_event[5] <= 1'b0; end always @(new_rw[6]) begin new_rw_event[6] <= 1'b1; #1000 new_rw_event[6] <= 1'b0; end always @(new_rw[7]) begin new_rw_event[7] <= 1'b1; #1000 new_rw_event[7] <= 1'b0; end //----------------------------------------- always @(negedge write_finished[0]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[0] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[1]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[1] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[2]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[2] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[3]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[3] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[4]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[4] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[5]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[5] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[6]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[6] <= #(1000*tdevice_WR) TRUE; end always @(negedge write_finished[7]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); write_finished[7] <= #(1000*tdevice_WR) TRUE; end //----------------------------------------- always @(negedge wap_finished[0]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[0] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[1]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[1] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[2]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[2] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[3]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[3] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[4]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[4] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[5]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[5] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[6]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[6] <= #(WR *t_CK) TRUE; end always @(negedge wap_finished[7]) begin while (UDQSIn !== 1'b0) # (t_CK/4); while ((UDQSIn === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); wap_finished[7] <= #(WR *t_CK) TRUE; end //----------------------------------------- always @(negedge read_finished[0]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[0] <= TRUE; end always @(negedge read_finished[1]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[1] <= TRUE; end always @(negedge read_finished[2]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[2] <= TRUE; end always @(negedge read_finished[3]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[3] <= TRUE; end always @(negedge read_finished[4]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[4] <= TRUE; end always @(negedge read_finished[5]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[5] <= TRUE; end always @(negedge read_finished[6]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[6] <= TRUE; end always @(negedge read_finished[7]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); read_finished[7] <= TRUE; end //----------------------------------------- always @(negedge rap_finished[0]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[0] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[1]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[1] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[2]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[2] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[3]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[3] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[4]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[4] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[5]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[5] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[6]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[6] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end always @(negedge rap_finished[7]) begin while (UDQSOut_zd !== 1'b0) # (t_CK/4); while ((UDQSOut_zd === 1'b0) || (UDQSIn === 1'b1)) # (t_CK/4); rap_finished[7] <= #(1000*(tdevice_RP + tdevice_RTP)) TRUE; end //----------------------------------------- reg BuffInOE, BuffInCE, BuffInADDR; wire BuffOutOE, BuffOutCE, BuffOutADDR; BUFFER BUFOE (BuffOutOE , BuffInOE); BUFFER BUFCE (BuffOutCE , BuffInCE); BUFFER BUFADDR (BuffOutADDR, BuffInADDR); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInADDR = 1'b1; end always @(posedge BuffOutOE) begin end always @(posedge BuffOutCE) begin end always @(posedge BuffOutADDR) begin end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule