////////////////////////////////////////////////////////////////////////////// // File name : fm22l16.v ////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2009 Free Model Foundry; http://www.FreeModelFoundry.com // // MODIFICATION HISTORY: // // version: | author: | mod date: | changes made: // V1.0 J.Stoickov 09 May 13 Initial Release // ////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // // Library: RAM // Technology: F-RAM // Part: FM22L16 // // Description: 4Mbit (256K x 16 bit) Ferroelectric Nonvolatile RAM Memory // ////////////////////////////////////////////////////////////////////////////// // Known Bugs: // ////////////////////////////////////////////////////////////////////////////// // Comments : // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module fm22l16 ( A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, CENeg, OENeg, WENeg, ZZNeg, UBNeg, LBNeg ); //////////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations // //////////////////////////////////////////////////////////////////////////// input A17; input A16; input A15; input A14; input A13; input A12; input A11; input A10; input A9; input A8; input A7; input A6; input A5; input A4; input A3; input A2; input A1; input A0; inout DQ15; inout DQ14; inout DQ13; inout DQ12; inout DQ11; inout DQ10; inout DQ9; inout DQ8; inout DQ7; inout DQ6; inout DQ5; inout DQ4; inout DQ3; inout DQ2; inout DQ1; inout DQ0; input CENeg; input OENeg; input WENeg; input ZZNeg; input UBNeg; input LBNeg; // interconnect path delay signals wire A17_ipd ; wire A16_ipd ; wire A15_ipd ; wire A14_ipd ; wire A13_ipd ; wire A12_ipd ; wire A11_ipd ; wire A10_ipd ; wire A9_ipd ; wire A8_ipd ; wire A7_ipd ; wire A6_ipd ; wire A5_ipd ; wire A4_ipd ; wire A3_ipd ; wire A2_ipd ; wire A1_ipd ; wire A0_ipd ; wire [17 : 0] A; assign A = {A17_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire DQ15_ipd ; wire DQ14_ipd ; wire DQ13_ipd ; wire DQ12_ipd ; wire DQ11_ipd ; wire DQ10_ipd ; wire DQ9_ipd ; wire DQ8_ipd ; wire DQ7_ipd ; wire DQ6_ipd ; wire DQ5_ipd ; wire DQ4_ipd ; wire DQ3_ipd ; wire DQ2_ipd ; wire DQ1_ipd ; wire DQ0_ipd ; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire CENeg_ipd ; wire OENeg_ipd ; wire WENeg_ipd ; wire ZZNeg_ipd ; wire UBNeg_ipd ; wire LBENeg_ipd ; wire DQ15_pass; wire DQ14_pass; wire DQ13_pass; wire DQ12_pass; wire DQ11_pass; wire DQ10_pass; wire DQ9_pass; wire DQ8_pass; wire DQ7_pass; wire DQ6_pass; wire DQ5_pass; wire DQ4_pass; wire DQ3_pass; wire DQ2_pass; wire DQ1_pass; wire DQ0_pass; reg [15:0] DOut_zd; reg [15:0] Dout_pass; assign {DQ15_pass, DQ14_pass, DQ13_pass, DQ12_pass, DQ11_pass, DQ10_pass, DQ9_pass, DQ8_pass, DQ7_pass, DQ6_pass, DQ5_pass, DQ4_pass, DQ3_pass, DQ2_pass, DQ1_pass, DQ0_pass } = Dout_pass; parameter mem_file_name = "none"; parameter TimingModel = "FM22L16-55-TG"; parameter PartID = "fm22l16"; parameter MaxData = 255; parameter TotalLOC = 18'h3FFFF; parameter HiAbit = 17; parameter HiDbit = 7; parameter DataWidth = 8; parameter BlkNum = 7; parameter BlkSize = 16'h7FFF; // powerup reg PoweredUp; // FSM states parameter IDLE = 4'd0; parameter READ_1 = 4'd1; parameter READ_2 = 4'd2; parameter READ_3 = 4'd3; parameter READ_4 = 4'd4; parameter READ_5 = 4'd5; parameter READ_BYTE_PROT = 4'd6; parameter WRITE_1 = 4'd7; parameter WRITE_2 = 4'd8; parameter WRITE_3 = 4'd9; parameter READ_RETURN = 4'd10; parameter WRITE_RETURN = 4'd11; // states reg [3:0] current_state; reg [3:0] next_state ; //Command Register reg WRITE ; reg READ ; reg oe = 1'b0; reg OutputGen_Flag = 1'b0; integer NumBlk; //Value of the address bus integer AddressLatched ; integer Location = 0; reg[HiDbit:0] DataHDrive; reg[HiDbit:0] DataLDrive; integer DataTempH; integer DataTempL; reg[HiDbit:0] DTempH; reg[HiDbit:0] DTempL; //Protection byte reg[BlkNum:0] WriteProtByte; reg[BlkNum:0] TempProtByte; reg[BlkNum:0] ComplProtByte; integer CurrentReadPage; integer PreviousReadPage; integer CurrentWritePage; integer PreviousWritePage; reg InitialPageAccess; reg SubsequentPageAccess; reg[BlkNum:0] CorrectCompl; integer i; //TPD_XX_DATA time OEDQ_t; time CEDQ_t; time WEDQ_t; time ADDRDQ_t; time UBDQ_t; time LBDQ_t; time OENeg_event; time CENeg_event; time WENeg_event; time UBNeg_event; time LBNeg_event; time ADDR_event; reg FROMOE; reg FROMCE; reg FROMWE; reg FROMUB; reg FROMLB; integer OEDQ_01; integer CEDQ_01; integer WEDQ_01; integer UBDQ_01; integer LBDQ_01; integer UBDQ_01Z; integer LBDQ_01Z; integer ADDRDQIN_01; integer ADDRDQPAGE_01; integer ADDRDQIN_Z; integer ADDRDQPAGE_Z; reg[15:0] TempData; reg deq; // to check time between Address event and WENeg event time CheckTime; reg glitch = 0; // timing check violation reg Viol = 1'b0; integer MemDataH [0 : TotalLOC]; integer MemDataL [0 : TotalLOC]; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (CENeg_ipd , CENeg ); buf (OENeg_ipd , OENeg ); buf (WENeg_ipd , WENeg ); buf (ZZNeg_ipd , ZZNeg ); buf (UBNeg_ipd , UBNeg ); buf (LBNeg_ipd , LBNeg ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_pass , 1); nmos (DQ14, DQ14_pass , 1); nmos (DQ13, DQ13_pass , 1); nmos (DQ12, DQ12_pass , 1); nmos (DQ11, DQ11_pass , 1); nmos (DQ10, DQ10_pass , 1); nmos (DQ9 , DQ9_pass , 1); nmos (DQ8 , DQ8_pass , 1); nmos (DQ7 , DQ7_pass , 1); nmos (DQ6 , DQ6_pass , 1); nmos (DQ5 , DQ5_pass , 1); nmos (DQ4 , DQ4_pass , 1); nmos (DQ3 , DQ3_pass , 1); nmos (DQ2 , DQ2_pass , 1); nmos (DQ1 , DQ1_pass , 1); nmos (DQ0 , DQ0_pass , 1); // Needed for TimingChecks, VHDL CheckEnable Equivalent wire deg; wire NOT_PAGE_MODE; assign NOT_PAGE_MODE = InitialPageAccess && ~CENeg; wire PAGE_MODE; assign PAGE_MODE = SubsequentPageAccess && ~CENeg; wire InitialPage; assign InitialPage = InitialPageAccess; wire SubsequentPage; assign SubsequentPage = SubsequentPageAccess; wire CE_EQU_1; assign CE_EQU_1 = CENeg ; wire CE_EQU_0; assign CE_EQU_0 = ~CENeg ; wire CENeg_OENeg_check; assign CENeg_OENeg_check = ~CENeg && ~OENeg; wire deq_we; assign deq_we = deq && ~CENeg; wire deq_ce; assign deq_ce = deq && ~WENeg; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_A0_DQ0_InitialPageAccess_EQ_1 = 1;//taa, toh specparam tpd_A0_DQ0_SubsequentPageAccess_EQ_1 = 1;//taap, tohp specparam tpd_CENeg_DQ0 = 1;//tce, thz specparam tpd_OENeg_DQ0 = 1;//toe, tohz specparam tpd_WENeg_DQ0 = 1;//twx,twz specparam tpd_UBNeg_DQ0_READ = 1;//tba, tbhz specparam tpd_LBNeg_DQ0_READ = 1;//tba, tbhz specparam tpd_UBNeg_DQ0_WRITE = 1;//tba, tbhz specparam tpd_LBNeg_DQ0_WRITE = 1;//tba, tbhz specparam tpd_ZZNeg_DQ0 = 1;//tzzh // tsetup values specparam tsetup_A0_CENeg = 1; // tas edge \ specparam tsetup_A0_WENeg_no_page_mode = 1; // tawh edge / specparam tsetup_A0_WENeg_page_mode = 1; // tasp edge \ specparam tsetup_DQ0_WENeg = 1; // tds edge / specparam tsetup_DQ0_CENeg = 1; // tds edge / specparam tsetup_CENeg_WENeg_CE_EQU_0 = 1; // tcw edge / specparam tsetup_CENeg_WENeg_CE_EQU_1 = 1; // twh edge / specparam tsetup_WENeg_ZZNeg = 1; // twezz edge \ // thold values specparam thold_A0_CENeg = 1; // tah edge \ specparam thold_CENeg_WENeg_CE_EQU_0 = 1; // twlc edge \ specparam thold_CENeg_WENeg_CE_EQU_1 = 1; // tws edge \ specparam thold_A0_WENeg_no_page_mode = 1; // twla edge \ specparam thold_A0_WENeg_page_mode = 1; // tahp edge \ specparam thold_DQ0_WENeg = 1; // tdh edge / specparam thold_DQ0_CENeg = 1; // tdh edge / specparam thold_CENeg_ZZNeg_CE_EQU_0 = 1; // tzzen edge \ specparam thold_CENeg_ZZNeg = 1; // tzzex edge / // tpw values: pulse width specparam tpw_A0_negedge = 1; // trc,twc specparam tpw_WENeg_negedge = 1; // twp specparam tpw_CENeg_negedge = 1; // tca specparam tpw_CENeg_posedge = 1; // tpc specparam tpw_ZZNeg_negedge = 1; // tzzl // tperiod values specparam tperiod_WENeg_negedge = 1; // tpwc /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// if(InitialPageAccess) (A0=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A0=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A1=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A2=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A3=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A4=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A5=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A6=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A7=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A8=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A9=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A10=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A11=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A12=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A13=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A14=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A15=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A16=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ0) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ1) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ2) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ3) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ4) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ5) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ6) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ7) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ8) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ9) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ10) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ11) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ12) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ13) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ14) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(InitialPageAccess) (A17=>DQ15) =tpd_A0_DQ0_InitialPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ0) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ1) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ2) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ3) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ4) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ5) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ6) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ7) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ8) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ9) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ10) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ11) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ12) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ13) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ14) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A0=>DQ15) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ0) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ1) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ2) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ3) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ4) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ5) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ6) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ7) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ8) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ9) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ10) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ11) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ12) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ13) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ14) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if(SubsequentPageAccess) (A1=>DQ15) =tpd_A0_DQ0_SubsequentPageAccess_EQ_1; if (FROMCE) ( CENeg => DQ0 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ1 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ2 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ3 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ4 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ5 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ6 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ7 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ8 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ9 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ10 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ11 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ12 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ13 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ14 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ15 ) = tpd_CENeg_DQ0; if (FROMOE) ( OENeg => DQ0 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ1 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ2 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ3 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ4 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ5 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ6 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ7 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ8 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ9 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ10 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ11 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ12 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ13 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ14 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ15 ) = tpd_OENeg_DQ0; if (FROMUB) ( UBNeg => DQ8 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ9 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ10 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ11 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ12 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ13 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ14 ) = tpd_UBNeg_DQ0_READ; if (FROMUB) ( UBNeg => DQ15 ) = tpd_UBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ0 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ1 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ2 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ3 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ4 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ5 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ6 ) = tpd_LBNeg_DQ0_READ; if (FROMLB) ( LBNeg => DQ7 ) = tpd_LBNeg_DQ0_READ; if (~WENeg) ( UBNeg => DQ8 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ9 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ10 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ11 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ12 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ13 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ14 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( UBNeg => DQ15 ) = tpd_UBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ0 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ1 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ2 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ3 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ4 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ5 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ6 ) = tpd_LBNeg_DQ0_WRITE; if (~WENeg) ( LBNeg => DQ7 ) = tpd_LBNeg_DQ0_WRITE; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ0) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ1) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ2) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ3) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ4) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ5) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ6) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ7) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ8) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ9) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ10) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ11) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ12) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ13) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ14) =tpd_WENeg_DQ0; if (FROMWE && CENeg_OENeg_check) (WENeg=>DQ15) =tpd_WENeg_DQ0; (ZZNeg=>DQ0) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ1) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ2) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ3) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ4) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ5) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ6) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ7) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ8) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ9) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ10) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ11) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ12) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ13) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ14) =tpd_ZZNeg_DQ0; (ZZNeg=>DQ15) =tpd_ZZNeg_DQ0; //////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////// $setup ( A0 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A1 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A2 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A3 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A4 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A5 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A6 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A7 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A8 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A9 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A10 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A11 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A12 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A13 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A14 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A15 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A16 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A17 , negedge CENeg, tsetup_A0_CENeg, Viol); $setup ( A0 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A1 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A2 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A3 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A4 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A5 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A6 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A7 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A8 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A9 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A10 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A11 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A12 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A13 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A14 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A15 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A16 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A17 , posedge WENeg &&& NOT_PAGE_MODE, tsetup_A0_WENeg_no_page_mode, Viol); $setup ( A0 , negedge WENeg &&& PAGE_MODE, tsetup_A0_WENeg_page_mode, Viol); $setup ( A1 , negedge WENeg &&& PAGE_MODE, tsetup_A0_WENeg_page_mode, Viol); $setup ( DQ0 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge CENeg &&& deq_ce, tsetup_DQ0_CENeg, Viol); $setup ( DQ0 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ1 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ2 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ3 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ4 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ5 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ6 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ7 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ8 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ9 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ10 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ11 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ12 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ13 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ14 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( DQ15 , posedge WENeg &&& deq_we, tsetup_DQ0_WENeg, Viol); $setup ( CENeg , posedge WENeg &&& CE_EQU_0, tsetup_CENeg_WENeg_CE_EQU_0, Viol); $setup ( CENeg , posedge WENeg &&& CE_EQU_1, tsetup_CENeg_WENeg_CE_EQU_1, Viol); $setup ( WENeg , negedge ZZNeg &&& WENeg, tsetup_WENeg_ZZNeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A0 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A1 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A2 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A3 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A4 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A5 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A6 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A7 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A8 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A9 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A10 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A11 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A12 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A13 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A14 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A15 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A16 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===1), A17 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& CE_EQU_0 ,CENeg , thold_CENeg_WENeg_CE_EQU_0,Viol); $hold ( negedge WENeg &&& CE_EQU_1 ,CENeg , thold_CENeg_WENeg_CE_EQU_1,Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A0 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A1 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A2 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A3 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A4 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A5 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A6 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A7 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A8 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A9 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A10 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A11 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A12 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A13 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A14 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A15 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A16 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& NOT_PAGE_MODE, A17 , thold_A0_WENeg_no_page_mode, Viol); $hold ( negedge WENeg &&& PAGE_MODE, A0 , thold_A0_WENeg_page_mode, Viol); $hold ( negedge WENeg &&& PAGE_MODE, A1 , thold_A0_WENeg_page_mode, Viol); $hold ( posedge CENeg &&& deq_ce, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ1 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ2 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ3 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ4 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ5 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ6 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ7 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ8 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ9 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ10 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ11 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ12 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ13 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ14 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deq_ce, DQ15 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ0 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ1 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ2 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ3 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ4 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ5 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ6 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ7 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ8 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ9 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ10 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ11 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ12 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ13 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ14 , thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& deq_we, DQ15 , thold_DQ0_WENeg, Viol); $hold ( negedge ZZNeg &&& CE_EQU_0 ,CENeg , thold_CENeg_ZZNeg_CE_EQU_0,Viol); $hold ( posedge ZZNeg ,CENeg ,thold_CENeg_ZZNeg,Viol); $width (posedge A0 &&& InitialPage, tpw_A0_negedge); $width (posedge A1 &&& InitialPage, tpw_A0_negedge); $width (posedge A2 &&& InitialPage, tpw_A0_negedge); $width (posedge A3 &&& InitialPage, tpw_A0_negedge); $width (posedge A4 &&& InitialPage, tpw_A0_negedge); $width (posedge A5 &&& InitialPage, tpw_A0_negedge); $width (posedge A6 &&& InitialPage, tpw_A0_negedge); $width (posedge A7 &&& InitialPage, tpw_A0_negedge); $width (posedge A8 &&& InitialPage, tpw_A0_negedge); $width (posedge A9 &&& InitialPage, tpw_A0_negedge); $width (posedge A10 &&& InitialPage, tpw_A0_negedge); $width (posedge A11 &&& InitialPage, tpw_A0_negedge); $width (posedge A12 &&& InitialPage, tpw_A0_negedge); $width (posedge A13 &&& InitialPage, tpw_A0_negedge); $width (posedge A14 &&& InitialPage, tpw_A0_negedge); $width (posedge A15 &&& InitialPage, tpw_A0_negedge); $width (posedge A16 &&& InitialPage, tpw_A0_negedge); $width (posedge A17 &&& InitialPage, tpw_A0_negedge); $width (negedge A0 &&& InitialPage, tpw_A0_negedge); $width (negedge A1 &&& InitialPage, tpw_A0_negedge); $width (negedge A2 &&& InitialPage, tpw_A0_negedge); $width (negedge A3 &&& InitialPage, tpw_A0_negedge); $width (negedge A4 &&& InitialPage, tpw_A0_negedge); $width (negedge A5 &&& InitialPage, tpw_A0_negedge); $width (negedge A6 &&& InitialPage, tpw_A0_negedge); $width (negedge A7 &&& InitialPage, tpw_A0_negedge); $width (negedge A8 &&& InitialPage, tpw_A0_negedge); $width (negedge A9 &&& InitialPage, tpw_A0_negedge); $width (negedge A10 &&& InitialPage, tpw_A0_negedge); $width (negedge A11 &&& InitialPage, tpw_A0_negedge); $width (negedge A12 &&& InitialPage, tpw_A0_negedge); $width (negedge A13 &&& InitialPage, tpw_A0_negedge); $width (negedge A14 &&& InitialPage, tpw_A0_negedge); $width (negedge A15 &&& InitialPage, tpw_A0_negedge); $width (negedge A16 &&& InitialPage, tpw_A0_negedge); $width (negedge A17 &&& InitialPage, tpw_A0_negedge); $width (negedge WENeg, tpw_WENeg_negedge); $width (posedge CENeg, tpw_CENeg_posedge); $width (negedge CENeg, tpw_CENeg_negedge); $width (negedge ZZNeg, tpw_ZZNeg_negedge); $period(negedge WENeg &&& SubsequentPage, tperiod_WENeg_negedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// reg rising_edge_CENeg, falling_edge_CENeg; reg rising_edge_WENeg, falling_edge_WENeg; reg rising_edge_OENeg, falling_edge_OENeg; reg rising_edge_LBNeg, rising_edge_UBNeg; reg falling_edge_LBNeg, falling_edge_UBNeg; reg falling_edge_WRITE, rising_edge_oe; reg falling_edge_ZZNeg; reg A_event, D_event,AddressLatched_event ; // Power Up time tpu is 450 us initial begin : PowerupTime PoweredUp = 1'b0; #450000 PoweredUp = 1'b1; end // process for glitch always @(ADDR_event, WENeg_event) begin : DoutGenerate CheckTime = ADDR_event-WENeg_event ; if (CheckTime < WEDQ_01) glitch = 1; else glitch = 0; end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(negedge OENeg) begin OENeg_event = $time; end always @(negedge CENeg) begin CENeg_event = $time; end always @(posedge WENeg) begin WENeg_event = $time; end always @(negedge UBNeg) begin UBNeg_event = $time; end always @(negedge LBNeg) begin LBNeg_event = $time; end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(DOut_zd,falling_edge_UBNeg,falling_edge_LBNeg) begin : OutputGen if ((DOut_zd[0] !== 1'bz || DOut_zd[8] !== 1'bz)) begin OutputGen_Flag = 1'b1; CEDQ_t = CENeg_event + CEDQ_01; OEDQ_t = OENeg_event + OEDQ_01; WEDQ_t = WENeg_event + WEDQ_01; UBDQ_t = UBNeg_event + UBDQ_01; LBDQ_t = LBNeg_event + LBDQ_01; ADDRDQ_t = ADDR_event + ADDRDQIN_01; if (SubsequentPageAccess) ADDRDQ_t = ADDR_event + ADDRDQPAGE_01; FROMCE = ((CEDQ_t > OEDQ_t) && (CEDQ_t > WEDQ_t) && (CEDQ_t > UBDQ_t) && (CEDQ_t > LBDQ_t) && (CEDQ_t >= $time)); FROMOE = ((OEDQ_t > CEDQ_t) && (OEDQ_t > WEDQ_t) && (OEDQ_t > UBDQ_t) && (OEDQ_t > LBDQ_t) && (OEDQ_t >= $time)); FROMWE = ((WEDQ_t > CEDQ_t) && (WEDQ_t > OEDQ_t) && (WEDQ_t >= ADDRDQ_t ) && (WEDQ_t > UBDQ_t) && (WEDQ_t > LBDQ_t) && (WEDQ_t >= $time)); FROMUB = ((UBDQ_t > OEDQ_t) && (UBDQ_t > CEDQ_t) && (UBDQ_t >= ADDRDQ_t) && (UBDQ_t > WEDQ_t) && (UBDQ_t >= $time)); FROMLB = ((LBDQ_t > CEDQ_t) && (LBDQ_t > OEDQ_t) && (LBDQ_t >= ADDRDQ_t) && (LBDQ_t > WEDQ_t) && (LBDQ_t >= $time)); if (OEDQ_t < $time && CEDQ_t < $time && ADDRDQ_t > $time ) begin if ((falling_edge_LBNeg || falling_edge_UBNeg) && ~SubsequentPageAccess) begin #(LBDQ_01-1) Dout_pass = 16'bz; Dout_pass = DOut_zd ; if (~SubsequentPageAccess) Dout_pass <= #(ADDRDQ_t- ADDRDQIN_Z- $time ) 16'bzz; else Dout_pass <= #(ADDRDQ_t- ADDRDQPAGE_Z- $time ) 16'bzz; end else if (glitch ) begin if (~SubsequentPageAccess) Dout_pass <= #(ADDRDQ_t- ADDRDQIN_Z- $time +10) 16'bzz; else Dout_pass <= #(ADDRDQ_t- ADDRDQPAGE_Z- $time +5)16'bzz; end else Dout_pass = 16'bzz; Dout_pass <= # ( ADDRDQ_t - $time ) DOut_zd; end else begin Dout_pass = DOut_zd; end OutputGen_Flag <= #10 1'b0; end end always @(DOut_zd) begin if (DOut_zd === 16'bz && ~OutputGen_Flag) begin disable OutputGen; FROMCE = 1'b1; FROMOE = 1'b1; FROMWE = 1'b1; FROMUB = 1'b1; FROMLB = 1'b1; Dout_pass = DOut_zd; if ((falling_edge_LBNeg || falling_edge_UBNeg) && ~SubsequentPageAccess) begin #(LBDQ_01-1) Dout_pass = 16'bz; Dout_pass = DOut_zd ; if (~SubsequentPageAccess) Dout_pass <= #(ADDRDQ_t- ADDRDQIN_Z- $time ) 16'bzz; else Dout_pass <= #(ADDRDQ_t- ADDRDQPAGE_Z- $time ) 16'bzz; end end end always @(DOut_zd) begin if (DOut_zd[7:0] === 8'bz && LBNeg && ~FROMCE && ~FROMOE && ~FROMWE ) begin if (glitch) begin FROMLB = 1'b1; Dout_pass[7:0] <= # (LBDQ_01Z-1) DOut_zd[7:0]; end else begin FROMLB = 1'b1; Dout_pass[7:0] <= DOut_zd[7:0]; end end else if (DOut_zd[15:8] === 8'bz && UBNeg && ~FROMCE && ~FROMOE && ~FROMWE ) begin if (glitch) begin FROMUB = 1'b1; Dout_pass[15:8] <= # (UBDQ_01Z-1) DOut_zd[15:8]; end else begin FROMUB = 1'b1; Dout_pass[15:8] <= DOut_zd[15:8]; end end end initial begin WRITE = 1'b1; READ = 1'b1; PreviousReadPage = -1; PreviousWritePage = -1; Location = 0; current_state = IDLE; next_state = IDLE; for(i=0;i<=7;i=i+1) WriteProtByte[i] = 0; end /////////////////////////////////////////////////////////////////////////// //Latch address on falling edge of WE# or CE# what ever comes later //Latches data on rising edge of WE# or CE# what ever comes first // also Write cycle decode /////////////////////////////////////////////////////////////////////////// // Address Latch and Bus Cycle Decode always @(A_event, falling_edge_WENeg, falling_edge_CENeg,D_event, rising_edge_WENeg, rising_edge_CENeg, falling_edge_OENeg, falling_edge_UBNeg, falling_edge_LBNeg,AddressLatched_event) begin : BusCycleDecode if (PoweredUp!=1'b0 && ZZNeg !=1'b0) begin // WRITE Address Latch if ((falling_edge_WENeg && ~CENeg) || (falling_edge_CENeg && ~WENeg) || (falling_edge_WENeg && falling_edge_CENeg)) begin AddressLatched = A[HiAbit:0]; CurrentWritePage = ( AddressLatched / 4 ); SubsequentPageAccess =( PreviousWritePage == CurrentWritePage ); InitialPageAccess = ~SubsequentPageAccess; end //WRITE Data Latch if (D_event && ~CENeg && ~WENeg ) begin if (~LBNeg) DTempL = DIn[7 : 0]; if (~UBNeg) DTempH = DIn[15 : 8]; end if((rising_edge_WENeg && ~CENeg )|| (rising_edge_CENeg && ~WENeg)|| (rising_edge_WENeg && rising_edge_CENeg)) begin if (~LBNeg || rising_edge_LBNeg) DataTempL = DTempL; if (~UBNeg || rising_edge_UBNeg) DataTempH = DTempH; Location = AddressLatched; WRITE = 1'b0; #1 WRITE <= 1'b1; if (~OENeg && (WENeg ||rising_edge_WENeg)) begin READ = 1'b0; #1 READ <= 1'b1; end end //Read Address Latch if (falling_edge_CENeg && WENeg) begin AddressLatched = A[HiAbit:0]; Location = AddressLatched; end if (A_event && ~CENeg && ~OENeg && WENeg) begin ADDR_event = $time; CurrentReadPage = ( A[HiAbit:0] / 4 ); SubsequentPageAccess = ( PreviousReadPage == CurrentReadPage ); InitialPageAccess = ~SubsequentPageAccess; if (InitialPageAccess) //wait output hold time AddressLatched <= #(ADDRDQIN_Z-1) A[HiAbit:0]; else AddressLatched <= #(ADDRDQPAGE_Z-1) A[HiAbit:0]; end if ((falling_edge_OENeg && ~CENeg && WENeg) || (falling_edge_CENeg && ~OENeg && WENeg)) begin CurrentReadPage = ( AddressLatched / 4 ); SubsequentPageAccess = ( PreviousReadPage == CurrentReadPage ); InitialPageAccess = ~SubsequentPageAccess; READ = 1'b0; #1 READ <= 1'b1; end if ((falling_edge_UBNeg && ~CENeg && ~OENeg && WENeg ) || (falling_edge_LBNeg && ~CENeg && ~OENeg && WENeg)) begin READ = 1'b0; #1 READ <= 1'b1; end if ((AddressLatched_event && ~CENeg && ~OENeg && WENeg ) ) begin Location = AddressLatched; READ <= 1'b0; READ <= #1 1'b1; end end end // Terminate Page Access always @(posedge CENeg) begin PreviousReadPage = -1; PreviousWritePage = -1; CurrentReadPage = -1; CurrentWritePage = -1; end ////////////////////////////////////////////////////////////////////////// // Page Access Control Process ////////////////////////////////////////////////////////////////////////// always @(posedge READ) begin PreviousReadPage = CurrentReadPage; oe = 1'b1; oe <= #1 1'b0; end always @(posedge WRITE) begin PreviousWritePage = CurrentWritePage; end always @(next_state) begin: StateTransition #1 current_state <= next_state; end always @(falling_edge_ZZNeg) begin: SleepMode #1 current_state <= IDLE; end /////////////////////////////////////////////////////////////////////////// //// Main Behavior Process //// combinational process for next state generation /////////////////////////////////////////////////////////////////////////// always @(falling_edge_WRITE, falling_edge_CENeg, rising_edge_CENeg, rising_edge_oe) begin: StateGen1 if (PoweredUp!=1'b0 && ZZNeg !=1'b0) begin case (current_state) IDLE : begin if (falling_edge_CENeg) begin if (Location == 18'h24555) next_state = READ_1; else next_state = IDLE; end end READ_1 : begin if (falling_edge_CENeg) begin if (Location == 18'h3AAAA) next_state = READ_2; else next_state = IDLE; end else if (falling_edge_WRITE) next_state = IDLE; end READ_2 : begin if (falling_edge_CENeg) begin if (Location == 18'h2333) next_state = READ_3; else next_state = IDLE; end else if (falling_edge_WRITE) next_state = IDLE; end READ_3 : begin if (falling_edge_CENeg) begin if (Location == 18'h1CCCC) next_state = READ_4; else next_state = IDLE; end else if (falling_edge_WRITE) next_state = IDLE; end READ_4 : begin if (falling_edge_CENeg) begin if (Location == 18'h000FF) next_state = READ_5; else next_state = IDLE; end else if (falling_edge_WRITE) next_state = IDLE; end READ_5 : begin if (falling_edge_CENeg) begin if (Location == 18'h3EF00) next_state = WRITE_1; else next_state = IDLE; end else if (falling_edge_WRITE) next_state = IDLE; end WRITE_1 : begin if (Location == 18'h3AAAA ) begin if (falling_edge_WRITE) next_state = WRITE_2; else if (rising_edge_CENeg || rising_edge_oe) next_state = IDLE; end else if (Location == 18'h1CCCC ) begin if (falling_edge_WRITE) next_state = READ_BYTE_PROT; else if (rising_edge_CENeg) next_state = IDLE; end else if (falling_edge_CENeg && Location != 18'h3AAAA && Location != 18'h1CCCC ) next_state = IDLE; else if (falling_edge_WRITE) next_state = IDLE; end WRITE_2 : begin if (Location == 18'h1CCCC ) begin if (falling_edge_WRITE) next_state = WRITE_3; else if (rising_edge_CENeg || rising_edge_oe) next_state = IDLE; end else if (falling_edge_CENeg && Location != 18'h1CCCC ) next_state = IDLE; end WRITE_3 : begin if (Location == 18'h0FF00 ) begin if (falling_edge_WRITE ) begin if (CorrectCompl == 8'hFF) next_state = WRITE_RETURN; else next_state = IDLE; end else if (rising_edge_CENeg || rising_edge_oe) next_state = IDLE; end else if (falling_edge_CENeg && Location != 18'h0FF00 ) next_state = IDLE; end READ_BYTE_PROT : begin if (Location == 18'h1AAAA) begin if (rising_edge_oe) next_state = READ_RETURN; end else next_state = IDLE; if (falling_edge_WRITE) next_state = IDLE; end WRITE_RETURN : begin if (falling_edge_CENeg) begin if (Location == 18'h00000) next_state = IDLE; else next_state = WRITE_RETURN; end end READ_RETURN : begin if (falling_edge_CENeg) begin if (Location == 18'h00000) next_state = IDLE; else next_state = READ_RETURN; end end endcase end end /////////////////////////////////////////////////////////////////////////// //FSM Output generation and general funcionality /////////////////////////////////////////////////////////////////////////// always @(falling_edge_WRITE, rising_edge_oe, current_state, falling_edge_CENeg, rising_edge_CENeg) begin : Functional if (PoweredUp!=1'b0 && ZZNeg !=1'b0) begin case (current_state) IDLE : begin if(rising_edge_oe) ReadMem; else if(falling_edge_WRITE) begin NumBlk = ReturnBank(Location); WriteMem(NumBlk); end end READ_1 : begin AddressSeguence (18'h3AAAA); end READ_2 : begin AddressSeguence (18'h2333); end READ_3 : begin AddressSeguence (18'h1CCCC); end READ_4 : begin AddressSeguence (18'h000FF); end READ_5 : begin AddressSeguence (18'h3EF00); end WRITE_1 : begin if (Location == 18'h3AAAA ) begin if (falling_edge_WRITE) TempProtByte = DTempL; else if (rising_edge_CENeg || rising_edge_oe) begin $display (" Write-protect process is aborted! "); $display (" Seventh read adrress is issued "); end if (rising_edge_oe) ReadMem; end else if (Location == 18'h1CCCC ) begin if (falling_edge_WRITE) $display (" Read protect process is started! "); else if (rising_edge_CENeg || rising_edge_oe) begin $display (" Read process is aborted! "); $display (" Seventh read adrress is issued "); end if (rising_edge_oe) ReadMem; end else if (falling_edge_CENeg && Location != 18'h3AAAA && Location != 18'h1CCCC ) begin $display (" Wrong address: %h", Location); $display (" Write-protect process is aborted! "); end else if (rising_edge_oe ) ReadMem; else if (falling_edge_WRITE) $display (" Process is aborted! "); end WRITE_2 : begin if (Location == 18'h1CCCC ) begin if (falling_edge_WRITE) begin ComplProtByte = DTempL; CorrectCompl = TempProtByte ^ ComplProtByte; end else if (rising_edge_CENeg || rising_edge_oe) begin $display (" Write-protect process is aborted! "); $display (" Write operation must be issued "); end if (rising_edge_oe) ReadMem; end else if (falling_edge_CENeg && Location != 18'h1CCCC ) begin $display (" Wrong address: %h", Location); $display (" Write-protect process is aborted! "); end end WRITE_3 : begin if (Location == 18'h0FF00) begin if (falling_edge_WRITE ) begin if ( CorrectCompl != 8'hFF) begin $display ("Complement of the protection byte "); $display (" is incorrect, "); $display ("Write-protect process is aborted! "); end end else if (rising_edge_CENeg || rising_edge_oe) begin $display (" Write-protect process is aborted! "); $display (" Write operation must be issued "); end if (rising_edge_oe) ReadMem; end else if (falling_edge_CENeg && Location != 18'h1CCCC ) begin $display (" Wrong address: %h", Location); $display (" Write-protect process is aborted! "); end end READ_BYTE_PROT : begin if ( Location == 18'h1AAAA) begin if (rising_edge_oe) begin DOut_zd [7:0] = WriteProtByte; $display (" Protection data byte is , %h", WriteProtByte); end end else if (falling_edge_CENeg && Location != 18'h1AAAA ) begin $display (" Read from wrong address: %h", Location); $display (" Read process is aborted! "); end end WRITE_RETURN : begin if(falling_edge_CENeg) begin if ( Location == 18'h00000) begin WriteProtByte = TempProtByte; $display (" Return to Normal Operation, "); $display (" Protection data byte is set. "); end else begin $display (" Read from wrong address: %h", Location); $display (" Read from 0000 address will return "); $display (" device to Normal Operation and "); $display (" Protection data byte will be set ! "); end end if (rising_edge_oe) ReadMem; end READ_RETURN : begin if(falling_edge_CENeg) begin if ( Location == 18'h00000) begin $display (" Return to Normal Operation! "); end else begin $display (" Read from wrong address: %h", Location); $display (" Read from 0000 address will return "); $display (" device to Normal Operation! "); end end if (rising_edge_oe) ReadMem; end endcase end end //Output Disable Control always @(posedge CENeg) begin DOut_zd = 16'bZ; end //Output Disable Control always @(posedge OENeg) begin DOut_zd = 16'bZ; end //Output Disable Control always @(negedge ZZNeg) begin DOut_zd = 16'bZ; end //Output Disable Control always @(negedge WENeg) begin DOut_zd = 16'bZ; end //Output Disable Control always @(posedge UBNeg) begin #1 DOut_zd[15:8] = 8'bZ; end //Output Disable Control always @(posedge LBNeg) begin #1 DOut_zd[7:0] = 8'bZ; end ///////////////////////////////////////////////////////////////////////////// ////Read Memory task ///////////////////////////////////////////////////////////////////////////// task ReadMem; begin if (~LBNeg) begin DataTempL = MemDataL[Location]; DataLDrive = 8'bxxxx; if (DataTempL >= 0) DataLDrive = DataTempL; DOut_zd [7:0]<= DataLDrive; end if (~UBNeg) begin DataTempH = MemDataH[Location]; DataHDrive = 8'bxxxx; if (DataTempH >= 0) DataHDrive = DataTempH; DOut_zd [15:8]<=DataHDrive; end end endtask ///////////////////////////////////////////////////////////////////////////// ////Write Memory task ///////////////////////////////////////////////////////////////////////////// task WriteMem; input integer NumBlock; begin if (~UBNeg || rising_edge_UBNeg) begin if (WriteProtByte[NumBlock] !=1'b1) begin MemDataH[Location] = -1; if (~Viol) MemDataH[Location] = DataTempH; end end if (~LBNeg || rising_edge_LBNeg) begin if (WriteProtByte[NumBlock] !=1'b1) begin MemDataL[Location] = -1; if (~Viol) MemDataL[Location] = DataTempL; end end end endtask ///////////////////////////////////////////////////////////////////////////// ////Adrress sequence task ///////////////////////////////////////////////////////////////////////////// task AddressSeguence; input integer ReadAddr; begin if (falling_edge_CENeg) begin if (Location != ReadAddr) begin $display (" Read from wrong address: %h", Location); $display (" Process is aborted! "); end end if (rising_edge_oe) begin ReadMem; end if (falling_edge_WRITE) $display (" Process is aborted! "); end endtask ///////////////////////////////////////////////////////////////////////////// ////Determination number of block ///////////////////////////////////////////////////////////////////////////// function integer ReturnBank; input integer ADDR; begin ReturnBank = ADDR / (BlkSize +1); end endfunction always @(negedge CENeg) begin falling_edge_CENeg = 1; #1 falling_edge_CENeg = 0; end always @(negedge WENeg) begin falling_edge_WENeg = 1; #1 falling_edge_WENeg = 0; end always @(posedge CENeg) begin rising_edge_CENeg = 1; #1 rising_edge_CENeg = 0; end always @(posedge WENeg) begin rising_edge_WENeg = 1; #1 rising_edge_WENeg = 0; end always @(negedge OENeg) begin falling_edge_OENeg = 1; #1 falling_edge_OENeg = 0; end always @(posedge OENeg) begin rising_edge_OENeg = 1; #1 rising_edge_OENeg = 0; end always @(posedge LBNeg) begin rising_edge_LBNeg = 1; #1 rising_edge_LBNeg = 0; end always @(posedge UBNeg) begin rising_edge_UBNeg = 1; #1 rising_edge_UBNeg = 0; end always @(negedge LBNeg) begin #1 falling_edge_LBNeg = 1; #1 falling_edge_LBNeg = 0; end always @(negedge UBNeg) begin #1 falling_edge_UBNeg = 1; #1 falling_edge_UBNeg = 0; end always @(negedge ZZNeg) begin falling_edge_ZZNeg = 1; #1 falling_edge_ZZNeg = 0; end always @(A) begin A_event = 1; #1 A_event = 0; end always @(AddressLatched) begin AddressLatched_event = 1; #1 AddressLatched_event = 0; end always @(DIn) begin D_event = 1; #1 D_event = 0; end always @(posedge oe) begin rising_edge_oe = 1; #1 rising_edge_oe = 0; end always @(negedge WRITE) begin falling_edge_WRITE = 1; #1 falling_edge_WRITE = 0; end reg BuffInOE, BuffInCE, BuffInADDR_Initial, BuffInADDR_Subsequent, BuffInWE, BuffInUB, BuffInLB, BuffInADDR_InitialZ, BuffInADDR_SubsequentZ , BuffInUBZ, BuffInLBZ; wire BuffOutOE, BuffOutCE, BuffOutADDR_Initial, BuffOutADDR_Subsequent, BuffOutWE, BuffOutUB, BuffOutLB, BuffOutADDR_InitialZ, BuffOutADDR_SubsequentZ, BuffOutUBZ, BuffOutLBZ; BUFFER BUFOE (BuffOutOE , BuffInOE); BUFFER BUFCE (BuffOutCE , BuffInCE); BUFFER BUFWE (BuffOutWE , BuffInWE); BUFFER BUFUB (BuffOutUB , BuffInUB); BUFFER BUFLB (BuffOutLB , BuffInLB); BUFFER BUFUBZ (BuffOutUBZ , BuffInUBZ); BUFFER BUFLBZ (BuffOutLBZ , BuffInLBZ); BUFFER BUFADDRIN (BuffOutADDR_Initial , BuffInADDR_Initial ); BUFFER BUFADDRPAGE (BuffOutADDR_Subsequent, BuffInADDR_Subsequent); BUFFER BUFADDRINZ (BuffOutADDR_InitialZ , BuffInADDR_InitialZ ); BUFFER BUFADDRPAGEZ (BuffOutADDR_SubsequentZ, BuffInADDR_SubsequentZ); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInWE = 1'b1; BuffInUB = 1'b1; BuffInLB = 1'b1; BuffInUBZ = 1'b1; BuffInLBZ = 1'b1; BuffInADDR_Initial = 1'b1; BuffInADDR_Subsequent = 1'b1; BuffInADDR_InitialZ = 1'b1; BuffInADDR_SubsequentZ = 1'b1; end always @(posedge BuffOutOE) begin OEDQ_01 = $time; end always @(posedge BuffOutCE) begin CEDQ_01 = $time; end always @(posedge BuffOutWE) begin WEDQ_01 = $time; end always @(posedge BuffOutUB) begin UBDQ_01 = $time; end always @(posedge BuffOutLB) begin LBDQ_01 = $time; end always @(posedge BuffOutUBZ) begin UBDQ_01Z = $time; end always @(posedge BuffOutLBZ) begin LBDQ_01Z = $time; end always @(posedge BuffOutADDR_Initial) begin ADDRDQIN_01 = $time; end always @(posedge BuffOutADDR_Subsequent) begin ADDRDQPAGE_01 = $time; end always @(posedge BuffOutADDR_InitialZ) begin ADDRDQIN_Z = $time; end always @(posedge BuffOutADDR_SubsequentZ) begin ADDRDQPAGE_Z = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf (OUT, IN); endmodule