////////////////////////////////////////////////////////////////////////////// // File name : edj1308ba.v ////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY : // // version: | author: | mod date: | changes made: // V1.0 S.Janevski 07 Jan 17 Initial release // V1.1 R.Miodragovic 07 June 22 Correction of state // transitions with warnings; // Implemented warnings for // time delays; // Start address of write // burst is corrected; ////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // Library: RAM // Technology: CMOS // Part: EDJ1308BA // // Description: 1024 Mb (16 M Words x 8 bits x 8 banks) DDR3 SDRAM // ////////////////////////////////////////////////////////////////////////////// // Comments : // For correct simulation, simulator resolution should be set to 1ps // ////////////////////////////////////////////////////////////////////////////// // Known Bugs: // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps module edj1308ba ( BA2, BA1, BA0, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, ODT, CK, CKNeg, CKE, CSNeg, RASNeg, CASNeg, WENeg, TDQS, TDQSNeg, DQS, DQSNeg, RESETNeg ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input BA2; input BA1; input BA0; input A13; input A12; input A11; input A10; input A9; input A8; input A7; input A6; input A5; input A4; input A3; input A2; input A1; input A0; inout DQ7 ; inout DQ6 ; inout DQ5 ; inout DQ4 ; inout DQ3 ; inout DQ2 ; inout DQ1 ; inout DQ0 ; input ODT; input CK; input CKNeg; input CKE; input CSNeg; input RASNeg; input CASNeg; input WENeg; inout TDQS; inout TDQSNeg; inout DQS; inout DQSNeg; input RESETNeg; // interconnect path delay signals wire BA2_ipd; wire BA1_ipd; wire BA0_ipd; wire A13_ipd; wire A12_ipd; wire A11_ipd; wire A10_ipd; wire A9_ipd; wire A8_ipd; wire A7_ipd; wire A6_ipd; wire A5_ipd; wire A4_ipd; wire A3_ipd; wire A2_ipd; wire A1_ipd; wire A0_ipd; wire DQ7_ipd; wire DQ6_ipd; wire DQ5_ipd; wire DQ4_ipd; wire DQ3_ipd; wire DQ2_ipd; wire DQ1_ipd; wire DQ0_ipd; wire ODT_ipd; wire CK_ipd; wire CKNeg_ipd; wire CKE_ipd; wire CSNeg_ipd ; wire RASNeg_ipd; wire CASNeg_ipd; wire WENeg_ipd; wire TDQS_ipd; wire TDQSNeg_ipd; wire DQS_ipd; wire DQSNeg_ipd; wire RESETNeg_ipd; wire [2 : 0] BA; assign BA = {BA2_ipd, BA1_ipd, BA0_ipd }; wire [13 : 0] A; assign A = { A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire [7 : 0 ] DIn; assign DIn = { DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [7 : 0 ] DOut; assign DOut ={ DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire DQSIn; assign DQSIn = DQS_ipd; wire DQSOut; assign DQSOut = DQS; wire TDQSIn; assign TDQSIn = TDQS_ipd; wire TDQSOut; assign TDQSOut = TDQS; wire DQSNegIn; assign DQSNegIn = DQSNeg_ipd; wire DQSNegOut; assign DQSNegOut = DQSNeg; wire TDQSNegIn; assign TDQSNegIn = TDQSNeg_ipd; wire TDQSNegOut; assign TDQSNegOut = TDQSNeg; wire RESETNegIn; assign RESETNegIn = RESETNeg_ipd; reg [7 : 0] tRC_out; // ACTIVE-to-ACTIVE same bank reg [7 : 0] tRC_in; reg tRRD_out; // ACTIVE bank a to ACTIVE bank b reg tRRD_in; reg [7 : 0] tRCD_out; // ACTIVE-to-READ or WRITE reg [7 : 0] tRCD_in; reg [3 : 0] tFAW_out; // four bank activate period reg [3 : 0] tFAW_in; reg [7 : 0] tRASMIN_out; // ACTIVE-to-PRECHARGE minimum period reg [7 : 0] tRASMIN_in; reg [7 : 0] tRASMAX_out; // ACTIVE-to-PRECHARGE maximum period reg [7 : 0] tRASMAX_in; reg [7 : 0] tRTP_out; // Internal READ-to-PRECHARGE reg [7 : 0] tRTP_in; reg [7 : 0] tWR_out; // WRITE Recovery time reg [7 : 0] tWR_in; reg [7 : 0] tWTR_out; // Internal WRITE-to-READ reg [7 : 0] tWTR_in; reg [7 : 0] tRP_out; // PRECHARGE command period reg [7 : 0] tRP_in; reg [7 : 0] tCKESR_out; // reg [7 : 0] tCKESR_in; reg tRFCMIN_out; // REFRESH-to-ACTIVE or REFRESH-to-REFRESH reg tRFCMIN_in; reg tXS_out; // exit self refresh to non-READ command reg tXS_in; reg tREFPer_out; // REFRESH period reg tREFPer_in; reg tCKAVGMAX_out; // maximum clock cycle time reg tCKAVGMAX_in; reg tCKSRX_out; // Valid clock requirements before reg tCKSRX_in; // self-refresh operation reg tCKSRE_out; // Valid clock requirements after reg tCKSRE_in; // self-refresh operation reg tWLDQSEN_out; // DQS/DQS delay after tDQSS margining moded reg tWLDQSEN_in; // is programmed reg tWLMRD_out; // First DQS pulse rising edge after tDQSS marginig reg tWLMRD_in; // mode is programmed reg tWLOMAX_out; // Write leveling output delay reg tWLOMAX_in; reg tWLOEMAX_out; // Write leveling output error reg tWLOEMAX_in; reg tMRD_out; // Mode register set command cycle time reg tMRD_in; reg tMOD_out; // Mode register set command cycle time reg tMOD_in; reg tMOD_out_tmp; // Mode register set command cycle time reg tMOD_in_tmp; reg tXPR_out; // Exit reset from CKE high to a valid command reg tXPR_in; reg tZQINIT_out; // Power-up and reset calibration time reg tZQINIT_in; reg tZQOPER_out; // Normal operation full calibration time reg tZQOPER_in; reg tZQCS_out; // Normal operation full calibration time reg tZQCS_in; reg mrs_active; reg [7 : 0] DOut_zd = 8'bz; assign { DQ7_zd, DQ6_zd, DQ5_zd, DQ4_zd, DQ3_zd, DQ2_zd, DQ1_zd, DQ0_zd } = DOut_zd; reg DQS_zd = 1'bz; reg DQSNeg_zd = 1'bz; reg TDQS_zd = 1'bz; reg TDQSNeg_zd = 1'bz; parameter mem_file_name = "edj1308ba.mem"; parameter UserPreload = 1'b1; parameter TimingModel = "defaulttimingmodel"; parameter PartID = "edj1308ba"; parameter MaxData = 8'hFF; parameter MemSize = 24'hFFFFFF; parameter BankNum = 7; parameter RowNum = 14'h3FFF; parameter ColNum = 10'h3FF; parameter HiAddrBit = 13; integer TScal = 1000; //varaibles to resolve timing model used reg [20*8-1:0] tmp_timing;//stores copy of TimingModel reg [7:0] char [5:0]; integer found = 1'b0; integer pos; integer PD_del; //used to determine tXPDLL delay integer indust; //determine if tested model support //industrial temperature range // powerup reg PoweredUp = 1'b0; reg CK_stable = 1'b0; integer CK_COUNT = 0; //differential inputs reg CKDiff = 1'bz ; reg DQSDiff = 1'bz ; // DLL implementation time CKPeriod = 3000; time CKHalfPer = 0; time CKDLLDelay = 0; integer DLL_TIME; reg CKInt = 1'b0; reg CKtemp = 1'b1; // WRITE LEVELING PROCEDURE reg WL_on = 1'b0; // Write Leveling enabled reg ODTLOFF = 1'b0; reg DQ_driven = 1'b0; reg In_d = 1'b0; //delay before first MRS command tXPR reg In_d1 = 1'b0; //mode register set comand cycle time //during initialization reg In_d2 = 1'b0; //delay during initial ZQ calibration reg In_d3 = 1'b0; //delay during reset ZQ calibration reg In_d4 = 1'b0; //delay before first precharge all reg Init_delay = 1'b0; //command during initialization reg Init_delay1 = 1'b0; //command during initialization reg Init_delay2 = 1'b0; //command during initialization reg Init_delay3 = 1'b0; //command during initialization reg Init_delay4 = 1'b0; //command during initialization reg Initialized = 1'b0; //initialization completed reg DLL_delay = 1'b0; //DLL delay reg DLL_delay_elapsed = 1'b0; //reset and read command reg In_data = 1'b0; //start of write operation reg preamble_gen = 1'bz; //preamble before read operation reg Out_data = 1'bz; //start of read operation reg fly_flag = 1'bz; //Determine weather read or write // command is BL4 or BL8 on the fly //burst sequences integer Seq[0 : 63]; integer Inl[0 : 63]; integer burst_cnt_aux; //memory definition integer Mem[0:(BankNum+1)*(MemSize+1)-1]; //mode registers reg [15 : 0] MR0 = 16'b0; reg [15 : 0] MR1 = 16'b0; reg [15 : 0] MR2 = 16'b0; reg [15 : 0] MR3 = 16'b0; integer burst_len ; //burst length integer add_lat = 0 ; //additive latency integer cas_lat = 0 ; //CAS# latency integer wr_rec ; //write recovery integer wr_lat = 0 ; //write latency reg active_forbid = 1'b0; //more than 4 active commands during tFAW //bank, row and column addresses of scheduled read or write operation integer current_bank ; integer current_row ; integer current_column ; integer WAddr; integer RAddr; //latencies of scheduled read and write operations integer AL[0:(BankNum+1)*11 - 1]; integer CL[0:(BankNum+1)*11 - 1]; integer WL[0:(BankNum+1)*11 - 1]; integer RL_tmp; integer rd_pd_cnt; integer mrs_cnt; //all scheduled reads within all banks reg [10 : 0] read_sch [BankNum : 0] ; //reads that should be preceeded by preamble reg [10 : 0] preamble [BankNum : 0] ; //wait_read triggers process that counts remaining cycles to the //beggining of scheduled read when aditive latency has elapsed, and //read_delay keeps information of number of remaining cycles reg [10 : 0] wait_read [BankNum : 0] ; integer read_delay = 0; //needed for check if all rows were refreshed during refresh period reg Ref_per_start = 1'b0; reg Ref_per_expired = 1'b0; integer Ref_cnt = 0; time CK_rise = 0; time CK_period = 0; time previous = 0; time tmpper = 0; reg SR_cond = 1'b0; //self refresh can be entered reg SelfRefresh = 1'b0; //self refresh active reg PartialSelfRefresh = 1'b0; //partial self refresh active reg SR_exit = 1'b0; //CKE high, self refresh exit reg SR_enter_cycle = 1'b0; //clock can be turned off integer sf_array =0; reg Pre_PD = 1'b0; //precharge power down active reg Act_PD = 1'b0; //active power down active reg Read_Start = 1'b0; //read burst in progress, reg ReadStart = 1'b0; //no pd entry reg RST = 1'b1; reg Reset = 1'b0; //reset function active reg Reset_enter_cycle = 1'b0; //clocks can be turned off reg SimulationEnd = 1'b0; reg preamble_check = 1'b0; reg postamble_check = 1'b0; reg skew_check = 1'b0; reg prechall_viol = 1'b0; //command other than NOP or DESL issued //tRPA after precharge all reg idle = 1'b0; //all banks idle state integer active_row[0:BankNum]; //activated rows //starting columns of scheduled read or write operations integer start_column[0:(BankNum+1)*11 - 1]; //needed when multiple reads or writes scheduled in same bank integer free_slot; //all scheduled writes within all banks reg [10 : 0] write_sch [BankNum : 0] ; //elapsed aditive latencies of scheduled reads reg [10 : 0] AL_elapsed [BankNum : 0] ; //needed for verification of durations measured since end of write burst reg [BankNum : 0] last_write = 0; //programmed write latency elapsed since end of write burst reg [BankNum : 0] WR_elapsed = 8'b11111111; //2 cycles elapsed since end of write burst reg [BankNum : 0] WTR_elapsed = 8'b11111111; //AL + BL/2 elapsed since read command reg [BankNum : 0] RTP_elapsed = 8'b11111111; //cycles elapsed since read or write command before precharge command integer precharge_cnt[0 : BankNum]; //cycles elapsed since write command before end of write burst integer wr_rd_cnt[0 : BankNum]; //cycles elapsed since read command before bank returns to active state integer rd_act_cnt[0 : BankNum]; //cycles elapsed since read command before write command //-- must be //--RL+tCCD/2+2tCK-WL for BL=4 //--RL+tCCD+2tCK-WL for BL=8 integer rd_wr_cnt; //BL/2 + 2 cycles elapsed since read command reg RTW_elapsed = 1'b1; //cycles elapsed since write command before another write command integer wr_wr_cnt; //cycles elapsed since read command before another read command integer rd_rd_cnt; reg read_permit = 1'b0 ; //read command accepted reg write_permit = 1'b0; //write command accepted reg defined_logic_levels = 1'b1; integer CK_cnt; //between commands during initialization reg power_down_cond = 1'b0; //pd can be entered reg active_pd_cond = 1'b0; //active pd can be entered integer PD_exit_cnt = 1; //cycles since CKE went high reg PD_read_delay = 1'b0; //tXSRD elapsed integer PD_read_del_cnt = 1; //cycles of tXSRD reg ODT_off = 1'b0; //ODT turned off when precharge pd entered reg freq_change = 1'b0; //frequency has changed during precharge pd integer freq_ch_cnt = 0; //cycles before frequency can change reg DLL_reset_needed = 1'b0; //DLL must be reset prior to read command integer WR [0 : 12]; reg ZQINIT = 1'b1; // For ZQ calibration after power-up // If 0 ZQ calibration after reset reg TDQS_EN = 1'bz; //needed for CKE pulse width check integer CKEcnt = 3; reg CKErise = 1'b0; reg CKEfall = 1'b1; //needed for write integer In_colw ; integer Start_bankw ; integer Start_roww ; integer Start_colw ; integer burst_cnt = 8 ; integer burst_seqw[0 : 7] ; integer seqw ; //needed for read reg preamble_done = 1'b1; reg preamble_allow = 1'b0; integer In_colr ; integer Start_bankr ; integer Start_rowr ; integer Start_colr ; integer burst_cntr = 9; integer burst_seqr[0 : 7]; integer seqr ; integer read_bank ; integer read_row ; integer read_column ; reg [7 : 0] out_buffer ; integer delay[0:(BankNum+1)*11 - 1]; integer temp_bank[0:(BankNum+1)*11 - 1] ; integer temp_row[0:(BankNum+1)*11 - 1] ; integer temp_column[0:(BankNum+1)*11 - 1] ; event wr_event; event sim_end; integer act_num[0 : 3] ; reg next_slot = 1'b0; // timing check violation reg Viol = 1'b0; // DLL delay counter integer cnt; integer i,j,k,l; integer itmp, jtmp; reg foundone = 1'b0; reg deq; reg dmq; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (BA2_ipd, BA2); buf (BA1_ipd, BA1); buf (BA0_ipd, BA0); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (ODT_ipd , ODT ); buf (CK_ipd , CK ); buf (CKNeg_ipd , CKNeg ); buf (CKE_ipd , CKE ); buf (CSNeg_ipd , CSNeg ); buf (RASNeg_ipd , RASNeg ); buf (CASNeg_ipd , CASNeg ); buf (WENeg_ipd , WENeg ); buf (DQS_ipd , DQS ); buf (DQSNeg_ipd , DQSNeg); buf (TDQS_ipd , TDQS ); buf (TDQSNeg_ipd , TDQSNeg); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ7 , DQ7_zd,1); nmos (DQ6 , DQ6_zd,1); nmos (DQ5 , DQ5_zd,1); nmos (DQ4 , DQ4_zd,1); nmos (DQ3 , DQ3_zd,1); nmos (DQ2 , DQ2_zd,1); nmos (DQ1 , DQ1_zd,1); nmos (DQ0 , DQ0_zd,1); nmos (DQS , DQS_zd , 1); nmos (DQSNeg , DQSNeg_zd , 1); nmos (TDQS , TDQS_zd , 1); nmos (TDQSNeg , TDQSNeg_zd , 1); wire deg; wire dmg; //VHDL VITAL CheckEnable equivalents // Setup/Hold Check between DQIn and DQS wire ChEn_DQ_DS; assign ChEn_DQ_DS = ~MR1[11] && deg; // Setup/Hold Check between CKE and CK wire ChSetup_CKE_CK; assign ChSetup_CKE_CK = Reset_enter_cycle && (CK_COUNT == 5); wire ChHold_CKE_CK; assign ChHold_CKE_CK = Reset_enter_cycle && (CK_COUNT == 5); //Setup/Hold Check between DQSNegIn and CK wire ChSetup_DS_CK5; assign ChSetup_DS_CK5 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 5); wire ChSetup_DS_CK6; assign ChSetup_DS_CK6 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 6); wire ChSetup_DS_CK7; assign ChSetup_DS_CK7 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 7); wire ChSetup_DS_CK8; assign ChSetup_DS_CK8 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 8); wire ChSetup_DS_CK9; assign ChSetup_DS_CK9 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 9); wire ChSetup_DS_CK10; assign ChSetup_DS_CK10 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 10); wire ChHold_DS_CK5; assign ChHold_DS_CK5 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 5); wire ChHold_DS_CK6; assign ChHold_DS_CK6 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 6); wire ChHold_DS_CK7; assign ChHold_DS_CK7 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 7); wire ChHold_DS_CK8; assign ChHold_DS_CK8 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 8); wire ChHold_DS_CK9; assign ChHold_DS_CK9 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 9); wire ChHold_DS_CK10; assign ChHold_DS_CK10 = ~MR1[11] && (DQSDiff!==DQS_zd) && ~DQSNeg && ~postamble_check && In_data && (cas_lat == 10); wire ChSetup_CKE_RESETNeg; assign ChSetup_CKE_RESETNeg = Reset_enter_cycle; wire ChHold_CKE_RESETNeg; assign ChHold_CKE_RESETNeg = Reset_enter_cycle; wire ChEn_DQ_TDQS; assign ChEn_DQ_TDQS = ~MR1[11]; //Setup/Hold Check between CK and DQS wire ChSetup_CK_DQS; assign ChSetup_CK_DQS = WL_on; wire ChHold_CK_DQS; assign ChHold_CK_DQS = WL_on && (DQS_zd !== DQS_zd); //Setup/Hold Check between DQSIn and CK wire ChSetup_DSIn_CK5; assign ChSetup_DSIn_CK5 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 5); wire ChSetup_DSIn_CK6; assign ChSetup_DSIn_CK6 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 6); wire ChSetup_DSIn_CK7; assign ChSetup_DSIn_CK7 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 7); wire ChSetup_DSIn_CK8; assign ChSetup_DSIn_CK8 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 8); wire ChSetup_DSIn_CK9; assign ChSetup_DSIn_CK9 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 9); wire ChSetup_DSIn_CK10; assign ChSetup_DSIn_CK10 = (DQSIn!==DQS_zd) && ~DQSIn && ~postamble_check && In_data && (cas_lat == 10); wire ChHold_DSIn_CK5; assign ChHold_DSIn_CK5 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 5); wire ChHold_DSIn_CK6; assign ChHold_DSIn_CK6 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 6); wire ChHold_DSIn_CK7; assign ChHold_DSIn_CK7 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 7); wire ChHold_DSIn_CK8; assign ChHold_DSIn_CK8 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 8); wire ChHold_DSIn_CK9; assign ChHold_DSIn_CK9 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 9); wire ChHold_DSIn_CK10; assign ChHold_DSIn_CK10 = (DQSIn!==DQS_zd) && DQSIn && ~postamble_check && In_data && (cas_lat == 10); wire ChDQSNeg; assign ChDQSNeg = ~MR1[11] && (DQSNeg!==1'bz); wire ChDQSNegCL5; assign ChDQSNegCL5 = ChDQSNeg && (cas_lat == 5); wire ChDQSNegCL6; assign ChDQSNegCL6 = ChDQSNeg && (cas_lat == 6); wire ChDQSNegCL7; assign ChDQSNegCL7 = ChDQSNeg && (cas_lat == 7); wire ChDQSNegCL8; assign ChDQSNegCL8 = ChDQSNeg && (cas_lat == 8); wire ChDQSNegCL9; assign ChDQSNegCL9 = ChDQSNeg && (cas_lat == 9); wire ChDQSNegCL10; assign ChDQSNegCL10 = ChDQSNeg && (cas_lat == 10); wire ChNormal; assign ChNormal = ~preamble_check && ~postamble_check && (DQS!==1'bz); wire ChNormalCL5; assign ChNormalCL5 = ChNormal && (cas_lat == 5); wire ChNormalCL6; assign ChNormalCL6 = ChNormal && (cas_lat == 6); wire ChNormalCL7; assign ChNormalCL7 = ChNormal && (cas_lat == 7); wire ChNormalCL8; assign ChNormalCL8 = ChNormal && (cas_lat == 8); wire ChNormalCL9; assign ChNormalCL9 = ChNormal && (cas_lat == 9); wire ChNormalCL10; assign ChNormalCL10 = ChNormal && (cas_lat == 10); wire CheckPostambleCL5; assign CheckPostambleCL5 = ~MR1[11] && postamble_check && (cas_lat == 5); wire CheckPostambleCL6; assign CheckPostambleCL6 = ~MR1[11] && postamble_check && (cas_lat == 6); wire CheckPostambleCL7; assign CheckPostambleCL7 = ~MR1[11] && postamble_check && (cas_lat == 7); wire CheckPostambleCL8; assign CheckPostambleCL8 = ~MR1[11] && postamble_check && (cas_lat == 8); wire CheckPostambleCL9; assign CheckPostambleCL9 = ~MR1[11] && postamble_check && (cas_lat == 9); wire CheckPostambleCL10; assign CheckPostambleCL10 = ~MR1[11] && postamble_check && (cas_lat == 10); wire ChPostambleCL5; assign ChPostambleCL5 = postamble_check && (cas_lat == 5); wire ChPostambleCL6; assign ChPostambleCL6 = postamble_check && (cas_lat == 6); wire ChPostambleCL7; assign ChPostambleCL7 = postamble_check && (cas_lat == 7); wire ChPostambleCL8; assign ChPostambleCL8 = postamble_check && (cas_lat == 8); wire ChPostambleCL9; assign ChPostambleCL9 = postamble_check && (cas_lat == 9); wire ChPostambleCL10; assign ChPostambleCL10 = postamble_check && (cas_lat == 10); //PulseWidth and Period Check for CK wire ChEnable_CK5; assign ChEnable_CK5 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 5); wire ChEnable_CK6; assign ChEnable_CK6 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 6); wire ChEnable_CK7; assign ChEnable_CK7 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 7); wire ChEnable_CK8; assign ChEnable_CK8 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 8); wire ChEnable_CK9; assign ChEnable_CK9 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 9); wire ChEnable_CK10; assign ChEnable_CK10 = CK_stable && ~SR_enter_cycle && ~Reset_enter_cycle && (cas_lat == 10); wire ChEnable_PoweredUp_eq_0; assign ChEnable_PoweredUp_eq_0 = ~PoweredUp; wire ChEnable_PoweredUp_eq_1; assign ChEnable_PoweredUp_eq_1 = PoweredUp; wire CL5; assign CL5 = (cas_lat == 5); wire CL6; assign CL6 = (cas_lat == 6); wire CL7; assign CL7 = (cas_lat == 7); wire CL8; assign CL8 = (cas_lat == 8); wire CL9; assign CL9 = (cas_lat == 9); wire CL10; assign CL10 = (cas_lat == 10); wire CheckDM; assign CheckDM = ~MR1[11] && dmg; wire DM5; assign DM5 = CL5 && CheckDM; wire DM6; assign DM6 = CL6 && CheckDM; wire DM7; assign DM7 = CL7 && CheckDM; wire DM8; assign DM8 = CL8 && CheckDM; wire DM9; assign DM9 = CL9 && CheckDM; wire DM10; assign DM10 = CL10 && CheckDM; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_CK_DQ0 =1; specparam tpd_CK_DQ1 =1; specparam tpd_CK_DQS =1; // tsetup values: setup time specparam tsetup_DQ0_DQS =1; //tDS specparam tsetup_A0_CK =1; //tIS specparam tsetup_DQS_CK =1; //tDSS specparam tsetup_CKE_RESETNeg =1; specparam tsetup_CK_DQS =1; //tWLS // thold values: hold times specparam thold_DQ0_DQS =1; //tDH specparam thold_A0_CK =1; //tIH specparam thold_DQS_CK =1; //tDSH specparam thold_CKE_RESETNeg =1; specparam thold_CK_DQS =1; //tWLH // tpw values: pulse width specparam tpw_CK_posedge =1; //tCKHAVG specparam tpw_CK_negedge =1; //tCKLAVG specparam tpw_A0 =1; //tIPW specparam tpw_DQ0 =1; //tDIPW specparam tpw_DQS_posedge =1; //tDQSH specparam tpw_DQS_negedge =1; //tDQSL, tWPRE, tWPST specparam tpw_CKE_negedge =1; //tCKESR specparam tpw_RESETNeg_negedge =1; //from diagram on page 58. specparam tperiod_CK =1; //tCKAVG(min) // tdevice values: values for internal delays specparam tdevice_tRC = 49500; //tRC;-- specparam tdevice_tRRD = 6; //tRRD; specparam tdevice_tRCD = 13500; //tRCD;-- specparam tdevice_tFAW = 30; //tFAW; specparam tdevice_tRASMIN = 36; //tRAS(min); specparam tdevice_tRASMAX = 70200; //tRAS(max); specparam tdevice_tRTP = 7500; //tRTP; specparam tdevice_tWR = 15; //tWR; specparam tdevice_tWTR = 7500; //tWTR;-- specparam tdevice_tRP = 13500; // tRP;-- specparam tdevice_tRFCMIN = 90; //tRFC(min); specparam tdevice_REFPer = 78000; //refresh period; specparam tdevice_tCKAVGMAX = 3333; //tCKAVG(max)-- specparam tdevice_tMRD = 6; //tMRD; specparam tdevice_tMOD = 22500; //tMOD; specparam tdevice_tXPR = 7500; //tXPR;-- specparam tdevice_tZQINIT = 768; //tZQINIT; specparam tdevice_tZQOPER = 384; //tZQOPER; specparam tdevice_tZQCS = 96; //tZQCS; specparam tdevice_tCKSRX = 7500; //tCKSRX;-- specparam tdevice_tCKSRE = 7500; //tCKSRE;-- specparam tdevice_tCKESR = 7500; //tCKESR;-- specparam tdevice_tWLDQSEN = 37500; //tWLDQSEN;-- specparam tdevice_tWLMRD = 60; //tWLMRD; specparam tdevice_tWLOMAX = 10; //tWLO(MAX); specparam tdevice_tWLOEMAX = 2; //tWLOE(MAX); /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// (CK => DQS) = tpd_CK_DQS; (CK => DQSNeg) = tpd_CK_DQS; (CK => DQ0 ) = tpd_CK_DQ0; (CK => DQ1 ) = tpd_CK_DQ0; (CK => DQ2 ) = tpd_CK_DQ0; (CK => DQ3 ) = tpd_CK_DQ0; (CK => DQ4 ) = tpd_CK_DQ0; (CK => DQ5 ) = tpd_CK_DQ0; (CK => DQ6 ) = tpd_CK_DQ0; (CK => DQ7 ) = tpd_CK_DQ0; /////////////////////////////////////////////////////////////////////////////// // Timing Violation // /////////////////////////////////////////////////////////////////////////////// $setup ( DQ0 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ1 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ2 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ3 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ4 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ5 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ6 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ7 , posedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ0 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ1 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ2 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ3 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ4 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ5 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ6 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ7 , posedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ0 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ1 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ2 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ3 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ4 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ5 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ6 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ7 , negedge DQSNeg&&&ChEn_DQ_DS, tsetup_DQ0_DQS, Viol); $setup ( DQ0 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ1 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ2 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ3 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ4 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ5 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ6 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQ7 , negedge DQS&&°, tsetup_DQ0_DQS, Viol); $setup ( DQS , negedge TDQSNeg&&&ChEn_DQ_TDQS, tsetup_DQ0_DQS, Viol); $setup ( DQS , negedge TDQS, tsetup_DQ0_DQS, Viol); $setup ( ODT , posedge CK, tsetup_A0_CK, Viol); $setup ( CKE , posedge CK &&& ChSetup_CKE_CK, tsetup_A0_CK, Viol); $setup ( CSNeg , posedge CK, tsetup_A0_CK, Viol); $setup ( RASNeg , posedge CK, tsetup_A0_CK, Viol); $setup ( CASNeg , posedge CK, tsetup_A0_CK, Viol); $setup ( WENeg , posedge CK, tsetup_A0_CK, Viol); $setup ( BA2 , posedge CK, tsetup_A0_CK, Viol); $setup ( BA1 , posedge CK, tsetup_A0_CK, Viol); $setup ( BA0 , posedge CK, tsetup_A0_CK, Viol); $setup ( A13 , posedge CK, tsetup_A0_CK, Viol); $setup ( A12 , posedge CK, tsetup_A0_CK, Viol); $setup ( A11 , posedge CK, tsetup_A0_CK, Viol); $setup ( A10 , posedge CK, tsetup_A0_CK, Viol); $setup ( A9 , posedge CK, tsetup_A0_CK, Viol); $setup ( A8 , posedge CK, tsetup_A0_CK, Viol); $setup ( A7 , posedge CK, tsetup_A0_CK, Viol); $setup ( A6 , posedge CK, tsetup_A0_CK, Viol); $setup ( A5 , posedge CK, tsetup_A0_CK, Viol); $setup ( A4 , posedge CK, tsetup_A0_CK, Viol); $setup ( A3 , posedge CK, tsetup_A0_CK, Viol); $setup ( A2 , posedge CK, tsetup_A0_CK, Viol); $setup ( A1 , posedge CK, tsetup_A0_CK, Viol); $setup ( A0 , posedge CK, tsetup_A0_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK5,tsetup_DQS_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK6,tsetup_DQS_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK7,tsetup_DQS_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK8,tsetup_DQS_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK9,tsetup_DQS_CK, Viol); $setup ( DQSNeg , posedge CK&&&ChSetup_DS_CK10,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK5,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK6,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK7,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK8,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK9,tsetup_DQS_CK, Viol); $setup ( DQS , posedge CK&&&ChSetup_DSIn_CK10,tsetup_DQS_CK, Viol); $setup ( CKE, posedge RESETNeg&&&ChSetup_CKE_RESETNeg , tsetup_CKE_RESETNeg, Viol); $setup ( CK, posedge DQS&&&ChSetup_CK_DQS , tsetup_CK_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ0 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ1 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ2 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ3 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ4 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ5 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ6 , thold_DQ0_DQS, Viol); $hold ( posedge DQSNeg&&&ChEn_DQ_DS, DQ7 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ0 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ1 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ2 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ3 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ4 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ5 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ6 , thold_DQ0_DQS, Viol); $hold ( posedge DQS&&°, DQ7 , thold_DQ0_DQS, Viol); $hold ( posedge TDQSNeg&&&ChEn_DQ_TDQS, DQS , thold_DQ0_DQS, Viol); $hold ( posedge TDQS&&&ChEn_DQ_TDQS, DQS , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ0 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ1 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ2 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ3 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ4 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ5 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ6 , thold_DQ0_DQS, Viol); $hold ( negedge DQSNeg&&&ChEn_DQ_DS, DQ7 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ0 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ1 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ2 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ3 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ4 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ5 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ6 , thold_DQ0_DQS, Viol); $hold ( negedge DQS&&°, DQ7 , thold_DQ0_DQS, Viol); $hold ( posedge CK, ODT , thold_A0_CK, Viol); $hold ( posedge CK &&& ChHold_CKE_CK, CKE , thold_A0_CK, Viol); $hold ( posedge CK, CSNeg , thold_A0_CK, Viol); $hold ( posedge CK, RASNeg , thold_A0_CK, Viol); $hold ( posedge CK, CASNeg , thold_A0_CK, Viol); $hold ( posedge CK, WENeg , thold_A0_CK, Viol); $hold ( posedge CK, BA2 , thold_A0_CK, Viol); $hold ( posedge CK, BA1 , thold_A0_CK, Viol); $hold ( posedge CK, BA0 , thold_A0_CK, Viol); $hold ( posedge CK, A13 , thold_A0_CK, Viol); $hold ( posedge CK, A12 , thold_A0_CK, Viol); $hold ( posedge CK, A11 , thold_A0_CK, Viol); $hold ( posedge CK, A10 , thold_A0_CK, Viol); $hold ( posedge CK, A9 , thold_A0_CK, Viol); $hold ( posedge CK, A8 , thold_A0_CK, Viol); $hold ( posedge CK, A7 , thold_A0_CK, Viol); $hold ( posedge CK, A6 , thold_A0_CK, Viol); $hold ( posedge CK, A5 , thold_A0_CK, Viol); $hold ( posedge CK, A4 , thold_A0_CK, Viol); $hold ( posedge CK, A3 , thold_A0_CK, Viol); $hold ( posedge CK, A2 , thold_A0_CK, Viol); $hold ( posedge CK, A1 , thold_A0_CK, Viol); $hold ( posedge CK, A0 , thold_A0_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK5,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK6,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK7,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK8,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK9,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DS_CK10,posedge DQSNeg , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK5, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK6, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK7, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK8, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK9, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge CK&&&ChHold_DSIn_CK10, negedge DQS , thold_DQS_CK, Viol); $hold ( posedge RESETNeg&&&ChHold_CKE_RESETNeg , CKE, thold_CKE_RESETNeg, Viol); $hold ( posedge DQS&&&ChHold_CK_DQS , CK, thold_CK_DQS, Viol); $width (posedge BA2&&&CL5==1 , tpw_A0); $width (posedge BA1&&&CL5==1 , tpw_A0); $width (posedge BA0&&&CL5==1 , tpw_A0); $width (negedge BA2&&&CL5==1 , tpw_A0); $width (negedge BA1&&&CL5==1 , tpw_A0); $width (negedge BA0&&&CL5==1 , tpw_A0); $width (posedge BA2&&&CL6==1 , tpw_A0); $width (posedge BA1&&&CL6==1 , tpw_A0); $width (posedge BA0&&&CL6==1 , tpw_A0); $width (negedge BA2&&&CL6==1 , tpw_A0); $width (negedge BA1&&&CL6==1 , tpw_A0); $width (negedge BA0&&&CL6==1 , tpw_A0); $width (posedge BA2&&&CL7==1 , tpw_A0); $width (posedge BA1&&&CL7==1 , tpw_A0); $width (posedge BA0&&&CL7==1 , tpw_A0); $width (negedge BA2&&&CL7==1 , tpw_A0); $width (negedge BA1&&&CL7==1 , tpw_A0); $width (negedge BA0&&&CL7==1 , tpw_A0); $width (posedge BA2&&&CL8==1 , tpw_A0); $width (posedge BA1&&&CL8==1 , tpw_A0); $width (posedge BA0&&&CL8==1 , tpw_A0); $width (negedge BA2&&&CL8==1 , tpw_A0); $width (negedge BA1&&&CL8==1 , tpw_A0); $width (negedge BA0&&&CL8==1 , tpw_A0); $width (posedge BA2&&&CL9==1 , tpw_A0); $width (posedge BA1&&&CL9==1 , tpw_A0); $width (posedge BA0&&&CL9==1 , tpw_A0); $width (negedge BA2&&&CL9==1 , tpw_A0); $width (negedge BA1&&&CL9==1 , tpw_A0); $width (negedge BA0&&&CL9==1 , tpw_A0); $width (posedge BA2&&&CL10==1 , tpw_A0); $width (posedge BA1&&&CL10==1 , tpw_A0); $width (posedge BA0&&&CL10==1 , tpw_A0); $width (negedge BA2&&&CL10==1 , tpw_A0); $width (negedge BA1&&&CL10==1 , tpw_A0); $width (negedge BA0&&&CL10==1 , tpw_A0); $width (posedge A13&&&CL5==1 , tpw_A0); $width (posedge A12&&&CL5==1 , tpw_A0); $width (posedge A11&&&CL5==1 , tpw_A0); $width (posedge A10&&&CL5==1 , tpw_A0); $width (posedge A9&&&CL5==1 , tpw_A0); $width (posedge A8&&&CL5==1 , tpw_A0); $width (posedge A7&&&CL5==1 , tpw_A0); $width (posedge A6&&&CL5==1 , tpw_A0); $width (posedge A5&&&CL5==1 , tpw_A0); $width (posedge A4&&&CL5==1 , tpw_A0); $width (posedge A3&&&CL5==1 , tpw_A0); $width (posedge A2&&&CL5==1 , tpw_A0); $width (posedge A1&&&CL5==1 , tpw_A0); $width (posedge A0&&&CL5==1 , tpw_A0); $width (negedge A13&&&CL5==1 , tpw_A0); $width (negedge A12&&&CL5==1 , tpw_A0); $width (negedge A11&&&CL5==1 , tpw_A0); $width (negedge A10&&&CL5==1 , tpw_A0); $width (negedge A9&&&CL5==1 , tpw_A0); $width (negedge A8&&&CL5==1 , tpw_A0); $width (negedge A7&&&CL5==1 , tpw_A0); $width (negedge A6&&&CL5==1 , tpw_A0); $width (negedge A5&&&CL5==1 , tpw_A0); $width (negedge A4&&&CL5==1 , tpw_A0); $width (negedge A3&&&CL5==1 , tpw_A0); $width (negedge A2&&&CL5==1 , tpw_A0); $width (negedge A1&&&CL5==1 , tpw_A0); $width (negedge A0&&&CL5==1 , tpw_A0); $width (posedge A13&&&CL6==1 , tpw_A0); $width (posedge A12&&&CL6==1 , tpw_A0); $width (posedge A11&&&CL6==1 , tpw_A0); $width (posedge A10&&&CL6==1 , tpw_A0); $width (posedge A9&&&CL6==1 , tpw_A0); $width (posedge A8&&&CL6==1 , tpw_A0); $width (posedge A7&&&CL6==1 , tpw_A0); $width (posedge A6&&&CL6==1 , tpw_A0); $width (posedge A5&&&CL6==1 , tpw_A0); $width (posedge A4&&&CL6==1 , tpw_A0); $width (posedge A3&&&CL6==1 , tpw_A0); $width (posedge A2&&&CL6==1 , tpw_A0); $width (posedge A1&&&CL6==1 , tpw_A0); $width (posedge A0&&&CL6==1 , tpw_A0); $width (negedge A13&&&CL6==1 , tpw_A0); $width (negedge A12&&&CL6==1 , tpw_A0); $width (negedge A11&&&CL6==1 , tpw_A0); $width (negedge A10&&&CL6==1 , tpw_A0); $width (negedge A9&&&CL6==1 , tpw_A0); $width (negedge A8&&&CL6==1 , tpw_A0); $width (negedge A7&&&CL6==1 , tpw_A0); $width (negedge A6&&&CL6==1 , tpw_A0); $width (negedge A5&&&CL6==1 , tpw_A0); $width (negedge A4&&&CL6==1 , tpw_A0); $width (negedge A3&&&CL6==1 , tpw_A0); $width (negedge A2&&&CL6==1 , tpw_A0); $width (negedge A1&&&CL6==1 , tpw_A0); $width (negedge A0&&&CL6==1 , tpw_A0); $width (posedge A13&&&CL7==1 , tpw_A0); $width (posedge A12&&&CL7==1 , tpw_A0); $width (posedge A11&&&CL7==1 , tpw_A0); $width (posedge A10&&&CL7==1 , tpw_A0); $width (posedge A9&&&CL7==1 , tpw_A0); $width (posedge A8&&&CL7==1 , tpw_A0); $width (posedge A7&&&CL7==1 , tpw_A0); $width (posedge A6&&&CL7==1 , tpw_A0); $width (posedge A5&&&CL7==1 , tpw_A0); $width (posedge A4&&&CL7==1 , tpw_A0); $width (posedge A3&&&CL7==1 , tpw_A0); $width (posedge A2&&&CL7==1 , tpw_A0); $width (posedge A1&&&CL7==1 , tpw_A0); $width (posedge A0&&&CL7==1 , tpw_A0); $width (negedge A13&&&CL7==1 , tpw_A0); $width (negedge A12&&&CL7==1 , tpw_A0); $width (negedge A11&&&CL7==1 , tpw_A0); $width (negedge A10&&&CL7==1 , tpw_A0); $width (negedge A9&&&CL7==1 , tpw_A0); $width (negedge A8&&&CL7==1 , tpw_A0); $width (negedge A7&&&CL7==1 , tpw_A0); $width (negedge A6&&&CL7==1 , tpw_A0); $width (negedge A5&&&CL7==1 , tpw_A0); $width (negedge A4&&&CL7==1 , tpw_A0); $width (negedge A3&&&CL7==1 , tpw_A0); $width (negedge A2&&&CL7==1 , tpw_A0); $width (negedge A1&&&CL7==1 , tpw_A0); $width (negedge A0&&&CL7==1 , tpw_A0); $width (posedge A13&&&CL8==1 , tpw_A0); $width (posedge A12&&&CL8==1 , tpw_A0); $width (posedge A11&&&CL8==1 , tpw_A0); $width (posedge A10&&&CL8==1 , tpw_A0); $width (posedge A9&&&CL8==1 , tpw_A0); $width (posedge A8&&&CL8==1 , tpw_A0); $width (posedge A7&&&CL8==1 , tpw_A0); $width (posedge A6&&&CL8==1 , tpw_A0); $width (posedge A5&&&CL8==1 , tpw_A0); $width (posedge A4&&&CL8==1 , tpw_A0); $width (posedge A3&&&CL8==1 , tpw_A0); $width (posedge A2&&&CL8==1 , tpw_A0); $width (posedge A1&&&CL8==1 , tpw_A0); $width (posedge A0&&&CL8==1 , tpw_A0); $width (negedge A13&&&CL8==1 , tpw_A0); $width (negedge A12&&&CL8==1 , tpw_A0); $width (negedge A11&&&CL8==1 , tpw_A0); $width (negedge A10&&&CL8==1 , tpw_A0); $width (negedge A9&&&CL8==1 , tpw_A0); $width (negedge A8&&&CL8==1 , tpw_A0); $width (negedge A7&&&CL8==1 , tpw_A0); $width (negedge A6&&&CL8==1 , tpw_A0); $width (negedge A5&&&CL8==1 , tpw_A0); $width (negedge A4&&&CL8==1 , tpw_A0); $width (negedge A3&&&CL8==1 , tpw_A0); $width (negedge A2&&&CL8==1 , tpw_A0); $width (negedge A1&&&CL8==1 , tpw_A0); $width (negedge A0&&&CL8==1 , tpw_A0); $width (posedge A13&&&CL9==1 , tpw_A0); $width (posedge A12&&&CL9==1 , tpw_A0); $width (posedge A11&&&CL9==1 , tpw_A0); $width (posedge A10&&&CL9==1 , tpw_A0); $width (posedge A9&&&CL9==1 , tpw_A0); $width (posedge A8&&&CL9==1 , tpw_A0); $width (posedge A7&&&CL9==1 , tpw_A0); $width (posedge A6&&&CL9==1 , tpw_A0); $width (posedge A5&&&CL9==1 , tpw_A0); $width (posedge A4&&&CL9==1 , tpw_A0); $width (posedge A3&&&CL9==1 , tpw_A0); $width (posedge A2&&&CL9==1 , tpw_A0); $width (posedge A1&&&CL9==1 , tpw_A0); $width (posedge A0&&&CL9==1 , tpw_A0); $width (negedge A13&&&CL9==1 , tpw_A0); $width (negedge A12&&&CL9==1 , tpw_A0); $width (negedge A11&&&CL9==1 , tpw_A0); $width (negedge A10&&&CL9==1 , tpw_A0); $width (negedge A9&&&CL9==1 , tpw_A0); $width (negedge A8&&&CL9==1 , tpw_A0); $width (negedge A7&&&CL9==1 , tpw_A0); $width (negedge A6&&&CL9==1 , tpw_A0); $width (negedge A5&&&CL9==1 , tpw_A0); $width (negedge A4&&&CL9==1 , tpw_A0); $width (negedge A3&&&CL9==1 , tpw_A0); $width (negedge A2&&&CL9==1 , tpw_A0); $width (negedge A1&&&CL9==1 , tpw_A0); $width (negedge A0&&&CL9==1 , tpw_A0); $width (posedge A13&&&CL10==1 , tpw_A0); $width (posedge A12&&&CL10==1 , tpw_A0); $width (posedge A11&&&CL10==1 , tpw_A0); $width (posedge A10&&&CL10==1 , tpw_A0); $width (posedge A9&&&CL10==1 , tpw_A0); $width (posedge A8&&&CL10==1 , tpw_A0); $width (posedge A7&&&CL10==1 , tpw_A0); $width (posedge A6&&&CL10==1 , tpw_A0); $width (posedge A5&&&CL10==1 , tpw_A0); $width (posedge A4&&&CL10==1 , tpw_A0); $width (posedge A3&&&CL10==1 , tpw_A0); $width (posedge A2&&&CL10==1 , tpw_A0); $width (posedge A1&&&CL10==1 , tpw_A0); $width (posedge A0&&&CL10==1 , tpw_A0); $width (negedge A13&&&CL10==1 , tpw_A0); $width (negedge A12&&&CL10==1 , tpw_A0); $width (negedge A11&&&CL10==1 , tpw_A0); $width (negedge A10&&&CL10==1 , tpw_A0); $width (negedge A9&&&CL10==1 , tpw_A0); $width (negedge A8&&&CL10==1 , tpw_A0); $width (negedge A7&&&CL10==1 , tpw_A0); $width (negedge A6&&&CL10==1 , tpw_A0); $width (negedge A5&&&CL10==1 , tpw_A0); $width (negedge A4&&&CL10==1 , tpw_A0); $width (negedge A3&&&CL10==1 , tpw_A0); $width (negedge A2&&&CL10==1 , tpw_A0); $width (negedge A1&&&CL10==1 , tpw_A0); $width (negedge A0&&&CL10==1 , tpw_A0); $width (posedge ODT&&&CL5==1 , tpw_A0); $width (posedge ODT&&&CL6==1 , tpw_A0); $width (posedge ODT&&&CL7==1 , tpw_A0); $width (posedge ODT&&&CL8==1 , tpw_A0); $width (posedge ODT&&&CL9==1 , tpw_A0); $width (posedge ODT&&&CL10==1 , tpw_A0); $width (posedge CSNeg&&&CL5==1 , tpw_A0); $width (posedge CSNeg&&&CL6==1 , tpw_A0); $width (posedge CSNeg&&&CL7==1 , tpw_A0); $width (posedge CSNeg&&&CL8==1 , tpw_A0); $width (posedge CSNeg&&&CL9==1 , tpw_A0); $width (posedge CSNeg&&&CL10==1 , tpw_A0); $width (posedge RASNeg&&&CL5==1 , tpw_A0); $width (posedge RASNeg&&&CL6==1 , tpw_A0); $width (posedge RASNeg&&&CL7==1 , tpw_A0); $width (posedge RASNeg&&&CL8==1 , tpw_A0); $width (posedge RASNeg&&&CL9==1 , tpw_A0); $width (posedge RASNeg&&&CL10==1 , tpw_A0); $width (posedge CASNeg&&&CL5==1 , tpw_A0); $width (posedge CASNeg&&&CL6==1 , tpw_A0); $width (posedge CASNeg&&&CL7==1 , tpw_A0); $width (posedge CASNeg&&&CL8==1 , tpw_A0); $width (posedge CASNeg&&&CL9==1 , tpw_A0); $width (posedge CASNeg&&&CL10==1 , tpw_A0); $width (posedge WENeg&&&CL5==1 , tpw_A0); $width (posedge WENeg&&&CL6==1 , tpw_A0); $width (posedge WENeg&&&CL7==1 , tpw_A0); $width (posedge WENeg&&&CL8==1 , tpw_A0); $width (posedge WENeg&&&CL9==1 , tpw_A0); $width (posedge WENeg&&&CL10==1 , tpw_A0); $width (negedge ODT&&&CL5==1 , tpw_A0); $width (negedge ODT&&&CL6==1 , tpw_A0); $width (negedge ODT&&&CL7==1 , tpw_A0); $width (negedge ODT&&&CL8==1 , tpw_A0); $width (negedge ODT&&&CL9==1 , tpw_A0); $width (negedge ODT&&&CL10==1 , tpw_A0); $width (negedge CSNeg&&&CL5==1 , tpw_A0); $width (negedge CSNeg&&&CL6==1 , tpw_A0); $width (negedge CSNeg&&&CL7==1 , tpw_A0); $width (negedge CSNeg&&&CL8==1 , tpw_A0); $width (negedge CSNeg&&&CL9==1 , tpw_A0); $width (negedge CSNeg&&&CL10==1 , tpw_A0); $width (negedge RASNeg&&&CL5==1 , tpw_A0); $width (negedge RASNeg&&&CL6==1 , tpw_A0); $width (negedge RASNeg&&&CL7==1 , tpw_A0); $width (negedge RASNeg&&&CL8==1 , tpw_A0); $width (negedge RASNeg&&&CL9==1 , tpw_A0); $width (negedge RASNeg&&&CL10==1 , tpw_A0); $width (negedge CASNeg&&&CL5==1 , tpw_A0); $width (negedge CASNeg&&&CL6==1 , tpw_A0); $width (negedge CASNeg&&&CL7==1 , tpw_A0); $width (negedge CASNeg&&&CL8==1 , tpw_A0); $width (negedge CASNeg&&&CL9==1 , tpw_A0); $width (negedge CASNeg&&&CL10==1 , tpw_A0); $width (negedge WENeg&&&CL5==1 , tpw_A0); $width (negedge WENeg&&&CL6==1 , tpw_A0); $width (negedge WENeg&&&CL7==1 , tpw_A0); $width (negedge WENeg&&&CL8==1 , tpw_A0); $width (negedge WENeg&&&CL9==1 , tpw_A0); $width (negedge WENeg&&&CL10==1 , tpw_A0); $width (posedge DQ0&&&CL5==1 , tpw_DQ0); $width (posedge DQ1&&&CL5==1 , tpw_DQ0); $width (posedge DQ2&&&CL5==1 , tpw_DQ0); $width (posedge DQ3&&&CL5==1 , tpw_DQ0); $width (posedge DQ4&&&CL5==1 , tpw_DQ0); $width (posedge DQ5&&&CL5==1 , tpw_DQ0); $width (posedge DQ6&&&CL5==1 , tpw_DQ0); $width (posedge DQ7&&&CL5==1 , tpw_DQ0); $width (posedge DQ0&&&CL6==1 , tpw_DQ0); $width (posedge DQ1&&&CL6==1 , tpw_DQ0); $width (posedge DQ2&&&CL6==1 , tpw_DQ0); $width (posedge DQ3&&&CL6==1 , tpw_DQ0); $width (posedge DQ4&&&CL6==1 , tpw_DQ0); $width (posedge DQ5&&&CL6==1 , tpw_DQ0); $width (posedge DQ6&&&CL6==1 , tpw_DQ0); $width (posedge DQ7&&&CL6==1 , tpw_DQ0); $width (posedge DQ0&&&CL7==1 , tpw_DQ0); $width (posedge DQ1&&&CL7==1 , tpw_DQ0); $width (posedge DQ2&&&CL7==1 , tpw_DQ0); $width (posedge DQ3&&&CL7==1 , tpw_DQ0); $width (posedge DQ4&&&CL7==1 , tpw_DQ0); $width (posedge DQ5&&&CL7==1 , tpw_DQ0); $width (posedge DQ6&&&CL7==1 , tpw_DQ0); $width (posedge DQ7&&&CL7==1 , tpw_DQ0); $width (posedge DQ0&&&CL8==1 , tpw_DQ0); $width (posedge DQ1&&&CL8==1 , tpw_DQ0); $width (posedge DQ2&&&CL8==1 , tpw_DQ0); $width (posedge DQ3&&&CL8==1 , tpw_DQ0); $width (posedge DQ4&&&CL8==1 , tpw_DQ0); $width (posedge DQ5&&&CL8==1 , tpw_DQ0); $width (posedge DQ6&&&CL8==1 , tpw_DQ0); $width (posedge DQ7&&&CL8==1 , tpw_DQ0); $width (posedge DQ0&&&CL9==1 , tpw_DQ0); $width (posedge DQ1&&&CL9==1 , tpw_DQ0); $width (posedge DQ2&&&CL9==1 , tpw_DQ0); $width (posedge DQ3&&&CL9==1 , tpw_DQ0); $width (posedge DQ4&&&CL9==1 , tpw_DQ0); $width (posedge DQ5&&&CL9==1 , tpw_DQ0); $width (posedge DQ6&&&CL9==1 , tpw_DQ0); $width (posedge DQ7&&&CL9==1 , tpw_DQ0); $width (posedge DQ0&&&CL10==1 , tpw_DQ0); $width (posedge DQ1&&&CL10==1 , tpw_DQ0); $width (posedge DQ2&&&CL10==1 , tpw_DQ0); $width (posedge DQ3&&&CL10==1 , tpw_DQ0); $width (posedge DQ4&&&CL10==1 , tpw_DQ0); $width (posedge DQ5&&&CL10==1 , tpw_DQ0); $width (posedge DQ6&&&CL10==1 , tpw_DQ0); $width (posedge DQ7&&&CL10==1 , tpw_DQ0); $width (negedge DQ0&&&CL5==1 , tpw_DQ0); $width (negedge DQ1&&&CL5==1 , tpw_DQ0); $width (negedge DQ2&&&CL5==1 , tpw_DQ0); $width (negedge DQ3&&&CL5==1 , tpw_DQ0); $width (negedge DQ4&&&CL5==1 , tpw_DQ0); $width (negedge DQ5&&&CL5==1 , tpw_DQ0); $width (negedge DQ6&&&CL5==1 , tpw_DQ0); $width (negedge DQ7&&&CL5==1 , tpw_DQ0); $width (negedge DQ0&&&CL6==1 , tpw_DQ0); $width (negedge DQ1&&&CL6==1 , tpw_DQ0); $width (negedge DQ2&&&CL6==1 , tpw_DQ0); $width (negedge DQ3&&&CL6==1 , tpw_DQ0); $width (negedge DQ4&&&CL6==1 , tpw_DQ0); $width (negedge DQ5&&&CL6==1 , tpw_DQ0); $width (negedge DQ6&&&CL6==1 , tpw_DQ0); $width (negedge DQ7&&&CL6==1 , tpw_DQ0); $width (negedge DQ0&&&CL7==1 , tpw_DQ0); $width (negedge DQ1&&&CL7==1 , tpw_DQ0); $width (negedge DQ2&&&CL7==1 , tpw_DQ0); $width (negedge DQ3&&&CL7==1 , tpw_DQ0); $width (negedge DQ4&&&CL7==1 , tpw_DQ0); $width (negedge DQ5&&&CL7==1 , tpw_DQ0); $width (negedge DQ6&&&CL7==1 , tpw_DQ0); $width (negedge DQ7&&&CL7==1 , tpw_DQ0); $width (negedge DQ0&&&CL8==1 , tpw_DQ0); $width (negedge DQ1&&&CL8==1 , tpw_DQ0); $width (negedge DQ2&&&CL8==1 , tpw_DQ0); $width (negedge DQ3&&&CL8==1 , tpw_DQ0); $width (negedge DQ4&&&CL8==1 , tpw_DQ0); $width (negedge DQ5&&&CL8==1 , tpw_DQ0); $width (negedge DQ6&&&CL8==1 , tpw_DQ0); $width (negedge DQ7&&&CL8==1 , tpw_DQ0); $width (negedge DQ0&&&CL9==1 , tpw_DQ0); $width (negedge DQ1&&&CL9==1 , tpw_DQ0); $width (negedge DQ2&&&CL9==1 , tpw_DQ0); $width (negedge DQ3&&&CL9==1 , tpw_DQ0); $width (negedge DQ4&&&CL9==1 , tpw_DQ0); $width (negedge DQ5&&&CL9==1 , tpw_DQ0); $width (negedge DQ6&&&CL9==1 , tpw_DQ0); $width (negedge DQ7&&&CL9==1 , tpw_DQ0); $width (negedge DQ0&&&CL10==1 , tpw_DQ0); $width (negedge DQ1&&&CL10==1 , tpw_DQ0); $width (negedge DQ2&&&CL10==1 , tpw_DQ0); $width (negedge DQ3&&&CL10==1 , tpw_DQ0); $width (negedge DQ4&&&CL10==1 , tpw_DQ0); $width (negedge DQ5&&&CL10==1 , tpw_DQ0); $width (negedge DQ6&&&CL10==1 , tpw_DQ0); $width (negedge DQ7&&&CL10==1 , tpw_DQ0); $width (posedge ODT&&&CL5==1 , tpw_DQ0); $width (posedge ODT&&&CL6==1 , tpw_DQ0); $width (posedge ODT&&&CL7==1 , tpw_DQ0); $width (posedge ODT&&&CL8==1 , tpw_DQ0); $width (posedge ODT&&&CL9==1 , tpw_DQ0); $width (posedge ODT&&&CL10==1 , tpw_DQ0); $width (posedge CSNeg&&&CL5==1 , tpw_DQ0); $width (posedge CSNeg&&&CL6==1 , tpw_DQ0); $width (posedge CSNeg&&&CL7==1 , tpw_DQ0); $width (posedge CSNeg&&&CL8==1 , tpw_DQ0); $width (posedge CSNeg&&&CL9==1 , tpw_DQ0); $width (posedge CSNeg&&&CL10==1 , tpw_DQ0); $width (posedge RASNeg&&&CL5==1 , tpw_DQ0); $width (posedge RASNeg&&&CL6==1 , tpw_DQ0); $width (posedge RASNeg&&&CL7==1 , tpw_DQ0); $width (posedge RASNeg&&&CL8==1 , tpw_DQ0); $width (posedge RASNeg&&&CL9==1 , tpw_DQ0); $width (posedge RASNeg&&&CL10==1 , tpw_DQ0); $width (posedge CASNeg&&&CL5==1 , tpw_DQ0); $width (posedge CASNeg&&&CL6==1 , tpw_DQ0); $width (posedge CASNeg&&&CL7==1 , tpw_DQ0); $width (posedge CASNeg&&&CL8==1 , tpw_DQ0); $width (posedge CASNeg&&&CL9==1 , tpw_DQ0); $width (posedge CASNeg&&&CL10==1 , tpw_DQ0); $width (posedge WENeg&&&CL5==1 , tpw_DQ0); $width (posedge WENeg&&&CL6==1 , tpw_DQ0); $width (posedge WENeg&&&CL7==1 , tpw_DQ0); $width (posedge WENeg&&&CL8==1 , tpw_DQ0); $width (posedge WENeg&&&CL9==1 , tpw_DQ0); $width (posedge WENeg&&&CL10==1 , tpw_DQ0); $width (negedge ODT&&&CL5==1 , tpw_DQ0); $width (negedge ODT&&&CL6==1 , tpw_DQ0); $width (negedge ODT&&&CL7==1 , tpw_DQ0); $width (negedge ODT&&&CL8==1 , tpw_DQ0); $width (negedge ODT&&&CL9==1 , tpw_DQ0); $width (negedge ODT&&&CL10==1 , tpw_DQ0); $width (negedge CSNeg&&&CL5==1 , tpw_DQ0); $width (negedge CSNeg&&&CL6==1 , tpw_DQ0); $width (negedge CSNeg&&&CL7==1 , tpw_DQ0); $width (negedge CSNeg&&&CL8==1 , tpw_DQ0); $width (negedge CSNeg&&&CL9==1 , tpw_DQ0); $width (negedge CSNeg&&&CL10==1 , tpw_DQ0); $width (negedge RASNeg&&&CL5==1 , tpw_DQ0); $width (negedge RASNeg&&&CL6==1 , tpw_DQ0); $width (negedge RASNeg&&&CL7==1 , tpw_DQ0); $width (negedge RASNeg&&&CL8==1 , tpw_DQ0); $width (negedge RASNeg&&&CL9==1 , tpw_DQ0); $width (negedge RASNeg&&&CL10==1 , tpw_DQ0); $width (negedge CASNeg&&&CL5==1 , tpw_DQ0); $width (negedge CASNeg&&&CL6==1 , tpw_DQ0); $width (negedge CASNeg&&&CL7==1 , tpw_DQ0); $width (negedge CASNeg&&&CL8==1 , tpw_DQ0); $width (negedge CASNeg&&&CL9==1 , tpw_DQ0); $width (negedge CASNeg&&&CL10==1 , tpw_DQ0); $width (negedge WENeg&&&CL5==1 , tpw_DQ0); $width (negedge WENeg&&&CL6==1 , tpw_DQ0); $width (negedge WENeg&&&CL7==1 , tpw_DQ0); $width (negedge WENeg&&&CL8==1 , tpw_DQ0); $width (negedge WENeg&&&CL9==1 , tpw_DQ0); $width (negedge WENeg&&&CL10==1 , tpw_DQ0); $width (posedge DQSNeg&&&ChDQSNegCL5 , tpw_DQS_posedge); $width (posedge DQSNeg&&&ChDQSNegCL6 , tpw_DQS_posedge); $width (posedge DQSNeg&&&ChDQSNegCL7 , tpw_DQS_posedge); $width (posedge DQSNeg&&&ChDQSNegCL8 , tpw_DQS_posedge); $width (posedge DQSNeg&&&ChDQSNegCL9 , tpw_DQS_posedge); $width (posedge DQSNeg&&&ChDQSNegCL10, tpw_DQS_posedge); $width (negedge DQSNeg&&&ChDQSNegCL5 , tpw_DQS_negedge); $width (negedge DQSNeg&&&ChDQSNegCL6 , tpw_DQS_negedge); $width (negedge DQSNeg&&&ChDQSNegCL7 , tpw_DQS_negedge); $width (negedge DQSNeg&&&ChDQSNegCL8 , tpw_DQS_negedge); $width (negedge DQSNeg&&&ChDQSNegCL9 , tpw_DQS_negedge); $width (negedge DQSNeg&&&ChDQSNegCL10, tpw_DQS_negedge); $width (posedge DQS&&&ChNormalCL5 , tpw_DQS_posedge); $width (posedge DQS&&&ChNormalCL6 , tpw_DQS_posedge); $width (posedge DQS&&&ChNormalCL7 , tpw_DQS_posedge); $width (posedge DQS&&&ChNormalCL8 , tpw_DQS_posedge); $width (posedge DQS&&&ChNormalCL9 , tpw_DQS_posedge); $width (posedge DQS&&&ChNormalCL10 , tpw_DQS_posedge); $width (negedge DQS&&&ChNormalCL5 , tpw_DQS_negedge); $width (negedge DQS&&&ChNormalCL6 , tpw_DQS_negedge); $width (negedge DQS&&&ChNormalCL7 , tpw_DQS_negedge); $width (negedge DQS&&&ChNormalCL8 , tpw_DQS_negedge); $width (negedge DQS&&&ChNormalCL9 , tpw_DQS_negedge); $width (negedge DQS&&&ChNormalCL10 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL5 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL6 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL7 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL8 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL9 , tpw_DQS_negedge); $width (posedge DQSNeg&&&CheckPostambleCL10, tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL5 , tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL6 , tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL7 , tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL8 , tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL9 , tpw_DQS_negedge); $width (negedge DQS&&&ChPostambleCL10 , tpw_DQS_negedge); $width (posedge CK&&&ChEnable_CK5 , tpw_CK_posedge); $width (posedge CK&&&ChEnable_CK6 , tpw_CK_posedge); $width (posedge CK&&&ChEnable_CK7 , tpw_CK_posedge); $width (posedge CK&&&ChEnable_CK8 , tpw_CK_posedge); $width (posedge CK&&&ChEnable_CK9 , tpw_CK_posedge); $width (posedge CK&&&ChEnable_CK10 , tpw_CK_posedge); $width (negedge CK&&&ChEnable_CK5 , tpw_CK_negedge); $width (negedge CK&&&ChEnable_CK6 , tpw_CK_negedge); $width (negedge CK&&&ChEnable_CK7 , tpw_CK_negedge); $width (negedge CK&&&ChEnable_CK8 , tpw_CK_negedge); $width (negedge CK&&&ChEnable_CK9 , tpw_CK_negedge); $width (negedge CK&&&ChEnable_CK10 , tpw_CK_negedge); $width (negedge RESETNeg&&&ChEnable_PoweredUp_eq_0 , tpw_RESETNeg_negedge); $width (negedge RESETNeg&&&ChEnable_PoweredUp_eq_1 , tpw_RESETNeg_negedge); $period(negedge CK&&&ChEnable_CK5, tperiod_CK); $period(negedge CK&&&ChEnable_CK6, tperiod_CK); $period(negedge CK&&&ChEnable_CK7, tperiod_CK); $period(negedge CK&&&ChEnable_CK8, tperiod_CK); $period(negedge CK&&&ChEnable_CK9, tperiod_CK); $period(negedge CK&&&ChEnable_CK10,tperiod_CK); $period(posedge CK&&&ChEnable_CK5, tperiod_CK); $period(posedge CK&&&ChEnable_CK6, tperiod_CK); $period(posedge CK&&&ChEnable_CK7, tperiod_CK); $period(posedge CK&&&ChEnable_CK8, tperiod_CK); $period(posedge CK&&&ChEnable_CK9, tperiod_CK); $period(posedge CK&&&ChEnable_CK10,tperiod_CK); endspecify //tdevice parameters aligned to model timescale time tdevice_tRC_ts = tdevice_tRC; time tdevice_tRRD_ts = tdevice_tRRD * 1000; time tdevice_tRCD_ts = tdevice_tRCD; time tdevice_tFAW_ts = tdevice_tFAW * 1000; time tdevice_tRASMIN_ts = tdevice_tRASMIN * 1000; time tdevice_tRASMAX_ts = tdevice_tRASMAX * 1000; time tdevice_tRTP_ts = tdevice_tRTP ; time tdevice_tWR_ts = tdevice_tWR * 1000; time tdevice_tWTR_ts = tdevice_tWTR; time tdevice_tRP_ts = tdevice_tRP; time tdevice_tRFCMIN_ts = tdevice_tRFCMIN * 1000; time tdevice_tREFPer_ts = tdevice_REFPer * 1000; time tdevice_tCKAVGMAX_ts = tdevice_tCKAVGMAX; time tdevice_tMRD_ts = tdevice_tMRD * 1000; time tdevice_tMOD_ts = tdevice_tMOD; time tdevice_tXPR_ts = tdevice_tXPR; time tdevice_tZQINIT_ts = tdevice_tZQINIT * 1000; time tdevice_tZQOPER_ts = tdevice_tZQOPER * 1000; time tdevice_tZQCS_ts = tdevice_tZQCS * 1000; time tdevice_tCKSRX_ts = tdevice_tCKSRX; time tdevice_tCKSRE_ts = tdevice_tCKSRE; time tdevice_tCKESR_ts = tdevice_tCKESR; time tdevice_tWLDQSEN_ts = tdevice_tWLDQSEN; time tdevice_tWLMRD_ts = tdevice_tWLMRD * 1000; time tdevice_tWLOMAX_ts = tdevice_tWLOMAX * 1000; time tdevice_tWLOEMAX_ts = tdevice_tWLOEMAX * 1000; //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// // main FSM states parameter precharged =4'd0; parameter refreshing =4'd1; parameter mrsetting =4'd2; parameter activating =4'd3; parameter active =4'd4; parameter reading =4'd5; parameter readingap =4'd6; parameter writting =4'd7; parameter writtingap =4'd8; parameter precharging =4'd9; parameter prechall =4'd10; parameter zq_calib =4'd11; reg [4:0] Curr_bank_state[BankNum : 0] ; reg [4:0] Next_bank_state[BankNum : 0] ; //commands parameter MRS =4'd0; parameter REF =4'd1; parameter DESL =4'd2; parameter NOP =4'd3; parameter PRE =4'd4; parameter ACT =4'd5; parameter WRIT =4'd6; parameter READ =4'd7; parameter ILL =4'd8; parameter ZQCL =4'd9; parameter ZQCS =4'd10; reg [4:0] Command; // states during initialization parameter illegal =4'd0; parameter init0 =4'd1; parameter init1 =4'd2; parameter init2 =4'd3; parameter init3 =4'd4; parameter init4 =4'd5; parameter init5 =4'd6; parameter init6 =4'd7; reg [4:0] Current_state; reg [4:0] Next_state; always @(DIn, DOut_zd) begin if (DIn==DOut_zd || DIn===8'bx) deq=1'b0; else deq=1'b1; end always @(TDQS) begin if (TDQS===1'bx) dmq=1'b0; else dmq=1'b1; end // check when data is generated from model to avoid setuphold check in // those occasions assign deg=deq; assign dmg=dmq; initial begin //Timing model determination //assumptions: //1. TimingModel has format as //2. TimingModel does not have more then 20 characters tmp_timing = TimingModel;//copy of TimingModel i = 19; while ((i >= 0) && (found != 1'b1))//search for first non null character begin //i keeps position of first non null character j = 7; while ((j >= 0) && (found != 1'b1)) begin if (tmp_timing[i*8+j] != 1'd0) found = 1'b1; else j = j-1; end i = i - 1; end i = i +1; pos = i; if (found)//if non null character is found begin for (j=0;j<=5;j=j+1) begin for (k=0;k<=7;k=k+1) begin char[j][k] = TimingModel[(pos-13-j)*8+k]; end end end end // initialize memory and load preload files if any initial begin: InitMemory integer i; for (i=0;i<=((BankNum+1)*(MemSize+1)-1);i=i+1) begin Mem[i] = -2; end // - Memory preload file // edj1308ba.mem file // // - comment // @aaaaaaa - stands for address within memory, // 13 LSBits determine address within bank, // other bits determine bank address, // bytes within bank are written row by row // dd -
is byte data to be written at Mem(aaaaaaa++) // (aaaaaaa is incremented at every load) if (UserPreload && !(mem_file_name == "none")) $readmemh(mem_file_name,Mem); end // initialize burst sequences initial begin Seq[0] = 0; Seq[1] = 1; Seq[2] = 2; Seq[3] = 3; Seq[4] = 4; Seq[5] = 5; Seq[6] = 6; Seq[7] = 7; Seq[8] = 0; Seq[9] = 1; Seq[10] = 2; Seq[11] = -1; Seq[12] = 4; Seq[13] = 5; Seq[14] = 6; Seq[15] = 3; Seq[16] = 0; Seq[17] = 1; Seq[18] = -2; Seq[19] = -1; Seq[20] = 4; Seq[21] = 5; Seq[22] = 2; Seq[23] = 3; Seq[24] = 0; Seq[25] = -3; Seq[26] = -2; Seq[27] = -1; Seq[28] = 4; Seq[29] = 1; Seq[30] = 2; Seq[31] = 3; Seq[32] = 0; Seq[33] = 1; Seq[34] = 2; Seq[35] = 3; Seq[36] = -4; Seq[37] = -3; Seq[38] = -2; Seq[39] = -1; Seq[40] = 0; Seq[41] = 1; Seq[42] = 2; Seq[43] = -1; Seq[44] = -4; Seq[45] = -3; Seq[46] = -2; Seq[47] = -5; Seq[48] = 0; Seq[49] = 1; Seq[50] = -2; Seq[51] = -1; Seq[52] = -4; Seq[53] = -3; Seq[54] = -6; Seq[55] = -5; Seq[56] = 0; Seq[57] = -3; Seq[58] = -2; Seq[59] = -1; Seq[60] = -4; Seq[61] = -7; Seq[62] = -6; Seq[63] = -5; Inl[0] = 0; Inl[1] = 1; Inl[2] = 2; Inl[3] = 3; Inl[4] = 4; Inl[5] = 5; Inl[6] = 6; Inl[7] = 7; Inl[8] = 0; Inl[9] = -1; Inl[10] = 2; Inl[11] = 1; Inl[12] = 4; Inl[13] = 3; Inl[14] = 6; Inl[15] = 5; Inl[16] = 0; Inl[17] = 1; Inl[18] = -2; Inl[19] = -1; Inl[20] = 4; Inl[21] = 5; Inl[22] = 2; Inl[23] = 3; Inl[24] = 0; Inl[25] = -1; Inl[26] = -2; Inl[27] = -3; Inl[28] = 4; Inl[29] = 3; Inl[30] = 2; Inl[31] = 1; Inl[32] = 0; Inl[33] = 1; Inl[34] = 2; Inl[35] = 3; Inl[36] = -4; Inl[37] = -3; Inl[38] = -2; Inl[39] = -1; Inl[40] = 0; Inl[41] = -1; Inl[42] = 2; Inl[43] = 1; Inl[44] = -4; Inl[45] = -5; Inl[46] = -2; Inl[47] = -3; Inl[48] = 0; Inl[49] = 1; Inl[50] = -2; Inl[51] = -1; Inl[52] = -4; Inl[53] = -3; Inl[54] = -6; Inl[55] = -5; Inl[56] = 0; Inl[57] = -1; Inl[58] = -2; Inl[59] = -3; Inl[60] = -4; Inl[61] = -5; Inl[62] = -6; Inl[63] = -7; end initial begin for(i=0;i<=BankNum;i=i+1) begin for(j=0;j<=10;j=j+1) begin read_sch[i][j] = 1'b0; preamble[i][j] = 1'b0; wait_read[i][j] = 1'b0; write_sch[i][j] = 1'b0; AL_elapsed[i][j] = 1'b0; delay[i*11+j] = 0; temp_bank[i*11+j] = 0; temp_row[i*11+j] = 0; temp_column[i*11+j] = 0; end Curr_bank_state[i] = precharged; Next_bank_state[i] = precharged; tRC_in[i] = 1'b1;// tRC_out[i] = 1'b1;// tRP_in[i] = 1'b0;// tRP_out[i] = 1'b0;// tRCD_in[i] = 1'b0;// tRCD_out[i] = 1'b0;// tRASMIN_in[i] = 1'b1;// tRASMIN_out[i] = 1'b1;// tRASMAX_in[i] = 1'b0;// tRASMAX_out[i] = 1'b0;// tRTP_in[i] = 1'b1;// tRTP_out[i] = 1'b1;// tWR_in[i] = 1'b1;// tWR_out[i] = 1'b1;// tWTR_in[i] = 1'b1;// tWTR_out[i] = 1'b1;// tCKESR_in[i] = 1'b0;// tCKESR_out[i] = 1'b0;// end for(i=0;i<=3;i=i+1) begin act_num[i] = 0; tFAW_in[i] = 1'b0; tFAW_out[i] = 1'b0; end end initial begin Current_state = init0; Next_state = init0; Command = MRS; CK_cnt = 0; rd_wr_cnt = 0; wr_wr_cnt = 0; rd_rd_cnt = 0; tRRD_in = 1'b1;// tRRD_out = 1'b1;// tRFCMIN_in = 1'b0;// tRFCMIN_out = 1'b0;// tXS_in = 1'b0;// tXS_out = 1'b0;// tREFPer_in = 1'b0;// tREFPer_out = 1'b0;// tCKAVGMAX_in = 1'b0;// tCKAVGMAX_out = 1'b0;// tCKSRX_in = 1'b0;// tCKSRX_out = 1'b0;// tCKSRE_in = 1'b0;// tCKSRE_out = 1'b0;// tWLDQSEN_in = 1'b0;// tWLDQSEN_out = 1'b0;// tWLMRD_in = 1'b0;// tWLMRD_out = 1'b0;// tWLOMAX_in = 1'b0;// tWLOMAX_out = 1'b0;// tWLOEMAX_in = 1'b0;// tWLOEMAX_out = 1'b0;// tMRD_in = 1'b0;// tMRD_out = 1'b0;// tMOD_in = 1'b0;// tMOD_out = 1'b0;// tMOD_in_tmp = 1'b0; tMOD_out_tmp = 1'b1; tXPR_in = 1'b0;// tXPR_out = 1'b0;// tZQINIT_in = 1'b0;// tZQINIT_out = 1'b0;// tZQOPER_in = 1'b0;// tZQOPER_out = 1'b0;// mrs_active = 1'b0;// tZQCS_in = 1'b0;// tZQCS_out = 1'b0;// for(i=0;i<=BankNum;i=i+1) begin precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; rd_act_cnt[i] = 0; end end always @(posedge CK) begin: Clock_init if (CK && ~PoweredUp) CK_COUNT = CK_COUNT + 1; end always @(CK_stable,CK_COUNT) begin: PowerUp if (CK_stable && CK_COUNT >= 5 && ~PoweredUp) PoweredUp = 1'b1; end always @(posedge tRC_in[0]) begin: tRC0r #(tdevice_tRC_ts - 1000) tRC_out[0] = tRC_in[0]; end always @(negedge tRC_in[0]) begin: tRC0f #(1*TScal) tRC_out[0] = tRC_in[0]; end always @(posedge tRC_in[1]) begin: tRC1r #(tdevice_tRC_ts - 1000) tRC_out[1] = tRC_in[1]; end always @(negedge tRC_in[1]) begin: tRC1f #(1*TScal) tRC_out[1] = tRC_in[1]; end always @(posedge tRC_in[2]) begin: tRC2r #(tdevice_tRC_ts - 1000) tRC_out[2] = tRC_in[2]; end always @(negedge tRC_in[2]) begin: tRC2f #(1*TScal) tRC_out[2] = tRC_in[2]; end always @(posedge tRC_in[3]) begin: tRC3r #(tdevice_tRC_ts - 1000) tRC_out[3] = tRC_in[3]; end always @(negedge tRC_in[3]) begin: tRC3f #(1*TScal) tRC_out[3] = tRC_in[3]; end always @(posedge tRC_in[4]) begin: tRC4r #(tdevice_tRC_ts - 1000) tRC_out[4] = tRC_in[4]; end always @(negedge tRC_in[4]) begin: tRC4f #(1*TScal) tRC_out[4] = tRC_in[4]; end always @(posedge tRC_in[5]) begin: tRC5r #(tdevice_tRC_ts - 1000) tRC_out[5] = tRC_in[5]; end always @(negedge tRC_in[5]) begin: tRC5f #(1*TScal) tRC_out[5] = tRC_in[5]; end always @(posedge tRC_in[6]) begin: tRC6r #(tdevice_tRC_ts - 1000) tRC_out[6] = tRC_in[6]; end always @(negedge tRC_in[6]) begin: tRC6f #(1*TScal) tRC_out[6] = tRC_in[6]; end always @(posedge tRC_in[7]) begin: tRC7r #(tdevice_tRC_ts - 1000) tRC_out[7] = tRC_in[7]; end always @(negedge tRC_in[7]) begin: tRC7f #(1*TScal) tRC_out[7] = tRC_in[7]; end always @(posedge tRRD_in) begin: tRRDr #(tdevice_tRRD_ts - 1000) tRRD_out = tRRD_in; end always @(negedge tRRD_in) begin: tRRDf #(1*TScal) tRRD_out = tRRD_in; end always @(posedge tRCD_in[0]) begin: tRCD0r #(tdevice_tRCD_ts - 1000) tRCD_out[0] = tRCD_in[0]; end always @(negedge tRCD_in[0]) begin: tRCD0f #(1*TScal) tRCD_out[0] = tRCD_in[0]; end always @(posedge tRCD_in[1]) begin: tRCD1r #(tdevice_tRCD_ts - 1000) tRCD_out[1] = tRCD_in[1]; end always @(negedge tRCD_in[1]) begin: tRCD1f #(1*TScal) tRCD_out[1] = tRCD_in[1]; end always @(posedge tRCD_in[2]) begin: tRCD2r #(tdevice_tRCD_ts - 1000) tRCD_out[2] = tRCD_in[2]; end always @(negedge tRCD_in[2]) begin: tRCD2f #(1*TScal) tRCD_out[2] = tRCD_in[2]; end always @(posedge tRCD_in[3]) begin: tRCD3r #(tdevice_tRCD_ts - 1000) tRCD_out[3] = tRCD_in[3]; end always @(negedge tRCD_in[3]) begin: tRCD3f #(1*TScal) tRCD_out[3] = tRCD_in[3]; end always @(posedge tRCD_in[4]) begin: tRCD4r #(tdevice_tRCD_ts - 1000) tRCD_out[4] = tRCD_in[4]; end always @(negedge tRCD_in[4]) begin: tRCD4f #(1*TScal) tRCD_out[4] = tRCD_in[4]; end always @(posedge tRCD_in[5]) begin: tRCD5r #(tdevice_tRCD_ts - 1000) tRCD_out[5] = tRCD_in[5]; end always @(negedge tRCD_in[5]) begin: tRCD5f #(1*TScal) tRCD_out[5] = tRCD_in[5]; end always @(posedge tRCD_in[6]) begin: tRCD6r #(tdevice_tRCD_ts - 1000) tRCD_out[6] = tRCD_in[6]; end always @(negedge tRCD_in[6]) begin: tRCD6f #(1*TScal) tRCD_out[6] = tRCD_in[6]; end always @(posedge tRCD_in[7]) begin: tRCD7r #(tdevice_tRCD_ts - 1000) tRCD_out[7] = tRCD_in[7]; end always @(negedge tRCD_in[7]) begin: tRCD7f #(1*TScal) tRCD_out[7] = tRCD_in[7]; end always @(posedge tFAW_in[0]) begin: tFAW0r #(tdevice_tFAW_ts - 1000) tFAW_out[0] = tFAW_in[0]; end always @(negedge tFAW_in[0]) begin: tFAW0f #(1*TScal) tFAW_out[0] = tFAW_in[0]; end always @(posedge tFAW_in[1]) begin: tFAW1r #(tdevice_tFAW_ts - 1000) tFAW_out[1] = tFAW_in[1]; end always @(negedge tFAW_in[1]) begin: tFAW1f #(1*TScal) tFAW_out[1] = tFAW_in[1]; end always @(posedge tFAW_in[2]) begin: tFAW2r #(tdevice_tFAW_ts - 1000) tFAW_out[2] = tFAW_in[2]; end always @(negedge tFAW_in[2]) begin: tFAW2f #(1*TScal) tFAW_out[2] = tFAW_in[2]; end always @(posedge tFAW_in[3]) begin: tFAW3r #(tdevice_tFAW_ts - 1000) tFAW_out[3] = tFAW_in[3]; end always @(negedge tFAW_in[3]) begin: tFAW3f #(1*TScal) tFAW_out[3] = tFAW_in[3]; end always @(posedge tRASMIN_in[0]) begin: tRASMIN0r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[0] = tRASMIN_in[0]; end always @(negedge tRASMIN_in[0]) begin: tRASMIN0f #(1*TScal) tRASMIN_out[0] = tRASMIN_in[0]; end always @(posedge tRASMIN_in[1]) begin: tRASMIN1r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[1] = tRASMIN_in[1]; end always @(negedge tRASMIN_in[1]) begin: tRASMIN1f #(1*TScal) tRASMIN_out[1] = tRASMIN_in[1]; end always @(posedge tRASMIN_in[2]) begin: tRASMIN2r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[2] = tRASMIN_in[2]; end always @(negedge tRASMIN_in[2]) begin: tRASMIN2f #(1*TScal) tRASMIN_out[2] = tRASMIN_in[2]; end always @(posedge tRASMIN_in[3]) begin: tRASMIN3r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[3] = tRASMIN_in[3]; end always @(negedge tRASMIN_in[3]) begin: tRASMIN3f #(1*TScal) tRASMIN_out[3] = tRASMIN_in[3]; end always @(posedge tRASMIN_in[4]) begin: tRASMIN4r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[4] = tRASMIN_in[4]; end always @(negedge tRASMIN_in[4]) begin: tRASMIN4f #(1*TScal) tRASMIN_out[4] = tRASMIN_in[4]; end always @(posedge tRASMIN_in[5]) begin: tRASMIN5r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[5] = tRASMIN_in[5]; end always @(negedge tRASMIN_in[5]) begin: tRASMIN5f #(1*TScal) tRASMIN_out[5] = tRASMIN_in[5]; end always @(posedge tRASMIN_in[6]) begin: tRASMIN6r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[6] = tRASMIN_in[6]; end always @(negedge tRASMIN_in[6]) begin: tRASMIN6f #(1*TScal) tRASMIN_out[6] = tRASMIN_in[6]; end always @(posedge tRASMIN_in[7]) begin: tRASMIN7r #(tdevice_tRASMIN_ts - 1000) tRASMIN_out[7] = tRASMIN_in[7]; end always @(negedge tRASMIN_in[7]) begin: tRASMIN7f #(1*TScal) tRASMIN_out[7] = tRASMIN_in[7]; end always @(posedge tRASMAX_in[0]) begin: tRASMAX0r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[0] = tRASMAX_in[0]; end always @(negedge tRASMAX_in[0]) begin: tRASMAX0f #(1*TScal) tRASMAX_out[0] = tRASMAX_in[0]; end always @(posedge tRASMAX_in[1]) begin: tRASMAX1r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[1] = tRASMAX_in[1]; end always @(negedge tRASMAX_in[1]) begin: tRASMAX1f #(1*TScal) tRASMAX_out[1] = tRASMAX_in[1]; end always @(posedge tRASMAX_in[2]) begin: tRASMAX2r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[2] = tRASMAX_in[2]; end always @(negedge tRASMAX_in[2]) begin: tRASMAX2f #(1*TScal) tRASMAX_out[2] = tRASMAX_in[2]; end always @(posedge tRASMAX_in[3]) begin: tRASMAX3r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[3] = tRASMAX_in[3]; end always @(negedge tRASMAX_in[3]) begin: tRASMAX3f #(1*TScal) tRASMAX_out[3] = tRASMAX_in[3]; end always @(posedge tRASMAX_in[4]) begin: tRASMAX4r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[4] = tRASMAX_in[4]; end always @(negedge tRASMAX_in[4]) begin: tRASMAX4f #(1*TScal) tRASMAX_out[4] = tRASMAX_in[4]; end always @(posedge tRASMAX_in[5]) begin: tRASMAX5r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[5] = tRASMAX_in[5]; end always @(negedge tRASMAX_in[5]) begin: tRASMAX5f #(1*TScal) tRASMAX_out[5] = tRASMAX_in[5]; end always @(posedge tRASMAX_in[6]) begin: tRASMAX6r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[6] = tRASMAX_in[6]; end always @(negedge tRASMAX_in[6]) begin: tRASMAX6f #(1*TScal) tRASMAX_out[6] = tRASMAX_in[6]; end always @(posedge tRASMAX_in[7]) begin: tRASMAX7r #(tdevice_tRASMAX_ts - 1000) tRASMAX_out[7] = tRASMAX_in[7]; end always @(negedge tRASMAX_in[7]) begin: tRASMAX7f #(1*TScal) tRASMAX_out[7] = tRASMAX_in[7]; end always @(posedge tRTP_in[0]) begin: tRTP0r #(tdevice_tRTP_ts - 1000) tRTP_out[0] = tRTP_in[0]; end always @(negedge tRTP_in[0]) begin: tRTP0f #(1*TScal) tRTP_out[0] = tRTP_in[0]; end always @(posedge tRTP_in[1]) begin: tRTP1r #(tdevice_tRTP_ts - 1000) tRTP_out[1] = tRTP_in[1]; end always @(negedge tRTP_in[1]) begin: tRTP1f #(1*TScal) tRTP_out[1] = tRTP_in[1]; end always @(posedge tRTP_in[2]) begin: tRTP2r #(tdevice_tRTP_ts - 1000) tRTP_out[2] = tRTP_in[2]; end always @(negedge tRTP_in[2]) begin: tRTP2f #(1*TScal) tRTP_out[2] = tRTP_in[2]; end always @(posedge tRTP_in[3]) begin: tRTP3r #(tdevice_tRTP_ts - 1000) tRTP_out[3] = tRTP_in[3]; end always @(negedge tRTP_in[3]) begin: tRTP3f #(1*TScal) tRTP_out[3] = tRTP_in[3]; end always @(posedge tRTP_in[4]) begin: tRTP4r #(tdevice_tRTP_ts - 1000) tRTP_out[4] = tRTP_in[4]; end always @(negedge tRTP_in[4]) begin: tRTP4f #(1*TScal) tRTP_out[4] = tRTP_in[4]; end always @(posedge tRTP_in[5]) begin: tRTP5r #(tdevice_tRTP_ts - 1000) tRTP_out[5] = tRTP_in[5]; end always @(negedge tRTP_in[5]) begin: tRTP5f #(1*TScal) tRTP_out[5] = tRTP_in[5]; end always @(posedge tRTP_in[6]) begin: tRTP6r #(tdevice_tRTP_ts - 1000) tRTP_out[6] = tRTP_in[6]; end always @(negedge tRTP_in[6]) begin: tRTP6f #(1*TScal) tRTP_out[6] = tRTP_in[6]; end always @(posedge tRTP_in[7]) begin: tRTP7r #(tdevice_tRTP_ts - 1000) tRTP_out[7] = tRTP_in[7]; end always @(negedge tRTP_in[7]) begin: tRTP7f #(1*TScal) tRTP_out[7] = tRTP_in[7]; end always @(posedge tWR_in[0]) begin: tWR0r #(tdevice_tWR_ts - 1000) tWR_out[0] = tWR_in[0]; end always @(negedge tWR_in[0]) begin: tWR0f #(1*TScal) tWR_out[0] = tWR_in[0]; end always @(posedge tWR_in[1]) begin: tWR1r #(tdevice_tWR_ts - 1000) tWR_out[1] = tWR_in[1]; end always @(negedge tWR_in[1]) begin: tWR1f #(1*TScal) tWR_out[1] = tWR_in[1]; end always @(posedge tWR_in[2]) begin: tWR2r #(tdevice_tWR_ts - 1000) tWR_out[2] = tWR_in[2]; end always @(negedge tWR_in[2]) begin: tWR2f #(1*TScal) tWR_out[2] = tWR_in[2]; end always @(posedge tWR_in[3]) begin: tWR3r #(tdevice_tWR_ts - 1000) tWR_out[3] = tWR_in[3]; end always @(negedge tWR_in[3]) begin: tWR3f #(1*TScal) tWR_out[3] = tWR_in[3]; end always @(posedge tWR_in[4]) begin: tWR4r #(tdevice_tWR_ts - 1000) tWR_out[4] = tWR_in[4]; end always @(negedge tWR_in[4]) begin: tWR4f #(1*TScal) tWR_out[4] = tWR_in[4]; end always @(posedge tWR_in[5]) begin: tWR5r #(tdevice_tWR_ts - 1000) tWR_out[5] = tWR_in[5]; end always @(negedge tWR_in[5]) begin: tWR5f #(1*TScal) tWR_out[5] = tWR_in[5]; end always @(posedge tWR_in[6]) begin: tWR6r #(tdevice_tWR_ts - 1000) tWR_out[6] = tWR_in[6]; end always @(negedge tWR_in[6]) begin: tWR6f #(1*TScal) tWR_out[6] = tWR_in[6]; end always @(posedge tWR_in[7]) begin: tWR7r #(tdevice_tWR_ts - 1000) tWR_out[7] = tWR_in[7]; end always @(negedge tWR_in[7]) begin: tWR7f #(1*TScal) tWR_out[7] = tWR_in[7]; end always @(posedge tWTR_in[0]) begin: tWTR0r #(tdevice_tWTR_ts - 1000) tWTR_out[0] = tWTR_in[0]; end always @(negedge tWTR_in[0]) begin: tWTR0f #(1*TScal) tWTR_out[0] = tWTR_in[0]; end always @(posedge tWTR_in[1]) begin: tWTR1r #(tdevice_tWTR_ts - 1000) tWTR_out[1] = tWTR_in[1]; end always @(negedge tWR_in[1]) begin: tWTR1f #(1*TScal) tWTR_out[1] = tWTR_in[1]; end always @(posedge tWTR_in[2]) begin: tWTR2r #(tdevice_tWTR_ts - 1000) tWTR_out[2] = tWTR_in[2]; end always @(negedge tWTR_in[2]) begin: tWTR2f #(1*TScal) tWTR_out[2] = tWTR_in[2]; end always @(posedge tWTR_in[3]) begin: tWTR3r #(tdevice_tWTR_ts - 1000) tWTR_out[3] = tWTR_in[3]; end always @(negedge tWTR_in[3]) begin: tWTR3f #(1*TScal) tWTR_out[3] = tWTR_in[3]; end always @(posedge tWTR_in[4]) begin: tWTR4r #(tdevice_tWTR_ts - 1000) tWTR_out[4] = tWTR_in[4]; end always @(negedge tWTR_in[4]) begin: tWTR4f #(1*TScal) tWTR_out[4] = tWTR_in[4]; end always @(posedge tWTR_in[5]) begin: tWTR5r #(tdevice_tWTR_ts - 1000) tWTR_out[5] = tWTR_in[5]; end always @(negedge tWTR_in[5]) begin: tWTR5f #(1*TScal) tWTR_out[5] = tWTR_in[5]; end always @(posedge tWTR_in[6]) begin: tWTR6r #(tdevice_tWTR_ts - 1000) tWTR_out[6] = tWTR_in[6]; end always @(negedge tWTR_in[6]) begin: tWTR6f #(1*TScal) tWTR_out[6] = tWTR_in[6]; end always @(posedge tWTR_in[7]) begin: tWTR7r #(tdevice_tWTR_ts - 1000) tWTR_out[7] = tWTR_in[7]; end always @(negedge tWTR_in[7]) begin: tWTR7f #(1*TScal) tWTR_out[7] = tWTR_in[7]; end always @(posedge tCKESR_in[0]) begin: tCKESRr #(tdevice_tCKESR_ts - 1000) tCKESR_out[0] = tCKESR_in[0]; end always @(negedge tCKESR_in[0]) begin: tCKESR0f #(1*TScal) tCKESR_out[0] = tCKESR_in[0]; end always @(posedge tCKESR_in[1]) begin: tCKESR1r #(tdevice_tCKESR_ts - 1000) tCKESR_out[1] = tCKESR_in[1]; end always @(negedge tCKESR_in[1]) begin: tCKESR1f #(1*TScal) tCKESR_out[1] = tCKESR_in[1]; end always @(posedge tCKESR_in[2]) begin: tCKESR2r #(tdevice_tCKESR_ts - 1000) tCKESR_out[2] = tCKESR_in[2]; end always @(negedge tCKESR_in[2]) begin: tCKESR2f #(1*TScal) tCKESR_out[2] = tCKESR_in[2]; end always @(posedge tCKESR_in[3]) begin: tCKESR3r #(tdevice_tCKESR_ts - 1000) tCKESR_out[3] = tCKESR_in[3]; end always @(negedge tCKESR_in[3]) begin: tCKESR3f #(1*TScal) tCKESR_out[3] = tCKESR_in[3]; end always @(posedge tCKESR_in[4]) begin: tCKESR4r #(tdevice_tCKESR_ts - 1000) tCKESR_out[4] = tCKESR_in[4]; end always @(negedge tCKESR_in[4]) begin: tCKESR4f #(1*TScal) tCKESR_out[4] = tCKESR_in[4]; end always @(posedge tCKESR_in[5]) begin: tCKESR5r #(tdevice_tCKESR_ts - 1000) tCKESR_out[5] = tCKESR_in[5]; end always @(negedge tCKESR_in[5]) begin: tCKESR5f #(1*TScal) tCKESR_out[5] = tCKESR_in[5]; end always @(posedge tCKESR_in[6]) begin: tCKESR6r #(tdevice_tCKESR_ts - 1000) tCKESR_out[6] = tCKESR_in[6]; end always @(negedge tCKESR_in[6]) begin: tCKESR6f #(1*TScal) tCKESR_out[6] = tCKESR_in[6]; end always @(posedge tCKESR_in[7]) begin: tCKESR7r #(tdevice_tCKESR_ts - 1000) tCKESR_out[7] = tCKESR_in[7]; end always @(negedge tCKESR_in[7]) begin: tCKESR7f #(1*TScal) tCKESR_out[7] = tCKESR_in[7]; end always @(posedge tRP_in[0]) begin: tRP0r #(tdevice_tRP_ts - 1000) tRP_out[0] = tRP_in[0]; end always @(negedge tRP_in[0]) begin: tRP0f #(1*TScal) tRP_out[0] = tRP_in[0]; end always @(posedge tRP_in[1]) begin: tRP1r #(tdevice_tRP_ts - 1000) tRP_out[1] = tRP_in[1]; end always @(negedge tRP_in[1]) begin: tRP1f #(1*TScal) tRP_out[1] = tRP_in[1]; end always @(posedge tRP_in[2]) begin: tRP2r #(tdevice_tRP_ts - 1000) tRP_out[2] = tRP_in[2]; end always @(negedge tRP_in[2]) begin: tRP2f #(1*TScal) tRP_out[2] = tRP_in[2]; end always @(posedge tRP_in[3]) begin: tRP3r #(tdevice_tRP_ts - 1000) tRP_out[3] = tRP_in[3]; end always @(negedge tRP_in[3]) begin: tRP3f #(1*TScal) tRP_out[3] = tRP_in[3]; end always @(posedge tRP_in[4]) begin: tRP4r #(tdevice_tRP_ts - 1000) tRP_out[4] = tRP_in[4]; end always @(negedge tRP_in[4]) begin: tRP4f #(1*TScal) tRP_out[4] = tRP_in[4]; end always @(posedge tRP_in[5]) begin: tRP5r #(tdevice_tRP_ts - 1000) tRP_out[5] = tRP_in[5]; end always @(negedge tRP_in[5]) begin: tRP5f #(1*TScal) tRP_out[5] = tRP_in[5]; end always @(posedge tRP_in[6]) begin: tRP6r #(tdevice_tRP_ts - 1000) tRP_out[6] = tRP_in[6]; end always @(negedge tRP_in[6]) begin: tRP6f #(1*TScal) tRP_out[6] = tRP_in[6]; end always @(posedge tRP_in[7]) begin: tRP7r #(tdevice_tRP_ts - 1000) tRP_out[7] = tRP_in[7]; end always @(negedge tRP_in[7]) begin: tRP7f #(1*TScal) tRP_out[7] = tRP_in[7]; end always @(posedge tXS_in) begin: tXSr #(tdevice_tRFCMIN_ts + 9000) tXS_out = tXS_in; end always @(negedge tXS_in) begin: tXSf #(1*TScal) tXS_out = tXS_in; end always @(posedge tREFPer_in) begin: tREFPerr #(tdevice_tREFPer_ts - 1000) tREFPer_out = tREFPer_in; end always @(negedge tREFPer_in) begin: tREFPerf #(1*TScal) tREFPer_out = tREFPer_in; end always @(posedge tRFCMIN_in) begin: tRFCMINr #(tdevice_tRFCMIN_ts - 1000) tRFCMIN_out = tRFCMIN_in; end always @(negedge tRFCMIN_in) begin: tRFCMINf #(1*TScal) tRFCMIN_out = tRFCMIN_in; end always @(posedge tREFPer_in) begin: REFPerr #(tdevice_tREFPer_ts - 1000) tREFPer_out = tREFPer_in; end always @(negedge tREFPer_in) begin: REFPerf #(1*TScal) tREFPer_out = tREFPer_in; end always @(negedge tCKAVGMAX_in) begin: tCKAVGMAXf #(1*TScal) tCKAVGMAX_out = tCKAVGMAX_in; end always @(negedge tCKSRX_in) begin: tCKSRXf #(1*TScal) tCKSRX_out = tCKSRX_in; end always @(posedge tCKSRE_in) begin: tCKSREr #(tdevice_tCKSRE_ts - 1000) tCKSRE_out = tCKSRE_in; end always @(negedge tCKSRE_in) begin: tCKSREf #(1*TScal) tCKSRE_out = tCKSRE_in; end always @(posedge tWLDQSEN_in) begin: tWLDQSENr #(tdevice_tWLDQSEN_ts - 1000) tWLDQSEN_out = tWLDQSEN_in; end always @(negedge tWLDQSEN_in) begin: tWLDQSENf #(1*TScal) tWLDQSEN_out = tWLDQSEN_in; end always @(posedge tWLMRD_in) begin: tWLMRDr #(tdevice_tWLMRD_ts - 1000) tWLMRD_out = tWLMRD_in; end always @(negedge tWLMRD_in) begin: tWLMRDf #(1*TScal) tWLMRD_out = tWLMRD_in; end always @(posedge tWLOMAX_in) begin: tWLOMAXr #(tdevice_tWLOMAX_ts - 1000) tWLOMAX_out = tWLOMAX_in; end always @(negedge tWLOMAX_in) begin: tWLOMAXf #(1*TScal) tWLOMAX_out = tWLOMAX_in; end always @(negedge tWLOEMAX_in) begin: tWLOEMAXf #(1*TScal) tWLOEMAX_out = tWLOEMAX_in; end always @(posedge tMRD_in) begin: tMRDr #(tdevice_tMRD_ts - 1000) tMRD_out = tMRD_in; end always @(negedge tMRD_in) begin: tMRDf #(1*TScal) tMRD_out = tMRD_in; end always @(posedge tMOD_in) begin: tMODr #(tdevice_tMOD_ts - 1000) tMOD_out = tMOD_in; end always @(negedge tMOD_in) begin: tMODf #(1*TScal) tMOD_out = tMOD_in; end always @(negedge tXPR_in) begin: tXPRf #(1*TScal) tXPR_out = tXPR_in; end always @(negedge tZQINIT_in) begin: tZQINITf #(1*TScal) tZQINIT_out = tZQINIT_in; end always @(negedge tZQOPER_in) begin: tZQOPERf #(1*TScal) tZQOPER_out = tZQOPER_in; end always @(negedge tZQCS_in) begin: tZQCSf #(1*TScal) tZQCS_out = tZQCS_in; end always @(RESETNeg) begin: rst #(100000) RST = RESETNeg; end /////////////////////////////////////////////////////////////////////////////// // Process for clock frequency determination /////////////////////////////////////////////////////////////////////////////// always @(CKDiff) begin : CK_period_scan if (CKDiff) begin tmpper = $time - previous; if (tmpper > 0) CKPeriod = tmpper; previous = $time; CKHalfPer = CKPeriod/2; CKDLLDelay = CKPeriod + 2*DLL_TIME; end end /////////////////////////////////////////////////////////////////////////////// // Processes for generating internal clock from DLL /////////////////////////////////////////////////////////////////////////////// always @(CKDiff) begin : CK_temp if ($time != 0) CKtemp <= #(CKHalfPer - 3) ~CKtemp; end always @(CKtemp) begin : DLL_block CKInt <= #(CKDLLDelay + 3) CKtemp; end always @(In_d) begin : Init_d if (In_d) #(tdevice_tXPR_ts) Init_delay = 1'b1; else Init_delay = 1'b0; end always @(In_d1) begin : Init_d1 if (In_d1) #(tdevice_tMRD_ts) Init_delay1 = 1'b1; else Init_delay1 = 1'b0; end always @(In_d2) begin : Init_d2 if (In_d2) #(tdevice_tZQINIT_ts) Init_delay2 = 1'b1; else Init_delay2 = 1'b0; end always @(In_d3) begin : Init_d3 if (In_d3) #(tdevice_tZQOPER_ts) Init_delay3 = 1'b1; else Init_delay3 = 1'b0; end always @(In_d4) begin : Init_d4 if (In_d4) #(tdevice_tZQCS_ts) Init_delay4 = 1'b1; else Init_delay4 = 1'b0; end always @(posedge DLL_delay) begin : DLLdelay cnt = 0; DLL_delay_elapsed = 1'b0; end always @(posedge CKDiff) begin : DLLdelay1 cnt = cnt + 1; if (cnt == 511 && ~DLL_delay_elapsed) DLL_delay_elapsed = 1'b1; end always @(posedge mrs_active) begin mrs_cnt = 1; end /////////////////////////////////////////////////////////////////////////////// // Process for generating differential clock from CK and CKNeg /////////////////////////////////////////////////////////////////////////////// reg CKDiff2; always @(CK, CKNeg) begin : DiffCK if (CK && ~CKNeg) CKDiff = 1'b1; if (~CK && CKNeg) CKDiff = 1'b0; #1 CKDiff2 = CKDiff; end always @(DQSIn, DQSNegIn) begin : DiffDQS if (DQSIn && ~DQSNegIn) DQSDiff = 1'b1; if (~DQSIn && DQSNegIn) DQSDiff = 1'b0; end always @(MR0,fly_flag) begin if (MR0[1:0]==2'b00 || (MR0[1:0]==2'b01 && fly_flag == 1'b1)) burst_len = 8; else burst_len = 4; if (MR0[11:9]<=3) wr_rec = MR0[11:9] + 4; else wr_rec = 2*MR0[11:9]; cas_lat = MR0[6:4]+4; if ((( char[0]=="D" && char[1]=="G") && cas_lat==10) || (( char[0]=="D" && char[1]=="J") && (cas_lat==5 || cas_lat==7 || cas_lat==10)) || (( char[0]=="A" && char[1]=="C") && (cas_lat==9 || cas_lat==10)) || (( char[0]=="A" && char[1]=="E") && (cas_lat==5 || cas_lat==9 || cas_lat==10)) || (( char[0]=="A" && char[1]=="G") && (cas_lat==5 || cas_lat==7 || cas_lat==9 || cas_lat==10)) || (( char[0]=="8" && char[1]=="A") && (cas_lat>=7 || cas_lat<=10)) || (( char[0]=="8" && char[1]=="C") && (cas_lat!=6))) begin $display("Programmed CL value is not supported in "); $display("this speed grade! "); end end always @(MR1) begin if (MR1[4:3] != 0) add_lat = cas_lat - MR1[4:3]; else add_lat = 0; end always @(MR2) begin if (MR2[5:3] <= 0) wr_lat = MR2[5:3]+5; end ///////////////////////////////////////////////////////////////////////////// ////Check Read task ///////////////////////////////////////////////////////////////////////////// reg WTR_viol = 1'b0; reg rd_rd_viol = 1'b0; reg rd_DLL_viol = 1'b0; reg rd_PD_viol = 1'b0; reg rd_lock_viol = 1'b0; task CheckRead; begin read_permit = 1'b1; WTR_viol = 1'b0; rd_rd_viol = 1'b0; rd_DLL_viol = 1'b0; rd_PD_viol = 1'b0; rd_lock_viol = 1'b0; for(j=0;j<=BankNum;j=j+1) begin if (WTR_elapsed[j]==1'b0 || tWTR_out[j]==1'b0) begin WTR_viol = 1'b1; read_permit = 1'b0; end end if (rd_rd_cnt >= 1 && rd_rd_cnt < 4) begin rd_rd_viol = 1'b1; read_permit = 1'b0; end if (DLL_delay_elapsed == 1'b0) begin rd_DLL_viol = 1'b1; read_permit = 1'b0; end if (PD_read_delay == 1'b1) begin rd_PD_viol = 1'b1; read_permit = 1'b0; end if (DLL_reset_needed == 1'b1) begin rd_lock_viol = 1'b1; read_permit = 1'b0; end if (WTR_viol == 1'b1) $display("tWTR has not elapsed since the end of last write burst!"); if (rd_rd_viol == 1'b1) $display("4 cycles must elapse between consecutive READ commands!"); if (rd_DLL_viol == 1'b1) begin $display("512 cycles must elapse between DLL reset and READ "); $display("command!"); end if (rd_PD_viol == 1'b1) $display("tXPDLL has not elapsed since slow-exit power-down exit!"); if (rd_lock_viol == 1'b1) $display("DLL must be reset prior to read command!"); end endtask ///////////////////////////////////////////////////////////////////////////// ////Check Write task ///////////////////////////////////////////////////////////////////////////// reg RTW_viol = 1'b0; reg wr_wr_viol = 1'b0; task CheckWrite; begin write_permit = 1'b1; RTW_viol = 1'b0; wr_wr_viol = 1'b0; if (RTW_elapsed == 1'b0) begin RTW_viol = 1'b1; write_permit = 1'b0; end if (wr_wr_cnt < 4) begin wr_wr_viol = 1'b1; write_permit = 1'b0; end if (RTW_viol == 1'b1) begin $display("RL+tCCD/2+2tCK-WL for BL=4 or "); $display("RL+tCCD+2tCK-WL for BL=8"); $display("cycles must elapse "); $display("between READ and WRITE commands!"); end if (wr_wr_viol == 1'b1) begin $display("4 cycles must elapse between "); $display("consecutive WRITE commands!"); end end endtask always @(posedge CKDiff) begin : CK_frequency if (CK_rise != 0) begin if (CK_stable == 1'b1) begin if (($time - CK_rise)!= CK_period) begin if ((Pre_PD && ODT_off && freq_ch_cnt == 0)||(SelfRefresh)) freq_change = 1'b1; else if (~SR_enter_cycle && ~Reset_enter_cycle) begin $display("Input clock frequency is not stable!"); end end disable sim_process; ->sim_end; if ((CK_period > tdevice_tCKAVGMAX_ts) && ~SR_enter_cycle && ~Reset_enter_cycle) $display("Input clock period exceeds tCKAVG(max)!"); end CK_stable = 1'b1; end CK_period = $time - CK_rise; CK_rise = $time; end always @(posedge CKDiff) begin : logic_levels defined_logic_levels = 1'b1; if ((CKE !== 0 && CKE !== 1) || (RASNeg !== 0 && RASNeg !== 1) || (CASNeg !== 0 && CASNeg !== 1) || (WENeg !== 0 && WENeg !== 1)) defined_logic_levels = 1'b0; for(i=0;i<=2;i=i+1) begin if (BA[i] !== 0 && BA[i] !== 1) defined_logic_levels = 1'b0; end for(i=0;i<=13;i=i+1) begin if (A[i] !== 0 && A[i] !== 1) defined_logic_levels = 1'b0; end end always @(posedge CKDiff) begin : command_decode Command = ILL; if (defined_logic_levels) begin if (~CSNeg && ~RASNeg && ~CASNeg && ~WENeg) Command = MRS; else if (~CSNeg && ~RASNeg && ~CASNeg && WENeg) Command = REF; else if (CSNeg) Command = DESL; else if (~CSNeg && RASNeg && CASNeg && WENeg) Command = NOP; else if (~CSNeg && ~RASNeg && CASNeg && ~WENeg) Command = PRE; else if (~CSNeg && ~RASNeg && CASNeg && WENeg) Command = ACT; else if (~CSNeg && RASNeg && ~CASNeg && ~WENeg) Command = WRIT; else if (~CSNeg && RASNeg && ~CASNeg && WENeg) Command = READ; else if (~CSNeg && RASNeg && CASNeg && ~WENeg && A[10]) Command = ZQCL; else if (~CSNeg && RASNeg && CASNeg && ~WENeg && ~A[10]) Command = ZQCS; end end always @(posedge CKDiff) begin : initialization case (Current_state) init0 : begin if (CKE == 1) begin if (PoweredUp && (Command == NOP || Command == DESL)) begin Next_state = init1; In_d = 1'b1; if (((CK_period < tperiod_CK) && (cas_lat > 4) && (cas_lat < 11)) || CK_period > tdevice_tCKAVGMAX_ts) begin $display("Clock must be stable before CKE is "); $display("raised high!"); end end else begin $display("Invalid start of initialization!"); Next_state = illegal; end end end init1 : begin if (Init_delay && Command == MRS) begin Next_state = init2; In_d = 1'b0; In_d1 = 1'b1; MR2[12:0] = A[12:0]; MR2[15:13] = BA; end else if (Init_delay == 1'b0 && Command != NOP && Command != DESL) $display("Only NOP Command are valid during tXPR"); end init2 : begin if (Init_delay1 && Command == MRS) begin Next_state = init3; In_d = 1'b0; In_d1 = 1'b1; MR3[12:0] = A[12:0]; MR3[15:13] = BA; end end init3 : begin if (Init_delay1 && Command == MRS) begin Next_state = init4; In_d = 1'b0; In_d1 = 1'b1; MR1[12:0] = A[12:0]; MR1[15:13] = BA; end end init4 : begin if (Init_delay1 && Command == MRS) begin Next_state = init5; In_d = 1'b0; In_d1 = 1'b1; DLL_delay = 1; DLL_delay <= #(1000) 0; MR0[12:0] = A[12:0]; MR0[15:13] = BA; end end init5 : begin if (Init_delay1 && (Command == ZQCS || Command == ZQCL)) begin In_d = 1'b0; In_d1 = 1'b0; if(Command == ZQCL && ZQINIT) begin In_d2 = 1'b1; Next_state = init6; end else if( Command == ZQCL && ~ZQINIT) begin In_d3 = 1'b1; Next_state = init6; end end ODT_off = 1'b1; DOut_zd = 8'bz; end init6 : begin if ((Init_delay2 || Init_delay3) && (Command == NOP || Command == DESL)) begin Initialized = 1'b1; In_d2 = 1'b0; In_d3 = 1'b0; ZQINIT = 1'b0; end else if (~Initialized && Command != NOP && Command != DESL) $display("Illegal command during tZQINIT"); end illegal : begin Next_state = init0; end endcase Current_state = Next_state; end always @(posedge CKDiff2) begin : StateGen if (Initialized) begin idle = 1'b1; for(i=0;i<=BankNum;i=i+1) begin if (Curr_bank_state[i] != precharged) idle = 1'b0; end if (Command == REF && ~CKE && ~idle) begin $display("The SELF REFRESH command can only be "); $display("issued when all banks are idle"); end if (CKE && ~(SelfRefresh || Pre_PD || Act_PD || Reset)) begin if (Command == MRS) begin if (idle) begin mrs_active = 0; mrs_active <= #(1000) 1; tMOD_in_tmp = 1; tMOD_in_tmp <= #(1000) 0; for(i=0;i<=BankNum;i=i+1) begin Next_bank_state[i] = mrsetting; end if (BA == 0) begin MR0 = A[12:0]; if (MR0[8] == 1) fork DLL_delay = 1; DLL_delay <= #(1000) 0; ODT_off = 1'b0; freq_change = 1'b0; DLL_reset_needed = 1'b0; join if (MR0[11:9] == 0 || MR0[11:9] > 6 || cas_lat < 5 || cas_lat > 10 || MR0[1:0] == 3) $display("Invalid value programmed to MR0 !"); if (MR0[7] != 0) $display("Mode should be set to normal, not test!"); end if (BA == 1) begin MR1 = A[12:0]; TDQS_EN = MR1[11]; if ((MR1[4:3] == 3) || {MR1[9],MR1[6],MR1[2]} >= 6 || MR1[5] != 0 || MR1[8] != 0 || MR1[10] != 0 ) $display("Invalid value programmed to MR1 !"); if (MR1[0] != 0) $display("DLL must be enabled for normal oper. !"); end if (BA == 2) begin MR2 = A[12:0]; if (MR2[5:3] >= 4 || MR2[10:9] == 3 || MR2[12:11] != 0 || MR2[8] != 0) $display("Invalid value programmed to MR2!"); end if (BA == 3) begin MR3 = A[12:0]; if (MR3[1:0] != 0 && MR3[12:4] != 0) $display("Invalid value programmed to MR3!"); end end else begin $display("The MRS command can only be issued when"); $display("all banks are idle!"); end end if (mrs_cnt < 4 && tMOD_out_tmp == 1'b0 && (Command != NOP && Command != DESL)) begin $display("Only NOP or DESELECT commands are valid "); $display("during tMRD after MRS command"); end if (mrs_cnt == 4 && tMOD_out_tmp == 1'b0 && (Command != NOP && Command != DESL && Command != MRS)) begin $display("Command are issued during during tMOD "); $display("after MRS "); end if (Command == REF) begin if (idle) begin for(i=0;i<=BankNum;i=i+1) begin Next_bank_state[i] = refreshing; end tRFCMIN_in = 0; tREFPer_in = 0; fork tRFCMIN_in <= #(1000) 1; tREFPer_in <= #(1000) 1; join end else begin $display("The REFRESH command can only be "); $display("issued when all banks are idle!"); end end if (Curr_bank_state[0] == refreshing && Command != NOP && Command != DESL) begin $display("Only NOP or DESELECT commands are valid during "); $display("tRFC(min) after REFRESH command!"); end prechall_viol = 1'b0; for(i=0;i<=BankNum;i=i+1) begin if (Curr_bank_state[i] == prechall && Command != NOP && Command != DESL) prechall_viol = 1'b1; end if (prechall_viol) begin $display("Only NOP or DESELECT commands are valid during "); $display("tRPA after PRECHARGE ALL command!"); end if (Command == PRE && A[10] == 1 && tRASMIN_out != 8'hFF) begin $display("tRAS(min) has not elapsed since activation of "); $display("the last activated bank!"); end for(i=0;i<=BankNum;i=i+1) begin case (Curr_bank_state[i]) precharged : begin if (Command == ACT && BA == i && tMOD_out_tmp == 1'b1) begin if (~active_forbid) begin if (tRRD_out == 1) begin if (tRC_out[i] == 1) begin Next_bank_state[i] = activating; active_row[i] = A; tRCD_in[i] = 0; tRASMIN_in[i] = 0; tRASMAX_in[i] = 1; tRRD_in = 0; tRC_in[i] = 0; fork tRCD_in[i] <= #(1000) 1; tRASMIN_in[i] <= #(1000) 1; tRRD_in <= #(1000) 1; tRC_in[i] <= #(1000) 1; join end end else begin $display("tRRD has not elapsed since "); $display("activation of the last "); $display("activated bank! "); end end end else if (Command == ZQCS && tMOD_out_tmp == 1'b1) Next_bank_state[i] = zq_calib; else if ((Command == READ || Command == WRIT) && BA == i) $display("Illegal command when idle"); end mrsetting : begin Next_bank_state[i] = precharged; end zq_calib : begin In_d4 = 1'b1; DOut_zd = 8'bz; ODT_off = 1'b1; if (Init_delay4) begin Next_bank_state[i] = precharged; In_d4 = 1'b0; end end precharging : begin if (Command != NOP && Command != DESL && BA == i) begin $display("Illegal command during precharging"); end end prechall : begin if (Command != NOP && Command != DESL) begin $display("Illegal command during precharging"); end if (tRP_out[i] == 1) Next_bank_state[i] = precharged; end active : begin if (Command == PRE && A[10] == 0 && BA == i) begin if (tRASMIN_out[i] == 1'b1) begin Next_bank_state[i] = precharging; tRASMAX_in[i] = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end else begin $display("tRAS(min) has not elapsed "); $display("since activation of the bank!"); end end else if (Command == PRE && A[10] == 1) begin if (tRASMIN_out == 8'hFF) begin Next_bank_state[i] = prechall; tRASMAX_in = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end else if (Command == WRIT && BA == i) begin CheckWrite; if (write_permit) begin wr_wr_cnt = 0; start_column[i*11] = A[9:0]; AL[i*11] = add_lat; CL[i*11] = cas_lat; write_sch[i][0] = 1'b1; WR_elapsed[i] = 1'b0; tWR_in[i] = 1'b0; WTR_elapsed[i] = 1'b0; tWTR_in[i] = 1'b0; precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; if (A[10] == 0) begin Next_bank_state[i] = writting; fly_flag = A[12]; end else begin Next_bank_state[i] = writtingap; fly_flag = A[12]; end end end else if (Command == READ && BA == i) begin CheckRead; if (read_permit) begin start_column[i*11] = A[9:0]; AL[i*11] = add_lat; CL[i*11] = cas_lat; read_sch[i][0] = 1'b1; AL_elapsed[i][0] = 1'b0; RTP_elapsed[i] = 1'b0; tRTP_in[i] = 1'b0; RTW_elapsed = 1'b0; rd_wr_cnt = 0; precharge_cnt[i] = 0; rd_act_cnt[i] = 0; rd_pd_cnt = 0; if (rd_rd_cnt >= 3) preamble[i][0] = 1'b1; else preamble[i][0] = 1'b0; rd_rd_cnt = 0; if (add_lat == 0 && burst_len == 4) begin tRTP_in[i] = 0; tRTP_in[i] <= #(1000) 1; end if (A[10] == 0) begin Next_bank_state[i] = reading; fly_flag = A[12]; end else begin Next_bank_state[i] = readingap; fly_flag = A[12]; end end end if (Command == ACT && BA == i) begin $display("Previous active row in same bank "); $display("has not been closed (precharged)!"); end end activating : begin if (Command != NOP && Command != DESL && BA == i) begin $display("During activating the bank only"); $display("valid commands are NOP"); $display("and DESELECT"); end end writting : begin if (last_write[i] == 1'b1) begin precharge_cnt[i] = precharge_cnt[i] + 1; wr_rd_cnt[i] = wr_rd_cnt[i] + 1; if (precharge_cnt[i] == (burst_len/2)+wr_lat-1) begin tWR_in[i] = 0; tWR_in[i] <= #(1000) 1; end else if (precharge_cnt[i] == (burst_len/2) + wr_rec + wr_lat) WR_elapsed[i] = 1'b1; if (wr_rd_cnt[i] == wr_lat+(burst_len/2)) begin tWTR_in[i] = 0; tWTR_in[i] <= #(1000) 1; end end for(j=0;j<=10;j=j+1) begin if (write_sch[i][j]) begin if (AL[i*11+j] > 0) AL[i*11+j] = AL[i*11+j] - 1; else if (WL[i*11+j] > 5) WL[i*11+j] = WL[i*11+j] - 1; else fork current_bank = i; current_row = active_row[i]; current_column = start_column[i*11+j]; if(burst_len == 4) fork In_data = 0; In_data <= #((2*burst_len+3)*CK_period/4) 1; join else fork In_data = 0; In_data <= #(((burst_len+1)*CK_period/4) - 1000) 1; join write_sch[i][j] = 1'b0; last_write[i] = 1'b1; precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; WR_elapsed[i] = 1'b0; WTR_elapsed[i] = 1'b0; join end end if (Command == WRIT && BA == i) begin CheckWrite; if (write_permit) begin wr_wr_cnt = 0; last_write[i] = 1'b0; precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; WR_elapsed[i] = 1'b0; WTR_elapsed[i] = 1'b0; free_slot = freeslot(write_sch[i]); start_column[i*11+free_slot] = A[9:0]; AL[i*11+free_slot] = add_lat; CL[i*11+free_slot] = cas_lat; write_sch[i][free_slot] = 1'b1; tWR_in[i] = 0; tWTR_in[i] = 1'b0; if (A[10] == 0) begin Next_bank_state[i] = writting; fly_flag = A[12]; end else begin Next_bank_state[i] = writtingap; fly_flag = A[12]; end end end else if (Command == READ && BA == i) begin CheckRead; if (read_permit) begin start_column[i*11] = A[9:0]; AL[i*11] = add_lat; CL[i*11] = cas_lat; read_sch[i][0] = 1'b1; AL_elapsed[i][0] = 1'b0; RTP_elapsed[i] = 1'b0; tRTP_in[i] = 1'b0; RTW_elapsed = 1'b0; rd_wr_cnt = 0; precharge_cnt[i] = 0; rd_act_cnt[i] = 0; preamble[i][0] = 1'b1; rd_rd_cnt = 0; rd_pd_cnt = 0; if (add_lat == 0 && burst_len == 4) begin tRTP_in[i] = 0; tRTP_in[i] <= #(1000) 1; end if (A[10] == 0) begin Next_bank_state[i] = reading; fly_flag = A[12]; end else begin Next_bank_state[i] = readingap; fly_flag = A[12]; end end end else if (WR_elapsed[i]) begin if (tWR_out[i]) begin if (Command == PRE && A[10] == 0 && BA == i) begin if (tRASMIN_out[i] == 1'b1) begin Next_bank_state[i] = precharging; tRASMAX_in[i] = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end else if (Command == PRE && A[10] == 1) begin if (tRASMIN_out == 8'hFF) begin Next_bank_state[i] = prechall; tRASMAX_in = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end else Next_bank_state[i] = active; end else if (Command == PRE && (BA == i || A[10] == 1)) $display("Illegal command PRE during WRITE"); end else if (Command == PRE && (BA == i || A[10] == 1)) $display("Illegal command PRE during WRITE"); if (wr_rd_cnt[i] == 3) WTR_elapsed[i] = 1'b1; if (Command == ACT && BA == i) $display("Illegal command ACT during WRITE"); end writtingap : begin if (last_write[i] == 1'b1) begin precharge_cnt[i] = precharge_cnt[i] + 1; wr_rd_cnt[i] = wr_rd_cnt[i] + 1; if (precharge_cnt[i] == (burst_len/2)+wr_lat-1) begin tWR_in[i] = 0; tWR_in[i] <= #(1000) 1; end else if (precharge_cnt[i] == (burst_len/2) + wr_lat + wr_rec) WR_elapsed[i] = 1'b1; if (wr_rd_cnt[i] == (burst_len/2)+wr_lat) begin tWTR_in[i] = 0; tWTR_in[i] <= #(1000) 1; end else if (wr_rd_cnt[i] == (burst_len/2) + wr_lat + 3) WTR_elapsed[i] = 1'b1; end for(j=0;j<=10;j=j+1) begin if (write_sch[i][j]) begin if (AL[i*11+j] > 0) AL[i*11+j] = AL[i*11+j] - 1; else if (WL[i*11+j] > 5) WL[i*11+j] = WL[i*11+j] - 1; else fork current_bank = i; current_row = active_row[i]; current_column = start_column[i*11+j]; if(burst_len == 4) fork In_data = 0; In_data <= #((2*burst_len+3)*CK_period/4) 1; join else fork In_data = 0; In_data <= #(((burst_len+1)*CK_period/4) - 1000) 1; join write_sch[i][j] = 1'b0; last_write[i] = 1'b1; precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; WR_elapsed[i] = 1'b0; join end end if (((Command == ACT || Command == READ || Command == WRIT) && BA == i) || (Command == PRE && (BA == i || A[10] == 1))) $display("Illegal command after WRITE AP"); if (WR_elapsed[i]) begin if (tWR_out[i]) begin Next_bank_state[i] = precharging; tRASMAX_in[i] = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end end reading : begin precharge_cnt[i] = precharge_cnt[i] + 1; rd_act_cnt[i] = rd_act_cnt[i] + 1; if (precharge_cnt[i] == 4) // tRTRP begin tRTP_in[i] = 0; tRTP_in[i] <= #(1000) 1; end else if (tRTP_out[i]==1) RTP_elapsed[i] = 1'b1; for(j=0;j<=10;j=j+1) begin if (read_sch[i][j] == 1'b1 && AL_elapsed[i][j] == 1'b0) begin if (AL[i*11+j] > 0) AL[i*11+j] = AL[i*11+j] - 1; else begin current_bank = i; current_row = active_row[i]; current_column = start_column[i*11+j]; read_delay = CL[i*11+j]; if (read_delay == 3) begin if (preamble[i][j]) fork preamble_gen = 1'b0; preamble_gen <= #((3*CK_period/4) - 1000) 1'b1; preamble_gen <= #(CK_period) 1'bz; join end itmp = i; jtmp = j; wait_read[i][j] = 0; ->wr_event; AL_elapsed[i][j] = 1'b1; end end end if (Command == READ && BA == i) begin CheckRead; if (read_permit) begin precharge_cnt[i] = 0; rd_wr_cnt = 0; rd_act_cnt[i] = 0; RTP_elapsed[i] = 1'b0; RTW_elapsed = 1'b0; free_slot = freeslot(read_sch[i]); start_column[i*11+free_slot] = A[9:0]; AL[i*11+free_slot] = add_lat; CL[i*11+free_slot] = cas_lat; read_sch[i][free_slot] = 1'b1; AL_elapsed[i][free_slot] = 1'b0; tRTP_in[i] = 1'b0; if (rd_rd_cnt >= 3) preamble[i][free_slot] = 1'b1; else preamble[i][free_slot] = 1'b0; rd_rd_cnt = 0; rd_pd_cnt = 0; if (add_lat == 0 && burst_len == 4) begin tRTP_in[i] = 0; tRTP_in[i] <= #(1000) 1; end if (A[10] == 0) begin Next_bank_state[i] = reading; fly_flag = A[12]; end else begin Next_bank_state[i] = readingap; fly_flag = A[12]; end end end else if (Command == WRIT && BA == i) begin CheckWrite; if (write_permit) begin wr_wr_cnt = 0; start_column[i*11] = A[9:0]; AL[i*11] = add_lat; CL[i*11] = cas_lat; WL[i*11] = wr_lat; write_sch[i][0] = 1'b1; tWR_in[i] = 0; WTR_elapsed[i] = 1'b0; WR_elapsed[i] = 1'b0; tWTR_in[i] = 1'b0; precharge_cnt[i] = 0; wr_rd_cnt[i] = 0; if (A[10] == 0) begin Next_bank_state[i] = writting; fly_flag = A[12]; end else begin Next_bank_state[i] = writtingap; fly_flag = A[12]; end end end else if (RTP_elapsed[i] && tRTP_out[i] && Command == PRE && (BA == i || A[10] == 1)) begin if (A[10] == 0 && BA == i) begin if (tRASMIN_out[i] == 1'b1) begin Next_bank_state[i] = precharging; tRASMAX_in[i] = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end else begin $display("tRAS(min) has not elapsed "); $display("since activ. of the bank!"); end end else begin if (tRASMIN_out == 8'hFF) begin Next_bank_state[i] = prechall; tRASMAX_in = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end end else if (Command == PRE && (BA == i || A[10] == 1)) $display("Illegal command PRE while reading"); if (Command == ACT && BA == i) $display("Illegal command ACT after READ"); end readingap : begin precharge_cnt[i] = precharge_cnt[i] + 1; if (precharge_cnt[i] == add_lat + (burst_len/2)) begin tRTP_in[i] = 0; tRTP_in[i] <= #(1000) 1; end else if (tRTP_out[i]==1) RTP_elapsed[i] = 1'b1; for(j=0;j<=10;j=j+1) begin if (read_sch[i][j] == 1'b1 && AL_elapsed[i][j] == 1'b0) begin if (AL[i*11+j] > 0) AL[i*11+j] = AL[i*11+j] - 1; else begin current_bank = i; current_row = active_row[i]; current_column = start_column[i*11+j]; read_delay = CL[i*11+j]; if (read_delay == 3) begin if (preamble[i][j]) fork preamble_gen = 1'b0; preamble_gen <= #((3*CK_period/4) - 1000) 1'b1; preamble_gen <= #(CK_period) 1'bz; join end itmp = i; jtmp = j; wait_read[i][j] = 0; AL_elapsed[i][j] = 1'b1; ->wr_event; end end end if (((Command == ACT || Command == READ || Command == WRIT) && BA == i) || (Command == PRE && (BA == i || A[10] == 1))) $display("Illegal command after READ AP"); if (RTP_elapsed[i] && tRTP_out[i]) begin Next_bank_state[i] = precharging; tRASMAX_in[i] = 0; tRP_in[i] = 0; tRP_in[i] <= #(1000) 1; end end endcase Curr_bank_state[i] = Next_bank_state[i]; end // end loop if (rd_rd_cnt < 4)// tCCD rd_rd_cnt = rd_rd_cnt + 1; if (wr_wr_cnt < 4)// tCCD wr_wr_cnt = wr_wr_cnt + 1; if (rd_wr_cnt == (cas_lat + add_lat - wr_lat + 2 + burst_len/8)) RTW_elapsed = 1'b1; if (rd_wr_cnt < cas_lat+add_lat-wr_lat+2+burst_len/8) rd_wr_cnt = rd_wr_cnt + 1; // WRITE LEVELING PROCEDURE if (idle && Command == MRS && ((MR1[7] && MR1[12]) || (MR1[7] && ~MR1[12] && {MR1[9],MR1[6],MR1[2]} <= 3))) fork tMOD_in = 0; tMOD_in <= #(1000) 1; tWLDQSEN_in = 0; tWLDQSEN_in <= #(1000) 1; tWLMRD_in = 0; tWLMRD_in <= #(1000) 1; join if (tMOD_out && ODT) ODT_off = 1'b0; if (tWLDQSEN_out && ODT) WL_on = 1'b1; end if (tWLDQSEN_in == 1'b1 && tWLDQSEN_out == 1'b0 && DQS == 1'b0) $display("DQS should not be asserted during tWLDQSEN"); if (tWLMRD_in == 1'b1 && tWLMRD_out == 1'b0 && DQS == 1'b1) $display("DQS should not be deasserted during tWLMRD"); if (~CKE && ~CKEfall) begin CKEfall = 1'b1; CKErise = 1'b0; if (CKEcnt != 3) $display("CKE has not been high for tCKE(min)!"); CKEcnt = 0; end if (CKE && ~CKErise) begin CKErise = 1'b1; CKEfall = 1'b0; if (CKEcnt != 3) $display("CKE has not been low for tCKE(min)!"); CKEcnt = 0; end if (CKEcnt < 3) CKEcnt = CKEcnt + 1; if (~CKE && idle && Command == REF && ~SelfRefresh && (~ODT || (~MR1[6] && ~MR1[2] && ~MR1[9])) && ~Act_PD && ~Pre_PD && ~Reset && ~WL_on && tMOD_out_tmp == 1'b1) begin SR_cond = 1'b1; SelfRefresh = 1'b1; if (MR2[2:0] != 3'b000) PartialSelfRefresh = 1'b1; SR_exit = 1'b0; end if (SelfRefresh && ~SR_exit && ~SR_enter_cycle && ~CKE) begin SR_enter_cycle = 1'b1; if (MR2[2:0] < 4) begin sf_array = 2**(3 - MR2[2:0])-1; for(j=0;j<=sf_array;j=j+1) begin tCKESR_in[j] = 0; tCKESR_in[j] <= #(1000) 1; for(k=sf_array;k<=BankNum;k=k+1) begin if (MR2[2:0] !=0) begin for(l=0;l<=MemSize;l=l+1) Mem[k*MemSize+l] = -1; end end end end else if (MR2[2:0] >= 4 && MR2[2:0] < 7) begin sf_array = 2*(MR2[2:0]-3); for(j=sf_array;j<=7;j=j+1) begin tCKESR_in[j] = 0; tCKESR_in[j] <= #(1000) 1; for(k=0;k<=sf_array;k=k+1) begin for(l=0;l<=MemSize;l=l+1) Mem[k*MemSize+l] = -1; end end end else begin tCKESR_in = 8'b00000001; for(k=0;k<=sf_array;k=k+1) begin for(l=0;l<=MemSize;l=l+1) Mem[k*MemSize+l] = -1; end end end if (CKE == 1'b0 && idle && Command == REF && tMOD_out_tmp == 1'b0) $display("SELF REFRESH command is issued during tMOD"); if (CKE && SelfRefresh && ~SR_exit && tCKESR_out == 8'hFF) begin SR_exit = 1'b1; tXS_in = 0; tXS_in <= #(1000) 1; DLL_delay = 0; DLL_delay <= #(1000) 1; if (freq_change && MR1[0]) DLL_reset_needed = 1'b1; else DLL_reset_needed = 1'b0; end if (Command != NOP && Command != DESL && SR_exit && SelfRefresh) begin $display("Only NOP and DESELECT commands are valid tXS "); $display("after self refresh exit!"); end RL_tmp = add_lat + cas_lat + 5; if (rd_pd_cnt <= RL_tmp) rd_pd_cnt = rd_pd_cnt + 1; if (~CKE && (Command == NOP || Command == DESL) && ~Act_PD && ~Pre_PD && ~SelfRefresh && ~Reset && ~WL_on) begin power_down_cond = 1'b1; active_pd_cond = 1'b0; for(i=0;i<=BankNum;i=i+1) begin if ((Curr_bank_state[i] == reading && rd_pd_cnt < RL_tmp) || Curr_bank_state[i] == readingap) begin power_down_cond = 1'b0; $display("not elapsed tRDPDEN after READ"); end else if (Curr_bank_state[i] == writting && ~(WTR_elapsed[i] && tWTR_out[i])) begin power_down_cond = 1'b0; $display("not elapsed tWRPDEN after WRITE"); end else if (Curr_bank_state[i] == writtingap) begin power_down_cond = 1'b0; $display("not elapsed tWRAPDEN after WRITE"); end else if (Curr_bank_state[i] == mrsetting || tMOD_out_tmp == 1'b0) begin power_down_cond = 1'b0; $display("not elapsed tMRSPDEN after MRS"); end else if (ReadStart || Read_Start) power_down_cond = 1'b0; else if (Curr_bank_state[i] == activating || Curr_bank_state[i] == active || (Curr_bank_state[i] == writting && WTR_elapsed[i] && tWTR_out[i])) active_pd_cond = 1'b1; end if (power_down_cond) begin if (~DLL_delay_elapsed && MR0[8]) DLL_reset_needed = 1'b1; if (active_pd_cond) begin Act_PD = 1'b1; for(i=0;i<=BankNum;i=i+1) begin if (Curr_bank_state[i] == activating || Curr_bank_state[i] == writting || Curr_bank_state[i] == active) Curr_bank_state[i] = active; else Curr_bank_state[i] = precharged; Curr_bank_state[i] = Next_bank_state[i]; end end else begin Pre_PD = 1'b1; if (~ODT || (~MR1[9] && ~MR1[6] && ~MR1[2])) ODT_off = 1'b1; freq_ch_cnt = 5;// tCKSRE for(i=0;i<=BankNum;i=i+1) begin Curr_bank_state[i] = precharged; Next_bank_state[i] = precharged; end end end end if (freq_ch_cnt > 0) freq_ch_cnt = freq_ch_cnt - 1; if (CKE && Pre_PD) begin if (PD_exit_cnt == 0) begin power_down_cond = 1'b0; PD_exit_cnt = 1; Pre_PD = 1'b0; end else begin PD_exit_cnt = 0; //// slow exit precharge power-down to read if (~PD_read_delay && ~MR0[12]) begin PD_read_delay = 1'b1; PD_read_del_cnt = 10; //tXPDLL end //// fast exit precharge power-down to read else if (~PD_read_delay && MR0[12]) begin PD_read_delay = 1'b1; PD_read_del_cnt = 3; //tXP end if (freq_change) DLL_reset_needed = 1'b1; end end if (DLL_delay_elapsed) DLL_reset_needed = 1'b0; if (CKE && Act_PD) begin if (PD_exit_cnt == 0) begin Act_PD = 1'b0; PD_exit_cnt = 1; end else begin PD_exit_cnt = 0; // slow exit active power-down to read if (~PD_read_delay && ~MR0[12]) begin PD_read_delay = 1'b1; PD_read_del_cnt = 10; //tXPDLL end // fast exit active power-down to read else if (~PD_read_delay && MR0[12]) begin PD_read_delay = 1'b1; PD_read_del_cnt = 3; //tXP end end end if (PD_read_del_cnt > 1 && PD_read_delay) PD_read_del_cnt = PD_read_del_cnt - 1; else PD_read_delay = 1'b0; end // en of Initialized end // end of StateGen always @(posedge CKDiff) begin if (mrs_cnt < 4) mrs_cnt = mrs_cnt + 1; end always @(posedge tMOD_in_tmp) begin tMOD_out_tmp = 1'b0; #(tdevice_tMOD - 1000) tMOD_out_tmp = 1'b1; end always @(negedge CKE) begin if (~Initialized && $time != 0) begin $display("CKE must be driven high during initialization!"); Current_state = illegal; Next_state = illegal; end end always @(tRFCMIN_out) begin if (tRFCMIN_out) begin for(i=0;i<=BankNum;i=i+1) begin if (Curr_bank_state[i] == refreshing) begin Curr_bank_state[i] = precharged; Next_bank_state[i] = precharged; end end end end always @(negedge RST) begin if (~RESETNeg && PoweredUp) begin Reset_enter_cycle = 1'b1; Reset = 1'b1; SR_cond = 1'b0; power_down_cond = 1'b0; Act_PD = 1'b0; Pre_PD = 1'b0; SelfRefresh = 1'b0; WL_on = 1'b0; end end always @(posedge tREFPer_out) begin if (tREFPer_out) $display("tREFPer(max) has elapsed since last REFRESH command!"); end always @(posedge ODT) begin if (SelfRefresh && SR_exit && ~(~MR1[9] && ~MR1[6] && ~MR1[2])) begin $display("After exiting self refresh, ODT must remain turned "); $display("off until tXS is satisfied!"); end if (~(~MR1[9] && ~MR1[6] && ~MR1[2]) && ODT_off) ODT_off = 1'b0; end always @(tXS_out) begin if (tXS_out && SelfRefresh && SR_exit) begin SR_cond = 1'b0; SelfRefresh = 1'b0; SR_exit = 1'b0; PartialSelfRefresh = 1'b0; end end always @(posedge CKE) begin if (SelfRefresh && ~SR_exit) begin SR_enter_cycle = 1'b0; if (((CK_period < tperiod_CK) && (cas_lat > 4) && (cas_lat < 11)) || CK_period > tdevice_tCKAVGMAX_ts) begin $display("Clock must be stable and meeting tCK specifications "); $display("at least 5 x tCK prior to exiting self refresh mode!"); end end end always @(negedge CKE) begin if (SelfRefresh && SR_exit) $display("CKE must stay high until tXS is met!"); end always @(posedge CKE) begin if (Reset) begin Reset = 1'b0; Reset_enter_cycle = 1'b0; Initialized = 1'b0; Current_state = init0; for(i=0;i<=BankNum;i=i+1) begin Curr_bank_state[i] = precharged; end end end always @(SR_exit) begin if (SR_exit) fork Ref_cnt = 0; Ref_per_start = 0; Ref_per_start <= #(1000) 1; join end always @(SelfRefresh) begin if (SelfRefresh) Ref_per_start = 0; end always @(SimulationEnd) begin if (SimulationEnd && ~SR_enter_cycle && ~Reset_enter_cycle) Ref_per_start = 0; end always @(Ref_per_expired) begin if (Ref_per_expired) begin Ref_cnt = 0; Ref_per_start = 0; Ref_per_start <= #(1000) 1; end end always @(Initialized) begin if (Initialized) begin Ref_cnt = 0; Ref_per_start = 0; Ref_per_start <= #(1000) 1; end end always @(Reset) begin if (Reset) Ref_per_start = 0; end always @(posedge Ref_per_start) begin : REFPer indust = MR2[7]; #((tdevice_tREFPer_ts/(indust+1))-1000) Ref_per_expired = 1; end always @(negedge Ref_per_start) begin #(1000) Ref_per_expired = 0; end always @(tRASMAX_out) begin: TRASMAXOUT if (tRASMAX_out != 0) begin $display("tRAS(max) has elapsed since activation of bank, and "); $display("PRECHARGE command still hasn't been issued!"); end end ////////////////////////////// // WRITE LEVELING ////////////////////////////// always @(posedge ODT) begin:Write_leveling_1 ODTLOFF = 1'b0; end always @(negedge ODT) begin:Write_leveling_2 ODTLOFF = 1'b1; end always @(posedge DQSDiff) begin:Write_leveling_3 if (tWLMRD_out && ~DQ_driven) begin tWLOMAX_in = 0; tWLOMAX_in <= #(1000) 1; end else if (DQ_driven && ODT) begin tWLOMAX_in = 0; tWLOMAX_in <= #(1000) 1; end end always @(tWLOMAX_out) begin : Write_leveling_4 if (tWLOMAX_out && ~DQ_driven && ODT) begin DOut_zd = 0; DQ_driven = 1'b1; end else if(tWLOMAX_out && DQ_driven && ODT) begin DOut_zd = 8'hFF; DQ_driven = 1'b0; end end always @(negedge WL_on) begin:Write_leveling_5 if (~ODT && ~MR1[7]) fork tMRD_in = 0; tMRD_in <= #(1000) 1; tMOD_in = 0; tMOD_in <= #(1000) 1; join end always @(tMOD_out) begin:Write_leveling_6 if ( ~ODT && ~MR1[7] && tMOD_out) begin DOut_zd = 8'bz; end end always @(MR1) begin:Write_leveling_7 if (~MR1[7]) WL_on = 1'b0; //-- END OF WRITE LEVELING PROCEDURE end /********************************* ******END WRITE LEVELING********** **********************************/ ///////////////////////////////////////////////////////////////////////////// ////Write Memory task ///////////////////////////////////////////////////////////////////////////// integer waddr_temp = 0; reg cross = 1'b0; reg cross1 = 1'b0; task WriteMem; begin waddr_temp = Start_roww*(ColNum+1) + In_colw; WAddr = Start_bankw*(MemSize+1) + Start_roww*(ColNum+1) + In_colw; if ((TDQSIn != 1'b1 && ~MR1[11]) || MR1[11]) begin Mem[WAddr] = -1; if (~Viol) Mem[WAddr] = DIn; end end endtask always @(posedge In_data) begin : indata Start_bankw = current_bank; Start_roww = current_row; Start_colw = current_column; if (burst_len == 4) Start_colw = current_column - (current_column % 4); else Start_colw = current_column - (current_column % 8); In_colw = Start_colw; burst_cnt = 0; burst_cnt_aux = 0; seqw = In_colw % 8; if (~MR0[3]) begin for(j=0;j<=7;j=j+1) begin burst_seqw[j] = Seq[j]; end end else begin for(j=0;j<=7;j=j+1) begin burst_seqw[j] = Inl[j]; end end fork skew_check = 1'b1; preamble_check = 1'b1; preamble_check <= #((CK_period/2) + 1000) 1'b0; join end always @(DQSIn) begin : writein if (DQSIn) begin for(j=0;j<=7;j=j+1) begin if (burst_cnt_aux < 2 && (Curr_bank_state[j] == writting || Curr_bank_state[j] == writtingap) && ~cross) begin cross = 1'b1; burst_cnt_aux = burst_cnt_aux + 1; end end cross = 1'b0; end for(j=0;j<=7;j=j+1) begin if (burst_cnt_aux > 1 && burst_cnt < burst_len && (Curr_bank_state[j] == writting || Curr_bank_state[j] == writtingap) && ~cross1) begin In_colw = Start_colw + burst_seqw[burst_cnt]; cross1 = 1'b1; if (burst_cnt == (burst_len - 1)) fork burst_cnt_aux = 0; if (burst_len == 8) burst_cnt = 8; else burst_cnt = 4; skew_check = 1'b0; postamble_check = 1'b1; postamble_check <= #(CK_period) 1'b0; join else burst_cnt = burst_cnt + 1; WriteMem; end end cross1 = 1'b0; end ///////////////////////////////////////////////////////////////////////////// ////Read Memory task ///////////////////////////////////////////////////////////////////////////// integer raddr_temp; integer data_temp; task ReadMem; begin raddr_temp = Start_rowr*(ColNum+1) + In_colr; RAddr = Start_bankr*(MemSize+1) + raddr_temp; data_temp = Mem[RAddr]; out_buffer = 8'bx; if (data_temp >= 0) out_buffer = data_temp; end endtask always @(posedge CKInt) begin if ($time != 0) begin preamble_allow = 1'b0; if (~preamble_done) begin preamble_allow = 1'b1; preamble_done = 1'b1; if (~MR1[12]) fork DQS_zd = ~CKInt; DQSNeg_zd = CKInt; join end end end always @(preamble_gen) begin if (preamble_gen) preamble_done = 1'b0; end always @(posedge Out_data) begin Start_bankr = read_bank; Start_rowr = read_row; Start_colr = read_column; In_colr = Start_colr; burst_cntr = 0; seqr = In_colr % 8; if (~MR0[3]) begin for(j=0;j<=7;j=j+1) begin burst_seqr[j] = Seq[(seqr*8)+j]; end end else begin for(j=0;j<=7;j=j+1) begin burst_seqr[j] = Inl[(seqr*8)+j]; end end end always @(CKInt) begin : outgen if (CKInt && burst_cntr == 0) begin burst_cntr = 1; ReadMem; if (~MR1[12]) fork DQS_zd = CKInt; DQSNeg_zd = ~CKInt; DOut_zd = out_buffer; join end else if ((burst_cntr > 0) && (burst_cntr < burst_len)) begin ReadStart = 1'b1; In_colr = Start_colr + burst_seqr[burst_cntr]; burst_cntr = burst_cntr + 1; ReadMem; if (~MR1[12]) fork DQS_zd = CKInt; DQSNeg_zd = ~CKInt; DOut_zd = out_buffer; join end else if ((burst_cntr == burst_len) && ~preamble_allow) fork burst_cntr = 9; DQS_zd = 1'bz; DQSNeg_zd = 1'bz; DOut_zd = 8'bz; ReadStart <= #((CK_period/4) + 1000) 1'b0; Read_Start = 1'b0; join end always @(wr_event) fork wait_read[itmp][jtmp] <= #(1000) 1; Read_Start = 1'b1; delay[itmp*11+jtmp] = read_delay; temp_bank[itmp*11+jtmp] = current_bank; temp_row[itmp*11+jtmp] = current_row; temp_column[itmp*11+jtmp] = current_column; wait_read[itmp][jtmp] <= #(2000) 0; join always @(sim_end) begin : sim_process SimulationEnd <= #(1000) 1'b0; SimulationEnd <= #(2*CK_period) 1'b1; end always @(posedge CKDiff) begin : readsch for(i=0;i<=BankNum;i=i+1) begin for(j=0;j<=10;j=j+1) begin if (delay[i*11+j] > 4) delay[i*11+j] = delay[i*11+j] - 1; else if (delay[i*11+j] == 4) begin delay[i*11+j] = delay[i*11+j] - 1; if (preamble[i][j]) fork preamble_gen = 1'b0; preamble_gen <= #((3*CK_period/4) - 1000) 1'b1; preamble_gen <= #(3*CK_period/4) 1'bz; join end else if (delay[i*11+j] == 3) fork delay[i*11+j] = delay[i*11+j] - 1; read_bank = temp_bank[i*11+j]; read_row = temp_row[i*11+j]; read_column = temp_column[i*11+j]; read_sch[i][j] = 1'b0; Out_data = 1'b0; Out_data <= #((3*CK_period/4) - 1000) 1'b1; Out_data <= #(3*CK_period/4) 1'bz; join end end end always @(posedge tRRD_in) begin if ($time != 0 ) begin for(i=0;i<=3;i=i+1) begin if (act_num[i] == 0) begin if (i == 0) fork act_num[0] = 1; tFAW_in[0] = 1'b0; tFAW_in[0] <= #(1000) 1'b1; join else begin next_slot = 1'b1; for(j=0;j<=(i-1);j=j+1) begin if (act_num[j] == 0) next_slot = 1'b0; end if (next_slot) fork act_num[i] = 1; tFAW_in[i] = 1'b0; tFAW_in[i] <= #(1000) 1'b1; join end end else begin if (act_num[i] == 3) active_forbid = 1'b1; else act_num[i] = act_num[i] + 1; end end end end always @(posedge tFAW_out[0]) begin act_num[0] = 0; active_forbid = 1'b0; end always @(posedge tFAW_out[1]) begin act_num[1] = 0; active_forbid = 1'b0; end always @(posedge tFAW_out[2]) begin act_num[2] = 0; active_forbid = 1'b0; end always @(posedge tFAW_out[3]) begin act_num[3] = 0; active_forbid = 1'b0; end always @(tRCD_out) begin for (i=0; i<=BankNum; i=i+1) begin if (tRCD_out[i] && Curr_bank_state[i] == activating) begin Curr_bank_state[i] = active; Next_bank_state[i] = active; end end end always @(tRP_out) begin for (i=0; i<=BankNum; i=i+1) begin if (tRP_out[i] && Curr_bank_state[i] == precharging) begin Curr_bank_state[i] = precharged; Next_bank_state[i] = precharged; end end end function integer freeslot; input [10:0] sch; begin freeslot = 0; while (sch[freeslot]) begin freeslot = freeslot + 1; end end endfunction always @(TDQS_EN) begin:tdqs_function if (TDQS_EN) begin TDQS_zd = TDQS_EN; TDQSNeg_zd = ~TDQS_EN; end else begin TDQSNeg_zd = 8'bz; TDQS_zd = 8'bz; end end reg BuffInDLL; wire BuffOutDLL; BUFFER BUFDLL (BuffOutDLL, BuffInDLL); initial begin BuffInDLL = 1'b1; end always @(posedge BuffOutDLL) begin DLL_TIME = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf (OUT, IN); endmodule