//////////////////////////////////////////////////////////////////////////////
//  File name : s29jl032j4.v
//////////////////////////////////////////////////////////////////////////////
A//  Copyright (C) 2008 Free Model Foundry; http://www.FreeModelFoundry.com
//
//  This program is free software; you can redistribute it and/or modify
//  it under the terms of the GNU General Public License version 2 as
//  published by the Free Software Foundation.
//
//  MODIFICATION HISTORY :
//
//  version: | author:        |  date:    | changes made:
//    V1.0     B.Colakovic      08 Dec 02   Initial release
//////////////////////////////////////////////////////////////////////////////
//  PART DESCRIPTION:
//
//  Library:        FLASH
//  Technology:     Flash Memory
//  Part:           S29JL032J4
//
//  Description:    32 Megabit Simultaneous Read/Write Flash Memory
//
//////////////////////////////////////////////////////////////////////////////
//  Known Bugs:
//
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION                                                       //
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns

module s29jl032j4
(
    A20      ,
    A19      ,
    A18      ,
    A17      ,
    A16      ,
    A15      ,
    A14      ,
    A13      ,
    A12      ,
    A11      ,
    A10      ,
    A9       ,
    A8       ,
    A7       ,
    A6       ,
    A5       ,
    A4       ,
    A3       ,
    A2       ,
    A1       ,
    A0       ,

    DQ15     ,
    DQ14     ,
    DQ13     ,
    DQ12     ,
    DQ11     ,
    DQ10     ,
    DQ9      ,
    DQ8      ,
    DQ7      ,
    DQ6      ,
    DQ5      ,
    DQ4      ,
    DQ3      ,
    DQ2      ,
    DQ1      ,
    DQ0      ,

    CENeg    ,
    OENeg    ,
    WENeg    ,
    WPNeg    ,
    RESETNeg ,
    BYTENeg,
    RY      );

////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations
////////////////////////////////////////////////////////////////////////
    input  A20  ;
    input  A19  ;
    input  A18  ;
    input  A17  ;
    input  A16  ;
    input  A15  ;
    input  A14  ;
    input  A13  ;
    input  A12  ;
    input  A11  ;
    input  A10  ;
    input  A9   ;
    input  A8   ;
    input  A7   ;
    input  A6   ;
    input  A5   ;
    input  A4   ;
    input  A3   ;
    input  A2   ;
    input  A1   ;
    input  A0   ;

    inout  DQ15  ;
    inout  DQ14  ;
    inout  DQ13  ;
    inout  DQ12  ;
    inout  DQ11  ;
    inout  DQ10  ;
    inout  DQ9   ;
    inout  DQ8   ;
    inout  DQ7   ;
    inout  DQ6   ;
    inout  DQ5   ;
    inout  DQ4   ;
    inout  DQ3   ;
    inout  DQ2   ;
    inout  DQ1   ;
    inout  DQ0   ;

    input  CENeg    ;
    input  OENeg    ;
    input  WENeg    ;
    input  WPNeg    ;
    input  BYTENeg ;
    input  RESETNeg ;
    output RY       ;

    // interconnect path delay signals
    wire  A20_ipd  ;
    wire  A19_ipd  ;
    wire  A18_ipd  ;
    wire  A17_ipd  ;
    wire  A16_ipd  ;
    wire  A15_ipd  ;
    wire  A14_ipd  ;
    wire  A13_ipd  ;
    wire  A12_ipd  ;
    wire  A11_ipd  ;
    wire  A10_ipd  ;
    wire  A9_ipd   ;
    wire  A8_ipd   ;
    wire  A7_ipd   ;
    wire  A6_ipd   ;
    wire  A5_ipd   ;
    wire  A4_ipd   ;
    wire  A3_ipd   ;
    wire  A2_ipd   ;
    wire  A1_ipd   ;
    wire  A0_ipd   ;

    wire [20 : 0] A;
    assign A = {
                A20_ipd,
                A19_ipd,
                A18_ipd,
                A17_ipd,
                A16_ipd,
                A15_ipd,
                A14_ipd,
                A13_ipd,
                A12_ipd,
                A11_ipd,
                A10_ipd,
                A9_ipd,
                A8_ipd,
                A7_ipd,
                A6_ipd,
                A5_ipd,
                A4_ipd,
                A3_ipd,
                A2_ipd,
                A1_ipd,
                A0_ipd };

    wire  DQ15_ipd  ;
    wire  DQ14_ipd  ;
    wire  DQ13_ipd  ;
    wire  DQ12_ipd  ;
    wire  DQ11_ipd  ;
    wire  DQ10_ipd  ;
    wire  DQ9_ipd   ;
    wire  DQ8_ipd   ;
    wire  DQ7_ipd   ;
    wire  DQ6_ipd   ;
    wire  DQ5_ipd   ;
    wire  DQ4_ipd   ;
    wire  DQ3_ipd   ;
    wire  DQ2_ipd   ;
    wire  DQ1_ipd   ;
    wire  DQ0_ipd   ;

    wire [15 : 0 ] DIn;
    assign DIn = {DQ15_ipd,
                  DQ14_ipd,
                  DQ13_ipd,
                  DQ12_ipd,
                  DQ11_ipd,
                  DQ10_ipd,
                  DQ9_ipd,
                  DQ8_ipd,
                  DQ7_ipd,
                  DQ6_ipd,
                  DQ5_ipd,
                  DQ4_ipd,
                  DQ3_ipd,
                  DQ2_ipd,
                  DQ1_ipd,
                  DQ0_ipd };

    wire [15 : 0 ] DOut;
    assign DOut = {DQ15,
                  DQ14,
                  DQ13,
                  DQ12,
                  DQ11,
                  DQ10,
                  DQ9,
                  DQ8,
                  DQ7,
                  DQ6,
                  DQ5,
                  DQ4,
                  DQ3,
                  DQ2,
                  DQ1,
                  DQ0 };

    wire  CENeg_ipd    ;
    wire  OENeg_ipd    ;
    wire  WENeg_ipd    ;
    wire  RESETNeg_ipd ;
    wire  WPNeg_ipd    ;
    wire  BYTENeg_ipd  ;

    //  internal delays
    reg HANG_out      ;// Program/Erase Timing Limit
    reg HANG_in       ;
    reg START_T1      ;// Start TimeOut
    reg START_T1_in   ;
    reg CTMOUT        ;// Sector Erase TimeOut
    reg CTMOUT_in     ;
    reg READY_in      ;
    reg READY         ;// Device ready after reset
    reg PBPROG_in     ;
    reg PBPROG_out    ;// Protection Bit Program
    reg PBERASE_in    ;
    reg PBERASE_out   ;// Protection Bit Erase
    reg UNLOCKDONE_in ;
    reg UNLOCKDONE_out;// Password Unlock
    reg PASSPDONE_in  ;
    reg PASSPDONE_out ;// Password Program

    reg [15 : 0] DOut_zd;

    wire  DQ15_Pass  ;
    wire  DQ14_Pass  ;
    wire  DQ13_Pass  ;
    wire  DQ12_Pass  ;
    wire  DQ11_Pass  ;
    wire  DQ10_Pass  ;
    wire  DQ9_Pass   ;
    wire  DQ8_Pass   ;
    wire  DQ7_Pass   ;
    wire  DQ6_Pass   ;
    wire  DQ5_Pass   ;
    wire  DQ4_Pass   ;
    wire  DQ3_Pass   ;
    wire  DQ2_Pass   ;
    wire  DQ1_Pass   ;
    wire  DQ0_Pass   ;

    reg [15 : 0] DOut_Pass;

    assign {DQ15_Pass,
            DQ14_Pass,
            DQ13_Pass,
            DQ12_Pass,
            DQ11_Pass,
            DQ10_Pass,
            DQ9_Pass,
            DQ8_Pass,
            DQ7_Pass,
            DQ6_Pass,
            DQ5_Pass,
            DQ4_Pass,
            DQ3_Pass,
            DQ2_Pass,
            DQ1_Pass,
            DQ0_Pass  } = DOut_Pass;

    reg RY_zd = 1;

    reg POW_in     ;
    reg POW_out    ;
    reg POB_in     ;
    reg POB_out    ;
    reg POU_in     ;
    reg POU_out    ;

    reg SEO_in      ;
    reg SEO_out     ;

    parameter UserPreload     = 1'b0;
    parameter flash_file_name = "none";
    parameter prot_file_name  = "none";
    parameter secsi_file_name  = "none";
    parameter TimingModel     = "DefaultTimingModel";

    parameter DelayValues = "FROM_PLI";
    parameter PartID        = "s29jl032j4";
    parameter MaxData       = 255;
    parameter GroupNum      = 16;
    parameter SecSize       = 16'hFFFF;
    parameter SecNum        = 63;
    parameter SubSecNum     = 7;
    parameter HiAddrBit     = 20;
    parameter SecSiSize     = 255;

    parameter OW = 8'b00011010;
    parameter PL = 8'b00001010;
    parameter SL = 8'b00010010;
    parameter WP = 8'b00000010;

    parameter MEMORY             =3'h0;
    parameter OTP_MEM            =3'h1;

    // If speedsimulation is needed uncomment following line
//     `define SPEEDSIM;

    // powerup
    reg PoweredUp;

   //varaibles to resolve if bottom or top architecture is used
    reg [20*8-1:0] tmp_timing;//stores copy of TimingModel
    reg [7:0] tmp_char;
    integer found = 1'b0;

    //FSM control signals
    reg ULBYPASS ; ////Unlock Bypass Active
    reg OTP_ACT  ; ////SecSi access
    reg ESP_ACT  ; ////Erase Suspend
    reg PSP_ACT  ; ////Program Suspend
    reg PDONE    ; ////Prog. Done
    reg PSTART   ; ////Start Programming
    reg PSUSP    ; ////Program suspend
    reg PRES     ; ////Resume Program
    //Program location is in protected sector
    reg PERR     ;

    reg EDONE    ; ////Ers. Done
    reg ESTART   ; ////Start Erase
    reg ESUSP    ; ////Suspend Erase
    reg ERES     ; ////Resume Erase
    //All sectors selected for erasure are protected
    reg EERR     ;
    //Sectors selected for erasure
    reg [SecNum:0] Ers_Queue; // = SecNum'b0;
    reg [SubSecNum:0] Ers_Sub_Queue;

    //Command Register
    reg write ;
    reg read  ;

    //Sector Address
    integer SecAddr = 0;         // 0 - SecNum
    integer SubSect = 0;         // 0 - SubSecNum
    integer SA      = 0;         // 0 TO SecNum
    integer SSA     = 0;         // 0 TO SubSecNum
    integer BA     = 0;         // 0 TO SubSecNum
    //Address within sector
    integer Address = 0;         // 0 - SecSize
    integer SubAddr = 0;
    integer SecSiAddr = 0;         // 0 - SecNum

    integer D_tmp0; //0 TO MaxData;
    integer D_tmp1; //0 TO MaxData;

    //A19:A11 Don't Care
    integer Addr;         //0 TO 16'h7FF#
    integer ASAddr;

    reg PR_FLAG = 0;
    reg ER_FLAG = 0;

    //glitch protection
    wire gWE_n ;
    wire gCE_n ;
    wire gOE_n ;

    reg[7:0]  old_bit, new_bit;
    integer old_int, new_int;
    integer wr_cnt;

    reg RST ;
    reg reseted ;
    reg BYTE ;

    integer Mem[0:(SecNum+1)*(SecSize+1)-1];
    //Sector Protection for sub sectors
    reg [SubSecNum:0] SubSec_Prot =8'hFF;
    //Sector Protection Status
    integer Password[0:7];
    reg[SecNum:0] DYB;
    reg[GroupNum:0] PPB;
    reg[SubSecNum:0] DYB_SubSec;
    reg[SubSecNum:0]PPB_SubSec;
    reg PPBLock;
    reg PPMLB;
    reg SPMLB;
    reg SSPB;

    integer SecSi[0:SecSiSize];
    integer CFI_array[16:91];

    reg Viol = 1'b0;

    // Address of variable size sector
    integer VarSect = -1;
    reg     vs;

    integer     BankNum = 1;

    // Addresses of the Protected Sector
    integer ProtSecNum_1 = 0;
    integer ProtSecNum_2 = 1;

    reg [2:0]  PGMS_FLAG;

    integer WData[0:1];
    integer WAddr[0:1];

    reg [1:0] BankAddress;

    event MergeE;

    integer cnt = 0;

    reg oe = 1'b0;
    event oe_event;

    event initOK;
    reg[7:0] temp;

    //Status reg.
    reg[7:0] Status = 16'b0;

    integer WAddrPass;
    reg[15:0] WDataPassLo;
    reg[15:0] WDataPassHi;
    reg UnlockPass;
    integer PBSecAddr;
    integer PBSubSecAddr;
    integer PPB_ers_ccl;

    // iterator for FOR loop
    integer i,j,k;

    //TPD_XX_DATA
    time OEDQ_t;
    time CEDQ_t;
    time BYTEDQ_t;
    time ADDRDQ_t;
    time OENeg_posEvent;
    time CENeg_posEvent;
    time OENeg_event;
    time CENeg_event;
    time BYTENeg_event;
    time ADDR_event;
    reg FROMOE;
    reg FROMCE;
    reg FROMBYTE;
    reg FROMADDR;
    time   OEDQ_01;
    time   CEDQ_01;
    time   ADDRDQ_01;

    reg[15:0] TempData;

///////////////////////////////////////////////////////////////////////////////
//Interconnect Path Delay Section
///////////////////////////////////////////////////////////////////////////////

    buf   (A20_ipd, A20);
    buf   (A19_ipd, A19);
    buf   (A18_ipd, A18);
    buf   (A17_ipd, A17);
    buf   (A16_ipd, A16);
    buf   (A15_ipd, A15);
    buf   (A14_ipd, A14);
    buf   (A13_ipd, A13);
    buf   (A12_ipd, A12);
    buf   (A11_ipd, A11);
    buf   (A10_ipd, A10);
    buf   (A9_ipd , A9 );
    buf   (A8_ipd , A8 );
    buf   (A7_ipd , A7 );
    buf   (A6_ipd , A6 );
    buf   (A5_ipd , A5 );
    buf   (A4_ipd , A4 );
    buf   (A3_ipd , A3 );
    buf   (A2_ipd , A2 );
    buf   (A1_ipd , A1 );
    buf   (A0_ipd , A0 );

    buf   (DQ15_ipd, DQ15);
    buf   (DQ14_ipd, DQ14);
    buf   (DQ13_ipd, DQ13);
    buf   (DQ12_ipd, DQ12);
    buf   (DQ11_ipd, DQ11);
    buf   (DQ10_ipd, DQ10);
    buf   (DQ9_ipd , DQ9 );
    buf   (DQ8_ipd , DQ8 );
    buf   (DQ7_ipd , DQ7 );
    buf   (DQ6_ipd , DQ6 );
    buf   (DQ5_ipd , DQ5 );
    buf   (DQ4_ipd , DQ4 );
    buf   (DQ3_ipd , DQ3 );
    buf   (DQ2_ipd , DQ2 );
    buf   (DQ1_ipd , DQ1 );
    buf   (DQ0_ipd , DQ0 );

    buf   (CENeg_ipd    , CENeg    );
    buf   (OENeg_ipd    , OENeg    );
    buf   (WENeg_ipd    , WENeg    );
    buf   (RESETNeg_ipd , RESETNeg );
    buf   (BYTENeg_ipd  , BYTENeg  );
    buf   (WPNeg_ipd    , WPNeg    );

///////////////////////////////////////////////////////////////////////////////
// Propagation  delay Section
///////////////////////////////////////////////////////////////////////////////
    nmos   (DQ15,   DQ15_Pass , 1);
    nmos   (DQ14,   DQ14_Pass , 1);
    nmos   (DQ13,   DQ13_Pass , 1);
    nmos   (DQ12,   DQ12_Pass , 1);
    nmos   (DQ11,   DQ11_Pass , 1);
    nmos   (DQ10,   DQ10_Pass , 1);
    nmos   (DQ9 ,   DQ9_Pass , 1);
    nmos   (DQ8 ,   DQ8_Pass , 1);
    nmos   (DQ7 ,   DQ7_Pass , 1);
    nmos   (DQ6 ,   DQ6_Pass , 1);
    nmos   (DQ5 ,   DQ5_Pass , 1);
    nmos   (DQ4 ,   DQ4_Pass , 1);
    nmos   (DQ3 ,   DQ3_Pass , 1);
    nmos   (DQ2 ,   DQ2_Pass , 1);
    nmos   (DQ1 ,   DQ1_Pass , 1);
    nmos   (DQ0 ,   DQ0_Pass , 1);

    nmos   (RY  ,   1'b0      , ~RY_zd);

    wire deg;

    wire Embd;

    //VHDL VITAL CheckEnable equivalents
    // Address setup/hold near WE# falling edge
    wire CheckEnable_A0_WE;
    assign CheckEnable_A0_WE = ~CENeg && OENeg;
    // Data setup/hold near WE# rising edge
    wire CheckEnable_DQ0_WE;
    assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg;
    // Address setup/hold near CE# falling edge
    wire CheckEnable_A0_CE;
    assign CheckEnable_A0_CE = ~WENeg && OENeg;
    // Data setup/hold near CE# rising edge
    wire CheckEnable_DQ0_CE;
    assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg;
    wire CheckEnable_A0_OE;
    assign CheckEnable_A0_OE =  WENeg && ~CENeg && Embd;

specify

        // tipd delays: interconnect path delays , mapped to input port delays.
        // In Verilog is not necessary to declare any tipd_ delay variables,
        // they can be taken from SDF file
        // With all the other delays real delays would be taken from SDF file

    // tpd delays
    specparam           tpd_RESETNeg_DQ0        =1;
    specparam           tpd_A0_DQ0              =1;//tacc ok
    specparam           tpd_CENeg_DQ0           =1;//ok
                      //(tCE,tCE,tDF,-,tDF,-)
    specparam           tpd_OENeg_DQ0           =1;//ok
                      //(tOE,tOE,tDF,-,tDF,-)
    specparam           tpd_WENeg_RY            =1;    //tBUSY
    specparam           tpd_CENeg_RY            =1;    //tBUSY
    specparam           tpd_BYTENeg_DQ0         =1;

    // tsetup values: setup time
    specparam           tsetup_A0_CENeg         =1;   //tAS edge \
    specparam           tsetup_DQ0_CENeg        =1;   //tDS edge /
    specparam           tsetup_OENeg_WENeg      =1;   //0 edge /
    specparam           tsetup_CENeg_WENeg      =1;   //0 ns /
    specparam           tsetup_A0_OENeg         =1;   //tASO edge \

    // thold values: hold times
    specparam           thold_A0_CENeg          =1; //tAH  edge \
    specparam           thold_DQ0_CENeg         =1; //tDH edge /
    specparam           thold_OENeg_WENeg       =1; //tOEH edge /
    specparam           thold_CENeg_WENeg       =1; //tOEH edge /
    specparam           thold_CENeg_RESETNeg    =1; //tRH  edge /
    specparam           thold_BYTENeg_CENeg     =1; //telf, tehfl
    specparam           thold_WENeg_OENeg       =1; //tGHVL edge /
    specparam           thold_A0_OENeg          =1; //tAHT edge /
     // tpw values: pulse width
    specparam           tpw_RESETNeg_negedge    =1; //tRP
    specparam           tpw_WENeg_negedge       =1; //tWP
    specparam           tpw_WENeg_posedge       =1; //tWPH
    specparam           tpw_CENeg_negedge       =1; //tCP
    specparam           tpw_CENeg_posedge       =1; //tCEPH
    specparam           tpw_A0_negedge          =1; //tWC tRC ok
    specparam           tpw_A0_posedge          =1; //tWC tRC ok
    specparam           tpw_OENeg_posedge       =1; //tOEPH

    // tdevice values: values for internal delays
            //Program Operation
    `ifdef SPEEDSIM
        specparam   tdevice_POB                     = 6000; //6 us;
        specparam   tdevice_POW                     = 6000; //6 us;
        specparam   tdevice_POU                     = 4000; //4 us;
            //Sector Erase Operation    tWHWH2
        specparam   tdevice_SEO                     = 400000; //0.4 ms
                //Timing Limit Exceeded
        specparam   tdevice_HANG                    = 500000000; //500 ms;
                //program/erase suspend timeout
        specparam   tdevice_START                   = 35000; //35 us;
                //sector erase command sequence timeout
        specparam   tdevice_CTMOUT                  = 80000; //80 us;
                //device ready after Hardware reset(during embeded algorithm)
        specparam   tdevice_READY                   = 20000; //20 us; //tReady
            //Password Unlock Operation
        specparam   tdevice_UNLOCK                  = 2000;  //2 us;
            // Protection Bit Program
        specparam   tdevice_PROTP                   = 100000;  //100 us;
            // Protection Bit Erase
        specparam  tdevice_PROTE                    = 1200000; //1200 us;
    `else
        specparam   tdevice_POB                     = 6000; //6 us;
        specparam   tdevice_POW                     = 6000; //6 us;
        specparam   tdevice_POU                     = 4000; //4 us;
            //Sector Erase Operation    tWHWH2
        specparam   tdevice_SEO                     = 400000000; //0.4 sec;
                //Timing Limit Exceeded
        specparam   tdevice_HANG                    = 500000000; //500 ms;
                //program/erase suspend timeout
        specparam   tdevice_START                   = 35000; //35 us;
                //sector erase command sequence timeout
        specparam   tdevice_CTMOUT                  = 80000; //80 us;
                //device ready after Hardware reset(during embeded algorithm)
        specparam   tdevice_READY                   = 20000; //20 us; //tReady
            //Password Unlock Operation
        specparam   tdevice_UNLOCK                  = 2000;  //2 us;
            // Protection Bit Program
        specparam   tdevice_PROTP                   = 100000;  //100 us;
            // Protection Bit Erase
        specparam  tdevice_PROTE                    = 1200000; //1200 us;
    `endif

    // If tpd values are fetched from specify block, these parameters
    // must change along with SDF values, SDF values change will NOT
    // imlicitly apply here !
    // If you want tpd values to be fetched by the model itself, please
    // use the PLI routine approach but be shure to set parameter
    // DelayValues to "FROM_PLI" as default

///////////////////////////////////////////////////////////////////////////////
// Input Port  Delays  don't require Verilog description
///////////////////////////////////////////////////////////////////////////////
// Path delays                                                               //
///////////////////////////////////////////////////////////////////////////////
//for DQ signals
    if (FROMCE)( CENeg => DQ0 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ1 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ2 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ3 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ4 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ5 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ6 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ7 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ8 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ9 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ10 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ11 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ12 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ13 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ14 ) = tpd_CENeg_DQ0;
    if (FROMCE)( CENeg => DQ15 ) = tpd_CENeg_DQ0;

    if (FROMOE)( OENeg => DQ0 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ1 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ2 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ3 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ4 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ5 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ6 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ7 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ8 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ9 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ10 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ11 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ12 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ13 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ14 ) = tpd_OENeg_DQ0;
    if (FROMOE)( OENeg => DQ15 ) = tpd_OENeg_DQ0;

    if (FROMADDR)( A0 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A0 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A1 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A2 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A3 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A4 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A5 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A6 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A7 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A8 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A9 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A10 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A11 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A12 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A13 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A14 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A15 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A16 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A17 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A18 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A19 => DQ15 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ0 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ1 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ2 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ3 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ4 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ5 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ6 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ7 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ8 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ9 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ10 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ11 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ12 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ13 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ14 ) = tpd_A0_DQ0;
    if (FROMADDR)( A20 => DQ15 ) = tpd_A0_DQ0;

    if (~BYTE && FROMADDR)( DQ15 => DQ0 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ1 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ2 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ3 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ4 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ5 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ6 ) = tpd_A0_DQ0;
    if (~BYTE && FROMADDR)( DQ15 => DQ7 ) = tpd_A0_DQ0;

    if (BYTENeg)( BYTENeg => DQ0 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ1 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ2 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ3 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ4 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ5 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ6 ) = tpd_BYTENeg_DQ0;
    if (BYTENeg)( BYTENeg => DQ7 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ8 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ9 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ10 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ11 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ12 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ13 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ14 ) = tpd_BYTENeg_DQ0;
        ( BYTENeg => DQ15 ) = tpd_BYTENeg_DQ0;

    if (~RESETNeg)( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ8 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg) ( RESETNeg => DQ9 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg) ( RESETNeg => DQ10 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ11 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ12 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ13 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg) ( RESETNeg => DQ14 ) = tpd_RESETNeg_DQ0;
    if (~RESETNeg)( RESETNeg => DQ15 ) = tpd_RESETNeg_DQ0;

//for RY signal
    (WENeg => RY)     = tpd_WENeg_RY;
    (CENeg => RY)     = tpd_CENeg_RY;

////////////////////////////////////////////////////////////////////////////////
// Timing Violation                                                           //
////////////////////////////////////////////////////////////////////////////////
    $setup (A0, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A1, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A2, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A3, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A4, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A5, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A6, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A7, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A8, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A9, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);
    $setup (A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_CENeg, Viol);

    $setup (A0, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A1, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A2, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A3, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A4, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A5, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A6, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A7, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A8, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A9, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A10, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A11, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A12, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A13, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A14, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A15, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A16, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A17, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A18, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A19, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);
    $setup (A20, negedge WENeg &&& CheckEnable_A0_WE,tsetup_A0_CENeg,Viol);

    $setup (A0, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A1, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A2, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A3, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A4, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A5, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A6, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A7, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A8, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A9, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A10, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A11, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A12, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A13, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A14, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A15, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A16, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A17, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A18, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A19, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);
    $setup (A20, negedge OENeg &&& CheckEnable_A0_OE,tsetup_A0_OENeg,Viol);

    $setup (DQ0 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ1 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ2 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ3 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ4 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ5 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ6 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ7 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ8 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ9 , posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ10, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ11, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ12, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ13, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ14, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ15, posedge CENeg &&& CheckEnable_DQ0_CE,tsetup_DQ0_CENeg,Viol);
    $setup (DQ0 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ1 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ2 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ3 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ4 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ5 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ6 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ7 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ8 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ9 , posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ10,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ11,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ12,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ13,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ14,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);
    $setup (DQ15,posedge WENeg &&& CheckEnable_DQ0_WE,tsetup_DQ0_CENeg, Viol);

    $setup ( CENeg   , negedge WENeg , tsetup_A0_CENeg, Viol);
    $setup ( BYTENeg , negedge CENeg , tsetup_A0_CENeg, Viol);
    $setup ( BYTENeg , negedge WENeg , tsetup_A0_CENeg, Viol);
    $setup ( OENeg   , negedge WENeg , tsetup_A0_CENeg, Viol);

    $hold (posedge RESETNeg &&& (CENeg===1),CENeg ,thold_CENeg_RESETNeg,Viol);
    $hold (posedge RESETNeg &&& (OENeg===1), OENeg ,thold_CENeg_RESETNeg, Viol);
    $hold (posedge RESETNeg &&& (WENeg===1), WENeg ,thold_CENeg_RESETNeg, Viol);
    $hold (posedge OENeg, WENeg , thold_WENeg_OENeg, Viol);

    $hold ( posedge WENeg&&&Embd==0,OENeg , thold_OENeg_WENeg, Viol);
    $hold ( posedge WENeg&&&Embd==1,OENeg  , thold_OENeg_WENeg, Viol);

    $hold ( posedge WENeg, CENeg , thold_WENeg_OENeg, Viol);
    $hold ( negedge CENeg, BYTENeg, thold_BYTENeg_CENeg, Viol);
    $hold ( negedge WENeg, BYTENeg, thold_A0_CENeg, Viol);

    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A0 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A1 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A2 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A3 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A4 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A5 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A6 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A7 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A8 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A9 ,  thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_CENeg, Viol);
    $hold (  negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_CENeg, Viol);

    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A0 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A1 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A2 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A3 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A4 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A5 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A6 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A7 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A8 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A9 ,  thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A10 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A11 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A12 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A13 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A14 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A15 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A16 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A17 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A18 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A19 , thold_A0_OENeg, Viol);
    $hold (  posedge OENeg &&& CheckEnable_A0_OE, A20 , thold_A0_OENeg, Viol);

    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 ,  thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_CENeg, Viol);
    $hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_CENeg, Viol);

    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ8 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ9 ,  thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ10 , thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ11 , thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ12 , thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ13 , thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ14 , thold_DQ0_CENeg, Viol);
    $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ15 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ8  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ9  , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ10 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ11 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ12 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ13 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ14 , thold_DQ0_CENeg, Viol);
    $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ15 , thold_DQ0_CENeg, Viol);

    $width (negedge RESETNeg, tpw_RESETNeg_negedge);
    $width (posedge WENeg&&&(CENeg===0), tpw_WENeg_posedge);
    $width (negedge WENeg&&&(CENeg===0), tpw_WENeg_negedge);
    $width (posedge CENeg, tpw_CENeg_posedge);
    $width (negedge CENeg, tpw_CENeg_negedge);
    $width (negedge A0, tpw_A0_negedge);
    $width (posedge A0, tpw_A0_posedge);
    $width (negedge A1, tpw_A0_negedge);
    $width (posedge A1, tpw_A0_posedge);
    $width (negedge A2, tpw_A0_negedge);
    $width (posedge A2, tpw_A0_posedge);
    $width (negedge A3, tpw_A0_negedge);
    $width (posedge A3, tpw_A0_posedge);
    $width (negedge A4, tpw_A0_negedge);
    $width (posedge A4, tpw_A0_posedge);
    $width (negedge A5, tpw_A0_negedge);
    $width (posedge A5, tpw_A0_posedge);
    $width (negedge A6, tpw_A0_negedge);
    $width (posedge A6, tpw_A0_posedge);
    $width (negedge A7, tpw_A0_negedge);
    $width (posedge A7, tpw_A0_posedge);
    $width (negedge A8, tpw_A0_negedge);
    $width (posedge A8, tpw_A0_posedge);
    $width (negedge A9, tpw_A0_negedge);
    $width (posedge A9, tpw_A0_posedge);
    $width (negedge A10, tpw_A0_negedge);
    $width (posedge A10, tpw_A0_posedge);
    $width (negedge A11, tpw_A0_negedge);
    $width (posedge A11, tpw_A0_posedge);
    $width (negedge A12, tpw_A0_negedge);
    $width (posedge A12, tpw_A0_posedge);
    $width (negedge A13, tpw_A0_negedge);
    $width (posedge A13, tpw_A0_posedge);
    $width (negedge A14, tpw_A0_negedge);
    $width (posedge A14, tpw_A0_posedge);
    $width (negedge A15, tpw_A0_negedge);
    $width (posedge A15, tpw_A0_posedge);
    $width (negedge A16, tpw_A0_negedge);
    $width (posedge A16, tpw_A0_posedge);
    $width (negedge A17, tpw_A0_negedge);
    $width (posedge A17, tpw_A0_posedge);
    $width (negedge A18, tpw_A0_negedge);
    $width (posedge A18, tpw_A0_posedge);
    $width (negedge A19, tpw_A0_negedge);
    $width (posedge A19, tpw_A0_posedge);
    $width (negedge A20, tpw_A0_negedge);
    $width (posedge A20, tpw_A0_posedge);

    $width (posedge OENeg, tpw_OENeg_posedge);//ok
    endspecify

////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block                                                        //
////////////////////////////////////////////////////////////////////////////////

    // FSM states
    parameter RESET                =7'd0;
    parameter Z001                 =7'd1;
    parameter PREL_SETBWB          =7'd2;
    parameter PREL_ULBYPASS        =7'd3;
    parameter PREL_ULBYPASS_RESET  =7'd4;
    parameter CFI                  =7'd5;
    parameter AS                   =7'd6;
    parameter A0SEEN               =7'd7;
    parameter OTP                  =7'd8;
    parameter OTP_Z001             =7'd9;
    parameter OTP_PREL             =7'd10;
    parameter OTP_EXIT             =7'd11;
    parameter OTP_A0SEEN           =7'd12;
    parameter C8                   =7'd13;
    parameter C8_Z001              =7'd14;
    parameter C8_PREL              =7'd15;
    parameter ERS                  =7'd16;
    parameter SERS                 =7'd17;
    parameter ESPS                 =7'd18;
    parameter SERS_EXEC            =7'd19;
    parameter ESP                  =7'd20;
    parameter ESP_SETBWB           =7'd21;
    parameter ESP_Z001             =7'd22;
    parameter ESP_A0SEEN           =7'd23;
    parameter PGMS                 =7'd24;
    parameter ESP_ULBYPASS         =7'd25;
    parameter ESP_ULBYPASS_RESET   =7'd26;
    parameter AS_CFI               =7'd27;
    parameter UBP_CFI              =7'd28;
    parameter ESP_AS               =7'd29;
    parameter ESP_CFI              =7'd30;
    parameter ESP_AS_CFI           =7'd31;
    parameter PSP                  =7'd32;
    parameter PSPS                 =7'd33;
    parameter PSP_CFI              =7'd34;
    parameter PSP_Z001             =7'd35;
    parameter PSP_PREL             =7'd36;
    parameter PSP_AS               =7'd37;
    parameter PSP_AS_CFI           =7'd38;
    parameter PASSPROG_PREL        =7'd39;
    parameter PASSPROG             =7'd40;
    parameter PASSVERIFY           =7'd41;
    parameter PASSUNLOCK0          =7'd42;
    parameter PASSUNLOCK1          =7'd43;
    parameter PASSUNLOCK2          =7'd44;
    parameter PASSUNLOCK3          =7'd45;
    parameter PASSUNLOCK4          =7'd46;
    parameter PASSUNLOCK5          =7'd47;
    parameter PASSUNLOCK6          =7'd48;
    parameter PASSUNLOCK7          =7'd49;
    parameter PROTBIT_PREL         =7'd50;
    parameter PPBDYB               =7'd51;
    parameter DYBWE                =7'd52;
    parameter PPB_PROGRAM          =7'd53;
    parameter PPB_VERIFY           =7'd54;
    parameter PPB_ERASE            =7'd55;
    parameter PPMLB_PROGRAM        =7'd56;
    parameter SPMLB_PROGRAM        =7'd57;
    parameter SSPB_PROGRAM         =7'd58;
    parameter PPMLB_VERIFY         =7'd59;
    parameter SPMLB_VERIFY         =7'd60;
    parameter SSPB_VERIFY          =7'd61;

    reg [5:0] current_state;
    reg [5:0] next_state;

    reg [1:0] BankProg;
    reg [1:0] BankAutosel;
    reg [1:0] BankBypassLock;
    reg [1:0] BankErase;
    reg [1:0] BankEraseExec;

    reg deq;
    reg Embeded;

    reg rising_edge_WENeg = 0;
    reg rising_edge_CTMOUT = 0;
    reg falling_edge_WENeg = 0;
    reg rising_edge_write = 0;
    reg rising_edge_CENeg = 0;
    reg falling_edge_CENeg = 0;
    reg falling_edge_OENeg = 0;
    reg A_event = 0;
    reg DIn_15_event = 0;
    reg rising_edge_reseted = 0;
    reg rising_edge_PSTART = 0;
    reg rising_edge_PSUSP = 0;
    reg rising_edge_PRES = 0;
    reg falling_edge_write = 0;
    reg falling_edge_PERR = 0;
    reg falling_edge_EERR = 0;
    reg falling_edge_RST = 0;
    reg rising_edge_UNLOCKDONE_out = 0;
    reg rising_edge_PASSPDONE_out = 0;
    reg rising_edge_EDONE = 0;
    reg rising_edge_PDONE = 0;
    reg Address_event = 0;
    reg current_state_event = 0;
    reg SecAddr_event = 0;
    reg rising_edge_read = 0;
    reg rising_edge_PBPROG_out = 0;
    reg rising_edge_PBERASE_out = 0;
    reg rising_edge_ERES = 0;
    reg rising_edge_ESUSP = 0;
    reg rising_edge_ESTART = 0;
    reg falling_edge_WPNeg = 0;
    reg rising_edge_WPNeg = 0;
    reg falling_edge_RESETNeg = 0;
    reg rising_edge_RESETNeg = 0;

    always @(DIn, DOut)
    begin
        if (DIn==DOut)
            deq=1'b1;
        else
            deq=1'b0;
    end
    // check when data is generated from model to avoid setuphold check in
    // those occasion
    assign deg=deq;

    always @(PDONE,EDONE)
    begin
        if ((PDONE == 0)|| (EDONE == 0))
            Embeded=1'b1;
        else
            Embeded=1'b0;
    end

    assign Embd=Embeded;

    // initialize memory and load preload files if any
    initial
    begin : NBlck
    integer i,j;
    integer tmp1,tmp2,tmp3;
    integer secure_silicon[0:SecSiSize];
    reg     sector_prot_tmp[0:SecNum+2*SubSecNum];
        tmp_timing = TimingModel;
        i = 19;
        while ((i >= 0) && (found != 1'b1))//search for first non null character
        begin                     //i keeps position of first non null character
            j = 7;
            while ((j >= 0) && (found != 1'b1))
            begin
                if (tmp_timing[i*8+j] != 1'd0)
                    found = 1'b1;
                else
                    j = j-1;
            end
            i = i - 1;
        end
        if (found)//if non null character is found
        begin
           for (j=0;j<=7;j=j+1)
           begin
               tmp_char[j] = tmp_timing[(i-14)*8+j];
           end
        end
        if (tmp_char == "1")
        begin
            VarSect       = SecNum;
            vs            = 1'b1;
            ProtSecNum_1   = 7;
            ProtSecNum_2   = 6;
        end
        else
        begin
           VarSect = 0;
           vs      = 1'b0;
           ProtSecNum_1 = 0;
           ProtSecNum_2 = 1;
        end

        for (i=0;i<=((SecNum+1)*(SecSize+1)-1);i=i+1)
        begin
            Mem[i]=MaxData;
        end

        for (i=0;i<=SecSiSize;i=i+1)
        begin
            secure_silicon[i]=MaxData;
        end

        for (i=0;i<=SecNum;i=i+1)
        begin
            Ers_Queue[i] = 0;
            DYB[i]=0;
        end
        for (i=0;i<=7;i=i+1)
        begin
            Ers_Sub_Queue[i] = 0;
            SubSec_Prot[i] = 0;
            DYB_SubSec[i] = 0;
            PPB_SubSec[i] = 0;
        end
        for (i=0;i<=GroupNum;i=i+1)
        begin
            PPB[i] = 0;
        end

        //- Sector protection preload
        //s29jl032j _prot.mem sector protect file
        // // - comment
        // @aaa - <aaa> stands for sector address
        // (aaaa is incremented at every load)
        // b - <b> is 1 for protected sector <aaa>, 0 for unprotect.
        // If <aaa> > SecNum SecSi is protected/unprotected
        if (UserPreload && !(prot_file_name == "none"))
        begin
            $readmemb(prot_file_name,sector_prot_tmp);
        end

        // - Secsi  preload
        // s29jl032j_secsi.mem secsi file
        // // - comment
        // @aaa - <aaa> stands for sector address
        // dd - <dd> is byte to be written at SecSi(aa++)
        //   (aa is incremented at every load)
        if (UserPreload && !(secsi_file_name == "none"))
        begin
            $readmemh(secsi_file_name,secure_silicon);
        end

        // - Memory  preload
        // s29jl032j.mem memory  file
        // // - comment
        // @aaa - <aaa> stands for sector address
        // dd - <dd> is byte to be written at SecSi(aa++)
        //   (aa is incremented at every load)
        if (UserPreload && !(flash_file_name == "none"))
        begin
            $readmemh(flash_file_name,Mem);
        end

        for (i=0;i<=SecSiSize;i=i+1)
        begin
            SecSi[i] = secure_silicon[i];
        end

        for (i=0;i<=SecNum+2*SubSecNum;i=i+1)
        begin
            if (i> SecNum)
            begin
                if (sector_prot_tmp[i])
                    PPB_SubSec[i-SecNum] = 1;
            end
            else
            begin
                if (sector_prot_tmp[i])
                begin
                    PPB[GroupID(i)] = 1;
                end
            end
        end
        for (i=0;i<=1;i=i+1)
        begin
            WData[i] = 0;
            WAddr[i] = -1;
        end
    end

    //Power Up time 100 ns;
    initial
    begin
        PoweredUp = 1'b0;
        #100 PoweredUp = 1'b1;
    end

    always @(RESETNeg)
    begin
        RST <= #499 RESETNeg;
    end

    always @(BYTENeg)
    begin
        BYTE = BYTENeg;
    end

    initial
    begin
        write    = 1'b0;
        read     = 1'b0;
        Addr   = 0;

        ULBYPASS = 1'b0;
        ESP_ACT  = 1'b0 ;
        OTP_ACT  = 1'b0 ;
        PSP_ACT  = 1'b0 ;

        PDONE    = 1'b1;
        PSTART   = 1'b0;
        PERR     = 1'b0;

        EDONE    = 1'b1;
        ESTART   = 1'b0;
        ESUSP    = 1'b0;
        ERES     = 1'b0;

        EERR     = 1'b0;
        READY_in = 1'b0;
        READY    = 1'b0;

        DYB = 0;
        DYB = 0;// unprotected state
        DYB_SubSec = 0;// unprotected state
        PPBLock = 1'b0;
        PPMLB = 1'b0;
        SPMLB = 1'b0;
        SSPB = 1'b0;
        for(i=0;i<=7;i=i+1)
            Password[i] = MaxData;

        PPB_ers_ccl = 0;

    end

    event bank_erase_event;

    always @(bank_erase_event)
    begin
        #100000 BankErase = BankEraseExec;
    end

    always @(posedge START_T1_in)
    begin:TESTARTT1r
        #tdevice_START START_T1 = START_T1_in;
    end
    always @(negedge START_T1_in)
    begin:TESTARTT1f
        #1 START_T1 = START_T1_in;
    end

    always @(posedge CTMOUT_in)
    begin:TCTMOUTr
        #tdevice_CTMOUT CTMOUT = CTMOUT_in;
    end
    always @(negedge CTMOUT_in)
    begin:TCTMOUTf
        #1 CTMOUT = CTMOUT_in;
    end

    always @(posedge READY_in)
    begin:TREADYr
        #tdevice_READY READY = READY_in;
    end
    always @(negedge READY_in)
    begin:TREADYf
        #1 READY = READY_in;
    end

   // Protection Bit Program
    always @(posedge PBPROG_in)
    begin : ProtProgTime
        #(tdevice_PROTP - 1) PBPROG_out = 1'b1;
    end
    always @(negedge PBPROG_in)
    begin
        disable ProtProgTime;
        PBPROG_out = 1'b0;
    end
    // Protection Bit Erase
    always @(posedge PBERASE_in)
    begin : ProtEraseTime
        #(tdevice_PROTE - 1) PBERASE_out = 1'b1;
    end
    always @(negedge PBERASE_in)
    begin
        disable ProtEraseTime;
        PBERASE_out = 1'b0;
    end
    // Password Unlock
    always @(posedge UNLOCKDONE_in)
    begin : UnlockTime
        #(tdevice_UNLOCK - 1) UNLOCKDONE_out = 1'b1;
    end
    always @(negedge UNLOCKDONE_in)
    begin
        disable UnlockTime;
        UNLOCKDONE_out = 1'b0;
    end
    // Password Program
    always @(posedge PASSPDONE_in)
    begin : PassTime
        #(tdevice_POW - 1) PASSPDONE_out = 1'b1;
    end
    always @(negedge PASSPDONE_in)
    begin
        disable PassTime;
        PASSPDONE_out = 1'b0;
    end

    ////////////////////////////////////////////////////////////////////////////
    ////     obtain 'LAST_EVENT information
    ///////////////////////////////////////////////////////////////////////////
    always @(negedge OENeg)
    begin
        OENeg_event = $time;
    end
    always @(negedge CENeg)
    begin
        CENeg_event = $time;
    end
    always @(negedge BYTENeg)
    begin
        BYTENeg_event = $time;
    end
    always @(A)
    begin
        ADDR_event = $time;
    end
    always @(DIn[15])
    begin
        if (~BYTE)
            ADDR_event = $time;
    end

    always @(posedge OENeg)
    begin
        OENeg_posEvent = $time;
    end
    always @(posedge CENeg)
    begin
        CENeg_posEvent = $time;
    end
    ////////////////////////////////////////////////////////////////////////////
    //// sequential process for reset control and FSM state transition
    ////////////////////////////////////////////////////////////////////////////
    always @(negedge RST)
    begin
        ESP_ACT = 1'b0;
        OTP_ACT = 1'b0;
        ULBYPASS = 1'b0;
        PSP_ACT = 1'b0;
    end

    always @(gOE_n or gCE_n or RESETNeg or RST )
    begin
        //Output Disable Control
        if (gOE_n || gCE_n || (~RESETNeg && ~RST))
            DOut_zd = 16'bZ;
    end

    reg R;
    reg E;
    always @(falling_edge_RESETNeg or PoweredUp or rising_edge_RESETNeg or
            RESETNeg or READY or next_state or RST)
    begin : StateTransition
        if (PoweredUp)
        begin
        //Hardware reset timing control
            if (falling_edge_RESETNeg)
            begin
                E = 1'b0;
                if (~PDONE || ~EDONE)
                begin
                    //if program or erase in progress
                    READY_in = 1'b1;
                    R = 1'b1;
                end
                else
                begin
                    READY_in = 1'b0;
                    R = 1'b0; //prog or erase not in progress
                end
            end
            else if (rising_edge_RESETNeg && RST)
            begin
                READY_in = 1'b0;
                R = 1'b0;
                E = 1'b1;
            end

            if (RESETNeg && (~R || (R && READY)))
            begin
                current_state = next_state;
                READY_in = 1'b0;
                E = 1'b0;
                R = 1'b0;
                reseted = 1'b1;
            end
            else if ((~R && ~RESETNeg && ~RST) ||
            (R && ~RESETNeg && ~RST && ~READY) ||
            (R && RESETNeg && ~RST && ~READY ))
            begin
                //no state transition while RESET# low
                current_state = RESET; //reset start
                reseted       = 1'b0;
            end
        end
        else
        begin
            current_state = RESET; // reset
            reseted = 1'b0;
            E = 1'b0;
            R = 1'b0;
        end
    end

    /////////////////////////////////////////////////////////////////////////
    //Glitch Protection: Inertial Delay does not propagate pulses <5ns
    //////////////////////////////////////////////////////////////////////////
    assign #3 gWE_n = WENeg_ipd;
    assign #3 gCE_n = CENeg_ipd;
    assign #3 gOE_n = OENeg_ipd;

    //latch address on rising edge and data on falling edge  of write
    always @(gWE_n or  gCE_n or  gOE_n )
    begin: write_dc
        if (RESETNeg!=1'b0)
        begin
            if (~gWE_n && ~gCE_n && gOE_n)
                write = 1'b1;
            else
                write = 1'b0;
        end
        if (gWE_n && ~gCE_n && ~gOE_n)
            read = 1'b1;
        else
            read = 1'b0;
    end

    ///////////////////////////////////////////////////////////////////////////
    //Process that reports warning when changes on signals WE#, CE#, OE# are
    //discarded
    ///////////////////////////////////////////////////////////////////////////
    always @(posedge WENeg)
    begin: PulseWatch1
         if ((gWE_n == WENeg)&& (CENeg === 0)) $display("Glitch on WE#");
    end
    always @(posedge CENeg)
    begin: PulseWatch2
        if (gCE_n == CENeg) $display("Glitch on CE#");
    end
    always @(posedge OENeg)
    begin: PulseWatch3
        if ((gOE_n == OENeg)&&(CENeg === 0)) $display("Glitch on OE#");
    end

    ///////////////////////////////////////////////////////////////////////////
    //Latch address on falling edge of WE# or CE# what ever comes later
    //Latches data on rising edge of WE# or CE# what ever comes first
    // also Write cycle decode
    ///////////////////////////////////////////////////////////////////////////
    integer A_tmp  ;
    integer SA_tmp ;
    integer A_tmp1 ;
    integer A_tmp2 ;
    integer BA_tmp;

    reg CE;

    // Address Latch and Bus Cycle Decode
    always @(A_event, DIn_15_event, falling_edge_WENeg, falling_edge_CENeg,
             rising_edge_WENeg, rising_edge_CENeg, falling_edge_OENeg,
             BYTENeg_event, reseted, read, rising_edge_write)
    begin : BusCycleDecode

        if ((reseted == 1) &&
        ((falling_edge_WENeg && ~CENeg && OENeg) ||
        (falling_edge_CENeg &&  WENeg != OENeg ) ||
        (falling_edge_OENeg && WENeg && ~CENeg)  ||
        ((A_event || (DIn_15_event && ~BYTENeg) || BYTENeg_event)
        && WENeg && ~CENeg && ~OENeg)))
        begin
            A_tmp  =  A[14:0];
            A_tmp2  =  A[11:0];
            SA_tmp =  A[HiAddrBit:15];
            BA_tmp =  A[HiAddrBit:18];

            if (~BYTE)
                A_tmp1 = { A[14:0],DIn[15] };
            else
                A_tmp1 = { A[14:0],1'b0};

            Address = A_tmp1;
            Addr   = A_tmp;
            SecAddr = SA_tmp;
            SubAddr<=A_tmp2;
        end
        else if(reseted && (rising_edge_WENeg || rising_edge_CENeg) && write)
        begin
            D_tmp0 = DIn[7 : 0];
            if (BYTENeg)
                D_tmp1 = DIn[15 :8];
        end
        if (reseted && (rising_edge_write || falling_edge_OENeg) ||
        falling_edge_CENeg || ((A_event || (DIn_15_event && ~BYTENeg) ||
        BYTENeg_event) && WENeg && ~CENeg && ~OENeg))
        begin
            SecAddr = SA_tmp;
            Address = A_tmp1;
            SubAddr = A_tmp2;
            for(i=0;i<=SubSecNum;i=i+1)
            begin
                if ( A_tmp >= sssa(i) && A_tmp <= ssea(i) )
                begin
                    SubSect = i;
                end
            end
            case (BA_tmp)
                0,1,2,3: BA = 0;
                4,5,6,7: BA = 1;
            endcase

            CE = CENeg;
            Addr   = A_tmp;
        end
    end

/////////////////////////////////////////////////////////////////////////////
//// Timing control for the Program/ Write Buffer Program Operations
//// start/ suspend/ resume
/////////////////////////////////////////////////////////////////////////////
    integer cnt_write = 0;
    time elapsed_write  ;
    time duration_write ;
    time start_write    ;
    event pdone_event;

    always @(posedge reseted)
    begin
        PDONE = 1'b1;
    end

    always @(OTP_ACT, rising_edge_PSTART, BYTENeg, ESP_ACT, rising_edge_reseted,
    rising_edge_PSUSP, rising_edge_PRES)
    begin : ProgTime
        if (rising_edge_reseted)
        begin
            #1 PDONE = 1;  // reset done, programing terminated
            disable pdone_process;
        end
        else if (reseted)
        begin
            if (rising_edge_PSTART && PDONE)
            begin
                if ((((SA != VarSect  && (~DYB[SA] && ~PPB[GroupID(SA)]) &&
                (~Ers_Queue[SA] || ~ESP_ACT)) ||
                (SA == VarSect && ~SubSec_Prot[SSA] &&
                (~DYB_SubSec[SSA] && ~PPB_SubSec[SSA]) &&
                (~Ers_Sub_Queue[SSA] || ~ESP_ACT))) &&
                (~OTP_ACT)) || (OTP_ACT && SecAddr == 0 && ~SSPB
                && (Address > 127) && (Address < 256)))
                begin
                    if(ULBYPASS)
                        duration_write = tdevice_POU;
                    else
                    begin
                        if (BYTENeg)
                            duration_write = tdevice_POW;
                        else
                            duration_write = tdevice_POB;
                    end
                    elapsed_write = 0;
                    PDONE = 1'b0;
                    ->pdone_event;
                    start_write = $time;
                end
                else
                begin
                    PERR = 1'b1;
                    PERR <= #1000 1'b0;
                end
            end
            else if (rising_edge_PSUSP && ~PDONE)
            begin
                elapsed_write = $time - start_write;
                duration_write = duration_write - elapsed_write;
                PDONE = 0;
                disable pdone_process;

            end
            else if (rising_edge_PRES && ~PDONE)
            begin
                start_write = $time;
                PDONE = 0;
                -> pdone_event;

            end
        end
    end

    always @(pdone_event)
    begin:pdone_process
        #duration_write PDONE = 1'b1;
    end

/////////////////////////////////////////////////////////////////////////////
//// Timing control for the Erase Operations
/////////////////////////////////////////////////////////////////////////////
    integer cnt_erase = 0;      // 0 - SecNum+2*SubSecNum
    time elapsed_erase;
    time duration_erase;
    time start_erase;
    event edone_event;

    always @(rising_edge_ESTART, rising_edge_ESUSP, rising_edge_ERES,
    Ers_Queue, Ers_Sub_Queue, rising_edge_reseted)
    begin : ErsTime
        if (rising_edge_reseted)
        begin
            disable edone_process;
            EDONE = 1'b1;  // reset done, ERASE terminated
        end
        else if (reseted)
        begin
            if (rising_edge_ESTART && EDONE)
            begin
                cnt_erase = 0;
                for (i=0;i<=SecNum;i=i+1)
                begin
                    if (i == VarSect)
                    begin
                        for(j=0;j<=SubSecNum;j=j+1)
                        begin
                            if((Ers_Sub_Queue[j]==1'b1)&&(~SubSec_Prot[j])
                            &&(~DYB_SubSec[j]&&(~PPB_SubSec[j])))
                                cnt_erase = cnt_erase + 1;
                        end
                    end
                    else if (Ers_Queue[i] && (~DYB[i] && ~PPB[GroupID(i)]))
                        cnt_erase = cnt_erase +1;
                end
                if (cnt_erase > 0)
                begin
                    duration_erase = cnt_erase * tdevice_SEO;
                    start_erase = $time;
                    EDONE = 1'b0;
                    -> edone_event;
                    elapsed_erase = 0;
                end
                else
                begin
                    EERR = 1'b1;
                    EERR <= #100000  1'b0;
                end
            end
            else if (rising_edge_ESUSP && ~EDONE)
            begin
                disable edone_process;
                elapsed_erase = $time - start_erase;
                duration_erase = duration_erase - elapsed_erase;
                EDONE = 1'b0;
            end
            else if (rising_edge_ERES && ~EDONE)
            begin
                start_erase = $time;
                EDONE = 1'b0;
                ->edone_event;

            end
        end
    end

   always @(edone_event)
    begin : edone_process
        EDONE = 1'b0;
        #duration_erase EDONE = 1'b1;
    end

    //////////////////////////////////////////////////////////////////////////
    // Main Behavior Process
    // combinational process for next state generation
    //////////////////////////////////////////////////////////////////////////
    reg PATTERN_1  = 1'b0;
    reg PATTERN_2  = 1'b0;
    reg A_PAT_1  = 1'b0;

    //DATA  High Byte
    integer DataHi   ;
    //DATA Low Byte
    integer DataLo   ;

    always @(falling_edge_write or Addr or D_tmp0
            or rising_edge_PDONE or rising_edge_EDONE or CTMOUT
            or BankAutosel or BankBypassLock or SecAddr or START_T1 or reseted
            or READY or falling_edge_PERR or falling_edge_EERR
            or rising_edge_UNLOCKDONE_out)
    begin: StateGen
        if (falling_edge_write)
        begin
            DataLo = DIn[7:0];
            if (BYTE)
                DataHi = DIn[15:8];
            PATTERN_1 = (Addr==16'h555) && (DataLo==8'hAA) ;
            PATTERN_2 = (Addr==16'h2AA) && (DataLo==8'h55) ;
            A_PAT_1   = ((Addr==16'h555) && ~ULBYPASS) || ULBYPASS;
        end
        if (reseted!=1'b1)
        begin
            next_state = current_state;
        end
        else
        case (current_state)
            RESET :
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_1)
                        next_state = Z001;
                    else if ((Addr==8'h55) && (DataLo==8'h98))
                        next_state = CFI;
                    else
                        next_state = RESET;
                end
            end

            Z001 :
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_2)
                        next_state = PREL_SETBWB;
                    else
                        next_state = RESET;
                end
            end

            PREL_SETBWB:
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && (DataLo==8'hA0))
                        next_state = A0SEEN;
                    else if (A_PAT_1 && (DataLo==8'h20))
                        next_state = PREL_ULBYPASS;
                    else if (A_PAT_1 && (DataLo==8'h90))
                        next_state = AS;
                    else if (A_PAT_1 && (DataLo==8'h80))
                        next_state = C8;
                    else if (A_PAT_1 && (DataLo==8'h88))
                        next_state = OTP;
                    else if (A_PAT_1 && (DataLo == 8'h38) && ~PPMLB)
                        next_state = PASSPROG_PREL;
                    else if (A_PAT_1 && (DataLo == 8'hC8))
                        next_state = PASSVERIFY;
                    else if (A_PAT_1 && (DataLo == 8'h28))
                        next_state = PASSUNLOCK0;
                    else if (A_PAT_1 && (DataLo == 8'h60))
                        next_state = PROTBIT_PREL;
                    else if (A_PAT_1 && (DataLo == 8'h78))
                        next_state = RESET;
                    else if (A_PAT_1 && (DataLo == 8'h58))
                        next_state = PPBDYB;
                    else if (A_PAT_1 && (DataLo == 8'h48))
                        next_state = DYBWE;
                    else
                        next_state = RESET;
                end
            end

            PREL_ULBYPASS:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo==8'h90)
                        next_state = PREL_ULBYPASS_RESET;
                    else if (A_PAT_1 && (DataLo==8'hA0))
                        next_state = A0SEEN;
                    else if (DataLo == 8'h98)
                        next_state <= UBP_CFI;
                    else if (DataLo == 8'h80)
                        next_state <= C8_PREL;
                    else
                        next_state = PREL_ULBYPASS;
                end
            end

            PREL_ULBYPASS_RESET:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo==8'h00)
                        next_state = RESET;
                    else
                        next_state = PREL_ULBYPASS;
                end
            end

            AS :
            begin
                if (falling_edge_write)
                begin
                    if (DataLo==16'hF0)
                        next_state = RESET;
                    else
                        if ((Addr== 16'h55) && (DataLo == 16'h98))
                            next_state = AS_CFI;
                        else
                            next_state = AS;
                end
            end

            CFI:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo==8'hF0)
                        next_state = RESET;
                    else
                        next_state <= CFI;
                end
            end

            A0SEEN:
            begin
                if (falling_edge_write)
                begin
                    if ((BankBypassLock[BA] && ULBYPASS) || ~ULBYPASS )
                        next_state = PGMS;
                    else
                        next_state = PREL_ULBYPASS;
                end
                else
                    next_state = A0SEEN;
            end

            OTP :
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_1)
                        next_state = OTP_Z001;
                    else
                        next_state = OTP;
                end
            end

            OTP_Z001 :
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_2)
                        next_state = OTP_PREL;
                    else
                        next_state = OTP;
                end
            end

            OTP_PREL :
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && (DataLo == 16'h90))
                        next_state = OTP_EXIT;
                    else if (A_PAT_1 && (DataLo == 16'hA0) && ~PSP_ACT
                    && ~ESP_ACT)
                        next_state = OTP_A0SEEN;
                    else
                        next_state = OTP;
                end
            end

            OTP_EXIT:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'h00)
                        if (PSP_ACT)
                            next_state = PSP;
                        else if (ESP_ACT)
                             next_state = ESP;
                        else
                            next_state = RESET;
                    else
                        next_state = OTP;
                end
            end

            OTP_A0SEEN :
            begin
                if (falling_edge_write)
                   next_state = PGMS;
                else
                   next_state = OTP_A0SEEN;
            end

            C8:
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_1)
                        next_state = C8_Z001;
                    else
                        next_state = RESET;
                end
            end

            C8_Z001:
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_2)
                        next_state = C8_PREL;
                    else
                        next_state = RESET;
                end
            end

            C8_PREL:
            begin
                if (falling_edge_write)
                begin
                    if ((A_PAT_1 || ULBYPASS) && DataLo==8'h10)
                        next_state = ERS;
                    else if(DataLo==8'h30)
                        next_state = SERS;
                    else
                        next_state = RESET;
                end
            end

            SERS:
            begin
                if (CTMOUT)
                    next_state = SERS_EXEC;
                else if (falling_edge_write)
                begin
                    if (DataLo == 8'hB0)
                        if (BankErase[BA])
                            next_state = ESP; // ESP according to datasheet
                        else
                            next_state = SERS;
                    else if (DataLo==8'h30)
                        next_state = SERS;
                    else
                        next_state = RESET;
                end
            end

            ESP:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 8'h30  && (BankErase[BA]))
                        next_state = SERS_EXEC;
                    else
                        if (Addr == 8'h55 && DataLo == 8'h98)
                            next_state = ESP_CFI;
                        else if (PATTERN_1)
                            next_state = ESP_Z001;
                end
            end

            ESP_ULBYPASS:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 8'hA0)
                        next_state = ESP_A0SEEN;
                    else if (DataLo == 8'h90)
                        next_state = ESP_ULBYPASS_RESET;
                end
            end

            ESP_ULBYPASS_RESET:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 8'h00)
                        next_state = ESP;
                    else
                        next_state = ESP_ULBYPASS;
                end
            end

            ESP_Z001:
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_2)
                        next_state = ESP_SETBWB;
                    else
                        next_state = ESP;
                end
            end

            ESP_SETBWB:
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && (DataLo==8'h90))
                        next_state = ESP_AS;
                    else if(A_PAT_1 && DataLo == 8'hA0)
                        next_state = ESP_A0SEEN;
                    else if(A_PAT_1 && DataLo == 8'h20)
                        next_state = ESP_ULBYPASS;
                    else if(A_PAT_1 && DataLo == 8'h88)
                        next_state = OTP;
                    else
                        next_state = ESP;
                end
            end

            ESP_A0SEEN:
            begin
                if (falling_edge_write)
                begin
                    if (((BankBypassLock[BA]) && (ULBYPASS))
                    || (~ULBYPASS))
                        next_state = PGMS;
                    else
                        next_state = ESP_ULBYPASS;
                end
            end

            PGMS:
            begin
                if (rising_edge_PDONE || falling_edge_PERR)
                begin
                    if (ESP_ACT)
                    begin
                        if (ULBYPASS)
                            next_state = ESP_ULBYPASS;
                        else
                            next_state = ESP;
                    end
                    else if (ULBYPASS)
                        next_state = PREL_ULBYPASS;
                    else if (OTP_ACT)
                        next_state = OTP;
                    else
                        next_state = RESET;
                end
                else if (falling_edge_write && PERR != 1)
                    if (DataLo == 16'hB0 && BankProg[BA] == 1)
                        next_state = PSPS;
            end

            UBP_CFI:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                    next_state = PREL_ULBYPASS;
            end

            AS_CFI:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo== 16'hF0)
                        next_state = AS;
                    else
                        next_state = AS_CFI;
                end
            end

            ERS:
            begin
                if (rising_edge_EDONE || falling_edge_EERR)
                begin
                    if (ULBYPASS)
                        next_state = PREL_ULBYPASS;
                    else
                        next_state = RESET;
                end
            end

            ESPS:
            begin
                if (START_T1)
                    next_state = ESP;
            end

            SERS_EXEC:
            begin
                if (rising_edge_EDONE || falling_edge_EERR)
                    next_state = RESET;
                else if (EERR != 1)
                begin
                    if (falling_edge_write)
                    begin
                        if (DataLo==16'hB0 && BankErase[BA] == 1)
                            next_state = ESPS;
                    end
                end
            end

            ESP_CFI:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        next_state = ESP;
                    else
                        next_state = ESP_CFI;
                end
            end

            ESP_AS:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        // resret ULBYPASS
                        next_state = ESP;
                    else if ((Addr==16'h55) && (DataLo==16'h98))
                        next_state = ESP_AS_CFI;
                end
            end

            ESP_AS_CFI:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        next_state = ESP_AS;
                    else
                        next_state = ESP_AS_CFI;
                end
            end

            PSPS:
            begin
                if (START_T1)
                    next_state = PSP;
            end

            PSP:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'h30 && BankProg[BA] == 1)
                        next_state = PGMS;
                    else if (Addr == 16'h55 && DataLo == 16'h98)
                        next_state = PSP_CFI;
                    else if (PATTERN_1)
                        next_state = PSP_Z001;
                end
            end

            PSP_CFI:
            begin
                if (falling_edge_write)
                begin
                    if (Addr == 16'h55 && DataLo == 16'h98)
                    begin
                    end
                    else if (DataLo == 16'hF0)
                        next_state = PSP;
                end
            end

            PSP_Z001:
            begin
                if (falling_edge_write)
                begin
                    if (PATTERN_2)
                        next_state = PSP_PREL;
                    else
                        next_state = PSP;
                end
            end

            PSP_PREL:
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && DataLo == 16'h90)
                        next_state = PSP_AS;
                    else if (A_PAT_1 && DataLo == 16'h88)
                        next_state = OTP;//set PS
                    else if (A_PAT_1 && DataLo == 16'h58)
                        next_state = PPBDYB;
                    else
                        next_state = PSP;
                end
            end

            PSP_AS:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        // reset ULBYPASS
                        next_state = PSP;
                    else if ((Addr==16'h55) && (DataLo==16'h98))
                        next_state = PSP_AS_CFI;
                end
            end

            PSP_AS_CFI:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        next_state = PSP_AS;
                    else
                        next_state = PSP_AS_CFI;
                end
            end

            PASSPROG_PREL:
            begin
                if (falling_edge_write)
                    next_state = PASSPROG;
            end

            PASSPROG:
            begin
                if (falling_edge_write && PASSPDONE_out && DataLo == 16'hF0)
                    next_state = RESET;
            end

            PASSVERIFY:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                    next_state = RESET;
            end

            PASSUNLOCK0:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK1;
            end

            PASSUNLOCK1:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK2;
            end

            PASSUNLOCK2:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK3;
            end

            PASSUNLOCK3:
            begin
                if (rising_edge_UNLOCKDONE_out)
                begin
                    if (BYTENeg == 1)
                        next_state = RESET;
                    else
                        next_state = PASSUNLOCK4;
                end
            end

            PASSUNLOCK4:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK5;
            end

            PASSUNLOCK5:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK6;
            end

            PASSUNLOCK6:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = PASSUNLOCK7;
            end

            PASSUNLOCK7:
            begin
                if (rising_edge_UNLOCKDONE_out)
                    next_state = RESET;
            end

            PROTBIT_PREL:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'h68 && (Addr % 16'h100 == WP))
                        next_state = PPB_PROGRAM;
                    else if (DataLo == 16'h60 && (Addr % 16'h100 == WP))
                        next_state = PPB_ERASE;
                    else if (DataLo == 16'h68 && (Addr % 16'h100 == PL))
                        next_state = PPMLB_PROGRAM;
                    else if (DataLo == 16'h68 && (Addr % 16'h100 == SL))
                        next_state = SPMLB_PROGRAM;
                    else if (DataLo == 16'h68 && (Addr % 16'h100 == OW))
                        next_state = SSPB_PROGRAM;
                    else if (DataLo == 16'h48 && (Addr % 16'h100 == PL))
                        next_state = PPMLB_VERIFY;
                    else if (DataLo == 16'h48 && (Addr % 16'h100 == SL))
                        next_state = SPMLB_VERIFY;
                    else if (DataLo == 16'h48 && (Addr % 16'h100 == OW))
                        next_state = SSPB_VERIFY;
                    else
                        next_state = RESET;
                end
            end

            PPBDYB:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                begin
                    if (PSP_ACT)
                        next_state = PSP;
                    else
                        next_state = RESET;
                end
            end

            DYBWE:
            begin
                if (falling_edge_write)
                    next_state = RESET;
            end

            PPB_PROGRAM:
            begin
                if (falling_edge_write && PBPROG_out == 1 && DataLo == 16'h48
                && (Addr % 16'h100 == WP))
                    next_state = PPB_VERIFY;
            end

            PPB_VERIFY:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                        next_state = RESET;
                end
            end

            PPB_ERASE:
            begin
                if (falling_edge_write && PBERASE_out == 1 && DataLo == 16'h40
                && (Addr % 16'h100 == WP))
                    next_state = PPB_VERIFY;
            end

            PPMLB_PROGRAM:
            begin
                if (falling_edge_write && PBPROG_out == 1 && DataLo == 16'h48
                && (Addr % 16'h100 == PL))
                    next_state = PPMLB_VERIFY;
            end

            SPMLB_PROGRAM:
            begin
                if (falling_edge_write && PBPROG_out == 1 && DataLo == 16'h48
                && (Addr % 16'h100 == SL))
                    next_state = SPMLB_VERIFY;
            end

            SSPB_PROGRAM:
            begin
                if (falling_edge_write && PBPROG_out == 1 && DataLo == 16'h48
                && (Addr % 16'h100 == OW))
                    next_state = SSPB_VERIFY;
            end

            PPMLB_VERIFY:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                    next_state = RESET;
            end

            SPMLB_VERIFY:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                    next_state = RESET;
            end

            SSPB_VERIFY:
            begin
                if (falling_edge_write && DataLo == 16'hF0)
                    next_state = RESET;
            end
        endcase
    end

    ///////////////////////////////////////////////////////////////////////////
    //FSM Output generation and general funcionality
    ///////////////////////////////////////////////////////////////////////////

    always @(falling_edge_write or rising_edge_read or D_tmp0 or D_tmp1
            or Address_event  or Addr or SecAddr_event or PDONE or EDONE
            or START_T1 or falling_edge_RST or reseted or CTMOUT
            or BYTENeg or READY  or gOE_n or current_state_event
            or rising_edge_PASSPDONE_out or rising_edge_UNLOCKDONE_out
            or rising_edge_PBPROG_out or rising_edge_PBERASE_out)
    begin:Functional
        if (falling_edge_write)
        begin
            DataLo    = D_tmp0;
            DataHi    = D_tmp1;
            PATTERN_1 = (Addr==16'h555) && (DataLo==8'hAA) ;
            PATTERN_2 = (Addr==16'h2AA) && (DataLo==8'h55) ;
            A_PAT_1   = (((Addr==16'h555) && ~ULBYPASS) || ULBYPASS);
        end

        if (falling_edge_RST && RESETNeg == 0)
        begin
            if (PPMLB)
                PPBLock = 1;
            else
                PPBLock = 0;

            Ers_Queue = 64'd0;
            Ers_Sub_Queue = 8'b00000000;
            DYB = 64'd0;
            DYB_SubSec = 8'd00000000;
            START_T1_in = 0;
        end

        oe = (rising_edge_read || (read && (Address_event || SecAddr_event)));
        if (reseted)
        begin
        case (current_state)
            RESET :
            begin
                ESP_ACT       = 1'b0;
                PSP_ACT       = 1'b0;
                OTP_ACT       = 1'b0;
                ULBYPASS      = 1'b0;
                CTMOUT_in     = 1'b0;
                BankErase     = 2'b00;
                BankEraseExec = 2'b00;
                BankBypassLock= 2'b00;
                BankAutosel   = 2'b00;
                BankProg      = 2'b00;
                Ers_Queue     = 64'd0;
                Ers_Sub_Queue = 8'b00000000;

                if (oe)
                    MemRead(DOut_zd);

                RY_zd = 1'b1;
            end

            Z001 :
            begin
            end

            AS, ESP_AS, PSP_AS:
            begin
                if (falling_edge_write)
                begin
                    if (DataLo == 16'hF0)
                    begin
                        OTP_ACT = 1'b0;
                        if (ESP_ACT || PSP_ACT)
                            ULBYPASS  = 1'b0;
                    end
                end
                else if (oe)
                begin
                    if (BankAutosel[BA] == 1)
                    begin
                        ASAddr = Addr % 16'd256;
                        if (BYTENeg && (ASAddr == 0 || ASAddr == 2
                        || ASAddr == 3))
                            DOut_zd[15:8] = 0;
                        else if (BYTENeg && (ASAddr == 1))
                            DOut_zd[15:8] = 8'h22;
                        else
                            DOut_zd[15:8] = 8'bz;

                        if (ASAddr == 0)
                            DOut_zd[7:0] = 1;
                        else if (ASAddr == 1)
                        begin
                            if (tmp_char == "1")
                                DOut_zd[7:0] = 8'h5C;
                            else
                                DOut_zd[7:0] = 8'h5F;
                        end
                        else if (ASAddr == 2)
                        begin
                            DOut_zd[7:1] = 7'b0;
                            if (SecAddr == VarSect )
                                DOut_zd[0] = PPB_SubSec[SubSect];
                            else
                                DOut_zd[0] = PPB[GroupID(SecAddr)];
                        end
                        else if (ASAddr == 3)
                        begin
                            if (~SSPB)
                                DOut_zd[7:0] =8'h80;
                            else
                                DOut_zd[7:0] =8'hC0;
                        end
                        else DOut_zd[7:0] = 8'bz;
                    end
                    else
                    begin
                        if ((ESP_ACT) &&
                        ((SecAddr != VarSect && Ers_Queue[SecAddr] == 1)
                        || (SecAddr == VarSect && Ers_Sub_Queue[SubSect] == 1)))
                        begin
                            //////////////////////////////////////
                            ///read status
                            ///////////////////////////////////////
                            Status[7] = 1;
                            // Status[6] No toggle
                            Status[5] = 0;
                            Status[2] = ~ Status[2]; //toggle
                            DOut_zd = Status;
                        end
                        else if (PSP_ACT && (((SecAddr == VarSect)
                        && (SecAddr == SA) && (SubSect == SSA))
                        || ((SecAddr != VarSect) && (SecAddr == SA))))
                        begin
                            //read program suspended sector
                            //Invalid (not allowed)
                            $display("Read from program suspended");
                            $display( "sector NOT allowed");
                        end
                        else
                            MemRead(DOut_zd);
                    end
                end
            end

            CFI, CFI, AS_CFI, ESP_CFI, ESP_AS_CFI, PSP_CFI, PSP_AS_CFI, UBP_CFI:
            begin
                if (oe)
                begin
                    if ((Addr >= 16'h10 && Addr <= 16'h3C) ||
                    (Addr >= 16'h40 && Addr <= 16'h50) ||
                    (Addr >= 16'h57 && Addr <= 16'h5B))
                    begin
                        DOut_zd[15:0] = CFI_array[Addr];
                        if (~BYTENeg)
                            DOut_zd[15:8] = 8'bZ;
                        if (~BYTENeg && !((Address % 2) == 0))
                            DOut_zd[7:0] = 8'bZ;
                    end
                    else
                    begin
                        DOut_zd[15:0] = 16'bZ;
                        $display ("Invalid CFI query address");
                    end
                end
            end

            OTP :
            begin
                if (oe)
                begin
                    //read SecSi Sector Region
                    SecSiAddr = Address%(SecSiSize +1);
                    if (SecSi[SecSiAddr]==-1)
                        DOut_zd[7:0] = 8'bx;
                    else
                        DOut_zd[7:0] = SecSi[SecSiAddr];

                    if (BYTENeg)
                        if (SecSi[SecSiAddr+1]==-1)
                            DOut_zd[15:8]= 8'bx;
                        else
                            DOut_zd[15:8] = SecSi[SecSiAddr+1];
                end
            //ready signal active
            RY_zd = 1'b1;
            end

            ERS :
            begin
                if (oe)
                begin
                    ///////////////////////////////////////////////////////////
                    // read status / embeded erase algorithm - Chip Erase
                    ///////////////////////////////////////////////////////////
                    Status[7] = 1'b0;
                    Status[6] = ~Status[6]; //toggle
                    Status[5] = 1'b0;
                    Status[3] = 1'b1;
                    Status[2] = ~Status[2]; //toggle

                    DOut_zd = Status;
                end
                if (EERR!=1'b1)
                    if (~ER_FLAG)
                    begin
                        ER_FLAG = 1;
                        for (i=0;i<=SecNum;i=i+1)
                        begin
                            if ( i == VarSect)
                            begin
                                for( j=0;j<=SubSecNum;j=j+1)
                                    if ( SubSec_Prot[j]!=1'b1
                                    && DYB_SubSec[j] == 1'b0
                                    && PPB_SubSec[j] == 1'b0)
                                        for(k=2*sssa(j);k<=2*ssea(j)+1;k=k+1)
                                            Mem[sa(i)+k] = -1;
                            end
                            else
                            begin
                                if (DYB[i] == 1'b0 && PPB[GroupID(i)] == 1'b0)
                                   for (j=0;j<=SecSize;j=j+1)
                                        Mem[sa(i)+j] = -1;
                            end
                        end
                    end

                    if (EDONE)
                    begin
                        ER_FLAG = 0;
                        for (i=0;i<=SecNum;i=i+1)
                        begin
                            if ( i == VarSect)
                            begin
                                for( j=0;j<=SubSecNum;j=j+1)
                                    if ( SubSec_Prot[j]!=1'b1
                                    && DYB_SubSec[j] == 1'b0
                                    && PPB_SubSec[j] == 1'b0)
                                        for(k=2*sssa(j);k<=2*ssea(j)+1;k=k+1)
                                            Mem[sa(i)+k] = MaxData;
                            end
                            else
                            begin
                                if (DYB[i] == 1'b0 && PPB[GroupID(i)] == 1'b0)
                                    for (j=0;j<=SecSize;j=j+1)
                                        Mem[sa(i)+j] = MaxData;
                            end
                        end
                        Ers_Queue     = 64'd0;
                        Ers_Sub_Queue = 8'b00000000;
                    end
                //busy signal active
                RY_zd = 1'b0;
            end

            SERS :
            begin
                if (CTMOUT)
                begin
                    CTMOUT_in = 1'b0;
                    START_T1_in = 1'b0;
                    ESUSP  = 1'b0;
                    ERES   = 1'b0;
                    ESTART = 1'b1;
                    ESTART = #1 1'b0;
                    for(i=0;i<=BankNum;i=i+1)
                    begin
                        if ((BankEraseExec[i]==0 && BankErase[i] == 1))
                        begin
                            ->bank_erase_event ;
                        end
                    end
                end
                else if (falling_edge_write)
                begin
                    if (DataLo == 16'hB0)
                    begin
                    //need to start erase process prior to suspend
                        if (BankErase[BA])
                        begin
                            CTMOUT_in = 1'b0;
                            ERES      = 1'b0;
                            ESTART    = 1'b1;
                            ESTART    = #1 1'b0;
                            ESUSP     = 1'b1;
                            ESUSP     = #1 1'b0;
                        end
                    end
                    else if (DataLo==16'h30)
                    begin
                        disable TCTMOUTr;
                        CTMOUT_in = 1'b0;
                        #1 CTMOUT_in <= 1'b1;
                        if (SecAddr == VarSect)
                            Ers_Sub_Queue[SubSect] = 1'b1;
                        else
                            Ers_Queue[SecAddr] = 1'b1;
                        BankErase[BA] = 1'b1;
                        if ((SecAddr != VarSect) && DYB[SecAddr]  == 1'b0
                        && PPB[GroupID(SecAddr)] == 1'b0)
                            BankEraseExec[BA] = 1'b1;
                        else if ((SecAddr == VarSect)&&
                        SubSec_Prot[SubSect] == 1'b0
                        && DYB_SubSec[SubSect] == 1'b0
                        && PPB_SubSec[SubSect] == 1'b0)
                            BankEraseExec[BA] = 1'b1;
                    end
                    else
                    begin
                        CTMOUT_in = 1'b0;
                    end
                end
                else if (oe)
                begin
                    if (BankErase[BA])
                    begin
                        ////////////////////////////////////////////////////////
                        //read status - sector erase timeout
                        ////////////////////////////////////////////////////////
                        Status[7] = 1'b1;
                        Status[3] = 1'b0;

                        DOut_zd = Status;
                    end
                    else
                        MemRead(DOut_zd);
                end
                //ready signal active
                RY_zd = 1'b0;
            end

            ESPS :
            begin
                if (START_T1)
                begin
                    ESP_ACT = 1;
                    START_T1_in = 0;
                end
                else if (oe)
                begin
                    if (BankErase[BA])
                    begin
                        ////////////////////////////////////////////////////////
                        //read status / erase suspend timeout - stil erasing
                        ////////////////////////////////////////////////////////
                        if (((SecAddr == VarSect)
                        && (Ers_Sub_Queue[SubSect] == 1'b1))
                        || ((SecAddr != VarSect)
                        && (Ers_Queue[SecAddr]==1'b1)))
                        begin
                            Status[7] = 1'b0;
                            Status[2] = ~Status[2]; //toggle
                        end
                        else
                            Status[7] = 1'b1;
                        Status[6] = ~Status[6]; //toggle
                        Status[5] = 1'b0;
                        Status[3] = 1'b1;
                        DOut_zd = Status;
                    end
                    else
                        MemRead(DOut_zd);

                end
                //busy signal active
                RY_zd = 1'b0;
            end

            SERS_EXEC:
            begin
                if (oe)
                begin
                    if (BankErase[BA])
                    begin
                        ///////////////////////////////////////////////////
                        //read status erase
                        ///////////////////////////////////////////////////
                        if(((SecAddr==VarSect)&&(Ers_Sub_Queue[SubSect]== 1'b1))
                        || ((SecAddr != VarSect)&&(Ers_Queue[SecAddr]==1'b1)))
                        begin
                            Status[7] = 1'b0;
                            Status[2] = ~Status[2]; //toggle
                        end
                        else
                            Status[7] = 1'b1;
                        Status[6] = ~Status[6]; //toggle
                        Status[5] = 1'b0;
                        Status[3] = 1'b1;
                        DOut_zd = Status;
                    end
                    else
                        MemRead(DOut_zd);
                end

                if (EERR!=1'b1)
                begin
                    if (~ER_FLAG)
                    begin
                        ER_FLAG = 1;
                        for (i=0;i<=SecNum;i=i+1)
                        begin
                            if ( i == VarSect)
                            begin
                                for( j=0;j<=SubSecNum;j=j+1)
                                begin
                                    if (SubSec_Prot[j]!=1'b1
                                    && DYB_SubSec[j] == 1'b0
                                    && PPB_SubSec[j] == 1'b0
                                    && Ers_Sub_Queue[j]==1'b1)
                                        for(k=2*sssa(j);k<=2*ssea(j)+1;k=k+1)
                                            Mem[sa(i)+k] = -1;
                                end
                            end
                            else
                            begin
                                if (Ers_Queue[i] && (DYB[i] == 1'b0
                                && PPB[GroupID(i)] == 1'b0))
                                    for (j=0;j<=SecSize;j=j+1)
                                        Mem[sa(i)+j] = -1;
                            end
                        end
                    end

                    if (EDONE)
                    begin
                        ER_FLAG = 0;
                        for (i=0;i<=SecNum;i=i+1)
                        begin
                            if (i == VarSect)
                            begin
                                for( j=0;j<=SubSecNum;j=j+1)
                                begin
                                    if (SubSec_Prot[j]!=1'b1
                                    && Ers_Sub_Queue[j] && DYB_SubSec[j] == 1'b0
                                    && PPB_SubSec[j] == 1'b0)
                                        for(k=2*sssa(j);k<=2*ssea(j)+1;k=k+1)
                                            Mem[sa(i)+k] = MaxData;
                                end
                            end
                            else if (Ers_Queue[i] && DYB[i] == 1'b0
                            && PPB[GroupID(i)] == 1'b0)
                                    for (j=0;j<=SecSize;j=j+1)
                                        Mem[sa(i)+j] = MaxData;

                        end
                        Ers_Queue = 64'd0;
                        Ers_Sub_Queue = 8'b00000000;
                    end
                    else if (falling_edge_write)
                    begin
                        if (DataLo == 16'hB0 && BankErase[BA])
                        begin
                            START_T1_in = 1;
                            ESUSP     = 1'b1;
                            ESUSP     = #1 1'b0;
                        end
                    end
                end

                //busy signal active
                RY_zd = 1'b0;
            end

            ESP :
            begin
                ESP_ACT = 1;
                BankProg = 2'b0;
                if (falling_edge_write)
                begin
                    if (DataLo == 16'h30 && BankErase[BA])
                    begin
                        //resume erase
                        ERES = 1'b1;
                        ERES = #1 1'b0;
                        ESP_ACT = 0;
                    end
                end
                if (oe)
                begin
                ///////////////////////////////////////////////////////////
                //read
                ///////////////////////////////////////////////////////////
                    if   (( SecAddr != VarSect  &&  Ers_Queue[SecAddr]!=1'b1)
                    ||( SecAddr == VarSect && Ers_Sub_Queue[SubSect]!=1'b1))
                    begin
                        MemRead(DOut_zd);
                    end
                    else
                    begin
                        ///////////////////////////////////////////////////////
                        //read status
                        ///////////////////////////////////////////////////////
                        Status[7] = 1'b1;
                        // Status[6) No toggle
                        Status[5] = 1'b0;
                        Status[2] = ~Status[2]; //toggle
                        DOut_zd = Status;
                    end
                end
                //ready signal active
                RY_zd = 1'b1;
            end

            PREL_ULBYPASS:
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && DataLo == 16'h90)
                        ULBYPASS = 0;
                end
                else if (oe)
                begin
                    if (BankBypassLock[BA]== 0)
                    begin
                        MemRead(DOut_zd);
                    end
                end
                //ready signal active
                RY_zd = 1'b1;
            end

            ESP_ULBYPASS :
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && DataLo == 16'h90)
                        ULBYPASS = 0;
                end
                else if (oe)
                begin
                    if (BankBypassLock[BA]== 0)
                    begin
                        if (( SecAddr != VarSect  &&  Ers_Queue[SecAddr]!=1'b1)
                        ||( SecAddr == VarSect && Ers_Sub_Queue[SubSect]!=1'b1))
                        begin
                            MemRead(DOut_zd);
                        end
                        else
                        begin
                            ////////////////////////////////////////////////////
                            //read status
                            ////////////////////////////////////////////////////
                            Status[7] = 1'b1;
                            // Status[6) No toggle
                            Status[5] = 1'b0;
                            Status[2] = ~Status[2]; //toggle
                            DOut_zd = Status;
                        end
                    end
                end
                //ready signal active
                RY_zd = 1'b1;
            end

            PGMS :
            begin
                if (oe)
                begin
                    if  (ESP_ACT == 0)
                    begin
                        if (BankProg[BA] == 1)
                        begin
                            //////////////////////////////////////////////////
                            //read status
                            //////////////////////////////////////////////////
                            Status[6] = ~Status[6]; //toggle
                            Status[5] = 1'b0;
                            //Status[2) no toggle
                            Status[1] = 1'b0;
                            DOut_zd = Status;

                            if (((SecAddr == VarSect)&&(SubSect == SSA)&&
                            (SecAddr == SA))
                            || ((SecAddr != VarSect && (SecAddr == SA))))
                                DOut_zd[7] = Status[7];
                            else
                                DOut_zd[7] = ~Status[7];

                            if(BYTE==0)
                                DOut_zd[15:8] = 8'bz;
                        end
                        else
                            MemRead(DOut_zd);
                    end
                    else
                    begin
                        if (BankProg[BA] != 1)
                        begin
                            if ((SecAddr != VarSect && Ers_Queue[SecAddr]!=1'b1)
                            ||(SecAddr == VarSect
                            && Ers_Sub_Queue[SubSect]!=1'b1))
                            begin
                                MemRead(DOut_zd);
                            end
                            else
                            begin
                                ////////////////////////////////////////////////
                                //read status
                                ////////////////////////////////////////////////
                                Status[7] = 1'b1;
                                // Status[6) No toggle
                                Status[5] = 1'b0;
                                Status[2] = ~Status[2]; //toggle
                                DOut_zd = Status;
                                if(BYTE==0)
                                    DOut_zd[15:8] = 8'bz;
                            end
                        end
                        else
                        begin
                            ////////////////////////////////////////////////////
                            //read status
                            ////////////////////////////////////////////////////
                            Status[6] = ~Status[6]; //toggle
                            Status[5] = 1'b0;
                            //Status[2) no toggle
                            Status[1] = 1'b0;
                            DOut_zd = Status;
                            if(((SecAddr == VarSect)&&(SubSect == SSA)&&
                            (SecAddr == SA)) || ((SecAddr != VarSect)&&
                            (SecAddr == SA)))
                                DOut_zd[7] = Status[7];
                            else
                                DOut_zd[7] = ~Status[7];

                            if(BYTE==0)
                                DOut_zd[15:8] = 8'bz;
                        end
                    end
                end
                if (PERR!=1'b1)
                begin
                    if (~PR_FLAG)
                    begin
                        PR_FLAG = 1;
                        //Word/Byte program
                        wr_cnt = 0;
                        if (WAddr[1] < 0 )
                            wr_cnt =0;
                        else
                            wr_cnt =1;

                        for (i=wr_cnt;i>=0;i=i-1)
                        begin
                            new_int= WData[i];
                            if (WAddr[i] < 0)
                                old_int = -1;
                            else if (PGMS_FLAG == MEMORY) //mem write
                                old_int = Mem[sa(SA) + WAddr[i]];
                            else if (PGMS_FLAG == OTP_MEM)
                                old_int = SecSi[WAddr[i]];

                            if (new_int>-1)
                            begin
                                new_bit = new_int;
                                if (old_int>-1 && (PGMS_FLAG == OTP_MEM
                                || PGMS_FLAG == MEMORY))
                                begin
                                    old_bit = old_int;
                                    for(j=0;j<=7;j=j+1)
                                        if (~old_bit[j])
                                            new_bit[j]=1'b0;
                                end
                                else
                                begin
                                    new_bit[0] = 1'bx;
                                end

                                if (new_bit[0] !== 1'bx)
                                begin
                                    new_int=new_bit;
                                    WData[i]= new_int;
                                end
                                else
                                begin
                                    WData[i]= -1;
                                end
                            end
                            else
                            begin
                                WData[i]= -1;
                            end
                        end

                        for (i=wr_cnt;i>=0;i=i-1)
                        begin
                            if (PGMS_FLAG == MEMORY)   //mem write
                                Mem[sa(SA) + WAddr[i]] = -1;
                            else if (PGMS_FLAG == OTP_MEM)
                                SecSi[WAddr[i]] = -1;
                        end
                    end

                    if (PDONE && ~PSTART)
                    begin
                        PR_FLAG = 0;
                        for (i=wr_cnt;i>=0;i=i-1)
                        begin
                            if (WAddr[i] > -1 && WData[i] > -1)
                            begin
                                if (PGMS_FLAG == MEMORY)   //mem write
                                    Mem[sa(SA) + WAddr[i]] = WData[i];
                                else if (PGMS_FLAG == OTP_MEM)
                                    SecSi[WAddr[i]] = WData[i];

                                WData[i]= -1;
                            end
                        end
                    end
                    else if (falling_edge_write)
                        if (DataLo == 16'hB0 && BankProg[BA])
                            START_T1_in = 1;
                end
                //busy signal active
                RY_zd = 1'b0;
            end

            PREL_SETBWB :
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && (DataLo==16'h20))
                    begin
                        BankBypassLock[BA] <= 1;
                        ULBYPASS = 1'b1;
                    end
                    else if (A_PAT_1 && (DataLo==16'h90))
                    begin
                        BankAutosel[BA] = 1;
                        ULBYPASS = 1'b0;
                    end
                    else if (A_PAT_1 && (DataLo==16'h88))
                    begin
                        OTP_ACT   = 1;
                        ULBYPASS = 1'b0;
                    end
                    else if (A_PAT_1 && (DataLo==16'h78))
                    begin
                        PPBLock   = 1;
                    end
                end
                //ready signal active
                RY_zd = 1'b0;
            end

            PREL_ULBYPASS_RESET, ESP_ULBYPASS_RESET:
            begin
                if (falling_edge_write)
                    if (DataLo==16'h00)
                        BankBypassLock = 2'b00;
                        ULBYPASS = 1'b0;
            end

            A0SEEN:
            begin
                if (falling_edge_write && ~current_state_event)
                begin
                    if ((BankBypassLock[BA] && ULBYPASS) || ~ULBYPASS )
                    begin
                        PGMS_FLAG = MEMORY;
                        BankProg[BA] = 1;
                        PSTART = 1'b1;
                        PSTART <= #1 1'b0;
                        PSUSP  = 1'b0;
                        PRES   = 1'b0;
                        PR_FLAG = 1'b0;
                        WData[0] = DataLo;
                        WData[1] = DataHi;
                        WAddr[0] = Address;
                        SA = SecAddr;
                        SSA = SubSect;
                        temp = DataLo;
                        Status[7] = ~temp[7];

                        if (BYTE)
                            WAddr[1] = WAddr[0] +1;
                        else
                            WAddr[1] = -1;
                    end
                end
            end

            OTP_Z001:
            begin
            end

            OTP_PREL:
            begin
                if (falling_edge_write)
                    if (A_PAT_1 && (DataLo == 16'h90))
                        ULBYPASS = 1'b0;
            end

            OTP_A0SEEN:
            begin
                if (falling_edge_write && ~current_state_event)
                begin
                    OTP_ACT = 1'b1;
                    BankProg[BA] = 1;
                    PSTART = 1'b1;
                    PSTART <= #1 1'b0;
                    PSUSP  = 1'b0;
                    PRES   = 1'b0;
                    PGMS_FLAG = OTP_MEM;
                    PR_FLAG = 1'b0;

                    WData[0] = DataLo;
                    WData[1] = DataHi;
                    WAddr[0] = Address;
                    SA = SecAddr;
                    temp = DataLo;
                    Status[7] = ~temp[7];

                    if (SecAddr == 0)
                        $display ("Invalid sector Address in SecSi");

                    if (Address < 256)
                    begin
                        $display ("Invalid program address in SecSi region. ");
                        $display ("Address= ", Address);
                    end

                    if (Address > 127)
                    begin
                         $display ("Invalid program address in factory");
                         $display (" SecSi region. Address= ", Address);
                    end

                    if (BYTE)
                        WAddr[1] = WAddr[0] + 1;
                    else
                        WAddr[1] = -1;

                end
            end

            C8:
            begin
                if (falling_edge_write)
                begin
                end
            end

            C8_Z001:
            begin
                if (falling_edge_write)
                begin
                end
            end

            C8_PREL :
            begin
                if (falling_edge_write)
                begin
                    if ((A_PAT_1 || ULBYPASS) && DataLo == 16'h10)
                    //Start Chip Erase
                    begin
                        ESUSP  = 1'b0;
                        ERES   = 1'b0;
                        Ers_Queue = 64'hFFFFFFFFFFFFFFFF;
                        Ers_Sub_Queue = 8'b11111111;
                        Status = 8'b00000000;
                        ESTART = 1'b1;
                        ESTART    = #1 1'b0;
                        ER_FLAG = 0;
                        BankErase = 4'b11;
                        for (i=0;i<=SecNum;i=i+1)
                        begin
                            if (i!=VarSect)
                            begin
                                if (DYB[i] == 0 && PPB[GroupID(i)] == 0)
                                    BankEraseExec[i] = 1'b1;
                            end
                            else
                            begin
                                for (j=0;j<=SubSecNum;j=j+1)
                                    if (~SubSec_Prot[j] && DYB_SubSec[i] == 0
                                    && PPB_SubSec[i] == 0)
                                        BankEraseExec[0] = 1'b1;
                            end
                        end
                       -> bank_erase_event;
                    end
                    else if (DataLo==16'h30)
                    begin
                        //put selected sector to sec. ers. queue
                        //start timeout
                        ESP_ACT = 1'b1;
                        Ers_Queue = 64'd0;
                        Ers_Sub_Queue = 8'b00000000;
                        if (SecAddr == VarSect)
                            Ers_Sub_Queue[SubSect] = 1'b1;
                        else
                        begin
                            Ers_Queue[SecAddr] = 1'b1;
                        end
                        BankErase[BA] = 1'b1;
                        if ((SecAddr != VarSect) && ~DYB[SecAddr]
                        && ~PPB[SecAddr])
                            BankEraseExec[BA] = 1'b1;
                        else if  (SecAddr == VarSect &&
                        ~SubSec_Prot[SubSect] && ~DYB_SubSec[SubSect]
                        && ~PPB_SubSec[SubSect])
                            BankEraseExec[BA] = 1'b1;

                        disable TCTMOUTr;
                        CTMOUT_in = 1'b0;
                        #1 CTMOUT_in <= 1'b1;
                    end
                end
            end

            ESP_Z001:
            begin
            end

            ESP_SETBWB :
            begin
                if (falling_edge_write)
                    if (A_PAT_1 && (DataLo == 16'h20))
                    begin
                        BankBypassLock[BA] = 1'b1;
                        ULBYPASS = 1'b1;
                    end
                    else if (A_PAT_1 && (DataLo == 16'h90))   //autoselect mode
                    begin
                        BankAutosel[BA] = 1'b1;
                    end
            end

            ESP_A0SEEN :
            begin
                if (falling_edge_write && ~current_state_event)
                begin
                    if ((BankBypassLock[BA] == 1 && ULBYPASS) || ~ULBYPASS)
                    begin
                        BankProg[BA] = 1;
                        PSTART = 1'b1;
                        PSTART <= #1 1'b0;
                        PSUSP = 1'b0;
                        PRES = 1'b0;
                        PGMS_FLAG = MEMORY;
                        PR_FLAG = 0;
                        WData[0] = DataLo;
                        WData[1] = DataHi;
                        WAddr[0] = Address;
                        SA = SecAddr;
                        SSA = SubSect;
                        temp = DataLo;
                        Status[7] = ~temp[7];

                        if (BYTE)
                            WAddr[1] = WAddr[0] +1;
                        else
                            WAddr[1] = -1;
                    end
                end
            end

            OTP_EXIT:
            begin
                if (falling_edge_write)
                    if (DataLo==16'h00)
                        OTP_ACT = 1'b0;
            end

            PSPS:
            begin
                PSUSP = 1'b1;
                if (START_T1)
                    START_T1_in = 0;
                else if (oe)
                begin
                    ///////////////////////////////////////
                    //read status / stil programming
                    ///////////////////////////////////////
                    if (~ESP_ACT)
                    begin
                        if (BankProg[BA] == 1)
                        begin
                        ////////////////////////////////////////////////////////
                        //read status
                        ////////////////////////////////////////////////////////

                            Status[6] = ~Status[6]; //toggle
                            Status[5] = 1'b0;
                            //Status[2) no toggle
                            Status[1] = 1'b0;

                            DOut_zd[7:0] = Status;
                            if (((SecAddr == VarSect) && (SecAddr == SA) &&
                            (SubSect == SSA)) || ((SecAddr != VarSect) &&
                            (SecAddr == SA)) || OTP_ACT == 1)
                                DOut_zd[7] = Status[7];
                            else
                                DOut_zd[7] = ~ Status[7];
                        end
                        else
                            MemRead(DOut_zd);

                    end
                    else
                    begin
                        if (BankProg[BA] != 1)
                        begin
                            if ((SecAddr != VarSect &&
                            Ers_Queue[SecAddr] != 1) || (SecAddr == VarSect
                            && Ers_Sub_Queue[SubSect] != 1))
                                MemRead(DOut_zd);
                            else
                            begin
                            ////////////////////////////////////////////////////
                            //read status
                            ////////////////////////////////////////////////////
                                Status[7] = 1;
                                // Status(6) No toggle
                                Status[5] = 0;
                                Status[2] = ~Status[2]; //toggle
                                DOut_zd = Status;
                            end
                        end
                        else
                        begin
                        ////////////////////////////////////////////////////////
                        //read status
                        ////////////////////////////////////////////////////////
                            Status[6] = ~Status[6]; //toggle
                            Status[5] = 0;
                            //Status(2) no toggle
                            Status[1] = 0;
                            DOut_zd = Status;
                            if (((SecAddr == VarSect) && (SecAddr == SA) &&
                            (SubSect == SSA)) || ((SecAddr != VarSect) &&
                            (SecAddr == SA)) || OTP_ACT == 1)
                                DOut_zd[7] = Status[7];
                            else
                                DOut_zd[7] = ~Status[7];
                        end
                    end
                    //busy signal active
                    RY_zd = 1'b0;
                end
            end

            PSP:
            begin
                PSUSP = 1'b0;
                if (falling_edge_write)
                begin
                    if (DataLo == 16'h30 && BankProg[BA] == 1)
                    begin
                        PRES = 1'b1;
                        PRES <= #1 1'b0;
                        PSP_ACT = 0;
                    end
                end
                else if (oe)
                begin
                    ////////////////////////////////////////////////////////////
                    //read  - program suspend
                    ////////////////////////////////////////////////////////////
                    if (((SecAddr == VarSect) && (SecAddr == SA)
                    && (SubSect == SSA)) || ((SecAddr != VarSect)
                    && (SecAddr == SA)))
                    begin
                        //read program suspended sector
                        //Invalid (not allowed)
                        $display ("Read from program suspended sector ");
                        $display ("is NOT allowed");
                    end
                    else if (ESP_ACT == 1 && ((SecAddr != VarSect
                    && Ers_Queue[SecAddr] == 1) || (SecAddr == VarSect
                    && Ers_Sub_Queue[SubSect] == 1)))
                    begin
                        ////////////////////////////////////////////////////////
                        //read status
                        ////////////////////////////////////////////////////////
                        Status[7] = 1;
                        // Status(6) No toggle
                        Status[5] = 0;
                        Status[2] = ~Status[2]; //toggle
                        DOut_zd = Status;
                    end
                    else
                    begin
                        //read sector other than suspended.
                        MemRead(DOut_zd);
                    end
                end
                //ready signal active
                RY_zd = 1'b1;
            end

            PSP_Z001:
            begin
            end

            PSP_PREL:
            begin
                if (falling_edge_write)
                begin
                    if (A_PAT_1 && (DataLo == 16'h88 || DataLo == 16'h58))
                        PSP_ACT = 1;
                    else if (A_PAT_1 && DataLo == 16'h90)
                    begin
                        BankAutosel[BA] = 1;
                        PSP_ACT = 1;
                    end
                end
            end

        PASSPROG_PREL :
        begin
            if (falling_edge_write )
            begin
                WAddrPass = Address % 8;
                WDataPassLo = DataLo;
                WDataPassHi = DataLo;
                PASSPDONE_in = 1'b0;
                #1 PASSPDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
        end

        PASSPROG :
        begin
            if (rising_edge_PASSPDONE_out)
            begin
                Password[WAddrPass] = WDataPassLo & Password[WAddrPass];
                if (BYTE)
                    Password[WAddrPass+1] = WDataPassHi & Password[WAddrPass+1];

                RY_zd = 1'b1;
            end
            if (oe && PASSPDONE_out == 0)
            begin
                Status[7] = ~WDataPassLo[7];
                Status[6] = ~Status[6];
                Status[5] = 1'b0;
                Status[1] = 1'b0;
                DOut_zd = Status;
            end
        end

        PASSVERIFY :
        begin
            if (oe)
            begin
                if (PPMLB != 1'b1)
                    DOut_zd[7:0]= Password[Address % 8];
                else
                    DOut_zd[7:0] = ~(0);
                if (BYTE)
                begin
                    if (PPMLB != 1'b1)
                        DOut_zd[15:8] = Password[(Address % 8)+1];
                    else
                        DOut_zd[15:8] = ~(0);
                end
            end
        end

        PASSUNLOCK0 :
        begin
            if (falling_edge_write)
            begin
                if (BYTE)
                begin
                    UnlockPass =((Password[0] == DataLo) && (Address % 8 == 0));
                    UnlockPass =((Password[1] == DataHi) && (Address % 8 == 0));
                end
                else
                    UnlockPass =((Password[0] == DataLo) && (Address % 8 == 0));
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
            begin
                RY_zd = 1'b1;
            end
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end

        end

        PASSUNLOCK1:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                if (BYTE)
                begin
                    UnlockPass = UnlockPass && (Password[2] == DataLo)
                    && ((Address % 8) == 2);
                    UnlockPass = UnlockPass && (Password[3] == DataHi)
                    && ((Address % 8) == 2);
                end
                else
                begin
                    UnlockPass = UnlockPass && (Password[1] == DataLo)
                    && ((Address % 8) == 1);
                end
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                RY_zd <= 1'b0;
            if ( oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK2:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                if (BYTE)
                begin
                    UnlockPass = UnlockPass && (Password[4] == DataLo)
                    && ((Address % 8) == 4);
                    UnlockPass = UnlockPass && (Password[5] == DataHi)
                    && ((Address % 8) == 4);
                end
                else
                begin
                    UnlockPass = UnlockPass && (Password[2] == DataLo)
                    && ((Address % 8) == 2);
                end
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                RY_zd <= 1'b0;
            if ( oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK3:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                if (BYTE)
                begin
                    UnlockPass = UnlockPass && (Password[6] == DataLo)
                    && ((Address % 8) == 6);
                    UnlockPass = UnlockPass && (Password[7] == DataHi)
                    && ((Address % 8) == 6);
                end
                else
                begin
                    UnlockPass = UnlockPass && (Password[3] == DataLo)
                    && ((Address % 8) == 3);
                end
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                if (BYTE)
                begin
                    if (UnlockPass)
                        PPBLock = 0;
                end
                RY_zd <= 1'b0;
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK4:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                UnlockPass = UnlockPass && (Password[4] == DataLo) &&
                ((Address % 8) == 4);
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                RY_zd = 1'b0;
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK5:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                UnlockPass = UnlockPass && (Password[5] == DataLo) &&
                ((Address % 8) == 5);
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                RY_zd = 1'b0;
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK6:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                UnlockPass = UnlockPass && (Password[6] == DataLo) &&
                ((Address % 8) == 6);
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
                RY_zd = 1'b0;
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PASSUNLOCK7:
        begin
            if (falling_edge_write && UNLOCKDONE_out == 1)
            begin
                UnlockPass = UnlockPass && (Password[7] == DataLo) &&
                ((Address % 8) == 7);
                UNLOCKDONE_in = 1'b0;
                #1 UNLOCKDONE_in <= 1'b1;
                RY_zd = 1'b0;
            end
            if (rising_edge_UNLOCKDONE_out)
            begin
                if (UnlockPass)
                    PPBLock = 1'b0;

                RY_zd =1'b1;
            end
            if (oe && UNLOCKDONE_out == 0)
            begin
                Status[6] = ~Status[6];
                DOut_zd = Status;
            end
        end

        PROTBIT_PREL :
        begin
            if (falling_edge_write)
                if (DataLo == 16'h68 && (Addr % 16'h100 == WP))
                begin
                    PBSecAddr = SecAddr;
                    PBSubSecAddr = SubSect;
                    PBPROG_in = 1'b0;
                    #1 PBPROG_in <= 1'b1;
                    RY_zd = 1'b0;
                end
                else if ( DataLo == 16'h60 && (Addr % 16'h100 == WP) )
                begin
                    PBERASE_in = 1'b0;
                    #1 PBERASE_in <= 1'b1;
                    RY_zd = 1'b0;
                end
                else if ( DataLo == 16'h68 && (Addr % 16'h100 == PL) )
                begin
                    PBPROG_in = 1'b0;
                    #1 PBPROG_in <= 1'b1;
                    RY_zd = 1'b0;
                end
                else if ( DataLo == 16'h68 && (Addr % 16'h100 == SL) )
                begin
                    PBPROG_in = 1'b0;
                    #1 PBPROG_in <= 1'b1;
                    RY_zd = 1'b0;
                end
                else if ( DataLo == 16'h68 && (Addr % 16'h100 == OW) )
                begin
                    PBPROG_in = 1'b0;
                    #1 PBPROG_in <= 1'b1;
                    RY_zd = 1'b0;
                end
        end

        PPBDYB :
        begin
            if (oe)
            begin
                DOut_zd[7:0] = 0;
                DOut_zd[1] = PPBLock;
                DOut_zd[0] = DYB[SecAddr];
                if (SecAddr == VarSect)
                    DOut_zd[0] = DYB_SubSec[SubSect];
                else
                    DOut_zd[0] = DYB[SecAddr];
                if (BYTE)
                    DOut_zd[15:8] = 0;
            end
        end

        DYBWE :
        begin
            if (falling_edge_write)
                if (DataLo % 2 == 0 )
                    if (SecAddr == VarSect)
                        DYB_SubSec[SubSect] = 1'b0;
                    else
                        DYB[SecAddr] = 1'b0;
                else
                    if (SecAddr == VarSect)
                        DYB_SubSec[SubSect] = 1'b1;
                    else
                        DYB[SecAddr] = 1'b1;
        end

        PPB_PROGRAM:
        begin
            if (rising_edge_PBPROG_out)
            begin
                if (PPBLock == 0)
                    if (SecAddr == VarSect)
                        PPB_SubSec[PBSubSecAddr] = 1;
                    else
                        PPB[GroupID(PBSecAddr)] = 1;
                RY_zd = 1'b0;
            end
        end

        PPB_VERIFY:
        begin
            if (oe)
            begin
                DOut_zd[7:1] = 0;
                if (SecAddr == VarSect)
                    DOut_zd[0] = PPB_SubSec[SubSect];
                else
                    DOut_zd[0] = PPB[GroupID(SecAddr)];

                if (BYTE)
                    DOut_zd[15:8] = 0;
            end
        end

        PPB_ERASE:
        begin
            if (rising_edge_PBERASE_out)
            begin
                if (PPBLock == 0)
                begin
                    if (PPB_ers_ccl < 100)
                    begin
                        PPB = 0;
                        PPB_SubSec = 0;
                        PPB_ers_ccl = PPB_ers_ccl +1;
                    end
                    else
                        $display ("PPBs are limited to 100 erase cycle");
                end
                RY_zd = 1'b1;
            end
        end

        PPMLB_PROGRAM:
        begin
            if (rising_edge_PBPROG_out)
                if (SPMLB != 1)
                    PPMLB = 1;

                RY_zd = 1'b1;
        end

        SPMLB_PROGRAM:
        begin
            if (rising_edge_PBPROG_out)
                if (PPMLB != 1)
                    SPMLB = 1;

                RY_zd = 1'b1;
        end

        SSPB_PROGRAM:
        begin
            if (rising_edge_PBPROG_out)
            begin
                SSPB = 1;
                RY_zd = 1'b1;
            end
        end

        PPMLB_VERIFY:
        begin
            if (oe)
            begin
                if (Addr % 16'h100 == PL)
                begin
                    DOut_zd[7:0] = 0;
                    DOut_zd[0] = PPMLB;
                    if (BYTE)
                        DOut_zd[15:8] =0;
                end
                else
                begin
                    DOut_zd = 16'bz;
                    DOut_zd[7:0] = 8'bz;
                    if (BYTE)
                        DOut_zd[15:8] = 8'bz;
                end
            end
        end

        SPMLB_VERIFY:
        begin
            if (oe)
            begin
                if (Addr % 16'h100 == SL)
                begin
                    DOut_zd[7:0] = 8'b0;
                    DOut_zd[0] = SPMLB;
                    if (BYTE)
                        DOut_zd[15:8] = 8'b0;
                end
                else
                begin
                    DOut_zd[7:0] = 8'bz;
                    if (BYTE)
                        DOut_zd[15:8] = 8'bz;
                end
            end
        end

        SSPB_VERIFY:
        begin
            if (oe)
            begin
                if (Addr % 16'h100 == OW)
                begin
                    DOut_zd[7:0] = 8'b0;
                    DOut_zd[0] = SSPB;
                    if (BYTE)
                        DOut_zd[15:8] = 8'b0;
                end
                else
                begin
                    DOut_zd[7:0] = 8'bz;
                    if (BYTE)
                        DOut_zd[15:8] = 8'bz;
                end
            end
        end
        endcase
        end
    end

    always @(DOut_zd)
    begin : OutputGen
        if (DOut_zd[0] !== 1'bz)
        begin
            CEDQ_t = CENeg_event  + CEDQ_01;
            OEDQ_t = OENeg_event  + OEDQ_01;
            ADDRDQ_t = ADDR_event + ADDRDQ_01;
            FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time));
            FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time));
            FROMADDR = 1'b1;
            if ((ADDRDQ_t > $time )&&
            (((ADDRDQ_t>OEDQ_t)&&FROMOE) ||
            ((ADDRDQ_t>CEDQ_t)&&FROMCE)))
            begin
                TempData = DOut_zd;
                FROMADDR = 1'b0;
                if (~BYTE)
                    DOut_Pass[15:8] = 8'bz;
                else
                    DOut_Pass[15:8] = 8'bx;
                DOut_Pass[7:0] = 8'bx;
                #(ADDRDQ_t - $time) DOut_Pass <= TempData;
            end
            else
            begin
                DOut_Pass = DOut_zd;
            end
        end
    end

    always @(DOut_zd)
    begin
        if (DOut_zd[0] === 1'bz)
        begin
           disable OutputGen;
           FROMCE = 1'b1;
           FROMOE = 1'b1;
           if ((CENeg_posEvent <= OENeg_posEvent) &&
           ( CENeg_posEvent + 5 >= $time))
               FROMOE = 1'b0;
           if ((OENeg_posEvent < CENeg_posEvent) &&
           ( OENeg_posEvent + 5 >= $time))
               FROMCE = 1'b0;
           FROMADDR = 1'b0;
           DOut_Pass = DOut_zd;
       end
    end

    initial
    begin
        ///////////////////////////////////////////////////////////////////////
        //CFI array data
        ///////////////////////////////////////////////////////////////////////

            //CFI query identification string
            for (i=16;i<92;i=i+1)
                 CFI_array[i] = -1;

            CFI_array[16'h10] = 16'h0051;
            CFI_array[16'h11] = 16'h0052;
            CFI_array[16'h12] = 16'h0059;
            CFI_array[16'h13] = 16'h0002;
            CFI_array[16'h14] = 16'h0000;
            CFI_array[16'h15] = 16'h0040;
            CFI_array[16'h16] = 16'h0000;
            CFI_array[16'h17] = 16'h0000;
            CFI_array[16'h18] = 16'h0000;
            CFI_array[16'h19] = 16'h0000;
            CFI_array[16'h1A] = 16'h0000;

            //system interface string
            CFI_array[16'h1B] = 16'h0027;
            CFI_array[16'h1C] = 16'h0036;
            CFI_array[16'h1D] = 16'h0000;
            CFI_array[16'h1E] = 16'h0000;
            CFI_array[16'h1F] = 16'h0003;
            CFI_array[16'h20] = 16'h0000;
            CFI_array[16'h21] = 16'h0009;
            CFI_array[16'h22] = 16'h0000;
            CFI_array[16'h23] = 16'h0005;
            CFI_array[16'h24] = 16'h0000;
            CFI_array[16'h25] = 16'h0004;
            CFI_array[16'h26] = 16'h0000;
            //device geometry definition
            CFI_array[16'h27] = 16'h0016;
            CFI_array[16'h28] = 16'h0002;
            CFI_array[16'h29] = 16'h0000;
            CFI_array[16'h2A] = 16'h0000;
            CFI_array[16'h2B] = 16'h0000;
            CFI_array[16'h2C] = 16'h0002;
            CFI_array[16'h2D] = 16'h0007;
            CFI_array[16'h2E] = 16'h0000;
            CFI_array[16'h2F] = 16'h0020;
            CFI_array[16'h30] = 16'h0000;
            CFI_array[16'h31] = 16'h003E;
            CFI_array[16'h32] = 16'h0000;
            CFI_array[16'h33] = 16'h0000;
            CFI_array[16'h34] = 16'h0001;
            CFI_array[16'h35] = 16'h0000;
            CFI_array[16'h36] = 16'h0000;
            CFI_array[16'h37] = 16'h0000;
            CFI_array[16'h38] = 16'h0000;
            CFI_array[16'h39] = 16'h0000;
            CFI_array[16'h3A] = 16'h0000;
            CFI_array[16'h3B] = 16'h0000;
            CFI_array[16'h3C] = 16'h0000;
            //primary vendor-specific extended query
            CFI_array[16'h40] = 16'h0050;
            CFI_array[16'h41] = 16'h0052;
            CFI_array[16'h42] = 16'h0049;
            CFI_array[16'h43] = 16'h0031;
            CFI_array[16'h44] = 16'h0033;
            CFI_array[16'h45] = 16'h000C;
            CFI_array[16'h46] = 16'h0002;
            CFI_array[16'h47] = 16'h0001;
            CFI_array[16'h48] = 16'h0001;
            CFI_array[16'h49] = 16'h0007;

            CFI_array[16'h4A] = 16'h0020;
            CFI_array[16'h58] = 16'h0027;

            CFI_array[16'h4B] = 16'h0000;
            CFI_array[16'h4C] = 16'h0000;
            CFI_array[16'h4D] = 16'h0085;
            CFI_array[16'h4E] = 16'h0095;
            CFI_array[16'h4F] = 16'h0002 + vs;
            CFI_array[16'h50] = 16'h0001;

            CFI_array[16'h5A] = 16'h0000;
            CFI_array[16'h57] = 16'h0002;
            CFI_array[16'h5B] = 16'h0000;

            CFI_array[16'h59] = 16'h0020;
    end

    //Hardware Write Protection
    always @(falling_edge_WPNeg, rising_edge_WPNeg)
    begin
        if($time>0)
        begin
            if (falling_edge_WPNeg)
            begin
                SubSec_Prot[ProtSecNum_1] = 1;
                SubSec_Prot[ProtSecNum_2] = 1;
            end
            else if (rising_edge_WPNeg)
            begin
                SubSec_Prot[ProtSecNum_1] = 0;
                SubSec_Prot[ProtSecNum_2] = 0;
            end
        end
    end

    always @(posedge WPNeg)
    begin
        rising_edge_WPNeg = 1;
        #1 rising_edge_WPNeg = 0;
    end

    always @(negedge WPNeg)
    begin
        falling_edge_WPNeg = 1;
        #1 falling_edge_WPNeg = 0;
    end

    always @(posedge EDONE)
    begin
        rising_edge_EDONE = 1;
        #1 rising_edge_EDONE = 0;
    end

    always @(negedge PERR)
    begin
        falling_edge_PERR = 1;
        #1 falling_edge_PERR = 0;
    end

    always @(posedge WENeg)
    begin
        rising_edge_WENeg = 1;
        #1 rising_edge_WENeg = 0;
    end

    always @(posedge CTMOUT)
    begin
        rising_edge_CTMOUT = 1;
        #1 rising_edge_CTMOUT = 0;
    end

    always @(negedge WENeg)
    begin
        falling_edge_WENeg = 1;
        #1 falling_edge_WENeg= 0;
    end

    always @(posedge write)
    begin
        rising_edge_write = 1;
        #1 rising_edge_write = 0;
    end

    always @(posedge CENeg)
    begin
        rising_edge_CENeg = 1;
        #1 rising_edge_CENeg = 0;
    end

    always @(posedge UNLOCKDONE_out)
    begin
        rising_edge_UNLOCKDONE_out = 1;
        #1 rising_edge_UNLOCKDONE_out = 0;
    end

    always @(posedge PBPROG_out)
    begin
        rising_edge_PBPROG_out = 1;
        #1 rising_edge_PBPROG_out = 0;
    end

    always @(posedge ERES)
    begin
        rising_edge_ERES = 1;
        #1 rising_edge_ERES = 0;
    end

    always @(posedge ESUSP)
    begin
        rising_edge_ESUSP = 1;
        #1 rising_edge_ESUSP = 0;
    end

    always @(posedge ESTART)
    begin
        rising_edge_ESTART = 1;
        #1 rising_edge_ESTART = 0;
    end

    always @(posedge PBERASE_out)
    begin
        rising_edge_PBERASE_out = 1;
        #1 rising_edge_PBERASE_out = 0;
    end

    always @(posedge PASSPDONE_out)
    begin
        rising_edge_PASSPDONE_out = 1;
        #1 rising_edge_PASSPDONE_out = 0;
    end

    always @(posedge PDONE)
    begin
        rising_edge_PDONE = 1;
        #1 rising_edge_PDONE = 0;
    end

    always @(current_state)
    begin
        current_state_event = 1;
        #1 current_state_event = 0;
    end

    always @(Address)
    begin
        Address_event = 1;
        #1 Address_event = 0;
    end

    always @(SecAddr)
    begin
        SecAddr_event = 1;
        #1 SecAddr_event = 0;
    end

    always @(posedge read)
    begin
        rising_edge_read = 1;
        #1 rising_edge_read = 0;
    end

    always @(negedge EERR)
    begin
        falling_edge_EERR = 1;
        #1 falling_edge_EERR = 0;
    end

    always @(negedge CENeg)
    begin
        falling_edge_CENeg = 1;
        #1 falling_edge_CENeg= 0;
    end

    always @(negedge OENeg)
    begin
        falling_edge_OENeg = 1;
        #1 falling_edge_OENeg= 0;
    end

    always @(A)
    begin
        A_event = 1;
        #1 A_event = 0;
    end

    always @(DIn[15])
    begin
        DIn_15_event = 1;
        #1 DIn_15_event = 0;
    end

    always @(posedge PSTART)
    begin
        rising_edge_PSTART = 1;
        #1 rising_edge_PSTART = 0;
    end

    always @(posedge reseted)
    begin
        rising_edge_reseted = 1;
        #1 rising_edge_reseted = 0;
    end

    always @(posedge PSUSP)
    begin
        rising_edge_PSUSP = 1;
        #1 rising_edge_PSUSP = 0;
    end

    always @(posedge PRES)
    begin
        rising_edge_PRES = 1;
        #1 rising_edge_PRES = 0;
    end

    always @(negedge write)
    begin
        falling_edge_write = 1;
        #1 falling_edge_write = 0;
    end

    always @(negedge RST)
    begin
        falling_edge_RST = 1;
        #1 falling_edge_RST = 0;
    end

    always @(negedge RESETNeg)
    begin
        falling_edge_RESETNeg = 1;
        #1 falling_edge_RESETNeg = 0;
    end

    always @(posedge RESETNeg)
    begin
        rising_edge_RESETNeg = 1;
        #1 rising_edge_RESETNeg = 0;
    end

    reg  BuffInOE, BuffInCE, BuffInADDR;
    wire BuffOutOE, BuffOutCE, BuffOutADDR;

    BUFFER    BUFOE   (BuffOutOE, BuffInOE);
    BUFFER    BUFCE   (BuffOutCE, BuffInCE);
    BUFFER    BUFADDR (BuffOutADDR, BuffInADDR);
    initial
    begin
        BuffInOE   = 1'b1;
        BuffInCE   = 1'b1;
        BuffInADDR = 1'b1;
    end

    always @(posedge BuffOutOE)
    begin
        OEDQ_01 = $time;
    end
    always @(posedge BuffOutCE)
    begin
        CEDQ_01 = $time;
    end
    always @(posedge BuffOutADDR)
    begin
        ADDRDQ_01 = $time;
    end

    function integer sa;
    input  [15:0] sect;
    begin
        sa = sect * (SecSize + 1);
    end
    endfunction

    function[9:0] GroupID;
    input SECADDR;
    integer SECADDR;
    begin
        if (tmp_char == "1")
        begin
            GroupID = 0;
            if ( SECADDR == 0 )
                GroupID = SECADDR;
            else if (( SECADDR >= 1 ) && ( SECADDR <= 3 ))
                GroupID = 1;
            else if (( SECADDR >= 4 ) && ( SECADDR <= 59 ))
                GroupID = (SECADDR - 4) / 4 + 2;
            else if (( SECADDR >= 60 ) && ( SECADDR <= 62 ))
                GroupID = 16;

        end
        else
        begin
            GroupID = 0;
            if (( SECADDR >= 1 ) && ( SECADDR <= 3 ))
                GroupID = 0;
            else if (( SECADDR >= 4 ) && ( SECADDR <= 59 ))
                GroupID = (SECADDR - 4) / 4 + 1;
            else if (( SECADDR >= 60 ) && ( SECADDR <= 62 ))
                GroupID = 15;
            else
                GroupID = 16;
        end
    end
    endfunction

    function integer sssa;
    input  [15:0] subsect;
    begin
        if (subsect == 0)
            sssa=16'h0000;
        else if (subsect == 1)
            sssa=16'h1000;
        else if (subsect == 2)
            sssa=16'h2000;
        else if (subsect == 3)
            sssa=16'h3000;
        else if (subsect == 4)
            sssa=16'h4000;
        else if (subsect == 5)
            sssa=16'h5000;
        else if (subsect == 6)
            sssa=16'h6000;
        else
            sssa=16'h7000;
    end
    endfunction

    function integer ssea;
    input  [15:0] subsect;
    begin
        if (subsect == 0)
            ssea=16'h0FFF;
        else if (subsect == 1)
            ssea=16'h1FFF;
        else if (subsect == 2)
            ssea=16'h2FFF;
        else if (subsect == 3)
            ssea=16'h3FFF;
        else if (subsect == 4)
            ssea=16'h4FFF;
        else if (subsect == 5)
            ssea=16'h5FFF;
        else if (subsect == 6)
            ssea=16'h6FFF;
        else
            ssea=16'h7FFF;
    end
    endfunction

    task MemRead;
    inout [15:0] DOut_zd;
    begin
        if (Mem[sa(SecAddr)+Address]==-1)
            DOut_zd[7:0] = 8'bx;
        else
            DOut_zd[7:0] = Mem[sa(SecAddr)+Address];
        if (BYTENeg)
            if (Mem[sa(SecAddr)+Address+1]==-1)
                DOut_zd[15:8]= 8'bx;
            else
                DOut_zd[15:8] = Mem[sa(SecAddr)+Address+1];
    end
    endtask
endmodule

module BUFFER (OUT,IN);
    input IN;
    output OUT;
    buf   ( OUT, IN);
endmodule