////////////////////////////////////////////////////////////////////////////// // File name : s29gl04gs.v ////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2011 Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY : // // version: | author: | date: | changes made: // V1.0 H. Dimitrijevic 11 April 01 Initial release // ////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // // Library: FLASH // Technology: Flash Memory // Part: S29GL04GS // // Description: 4 Gbit(512MByte) CMOS 3.0 Volt core with Non-volatile Flash // Memory,65nm MirrorBit Technology, x16 data bus // // ////////////////////////////////////////////////////////////////////////////// // Known Bugs: // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module s29gl04gs ( A27 , A26 , A25 , A24 , A23 , A22 , A21 , A20 , A19 , A18 , A17 , A16 , A15 , A14 , A13 , A12 , A11 , A10 , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 , DQ15 , DQ14 , DQ13 , DQ12 , DQ11 , DQ10 , DQ9 , DQ8 , DQ7 , DQ6 , DQ5 , DQ4 , DQ3 , DQ2 , DQ1 , DQ0 , CENeg , OENeg , WENeg , RESETNeg ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input A27 ; input A26 ; input A25 ; input A24 ; input A23 ; input A22 ; input A21 ; input A20 ; input A19 ; input A18 ; input A17 ; input A16 ; input A15 ; input A14 ; input A13 ; input A12 ; input A11 ; input A10 ; input A9 ; input A8 ; input A7 ; input A6 ; input A5 ; input A4 ; input A3 ; input A2 ; input A1 ; input A0 ; inout DQ15 ; inout DQ14 ; inout DQ13 ; inout DQ12 ; inout DQ11 ; inout DQ10 ; inout DQ9 ; inout DQ8 ; inout DQ7 ; inout DQ6 ; inout DQ5 ; inout DQ4 ; inout DQ3 ; inout DQ2 ; inout DQ1 ; inout DQ0 ; input CENeg ; input OENeg ; input WENeg ; input RESETNeg ; // interconnect path delay signals wire A27_ipd ; wire A26_ipd ; wire A25_ipd ; wire A24_ipd ; wire A23_ipd ; wire A22_ipd ; wire A21_ipd ; wire A20_ipd ; wire A19_ipd ; wire A18_ipd ; wire A17_ipd ; wire A16_ipd ; wire A15_ipd ; wire A14_ipd ; wire A13_ipd ; wire A12_ipd ; wire A11_ipd ; wire A10_ipd ; wire A9_ipd ; wire A8_ipd ; wire A7_ipd ; wire A6_ipd ; wire A5_ipd ; wire A4_ipd ; wire A3_ipd ; wire A2_ipd ; wire A1_ipd ; wire A0_ipd ; wire [27 : 0] A; assign A = {A27_ipd, A26_ipd, A25_ipd, A24_ipd, A23_ipd, A22_ipd, A21_ipd, A20_ipd, A19_ipd, A18_ipd, A17_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire DQ15_ipd ; wire DQ14_ipd ; wire DQ13_ipd ; wire DQ12_ipd ; wire DQ11_ipd ; wire DQ10_ipd ; wire DQ9_ipd ; wire DQ8_ipd ; wire DQ7_ipd ; wire DQ6_ipd ; wire DQ5_ipd ; wire DQ4_ipd ; wire DQ3_ipd ; wire DQ2_ipd ; wire DQ1_ipd ; wire DQ0_ipd ; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire CENeg_ipd ; wire OENeg_ipd ; wire WENeg_ipd ; wire RESETNeg_ipd ; // internal delays reg READY_in ; reg READY ; // Device ready after reset wire DQ15_Pass ; wire DQ14_Pass ; wire DQ13_Pass ; wire DQ12_Pass ; wire DQ11_Pass ; wire DQ10_Pass ; wire DQ9_Pass ; wire DQ8_Pass ; wire DQ7_Pass ; wire DQ6_Pass ; wire DQ5_Pass ; wire DQ4_Pass ; wire DQ3_Pass ; wire DQ2_Pass ; wire DQ1_Pass ; wire DQ0_Pass ; reg [15 : 0] DOut_zd; reg [15 : 0] DOut_Pass; assign {DQ15_Pass, DQ14_Pass, DQ13_Pass, DQ12_Pass, DQ11_Pass, DQ10_Pass, DQ9_Pass, DQ8_Pass, DQ7_Pass, DQ6_Pass, DQ5_Pass, DQ4_Pass, DQ3_Pass, DQ2_Pass, DQ1_Pass, DQ0_Pass } = DOut_Pass; parameter UserPreload = 1'b0; parameter mem_file_name = "none";//"s29gl04gs.mem"; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "S29GL04GS"; parameter MaxData = 16'hFFFF; parameter SecSize = 20'h1FFFF; //256KB parameter SecNum = 2047; parameter HiAddrBit = 27; parameter AddrRANGE = 28'hFFFFFFF; // If speedsimulation is needed uncomment following line // `define SPEEDSIM; integer ECCPage; //varaibles to resolve architecture used reg [20*8-1:0] tmp_timing;//stores copy of TimingModel // powerup reg PoweredUp; //FSM control signals reg CHECK_ACT = 1'b0; reg STAT_ACT = 1'b0; // status activation integer LCNT ; ////Load Counter 0-255 ////number of location to be writen in Write Buffer: 0-255 words. integer PCNT ; //0-256 reg PDONE ; ////Prog. Done reg PSTART ; ////Start Programming reg EDONE ; ////Ers. Done reg ESTART ; ////Start Erase reg BCDONE ; ////Bclk. check Done reg BCSTART ; ////Bclk. check Start //Command Register reg write ; reg read ; //Sector Address integer SecAddr = 0; // 0 - SecNum integer SA = 0; // 0 TO SecNum integer WBPage = 0; //Address within sector integer Address = 0; // 0 - SecSize integer D_tmp; integer D_tmp1; //Amax:A11 Don't Care integer Addr ; integer Addr1; integer WPage; integer RPage; reg RPchange ; //status register reg[15:0] StatusReg = 16'b0000000010000000; //glitch protection wire gWE_n ; wire gCE_n ; wire gOE_n ; reg RST ; reg reseted ; //ECC array integer ECC_array[24'hFFFFFF:0]; integer ECC_WB_array[24'hFFFFFF:0]; // timing check violation reg Viol = 1'b0; integer Mem[0:((SecNum+1)*(SecSize+1) -1) ]; integer WBData[0:255]; integer WBAddr[0:255]; integer BaseLoc = 0; integer cnt = 0; //Status reg. reg[7:0] Status = 8'b0; integer S_ind = 0; integer ind = 0; reg[15:0] old_bit, new_bit; integer old_int, new_int; integer wr_cnt; reg[15:0] temp; reg oe = 1'b0; event oe_event; //TPD_XX_DATA time OEDQ_t; time CEDQ_t; time ADDRDQ_t; time OENeg_event; time CENeg_event; time ADDR_event; reg FROMOE; reg FROMCE; reg FROMADDR; integer OEDQ_01; integer CEDQ_01; integer ADDRDQ_01_SHORT; integer ADDRDQ_01_LONG; reg[15:0] TempData; integer A_tmp; reg [16 :0] A_tmp1; reg [27 :0] A_tmp2; reg [27:0] AddressLatched; reg [20:0] sector; reg [20:0] AddrTmp; reg [20:0] AddrLOW; reg [20:0] AddrHIGH; reg PR_FLAG = 0; reg ER_FLAG = 0; reg CE; reg falling_edge_RESETNeg = 0; reg rising_edge_RESETNeg = 0; reg falling_edge_WENeg = 0; reg rising_edge_WENeg = 0; reg falling_edge_CENeg = 0; reg rising_edge_CENeg = 0; reg falling_edge_OENeg = 0; reg rising_edge_write = 0; reg falling_edge_write = 0; reg rising_edge_read = 0; reg A_event = 0; reg falling_edge_RST = 0; reg rising_edge_reseted = 0; reg rising_edge_EDONE = 0; reg rising_edge_ESTART = 0; reg rising_edge_PSTART = 0; reg rising_edge_PDONE = 0; reg rising_edge_BCSTART = 0; reg rising_edge_BCDONE = 0; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (A27_ipd, A27); buf (A26_ipd, A26); buf (A25_ipd, A25); buf (A24_ipd, A24); buf (A23_ipd, A23); buf (A22_ipd, A22); buf (A21_ipd, A21); buf (A20_ipd, A20); buf (A19_ipd, A19); buf (A18_ipd, A18); buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (CENeg_ipd , CENeg ); buf (OENeg_ipd , OENeg ); buf (WENeg_ipd , WENeg ); buf (RESETNeg_ipd , RESETNeg ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_Pass , 1); nmos (DQ14, DQ14_Pass , 1); nmos (DQ13, DQ13_Pass , 1); nmos (DQ12, DQ12_Pass , 1); nmos (DQ11, DQ11_Pass , 1); nmos (DQ10, DQ10_Pass , 1); nmos (DQ9 , DQ9_Pass , 1); nmos (DQ8 , DQ8_Pass , 1); nmos (DQ7 , DQ7_Pass , 1); nmos (DQ6 , DQ6_Pass , 1); nmos (DQ5 , DQ5_Pass , 1); nmos (DQ4 , DQ4_Pass , 1); nmos (DQ3 , DQ3_Pass , 1); nmos (DQ2 , DQ2_Pass , 1); nmos (DQ1 , DQ1_Pass , 1); nmos (DQ0 , DQ0_Pass , 1); wire deg; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_A0_DQ0 =1; specparam tpd_A0_DQ1 =1; //tPACC specparam tpd_CENeg_DQ0 =1; //(tCE,tCE,tDF,-,tDF,-) specparam tpd_OENeg_DQ0 =1; //(tOE,tOE,tDF,-,tDF,-) specparam tpd_RESETNeg_DQ0 =1; // tsetup values: setup time specparam tsetup_A0_CENeg =1; //tAS edge \ specparam tsetup_DQ0_CENeg =1; //tDS edge / specparam tsetup_CENeg_WENeg =1; //tCS edge \ // thold values: hold times specparam thold_A0_CENeg =1; //tAH edge \ specparam thold_DQ0_CENeg =1; //tDH edge / specparam thold_OENeg_WENeg =1; //tOEH edge / specparam thold_CENeg_RESETNeg =1; //tRH edge / specparam thold_WENeg_OENeg =1; //tGHVL edge / specparam thold_CENeg_WENeg =1; //tCH edge / // tpw values: pulse width specparam tpw_A0_negedge =1; //tWC tRC specparam tpw_RESETNeg_negedge =1; //tRP specparam tpw_WENeg_negedge =1; //tWP specparam tpw_WENeg_posedge =1; //tWPH // tdevice values: values for internal delays `ifdef SPEEDSIM //Effective Write Buffer Program Operation tWHWH1 specparam tdevice_WBPB = 340000; //ns; //Effective Write Buffer Program Operation tWHWH1 specparam tdevice_WBPBW = 1300; //ns; //Program Operation specparam tdevice_POW = 15000;///150/10 us ; //Sector Erase Operation tWHWH2 specparam tdevice_SEO = 90000000;///900/10 ms // Blank Check specparam tdevice_BC = 17000; /// 17/1000 ms //device ready after Hardware reset(during embeded algorithm) specparam tdevice_READY = 30000; `else //Effective Write Buffer Program Operation tWHWH1 specparam tdevice_WBPB = 340000; //ns; //Effective Write Buffer Program Operation tWHWH1 specparam tdevice_WBPBW = 1300; //ns; //Program Operation specparam tdevice_POW = 150000;//150 us per word; //Sector Erase Operation tWHWH2 specparam tdevice_SEO = 900000000; //900 ms // Blank Check specparam tdevice_BC = 17000000; //17 ms //device ready after Hardware reset(during embeded algorithm) specparam tdevice_READY = 30000; `endif //SPEEDSIM /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// if (FROMCE) (CENeg *> DQ0) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ1) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ2) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ3) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ4) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ5) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ6) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ7) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ8) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ9) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ10) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ11) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ12) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ13) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ14) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ15) = tpd_CENeg_DQ0; if (FROMOE) (OENeg *> DQ0) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ1) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ2) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ3) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ4) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ5) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ6) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ7) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ8) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ9) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ10) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ11) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ12) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ13) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ14) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ15) = tpd_OENeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ0) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ1) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ2) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ3) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ4) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ5) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ6) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ7) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ8) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ9) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ10) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ11) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ12) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ13) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ14) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ15) = tpd_RESETNeg_DQ0; if (RPchange && FROMADDR) (A0 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A0 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A1 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A2 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A3 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A4 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A5 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A6 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A7 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A8 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A9 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A10 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A11 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A12 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A13 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A14 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A15 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A16 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A17 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A18 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A19 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A20 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A21 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A22 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A23 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A24 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A25 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A26 *> DQ15) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ0) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ1) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ2) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ3) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ4) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ5) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ6) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ7) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ8) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ9) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ10) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ11) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ12) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ13) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ14) = tpd_A0_DQ0; if (RPchange && FROMADDR) (A27 *> DQ15) = tpd_A0_DQ0; if (~RPchange && FROMADDR) (A0 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A0 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A1 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A2 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A3 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A4 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A5 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A6 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A7 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A8 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A9 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A10 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A11 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A12 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A13 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A14 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A15 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A16 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A17 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A18 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A19 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A20 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A21 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A22 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A23 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A24 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A25 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A26 *> DQ15) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ0) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ1) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ2) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ3) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ4) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ5) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ6) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ7) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ8) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ9) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ10) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ11) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ12) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ13) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ14) = tpd_A0_DQ1; if (~RPchange && FROMADDR) (A27 *> DQ15) = tpd_A0_DQ1; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// $setup ( A0 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A0 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A1 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A2 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A3 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A4 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A5 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A6 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A7 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A8 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A9 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A10 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A11 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A12 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A13 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A14 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A15 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A16 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A17 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A18 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A19 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A20 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A21 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A22 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A23 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A24 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A25 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A26 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A27 , negedge CENeg &&& (WENeg===0),tsetup_A0_CENeg, Viol); $setup ( A0 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A1 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A2 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A3 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A4 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A5 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A6 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A7 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A8 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A9 , negedge WENeg &&& (CENeg===0), tsetup_A0_CENeg, Viol); $setup ( A10 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A11 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A12 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A13 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A14 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A15 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A16 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A17 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A18 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A19 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A20 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A21 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A22 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A23 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A24 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A25 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A26 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( A27 , negedge WENeg &&& (CENeg===0),tsetup_A0_CENeg, Viol); $setup ( DQ0 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge CENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ0 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge WENeg &&& deg, tsetup_DQ0_CENeg, Viol); $setup ( CENeg ,negedge WENeg, tsetup_CENeg_WENeg, Viol); $hold ( posedge RESETNeg &&& (CENeg===1), CENeg , thold_CENeg_RESETNeg, Viol); $hold ( posedge RESETNeg &&& (WENeg===1), WENeg , thold_CENeg_RESETNeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A0 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A1 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A2 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A3 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A4 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A5 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A6 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A7 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A8 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A9 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A10 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A11 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A12 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A13 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A14 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A15 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A16 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A17 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A18 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A19 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A20 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A21 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A22 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A23 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A24 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A25 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A26 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A27 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A0 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A1 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A2 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A3 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A4 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A5 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A6 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A7 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A8 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A9 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A10 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A11 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A12 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A13 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A14 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A15 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A16 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A17 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A18 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A19 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A20 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A21 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A22 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A23 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A24 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A25 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A26 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& (CENeg===0), A27 , thold_A0_CENeg, Viol); $hold ( posedge CENeg, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ1 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ2 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ3 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ4 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ5 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ6 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ7 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ8 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ9 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ10 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ11 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ12 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ13 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ14 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg, DQ15 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ1 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ2 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ3 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ4 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ5 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ6 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ7 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ8 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ9 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ10 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ11 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ12 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ13 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ14 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, DQ15 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg, OENeg , thold_OENeg_WENeg, Viol); $hold ( posedge OENeg, WENeg , thold_WENeg_OENeg, Viol); $hold ( posedge WENeg, CENeg , thold_CENeg_WENeg, Viol); $width (negedge RESETNeg, tpw_RESETNeg_negedge); $width (posedge WENeg, tpw_WENeg_posedge); $width (negedge WENeg, tpw_WENeg_negedge); $width (negedge A0, tpw_A0_negedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// // FSM states parameter RESET =5'd0; parameter READUL1 =5'd1; parameter READUL2 =5'd2; parameter READSR =5'd3; parameter BLCK =5'd4; parameter BLCKSR =5'd5; parameter CUL1 =5'd6; parameter ER =5'd7; parameter ERUL1 =5'd8; parameter ERUL2 =5'd9; parameter SER =5'd10; parameter ERSR =5'd11; parameter PG =5'd12; parameter PGSR =5'd13; parameter WBPGMS_WBCNT =5'd14; parameter WBPGMS_WBLSTA =5'd15; parameter WBPGMS_WBLOAD =5'd16; parameter WBPGMS_CONFB =5'd17; parameter AS =5'd18; parameter ECC_ENTRY =5'd19; reg [4:0] current_state; reg [4:0] next_state; reg deq; always @(DIn, DOut) begin if (DIn==DOut) deq=1'b1; else deq=1'b0; end // check when data is generated from model to avoid setuphold check in // those occasion assign deg=deq; // initialize memory and load preoload files if any initial begin: InitMemory integer i,j,k; for (i=0;i<(SecSize+1)*(SecNum+1);i=i+1) begin Mem[i]=MaxData; end for (i=0;i<((SecSize+1)*(SecNum+1)/16'h10);i=i+1) begin ECC_array[i]=0; ECC_WB_array[i]=0; end if ((UserPreload) && !(mem_file_name == "none")) begin // Memory Preload //s29gl04gs.mem, memory preload file // @aaaaaaa- stands for address within last defined sector // dd - is word to be written at Mem(nn)(aaaaaaa++) // (aaaaaaa is incremented at every load) $readmemh(mem_file_name,Mem); end end //Power Up time 300 ns initial begin PoweredUp = 1'b0; #300 PoweredUp = 1'b1; end always @(RESETNeg) begin RST <= #199 RESETNeg; end initial begin : Initialvalues integer i; write = 1'b0; read = 1'b0; Addr = 0; WPage = 0; RPage = 0; RPchange = 1'b1; LCNT = 0 ; PCNT = 0; PDONE = 1'b1; PSTART = 1'b0; EDONE = 1'b1; ESTART = 1'b0; BCDONE = 1'b1; BCSTART = 1'b0; READY_in = 1'b0; READY = 1'b0; end always @(posedge READY_in) begin:TREADYr #tdevice_READY READY = READY_in; end always @(negedge READY_in) begin:TREADYf #1 READY = READY_in; end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(negedge OENeg) begin OENeg_event = $time; end always @(negedge CENeg) begin CENeg_event = $time; end always @(A) begin ADDR_event = $time; end //////////////////////////////////////////////////////////////////////////// //// sequential process for reset control and FSM state transition //////////////////////////////////////////////////////////////////////////// reg R; reg E; always @(RESETNeg) begin if (PoweredUp) begin //Hardware reset timing control if (~RESETNeg) begin E = 1'b0; if (~PDONE || ~EDONE) begin //if program or erase in progress READY_in = 1'b1; R = 1'b1; end else begin READY_in = 1'b0; R = 1'b0; //prog or erase not in progress end end else if (RESETNeg && RST) begin READY_in = 1'b0; R = 1'b0; E = 1'b1; end end end always @(next_state or RESETNeg or CENeg or RST or READY or PoweredUp) begin: StateTransition if (PoweredUp) begin if (RESETNeg && (~R || (R && READY))) begin current_state = next_state; READY_in = 1'b0; E = 1'b0; R = 1'b0; reseted = 1'b1; end else if ((~R && ~RESETNeg && ~RST) || (R && ~RESETNeg && ~RST && ~READY) || (R && RESETNeg && ~RST && ~READY)) begin //no state transition while RESET# low current_state = RESET; //reset start reseted = 1'b0; end end else begin current_state = RESET; // reset reseted = 1'b0; E = 1'b0; R = 1'b0; end end ////////////////////////////////////////////////////////////////////////// //Glitch Protection: Inertial Delay does not propagate pulses <5ns ////////////////////////////////////////////////////////////////////////// assign #5 gWE_n = WENeg_ipd; assign #5 gCE_n = CENeg_ipd; assign #5 gOE_n = OENeg_ipd; //latch address on rising edge and data on falling edge of write always @(gWE_n or gCE_n or gOE_n or RESETNeg or reseted) begin: write_dc if (RESETNeg!=1'b0 && reseted == 1'b1) begin if (~gWE_n && ~gCE_n && gOE_n) write = 1'b1; else write = 1'b0; end if (gWE_n && ~gCE_n && ~gOE_n) read = 1'b1; else read = 1'b0; end ////////////////////////////////////////////////////////////////////////// //Process that reports warning when changes on signals WE#, CE#, OE# are //discarded ////////////////////////////////////////////////////////////////////////// always @(WENeg) begin: PulseWatch1 if (gWE_n == WENeg) $display("Glitch on WE#"); end always @(CENeg) begin: PulseWatch if (gCE_n == CENeg) $display("Glitch on CE#"); end always @(OENeg) begin: PulseWatch3 if (gOE_n == OENeg) $display("Glitch on OE#"); end ////////////////////////////////////////////////////////////////////////// //Latch address on falling edge of WE# or CE# what ever comes later //Latches data on rising edge of WE# or CE# what ever comes first // also Write cycle decode ////////////////////////////////////////////////////////////////////////// always @(falling_edge_WENeg or falling_edge_CENeg or falling_edge_OENeg or rising_edge_WENeg or rising_edge_CENeg or rising_edge_write or rising_edge_read or A_event) begin : BusCycleDecode if (reseted) begin if ((falling_edge_WENeg && ~CENeg && OENeg) || (falling_edge_CENeg && WENeg !== OENeg) || (falling_edge_OENeg && WENeg && ~CENeg) || (A_event && WENeg && ~CENeg && ~OENeg) ) begin A_tmp = A[11:0]; AddressLatched = A; sector = A[HiAddrBit:17]; A_tmp1 = A[16:0]; A_tmp2 = A[HiAddrBit:0]; end else if ((rising_edge_WENeg || rising_edge_CENeg) && write) begin D_tmp = DIn[15:0]; D_tmp1 = DIn[7:0]; end if (rising_edge_write || rising_edge_read || falling_edge_OENeg || (A_event && WENeg && ~CENeg && ~OENeg)) begin SecAddr = sector; Address = A_tmp1; WPage = A_tmp1 / 256; if ((RPage != (A_tmp1/16)) || (CENeg!=CE)) RPchange = 1'b1; else RPchange = 1'b0; RPage = A_tmp1/16; CE = CENeg; Addr = A_tmp; Addr1 = A_tmp2; end end end ////////////////////////////////////////////////////////////////////////// // Timing control for the Program/ Write Buffer Program Operations // start/ suspend/ resume ////////////////////////////////////////////////////////////////////////// integer cnt_write = 0; time elapsed_write ; time duration_write ; time start_write ; event pdone_event; always @(rising_edge_reseted or rising_edge_PSTART ) begin : ProgTime if (rising_edge_reseted) begin #1 PDONE = 1; // reset done, programming terminated disable pdone_process; end else if (reseted) begin if (rising_edge_PSTART && PDONE) begin if (PCNT<256) //buffer begin cnt_write = PCNT+1; duration_write = cnt_write* tdevice_WBPBW; end elapsed_write = 0; PDONE <= #1 1'b0; ->pdone_event; start_write = $time; end end end always @(pdone_event) begin:pdone_process #duration_write PDONE = 1'b1; end /////////////////////////////////////////////////////////////////////////// // Timing control for the Blank Check /////////////////////////////////////////////////////////////////////////// event bcdone_event; always @(rising_edge_BCSTART, reseted) begin:BCtime if (reseted) begin if (rising_edge_BCSTART && BCDONE) begin BCDONE <= #1 1'b0; ->bcdone_event; end end end always @(bcdone_event) begin:bcdone_process #tdevice_BC BCDONE = 1'b1; end ////////////////////////////////////////////////////////////////////////// // Timing control for the Erase Operations ////////////////////////////////////////////////////////////////////////// time elapsed_erase; time duration_erase; time start_erase; always @(posedge reseted) begin disable edone_process; EDONE = 1'b1; end event edone_event; always @(reseted or ESTART) begin: erase integer i; if (reseted) begin if (ESTART && EDONE) begin elapsed_erase = 0; duration_erase = tdevice_SEO; ->edone_event; start_erase = $time; end end end always @(edone_event) begin : edone_process EDONE = 1'b0; #duration_erase EDONE = 1'b1; end ////////////////////////////////////////////////////////////////////////// // Main Behavior Process // combinational process for next state generation ////////////////////////////////////////////////////////////////////////// reg PATTERN_1 = 1'b0; reg PATTERN_2 = 1'b0; reg A_PAT_1 = 1'b0; reg Continuity_Check_1 = 1'b0; reg Continuity_Check_2 = 1'b0; integer DataLo ; //DATA Low Byte integer Data ; //Data word always @(falling_edge_write or reseted or falling_edge_RST or STAT_ACT or rising_edge_BCDONE or rising_edge_EDONE or rising_edge_PDONE) begin: StateGen1 if (falling_edge_write) begin DataLo = D_tmp1; Data = D_tmp; PATTERN_1 = (Addr==16'h555) && (DataLo==8'hAA) ; PATTERN_2 = (Addr==16'h2AA) && (DataLo==8'h55) ; A_PAT_1 = (Addr==16'h555); Continuity_Check_1= (Addr1==28'h5555555) && (Data==16'h5555) ; Continuity_Check_2= (Addr1==28'hAAAAAAA) && (Data==16'hAAAA) ; end if (reseted!=1'b1) next_state = current_state; else case (current_state) RESET : begin if (falling_edge_write) begin if ((PATTERN_1) && ( ~Continuity_Check_1)) next_state = READUL1; else if (A_PAT_1 && (DataLo==16'h70)) next_state = READSR; else if (A_PAT_1 && (DataLo==16'h33)) next_state = BLCK; else if (Continuity_Check_1) next_state = CUL1; else next_state = RESET; end end READUL1 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = READUL2; else if (DataLo==16'hF0) next_state = RESET; else next_state = RESET; end end READUL2 : begin if (falling_edge_write) begin if (DataLo==16'h25) next_state = WBPGMS_WBCNT; else if (A_PAT_1 && (DataLo==16'h80)) next_state = ER; else if (A_PAT_1 && (DataLo==16'h90)) next_state = AS; else if (A_PAT_1 && (DataLo==16'h75)) next_state = ECC_ENTRY; else if (DataLo==16'hF0) next_state = RESET; else next_state = RESET; end end READSR : begin if (~STAT_ACT) next_state = RESET; else next_state = READSR; end BLCK : begin if ((falling_edge_write) && (A_PAT_1 && (DataLo==16'h70))) next_state = BLCKSR; else if (rising_edge_BCDONE) next_state = RESET; end BLCKSR : begin if (~STAT_ACT) begin if (~BCDONE) next_state = BLCK; else next_state = RESET; end else begin next_state = BLCKSR; end end CUL1 : begin if (falling_edge_write) begin if (Continuity_Check_2) next_state = RESET; else if (DataLo==16'hF0) next_state = RESET; else next_state = RESET; end end AS : begin if (falling_edge_write) begin if (DataLo==16'hF0) next_state = RESET; else next_state = AS; end end ER : begin if (falling_edge_write) begin if (PATTERN_1) next_state = ERUL1; else next_state = RESET; end end ERUL1 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = ERUL2; else next_state = RESET; end end ERUL2 : begin if (falling_edge_write) begin if (DataLo==16'h30) next_state = SER; else next_state = RESET; end end SER : begin if ((falling_edge_write) && (A_PAT_1 && (DataLo==16'h70))) next_state = ERSR; else if (rising_edge_EDONE) next_state = RESET; end ERSR : begin if (~STAT_ACT) begin if (~EDONE) next_state = SER; else next_state = RESET; end else begin next_state = ERSR; end end WBPGMS_WBCNT : begin if (falling_edge_write) begin if ((SecAddr == SA) && (Data < 256)) next_state = WBPGMS_WBLSTA; else next_state = RESET; end end WBPGMS_WBLSTA : begin if (falling_edge_write) begin if (SecAddr == SA) // fix WriteBufferPage WBPage if (LCNT > 0) next_state = WBPGMS_WBLOAD; else next_state = WBPGMS_CONFB; else next_state = RESET; end end WBPGMS_WBLOAD : begin if (falling_edge_write) begin if (WPage==WBPage) if (LCNT>0) next_state = WBPGMS_WBLOAD; else next_state = WBPGMS_CONFB; else next_state = RESET; end end WBPGMS_CONFB : begin if (falling_edge_write) begin if ((SecAddr == SA) && (DataLo == 16'h29)) next_state = PG; //WBPGMS else next_state = RESET; end end PG : begin if ((falling_edge_write) && (A_PAT_1 && (DataLo==16'h70))) next_state = PGSR; else if (rising_edge_PDONE) next_state = RESET; end PGSR : begin if (~STAT_ACT) begin if (~PDONE) next_state = PG; else next_state = RESET; end else begin next_state = PGSR; end end ECC_ENTRY : begin if (falling_edge_write && (DataLo==16'hF0)) next_state = RESET; end endcase end /////////////////////////////////////////////////////////////////////////// //FSM Output generation and general functionality /////////////////////////////////////////////////////////////////////////// integer i,j,k; always @(falling_edge_write or rising_edge_read or D_tmp or D_tmp1 or falling_edge_RST or reseted or gOE_n or A_event or reseted or rising_edge_PDONE or rising_edge_EDONE or rising_edge_BCDONE) begin : Functional if (falling_edge_write) begin DataLo = D_tmp1; Data = D_tmp; PATTERN_1 = (Addr == 12'h555 && DataLo == 8'hAA); PATTERN_2 = (Addr == 12'h2AA && DataLo == 8'h55); A_PAT_1 = Addr == 12'h555; Continuity_Check_1= (Addr1==28'h5555555) && (Data==16'h5555) ; Continuity_Check_2= (Addr1==28'hAAAAAAA) && (Data==16'hAAAA) ; end oe = rising_edge_read || (read && A_event); if (falling_edge_RST && ~RESETNeg) begin STAT_ACT = 0; StatusReg[7] = 1; StatusReg[6:0] = 7'b0000000; end if (reseted ==1) begin case (current_state) RESET : begin StatusReg[7] = 1; if (falling_edge_write) begin if ((Addr == 16'h555) && (DataLo == 16'h70) && (STAT_ACT == 1'b0)) begin STAT_ACT = 1'b1; end else if ((Addr == 16'h555) && (DataLo == 16'h71)) begin StatusReg[5:3] = 3'b0; StatusReg[0] = 1'b0; STAT_ACT = 1'b0; end else if (A_PAT_1 && (DataLo == 16'h33)) begin BCSTART = 1'b1; BCSTART <= #1 1'b0; StatusReg[7] = 0; StatusReg[5] = 0; SA = SecAddr; STAT_ACT = 0; end else if (Continuity_Check_1) CHECK_ACT = 1'b1; end if (oe) begin DOut_zd[15:0] = READMEM(SecAddr, Address); end end READUL1 : begin end READUL2 : begin if (falling_edge_write) begin if (DataLo == 16'h25) begin //fix SA SA = SecAddr; end end end READSR : begin if (oe && STAT_ACT == 1'b1) begin DOut_zd= StatusReg; STAT_ACT = 1'b0; end end BLCK : begin if (falling_edge_write) begin if (A_PAT_1 && DataLo == 16'h70 && ~STAT_ACT) STAT_ACT = 1; end if (oe) begin DOut_zd[15:0] = 16'bxxxx; end if (rising_edge_BCDONE) begin StatusReg[7] = 1; StatusReg[5] = 0; for (j=SA*SecSize;j<=SA*SecSize+SecSize;j=j+1) begin if ( Mem[j] != MaxData) StatusReg[5] = 1; end STAT_ACT = 0; end end BLCKSR : begin if (oe && STAT_ACT == 1'b1) begin DOut_zd= StatusReg; STAT_ACT = 1'b0; end if (rising_edge_BCDONE) begin StatusReg[7] = 1; StatusReg[5] = 0; for (j=SA*(SecSize+1);j<=SA*(SecSize+1)+SecSize;j=j+1) begin if ( Mem[j] != MaxData) StatusReg[5] = 1; end STAT_ACT = 0; end end CUL1 : begin if (falling_edge_write) begin if ((Continuity_Check_2) && (~Continuity_Check_1) && (CHECK_ACT == 1'b1)) begin StatusReg[0] = 1; CHECK_ACT = 1'b0; end end end AS : begin if (oe) begin if (Addr == 0) DOut_zd[15:0] = 16'h0001; else if (Addr == 1) DOut_zd[15:0] = 16'h227E; else if (Addr == 2) DOut_zd[15:0] = 16'h0000; else if (Addr == 3) DOut_zd[15:0] = 16'hFFFF; else if ( Addr>=16'h04 && Addr<=16'h0B) DOut_zd[15:0] = 16'hFFFF; else if (Addr==16'h0C) begin DOut_zd[15:4] = 0; DOut_zd[3:2] = 0;//Classic cmd set DOut_zd[1] = 0;//DQ bit polling not supported DOut_zd[0] = 1;//Status register supported end else if (Addr == 16'h0D) DOut_zd[15:0] = 0; else if (Addr == 16'h0E) DOut_zd[15:0] =16'h225E; else if (Addr == 16'h0F) DOut_zd[15:0] =16'h2201; else if ( Addr>=16'h0010 && Addr<=16'h1FFF) DOut_zd[15:0] = 16'hFFFF; end end ER : begin end ERUL1 : begin end ERUL2 : begin if (falling_edge_write) begin ESTART = 1'b1; ESTART <= #1 1'b0; StatusReg[7:0] = 8'b00000000; SA = SecAddr; ER_FLAG = 0; end end SER : begin if (falling_edge_write) begin if ((Addr == 16'h555) && (DataLo == 16'h70) && (STAT_ACT == 1'b0)) begin STAT_ACT = 1'b1; end end if (~ER_FLAG) begin ER_FLAG = 1; for (i=SA*(SecSize+1);i<=SA*(SecSize+1)+SecSize;i=i+1) begin Mem[i] = -1; end end if (rising_edge_EDONE)//rising edge begin ER_FLAG = 0; for (i=0;i<= SecSize;i=i+1) begin Mem[SA * (SecSize+1) + i] = MaxData; ECCPage = (SA * (SecSize+1) + i)/16'h10; ECC_array[ECCPage] = 0; ECC_WB_array[ECCPage] = 0; end StatusReg[7] = 1; end end ERSR : begin if (oe && STAT_ACT == 1'b1) begin DOut_zd= StatusReg; STAT_ACT = 1'b0; end if (rising_edge_EDONE)//rising edge begin ER_FLAG = 0; for (i=0;i<= SecSize;i=i+1) begin Mem[SA * (SecSize+1) + i] = MaxData; ECCPage = (SA * (SecSize+1) + i)/16'h10; ECC_array[ECCPage] = 0; ECC_WB_array[ECCPage] = 0; end StatusReg[7] = 1; end end WBPGMS_WBCNT : begin if (falling_edge_write) begin if ((SecAddr == SA) && Data <256) begin cnt = Data; PCNT = cnt; LCNT = cnt; end else StatusReg[4] = 1; end end WBPGMS_WBLSTA : begin if (falling_edge_write) begin if(SecAddr == SA) // fix WriteBufferPage WBPage begin WBData[cnt] = -1; if (~Viol) begin WBData[cnt] = Data; end WBAddr[cnt] = Address % 256; if (cnt>0) begin cnt = cnt -1; end WBPage = WPage; end LCNT = cnt; end end WBPGMS_WBLOAD : begin if (falling_edge_write) begin if (WPage == WBPage) begin WBData[cnt] = -1; if (~Viol) begin WBData[cnt] = Data; end WBAddr[cnt] = Address % 256; if (cnt>0) begin cnt = cnt -1; end end else begin StatusReg[4] = 1; end LCNT = cnt; end end WBPGMS_CONFB : begin if (falling_edge_write) begin if ((SecAddr == SA) && (DataLo == 16'h29)) begin PSTART = 1'b1; PSTART <= #1 1'b0; StatusReg[7] = 0; PR_FLAG = 0; end else begin StatusReg[4] = 1; end end end PG : begin if (falling_edge_write) begin if ((Addr == 16'h555) && (DataLo == 16'h70) && (STAT_ACT == 1'b0)) begin STAT_ACT = 1'b1; end end if ( ~PR_FLAG ) begin PR_FLAG = 1; BaseLoc = WBPage * 256; wr_cnt = PCNT; for (i=wr_cnt;i>=0;i=i-1) begin new_int= WBData[i]; old_int=Mem[SA*(SecSize+1) + BaseLoc+WBAddr[i]]; if (new_int>-1) begin new_bit = new_int; if (old_int>-1) begin old_bit = old_int; for(j=0;j<=15;j=j+1) begin if (~old_bit[j]) new_bit[j]=1'b0; end end else begin new_bit[0] = 1'bx; end if( new_bit[0] !== 1'bx ) begin new_int=new_bit; WBData[i]= new_int; end else WBData[i]= -1; end else WBData[i]= -1; end for (i=wr_cnt;i>=0;i=i-1) begin //mem write Mem[SA*(SecSize+1)+BaseLoc+WBAddr[i]] = -1; end end if (rising_edge_PDONE) begin PR_FLAG = 0; for (i=wr_cnt;i>=0;i=i-1) begin if (WBAddr[i]> -1 && WBData[i] > -1) begin Mem[SA*(SecSize+1)+BaseLoc+WBAddr[i]] = WBData[i]; ECCPage = (SA * (SecSize+1) + (BaseLoc + WBAddr[i]))/16'h10; if(ECC_WB_array[ECCPage] == 1) begin ECC_array[ECCPage] = 1; end ECC_WB_array[ECCPage] = 1; end WBData[i]= -1; end end if (rising_edge_PDONE) begin StatusReg[7] = 1; end end PGSR : begin if (oe && STAT_ACT == 1'b1) begin DOut_zd= StatusReg; STAT_ACT = 1'b0; end if (rising_edge_PDONE) begin PR_FLAG = 0; for (i=wr_cnt;i>=0;i=i-1) begin if (WBAddr[i]> -1 && WBData[i] > -1) begin Mem[SA*(SecSize+1)+BaseLoc+WBAddr[i]] = WBData[i]; ECCPage = (SA * (SecSize+1) + (BaseLoc + WBAddr[i]))/16'h10; if(ECC_WB_array[ECCPage] == 1) begin ECC_array[ECCPage] = 1; end ECC_WB_array[ECCPage] = 1; end WBData[i]= -1; end end if (rising_edge_PDONE) begin StatusReg[7] = 1; end end ECC_ENTRY : begin if (oe) begin ECCPage = (SecAddr * (SecSize+1) + Address)/16'h10; DOut_zd[15:0] = 15'b0; DOut_zd[0] = ECC_array[ECCPage]; end end endcase end end//functionality always @(posedge read) begin ->oe_event; end always @(Address) begin if (read) ->oe_event; end always @(oe_event) begin oe = 1'b1; #1 oe = 1'b0; end //Output timing control always @(DOut_zd) begin : OutputGen if (DOut_zd[0] !== 1'bz) begin CEDQ_t = CENeg_event + CEDQ_01; OEDQ_t = OENeg_event + OEDQ_01; if (RPchange) ADDRDQ_t = ADDR_event + ADDRDQ_01_LONG; else ADDRDQ_t = ADDR_event + ADDRDQ_01_SHORT; FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time)); FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time)); FROMADDR = 1'b1; if ((ADDRDQ_t > $time )&& (((ADDRDQ_t>OEDQ_t)&&FROMOE) || ((ADDRDQ_t>CEDQ_t)&&FROMCE))) begin TempData = DOut_zd; FROMADDR = 1'b0; DOut_Pass[15:0] = 16'hxxxx; DOut_Pass <= #( ADDRDQ_t - $time ) TempData; end else begin DOut_Pass = DOut_zd; end end end always @(A) begin A_event = 1; #1 A_event = 0; end always @(posedge reseted) begin rising_edge_reseted = 1; #1 rising_edge_reseted = 0; end always @(negedge RESETNeg) begin falling_edge_RESETNeg = 1; #1 falling_edge_RESETNeg = 0; end always @(posedge RESETNeg) begin rising_edge_RESETNeg = 1; #1 rising_edge_RESETNeg = 0; end always @(negedge WENeg) begin falling_edge_WENeg = 1; #1 falling_edge_WENeg = 0; end always @(negedge CENeg) begin falling_edge_CENeg = 1; #1 falling_edge_CENeg = 0; end always @(negedge OENeg) begin falling_edge_OENeg = 1; #1 falling_edge_OENeg = 0; end always @(posedge WENeg) begin rising_edge_WENeg = 1; #1 rising_edge_WENeg = 0; end always @(posedge CENeg) begin rising_edge_CENeg = 1; #1 rising_edge_CENeg = 0; end always @(posedge write) begin rising_edge_write = 1; #1 rising_edge_write = 0; end always @(negedge write) begin falling_edge_write = 1; #1 falling_edge_write = 0; end always @(posedge read) begin rising_edge_read = 1; #1 rising_edge_read = 0; end always @(negedge RST) begin falling_edge_RST = 1; #1 falling_edge_RST = 0; end always @(posedge PDONE) begin rising_edge_PDONE = 1; #1 rising_edge_PDONE = 0; end always @(posedge EDONE) begin rising_edge_EDONE = 1; #1 rising_edge_EDONE = 0; end always @(posedge BCSTART) begin rising_edge_BCSTART = 1; #1 rising_edge_BCSTART = 0; end always @(posedge BCDONE) begin rising_edge_BCDONE = 1; #1 rising_edge_BCDONE = 0; end always @(posedge PSTART) begin rising_edge_PSTART = 1; #1 rising_edge_PSTART = 0; end always @(posedge ESTART) begin rising_edge_ESTART = 1; #1 rising_edge_ESTART = 0; end always @(DOut_zd) begin if (DOut_zd[0] === 1'bz) begin disable OutputGen; FROMCE = 1'b1; FROMOE = 1'b1; FROMADDR = 1'b0; DOut_Pass = DOut_zd; end end always @(gOE_n or RESETNeg or RST or gCE_n) begin //Output Disable Control if (gOE_n || gCE_n || (~RESETNeg && ~RST)) DOut_zd = 16'bZ; end function[15:0] READMEM; input sector; input Address; integer sector; integer Address; integer AddrBASE; integer Data; begin AddrBASE = sector * (SecSize+1); Data = Mem[AddrBASE + Address]; if ( Data == -1 ) READMEM = 16'hxxxx; else READMEM = Data; end endfunction reg BuffInOE, BuffInCE, BuffInADDR_S, BuffInADDR_L; wire BuffOutOE, BuffOutCE, BuffOutADDR_S, BuffOutADDR_L; BUFFER BUFOE (BuffOutOE, BuffInOE); BUFFER BUFCE (BuffOutCE, BuffInCE); BUFFER BUFADDR_SHORT (BuffOutADDR_S, BuffInADDR_S); BUFFER BUFADDR_LONG (BuffOutADDR_L, BuffInADDR_L); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInADDR_S = 1'b1; BuffInADDR_L = 1'b1; end always @(posedge BuffOutOE) begin OEDQ_01 = $time; end always @(posedge BuffOutCE) begin CEDQ_01 = $time; end always @(posedge BuffOutADDR_S) begin ADDRDQ_01_SHORT = $time; end always @(posedge BuffOutADDR_L) begin ADDRDQ_01_LONG = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule