////////////////////////////////////////////////////////////////////////////// // File name : s29al641k.v ////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY : // // // version: | author: | mod date: | changes made: // V1.0 D.Kecan 07 Apr 28 Initial release // ////////////////////////////////////////////////////////////////////////////// // // PART DESCRIPTION: // // Library: FLASH // Technology: Flash memory // Part: s29al641k // // Description: 64Mbit (4M x 16-Bit) Flash Memory // // // /////////////////////////////////////////////////////////////////////////////// // Known Bugs: // /////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module s29al641k ( A21 , A20 , A19 , A18 , A17 , A16 , A15 , A14 , A13 , A12 , A11 , A10 , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 , DQ15 , DQ14 , DQ13 , DQ12 , DQ11 , DQ10 , DQ9 , DQ8 , DQ7 , DQ6 , DQ5 , DQ4 , DQ3 , DQ2 , DQ1 , DQ0 , CENeg , OENeg , WENeg , WPNeg , ACC , RESETNeg ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input A21 ; input A20 ; input A19 ; input A18 ; input A17 ; input A16 ; input A15 ; input A14 ; input A13 ; input A12 ; input A11 ; input A10 ; input A9 ; input A8 ; input A7 ; input A6 ; input A5 ; input A4 ; input A3 ; input A2 ; input A1 ; input A0 ; inout DQ15 ; inout DQ14 ; inout DQ13 ; inout DQ12 ; inout DQ11 ; inout DQ10 ; inout DQ9 ; inout DQ8 ; inout DQ7 ; inout DQ6 ; inout DQ5 ; inout DQ4 ; inout DQ3 ; inout DQ2 ; inout DQ1 ; inout DQ0 ; input CENeg ; input OENeg ; input WENeg ; input RESETNeg ; input WPNeg ; input ACC ; // interconnect path delay signals wire A21_ipd ; wire A20_ipd ; wire A19_ipd ; wire A18_ipd ; wire A17_ipd ; wire A16_ipd ; wire A15_ipd ; wire A14_ipd ; wire A13_ipd ; wire A12_ipd ; wire A11_ipd ; wire A10_ipd ; wire A9_ipd ; wire A8_ipd ; wire A7_ipd ; wire A6_ipd ; wire A5_ipd ; wire A4_ipd ; wire A3_ipd ; wire A2_ipd ; wire A1_ipd ; wire A0_ipd ; wire [21 : 0] A; assign A = { A21_ipd, A20_ipd, A19_ipd, A18_ipd, A17_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire DQ15_ipd ; wire DQ14_ipd ; wire DQ13_ipd ; wire DQ12_ipd ; wire DQ11_ipd ; wire DQ10_ipd ; wire DQ9_ipd ; wire DQ8_ipd ; wire DQ7_ipd ; wire DQ6_ipd ; wire DQ5_ipd ; wire DQ4_ipd ; wire DQ3_ipd ; wire DQ2_ipd ; wire DQ1_ipd ; wire DQ0_ipd ; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire CENeg_ipd ; wire OENeg_ipd ; wire WENeg_ipd ; wire RESETNeg_ipd ; wire BYTENeg_ipd ; wire WPNeg_ipd ; // internal delays reg HANG_out ; // Program/Erase Timing Limit reg HANG_in ; reg START_T1 ; // Start TimeOut reg START_T1_in ; reg CTMOUT ; // Sector Erase TimeOut reg CTMOUT_in ; reg READY_in ; reg READY ; // Device ready after reset wire DQ15_zd ; wire DQ14_zd ; wire DQ13_zd ; wire DQ12_zd ; wire DQ11_zd ; wire DQ10_zd ; wire DQ9_zd ; wire DQ8_zd ; wire DQ7_zd ; wire DQ6_zd ; wire DQ5_zd ; wire DQ4_zd ; wire DQ3_zd ; wire DQ2_zd ; wire DQ1_zd ; wire DQ0_zd ; reg [15 : 0] DOut_zd; assign {DQ15_zd, DQ14_zd, DQ13_zd, DQ12_zd, DQ11_zd, DQ10_zd, DQ9_zd, DQ8_zd, DQ7_zd, DQ6_zd, DQ5_zd, DQ4_zd, DQ3_zd, DQ2_zd, DQ1_zd, DQ0_zd } = DOut_zd; wire DQ15_Pass ; wire DQ14_Pass ; wire DQ13_Pass ; wire DQ12_Pass ; wire DQ11_Pass ; wire DQ10_Pass ; wire DQ9_Pass ; wire DQ8_Pass ; wire DQ7_Pass ; wire DQ6_Pass ; wire DQ5_Pass ; wire DQ4_Pass ; wire DQ3_Pass ; wire DQ2_Pass ; wire DQ1_Pass ; wire DQ0_Pass ; reg [15 : 0] DOut_Pass; assign {DQ15_Pass, DQ14_Pass, DQ13_Pass, DQ12_Pass, DQ11_Pass, DQ10_Pass, DQ9_Pass, DQ8_Pass, DQ7_Pass, DQ6_Pass, DQ5_Pass, DQ4_Pass, DQ3_Pass, DQ2_Pass, DQ1_Pass, DQ0_Pass } = DOut_Pass; parameter TimingChecksOn = 1'b0; //Should be =1'b1 when SDF is used parameter UserPreload = 1'b0; parameter mem_file_name = "none"; parameter prot_file_name = "none"; parameter secsi_file_name = "none"; parameter SecGroupNum = 1; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "s29al641k"; parameter MaxData = 255; parameter SecSize64 = 65535; parameter SecSize8 = 16'h1FFF; parameter SecSiSize = 255; parameter SecNum = 134; parameter HiAddrBit = 21; parameter MemSize = 25'h7FFFFF; integer SecNum_ers = 0; integer iter = 0; // If speedsimulation is needed uncomment following line //`define SPEEDSIM; //varaibles to resolve if bottom or top architecture is used reg [20*8-1:0] tmp_timing;//stores copy of TimingModel reg [20*8-1:0] tmp1_timing;//stores copy of TimingModel reg [7:0] tmp_char,tmp_char1;//stores "t" or "b" character integer found = 1'b0; reg [SecNum:0] Ers_queue = 0; // = SecNum'b0; // powerup reg PoweredUp; //FSM control signals reg ULBYPASS = 0 ; ////Unlock Bypass Active reg ESP_ACT =0; ////Erase Suspend reg OTP_ACT ; ////SecSi Access reg AS_ACT ; reg PSUSP = 0; // suspend programming reg PRES = 0; // Resume Programming reg PDONE ; ////Prog. Done reg PSTART ; ////Start Programming //Program location is in protected sector reg PERR = 0 ; //Erase location is in protected sector reg EERR = 0 ; reg EDONE ; ////Ers. Done reg ESTART ; ////Start Erase reg ESUSP ; ////Suspend Erase reg ERES ; ////Resume Erase //Command Register reg write ; reg read ; reg write_wait; reg ProtBit = 1'b1; reg START_in = 0; // Program/Erase suspend reg START_out = 0; // Timeout integer SecSiMem [0 : 255]; integer sgsaT [0:SecGroupNum]; integer sgsaB [0:SecGroupNum]; //Sector Address integer SecAddr = 0; integer SA_ERS = 0; integer SA = 0; //Address in memory integer Address = 0; //Address on the address lines integer Addr = 0; integer D_tmp0 = 0; integer D_tmp1 = 0; integer SecSiAddr = 0; //glitch protection wire gWE_n ; wire gCE_n ; wire gOE_n ; reg RST ; reg reseted ; integer WData[0:1]; integer WAddr[0:1]; integer Memory[0:MemSize]; //Sector Protection Status reg [SecNum:0] Sec_Prot = 0; reg [1:0] WPSec; // timing check violation reg Viol = 1'b0; // CFI query address integer SecSi[0:SecSiSize]; integer CFI_array[16:80]; //Status reg. reg[7:0] Status = 8'b0; reg[7:0] old_bit, new_bit; integer wr_cnt; integer S_ind = 0; integer ind = 0; integer i,j,k; //TPD_XX_DATA time OEDQ_t; time CEDQ_t; time ADDRDQ_t; time OENeg_event; time CENeg_event; time OENeg_posEvent; time CENeg_posEvent; time ADDR_event; reg FROMOE; reg FROMCE; reg FROMADDR; integer OEDQ_01; integer CEDQ_01; integer ADDRDQ_01; integer ADDRDQ; reg [15:0] TempData; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (A21_ipd, A21); buf (A20_ipd, A20); buf (A19_ipd, A19); buf (A18_ipd, A18); buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (CENeg_ipd , CENeg ); buf (OENeg_ipd , OENeg ); buf (WENeg_ipd , WENeg ); buf (RESETNeg_ipd , RESETNeg ); buf (WPNeg_ipd , WPNeg ); buf (ACC_ipd , ACC ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_zd , 1); nmos (DQ14, DQ14_zd , 1); nmos (DQ13, DQ13_zd , 1); nmos (DQ12, DQ12_zd , 1); nmos (DQ11, DQ11_zd , 1); nmos (DQ10, DQ10_zd , 1); nmos (DQ9 , DQ9_zd , 1); nmos (DQ8 , DQ8_zd , 1); nmos (DQ7 , DQ7_zd , 1); nmos (DQ6 , DQ6_zd , 1); nmos (DQ5 , DQ5_zd , 1); nmos (DQ4 , DQ4_zd , 1); nmos (DQ3 , DQ3_zd , 1); nmos (DQ2 , DQ2_zd , 1); nmos (DQ1 , DQ1_zd , 1); nmos (DQ0 , DQ0_zd , 1); wire deg; //VHDL VITAL CheckEnable equivalents // Address setup/hold near WE# falling edge wire CheckEnable_A0_WE; assign CheckEnable_A0_WE = ~CENeg && OENeg; // Data setup/hold near WE# rising edge wire CheckEnable_DQ0_WE; assign CheckEnable_DQ0_WE = ~CENeg && OENeg && deg; // Address setup/hold near CE# falling edge wire CheckEnable_A0_CE; assign CheckEnable_A0_CE = ~WENeg && OENeg; // Data setup/hold near CE# rising edge wire CheckEnable_DQ0_CE; assign CheckEnable_DQ0_CE = ~WENeg && OENeg && deg; // Needed for TimingChecks, VHDL CheckEnable Equivalent specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_A0_DQ0 =1; specparam tpd_A0_DQ1 =1; specparam tpd_A0_DQ2 =1; specparam tpd_A0_DQ3 =1; specparam tpd_A0_DQ4 =1; specparam tpd_A0_DQ5 =1; specparam tpd_A0_DQ6 =1; specparam tpd_A0_DQ7 =1; specparam tpd_A0_DQ8 =1; specparam tpd_A0_DQ9 =1; specparam tpd_A0_DQ10 =1; specparam tpd_A0_DQ11 =1; specparam tpd_A0_DQ12 =1; specparam tpd_A0_DQ13 =1; specparam tpd_A0_DQ14 =1; specparam tpd_A0_DQ15 =1; specparam tpd_A1_DQ0 =1; specparam tpd_A1_DQ1 =1; specparam tpd_A1_DQ2 =1; specparam tpd_A1_DQ3 =1; specparam tpd_A1_DQ4 =1; specparam tpd_A1_DQ5 =1; specparam tpd_A1_DQ6 =1; specparam tpd_A1_DQ7 =1; specparam tpd_A1_DQ8 =1; specparam tpd_A1_DQ9 =1; specparam tpd_A1_DQ10 =1; specparam tpd_A1_DQ11 =1; specparam tpd_A1_DQ12 =1; specparam tpd_A1_DQ13 =1; specparam tpd_A1_DQ14 =1; specparam tpd_A1_DQ15 =1; specparam tpd_A2_DQ0 =1; specparam tpd_A2_DQ1 =1; specparam tpd_A2_DQ2 =1; specparam tpd_A2_DQ3 =1; specparam tpd_A2_DQ4 =1; specparam tpd_A2_DQ5 =1; specparam tpd_A2_DQ6 =1; specparam tpd_A2_DQ7 =1; specparam tpd_A2_DQ8 =1; specparam tpd_A2_DQ9 =1; specparam tpd_A2_DQ10 =1; specparam tpd_A2_DQ11 =1; specparam tpd_A2_DQ12 =1; specparam tpd_A2_DQ13 =1; specparam tpd_A2_DQ14 =1; specparam tpd_A2_DQ15 =1; specparam tpd_A3_DQ0 =1; specparam tpd_A3_DQ1 =1; specparam tpd_A3_DQ2 =1; specparam tpd_A3_DQ3 =1; specparam tpd_A3_DQ4 =1; specparam tpd_A3_DQ5 =1; specparam tpd_A3_DQ6 =1; specparam tpd_A3_DQ7 =1; specparam tpd_A3_DQ8 =1; specparam tpd_A3_DQ9 =1; specparam tpd_A3_DQ10 =1; specparam tpd_A3_DQ11 =1; specparam tpd_A3_DQ12 =1; specparam tpd_A3_DQ13 =1; specparam tpd_A3_DQ14 =1; specparam tpd_A3_DQ15 =1; specparam tpd_A4_DQ0 =1; specparam tpd_A4_DQ1 =1; specparam tpd_A4_DQ2 =1; specparam tpd_A4_DQ3 =1; specparam tpd_A4_DQ4 =1; specparam tpd_A4_DQ5 =1; specparam tpd_A4_DQ6 =1; specparam tpd_A4_DQ7 =1; specparam tpd_A4_DQ8 =1; specparam tpd_A4_DQ9 =1; specparam tpd_A4_DQ10 =1; specparam tpd_A4_DQ11 =1; specparam tpd_A4_DQ12 =1; specparam tpd_A4_DQ13 =1; specparam tpd_A4_DQ14 =1; specparam tpd_A4_DQ15 =1; specparam tpd_A5_DQ0 =1; specparam tpd_A5_DQ1 =1; specparam tpd_A5_DQ2 =1; specparam tpd_A5_DQ3 =1; specparam tpd_A5_DQ4 =1; specparam tpd_A5_DQ5 =1; specparam tpd_A5_DQ6 =1; specparam tpd_A5_DQ7 =1; specparam tpd_A5_DQ8 =1; specparam tpd_A5_DQ9 =1; specparam tpd_A5_DQ10 =1; specparam tpd_A5_DQ11 =1; specparam tpd_A5_DQ12 =1; specparam tpd_A5_DQ13 =1; specparam tpd_A5_DQ14 =1; specparam tpd_A5_DQ15 =1; specparam tpd_A6_DQ0 =1; specparam tpd_A6_DQ1 =1; specparam tpd_A6_DQ2 =1; specparam tpd_A6_DQ3 =1; specparam tpd_A6_DQ4 =1; specparam tpd_A6_DQ5 =1; specparam tpd_A6_DQ6 =1; specparam tpd_A6_DQ7 =1; specparam tpd_A6_DQ8 =1; specparam tpd_A6_DQ9 =1; specparam tpd_A6_DQ10 =1; specparam tpd_A6_DQ11 =1; specparam tpd_A6_DQ12 =1; specparam tpd_A6_DQ13 =1; specparam tpd_A6_DQ14 =1; specparam tpd_A6_DQ15 =1; specparam tpd_A7_DQ0 =1; specparam tpd_A7_DQ1 =1; specparam tpd_A7_DQ2 =1; specparam tpd_A7_DQ3 =1; specparam tpd_A7_DQ4 =1; specparam tpd_A7_DQ5 =1; specparam tpd_A7_DQ6 =1; specparam tpd_A7_DQ7 =1; specparam tpd_A7_DQ8 =1; specparam tpd_A7_DQ9 =1; specparam tpd_A7_DQ10 =1; specparam tpd_A7_DQ11 =1; specparam tpd_A7_DQ12 =1; specparam tpd_A7_DQ13 =1; specparam tpd_A7_DQ14 =1; specparam tpd_A7_DQ15 =1; specparam tpd_A8_DQ0 =1; specparam tpd_A8_DQ1 =1; specparam tpd_A8_DQ2 =1; specparam tpd_A8_DQ3 =1; specparam tpd_A8_DQ4 =1; specparam tpd_A8_DQ5 =1; specparam tpd_A8_DQ6 =1; specparam tpd_A8_DQ7 =1; specparam tpd_A8_DQ8 =1; specparam tpd_A8_DQ9 =1; specparam tpd_A8_DQ10 =1; specparam tpd_A8_DQ11 =1; specparam tpd_A8_DQ12 =1; specparam tpd_A8_DQ13 =1; specparam tpd_A8_DQ14 =1; specparam tpd_A8_DQ15 =1; specparam tpd_A9_DQ0 =1; specparam tpd_A9_DQ1 =1; specparam tpd_A9_DQ2 =1; specparam tpd_A9_DQ3 =1; specparam tpd_A9_DQ4 =1; specparam tpd_A9_DQ5 =1; specparam tpd_A9_DQ6 =1; specparam tpd_A9_DQ7 =1; specparam tpd_A9_DQ8 =1; specparam tpd_A9_DQ9 =1; specparam tpd_A9_DQ10 =1; specparam tpd_A9_DQ11 =1; specparam tpd_A9_DQ12 =1; specparam tpd_A9_DQ13 =1; specparam tpd_A9_DQ14 =1; specparam tpd_A9_DQ15 =1; specparam tpd_A10_DQ0 =1; specparam tpd_A10_DQ1 =1; specparam tpd_A10_DQ2 =1; specparam tpd_A10_DQ3 =1; specparam tpd_A10_DQ4 =1; specparam tpd_A10_DQ5 =1; specparam tpd_A10_DQ6 =1; specparam tpd_A10_DQ7 =1; specparam tpd_A10_DQ8 =1; specparam tpd_A10_DQ9 =1; specparam tpd_A10_DQ10 =1; specparam tpd_A10_DQ11 =1; specparam tpd_A10_DQ12 =1; specparam tpd_A10_DQ13 =1; specparam tpd_A10_DQ14 =1; specparam tpd_A10_DQ15 =1; specparam tpd_A11_DQ0 =1; specparam tpd_A11_DQ1 =1; specparam tpd_A11_DQ2 =1; specparam tpd_A11_DQ3 =1; specparam tpd_A11_DQ4 =1; specparam tpd_A11_DQ5 =1; specparam tpd_A11_DQ6 =1; specparam tpd_A11_DQ7 =1; specparam tpd_A11_DQ8 =1; specparam tpd_A11_DQ9 =1; specparam tpd_A11_DQ10 =1; specparam tpd_A11_DQ11 =1; specparam tpd_A11_DQ12 =1; specparam tpd_A11_DQ13 =1; specparam tpd_A11_DQ14 =1; specparam tpd_A11_DQ15 =1; specparam tpd_A12_DQ0 =1; specparam tpd_A12_DQ1 =1; specparam tpd_A12_DQ2 =1; specparam tpd_A12_DQ3 =1; specparam tpd_A12_DQ4 =1; specparam tpd_A12_DQ5 =1; specparam tpd_A12_DQ6 =1; specparam tpd_A12_DQ7 =1; specparam tpd_A12_DQ8 =1; specparam tpd_A12_DQ9 =1; specparam tpd_A12_DQ10 =1; specparam tpd_A12_DQ11 =1; specparam tpd_A12_DQ12 =1; specparam tpd_A12_DQ13 =1; specparam tpd_A12_DQ14 =1; specparam tpd_A12_DQ15 =1; specparam tpd_A13_DQ0 =1; specparam tpd_A13_DQ1 =1; specparam tpd_A13_DQ2 =1; specparam tpd_A13_DQ3 =1; specparam tpd_A13_DQ4 =1; specparam tpd_A13_DQ5 =1; specparam tpd_A13_DQ6 =1; specparam tpd_A13_DQ7 =1; specparam tpd_A13_DQ8 =1; specparam tpd_A13_DQ9 =1; specparam tpd_A13_DQ10 =1; specparam tpd_A13_DQ11 =1; specparam tpd_A13_DQ12 =1; specparam tpd_A13_DQ13 =1; specparam tpd_A13_DQ14 =1; specparam tpd_A13_DQ15 =1; specparam tpd_A14_DQ0 =1; specparam tpd_A14_DQ1 =1; specparam tpd_A14_DQ2 =1; specparam tpd_A14_DQ3 =1; specparam tpd_A14_DQ4 =1; specparam tpd_A14_DQ5 =1; specparam tpd_A14_DQ6 =1; specparam tpd_A14_DQ7 =1; specparam tpd_A14_DQ8 =1; specparam tpd_A14_DQ9 =1; specparam tpd_A14_DQ10 =1; specparam tpd_A14_DQ11 =1; specparam tpd_A14_DQ12 =1; specparam tpd_A14_DQ13 =1; specparam tpd_A14_DQ14 =1; specparam tpd_A14_DQ15 =1; specparam tpd_A15_DQ0 =1; specparam tpd_A15_DQ1 =1; specparam tpd_A15_DQ2 =1; specparam tpd_A15_DQ3 =1; specparam tpd_A15_DQ4 =1; specparam tpd_A15_DQ5 =1; specparam tpd_A15_DQ6 =1; specparam tpd_A15_DQ7 =1; specparam tpd_A15_DQ8 =1; specparam tpd_A15_DQ9 =1; specparam tpd_A15_DQ10 =1; specparam tpd_A15_DQ11 =1; specparam tpd_A15_DQ12 =1; specparam tpd_A15_DQ13 =1; specparam tpd_A15_DQ14 =1; specparam tpd_A15_DQ15 =1; specparam tpd_A16_DQ0 =1; specparam tpd_A16_DQ1 =1; specparam tpd_A16_DQ2 =1; specparam tpd_A16_DQ3 =1; specparam tpd_A16_DQ4 =1; specparam tpd_A16_DQ5 =1; specparam tpd_A16_DQ6 =1; specparam tpd_A16_DQ7 =1; specparam tpd_A16_DQ8 =1; specparam tpd_A16_DQ9 =1; specparam tpd_A16_DQ10 =1; specparam tpd_A16_DQ11 =1; specparam tpd_A16_DQ12 =1; specparam tpd_A16_DQ13 =1; specparam tpd_A16_DQ14 =1; specparam tpd_A16_DQ15 =1; specparam tpd_A17_DQ0 =1; specparam tpd_A17_DQ1 =1; specparam tpd_A17_DQ2 =1; specparam tpd_A17_DQ3 =1; specparam tpd_A17_DQ4 =1; specparam tpd_A17_DQ5 =1; specparam tpd_A17_DQ6 =1; specparam tpd_A17_DQ7 =1; specparam tpd_A17_DQ8 =1; specparam tpd_A17_DQ9 =1; specparam tpd_A17_DQ10 =1; specparam tpd_A17_DQ11 =1; specparam tpd_A17_DQ12 =1; specparam tpd_A17_DQ13 =1; specparam tpd_A17_DQ14 =1; specparam tpd_A17_DQ15 =1; specparam tpd_A18_DQ0 =1; specparam tpd_A18_DQ1 =1; specparam tpd_A18_DQ2 =1; specparam tpd_A18_DQ3 =1; specparam tpd_A18_DQ4 =1; specparam tpd_A18_DQ5 =1; specparam tpd_A18_DQ6 =1; specparam tpd_A18_DQ7 =1; specparam tpd_A18_DQ8 =1; specparam tpd_A18_DQ9 =1; specparam tpd_A18_DQ10 =1; specparam tpd_A18_DQ11 =1; specparam tpd_A18_DQ12 =1; specparam tpd_A18_DQ13 =1; specparam tpd_A18_DQ14 =1; specparam tpd_A18_DQ15 =1; specparam tpd_A19_DQ0 =1; specparam tpd_A19_DQ1 =1; specparam tpd_A19_DQ2 =1; specparam tpd_A19_DQ3 =1; specparam tpd_A19_DQ4 =1; specparam tpd_A19_DQ5 =1; specparam tpd_A19_DQ6 =1; specparam tpd_A19_DQ7 =1; specparam tpd_A19_DQ8 =1; specparam tpd_A19_DQ9 =1; specparam tpd_A19_DQ10 =1; specparam tpd_A19_DQ11 =1; specparam tpd_A19_DQ12 =1; specparam tpd_A19_DQ13 =1; specparam tpd_A19_DQ14 =1; specparam tpd_A19_DQ15 =1; specparam tpd_CENeg_DQ0 =1; specparam tpd_CENeg_DQ1 =1; specparam tpd_CENeg_DQ2 =1; specparam tpd_CENeg_DQ3 =1; specparam tpd_CENeg_DQ4 =1; specparam tpd_CENeg_DQ5 =1; specparam tpd_CENeg_DQ6 =1; specparam tpd_CENeg_DQ7 =1; specparam tpd_CENeg_DQ8 =1; specparam tpd_CENeg_DQ9 =1; specparam tpd_CENeg_DQ10 =1; specparam tpd_CENeg_DQ11 =1; specparam tpd_CENeg_DQ12 =1; specparam tpd_CENeg_DQ13 =1; specparam tpd_CENeg_DQ14 =1; specparam tpd_CENeg_DQ15 =1; specparam tpd_OENeg_DQ0 =1; specparam tpd_OENeg_DQ1 =1; specparam tpd_OENeg_DQ2 =1; specparam tpd_OENeg_DQ3 =1; specparam tpd_OENeg_DQ4 =1; specparam tpd_OENeg_DQ5 =1; specparam tpd_OENeg_DQ6 =1; specparam tpd_OENeg_DQ7 =1; specparam tpd_OENeg_DQ8 =1; specparam tpd_OENeg_DQ9 =1; specparam tpd_OENeg_DQ10 =1; specparam tpd_OENeg_DQ11 =1; specparam tpd_OENeg_DQ12 =1; specparam tpd_OENeg_DQ13 =1; specparam tpd_OENeg_DQ14 =1; specparam tpd_OENeg_DQ15 =1; specparam tpd_DQ15_DQ0 =1; specparam tpd_DQ15_DQ1 =1; specparam tpd_DQ15_DQ2 =1; specparam tpd_DQ15_DQ3 =1; specparam tpd_DQ15_DQ4 =1; specparam tpd_DQ15_DQ5 =1; specparam tpd_DQ15_DQ6 =1; specparam tpd_DQ15_DQ7 =1; specparam tpd_BYTENeg_DQ8 =1; specparam tpd_BYTENeg_DQ9 =1; specparam tpd_BYTENeg_DQ10 =1; specparam tpd_BYTENeg_DQ11 =1; specparam tpd_BYTENeg_DQ12 =1; specparam tpd_BYTENeg_DQ13 =1; specparam tpd_BYTENeg_DQ14 =1; specparam tpd_BYTENeg_DQ15 =1; specparam tpd_RESETNeg_DQ0 =1; specparam tpd_RESETNeg_DQ1 =1; specparam tpd_RESETNeg_DQ2 =1; specparam tpd_RESETNeg_DQ3 =1; specparam tpd_RESETNeg_DQ4 =1; specparam tpd_RESETNeg_DQ5 =1; specparam tpd_RESETNeg_DQ6 =1; specparam tpd_RESETNeg_DQ7 =1; specparam tpd_RESETNeg_DQ8 =1; specparam tpd_RESETNeg_DQ9 =1; specparam tpd_RESETNeg_DQ10 =1; specparam tpd_RESETNeg_DQ11 =1; specparam tpd_RESETNeg_DQ12 =1; specparam tpd_RESETNeg_DQ13 =1; specparam tpd_RESETNeg_DQ14 =1; specparam tpd_RESETNeg_DQ15 =1; // tsetup values: setup time specparam tsetup_A0_WENeg =1; //tAS edge \ specparam tsetup_DQ0_WENeg =1; //tDS edge / specparam tsetup_DQ0_OENeg =1; //tDS edge / // thold values: hold times specparam thold_A0_WENeg =1; //tAH edge \ specparam thold_DQ0_CENeg =1; //tDH edge / specparam thold_DQ0_WENeg =1; //tDH edge / specparam thold_OENeg_WENeg =1; //tOEH edge / specparam thold_CENeg_RESETNeg =1; //tRH edge / specparam thold_WENeg_OENeg =1; //tGHVL edge / // tpw values: pulse width specparam tpw_RESETNeg_negedge =1; //tRP specparam tpw_WENeg_negedge =1; //tWP specparam tpw_WENeg_posedge =1; //tWPH specparam tpw_CENeg_negedge =1; //tCP specparam tpw_CENeg_posedge =1; //tCEPH specparam tpw_A0_negedge =1; //tWC tRC ok specparam tpw_A0_posedge =1; //tWC tRC ok // tdevice values: values for internal delays `ifdef SPEEDSIM //Program Operation specparam tdevice_POW = 7000; //9 us; specparam tdevice_POB = 7000; //9 us; //Sector Erase Operation specparam tdevice_SEO = 400000; //400 us; //Timing Limit Exceeded specparam tdevice_HANG = 400000000; //400 ms; //Erase suspend time specparam tdevice_START_T1 = 20000; //20 us; //sector erase command sequence timeout specparam tdevice_CTMOUT = 50000; //50 us; //device ready after Hardware reset(during embeded algorithm) specparam tdevice_READY = 20000; //20 us; //tReady `else //Program Operation specparam tdevice_POW = 7000; //9 us; specparam tdevice_POB = 7000; //9 us; //Sector Erase Operation specparam tdevice_SEO = 400000000; //700 ms; //Timing Limit Exceeded specparam tdevice_HANG = 400000000; //400 ms; //Erase suspend time specparam tdevice_START_T1 = 20000; //20 us; //sector erase command sequence timeout specparam tdevice_CTMOUT = 50000; //50 us; //device ready after Hardware reset(during embeded algorithm) specparam tdevice_READY = 20000; //20 us; //tReady `endif //SPEEDSIM // If tpd values are fetched from specify block, these parameters // must change along with SDF values, SDF values change will NOT // imlicitly apply here ! // If you want tpd values to be fetched by the model itself, please // use the PLI routine approach but be shure to set parameter // DelayValues to "FROM_PLI" as default /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// //for DQ signals if (FROMCE) ( CENeg => DQ0 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ1 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ2 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ3 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ4 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ5 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ6 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ7 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ8 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ9 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ10 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ11 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ12 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ13 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ14 ) = tpd_CENeg_DQ0; if (FROMCE) ( CENeg => DQ15 ) = tpd_CENeg_DQ0; if (FROMOE) ( OENeg => DQ0 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ1 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ2 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ3 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ4 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ5 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ6 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ7 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ8 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ9 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ10 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ11 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ12 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ13 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ14 ) = tpd_OENeg_DQ0; if (FROMOE) ( OENeg => DQ15 ) = tpd_OENeg_DQ0; if (FROMADDR) ( A0 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A0 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A1 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A2 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A3 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A4 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A5 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A6 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A7 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A8 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A9 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A10 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A11 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A12 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A13 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A14 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A15 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A16 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A17 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A18 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A19 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A20 => DQ15 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ0 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ1 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ2 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ3 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ4 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ5 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ6 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ7 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ8 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ9 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ10 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ11 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ12 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ13 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ14 ) = tpd_A0_DQ0; if (FROMADDR) ( A21 => DQ15 ) = tpd_A0_DQ0; if (~RESETNeg) ( RESETNeg => DQ0 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ1 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ2 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ3 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ4 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ5 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ6 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ7 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ8 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ9 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ10 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ11 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ12 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ13 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ14 ) = tpd_RESETNeg_DQ0; if (~RESETNeg) ( RESETNeg => DQ15 ) = tpd_RESETNeg_DQ0; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// $setup ( A0 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A1 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A2 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A3 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A4 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A5 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A6 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A7 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A8 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A9 , negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A10, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A11, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A12, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A13, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A14, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A15, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A16, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A17, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A18, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A19, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A20, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A21, negedge CENeg &&& CheckEnable_A0_CE, tsetup_A0_WENeg, Viol); $setup ( A0 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A1 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A2 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A3 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A4 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A5 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A6 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A7 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A8 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A9 , negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A10, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A11, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A12, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A13, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A14, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A15, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A16, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A17, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A18, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A19, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A20, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( A21, negedge WENeg &&& CheckEnable_A0_WE, tsetup_A0_WENeg, Viol); $setup ( DQ0, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ1, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ2, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ3, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ4, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ5, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ6, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ7, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ8, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ9, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ10, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ11, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ12, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ13, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ14, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ15, posedge CENeg&&&CheckEnable_DQ0_CE, tsetup_DQ0_WENeg, Viol); $setup ( DQ0, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ1, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ2, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ3, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ4, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ5, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ6, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ7, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ8, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ9, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ10, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ11, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ12, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ13, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ14, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ15, posedge WENeg&&&CheckEnable_DQ0_WE, tsetup_DQ0_WENeg, Viol); $setup ( DQ0, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ1, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ2, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ3, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ4, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ5, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ6, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ7, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ8, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ9, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ10, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ11, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ12, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ13, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ14, posedge OENeg, tsetup_DQ0_OENeg, Viol); $setup ( DQ15, posedge OENeg, tsetup_DQ0_OENeg, Viol); $hold ( posedge RESETNeg&&&(CENeg===1), CENeg, thold_CENeg_RESETNeg, Viol); $hold ( posedge RESETNeg&&&(OENeg===1), OENeg, thold_CENeg_RESETNeg, Viol); $hold ( posedge RESETNeg&&&(WENeg===1), WENeg, thold_CENeg_RESETNeg, Viol); $hold ( posedge OENeg, WENeg , thold_WENeg_OENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A0 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A1 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A2 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A3 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A4 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A5 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A6 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A7 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A8 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A9 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A10 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A11 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A12 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A13 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A14 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A15 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A16 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A17 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A18 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A19 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A20 , thold_A0_WENeg, Viol); $hold ( negedge CENeg &&& CheckEnable_A0_CE, A21 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A0 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A1 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A2 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A3 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A4 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A5 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A6 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A7 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A8 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A9 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A10 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A11 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A12 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A13 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A14 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A15 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A16 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A17 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A18 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A19 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A20 , thold_A0_WENeg, Viol); $hold ( negedge WENeg &&& CheckEnable_A0_WE, A21 , thold_A0_WENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ0, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ1, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ2, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ3, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ4, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ5, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ6, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ7, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ8, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ9, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ10, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ11, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ12, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ13, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ14, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& CheckEnable_DQ0_CE, DQ15, thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ0, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ1, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ2, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ3, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ4, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ5, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ6, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ7, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ8, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ9, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ10, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ11, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ12, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ13, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ14, thold_DQ0_WENeg, Viol); $hold ( posedge WENeg &&& CheckEnable_DQ0_WE, DQ15, thold_DQ0_WENeg, Viol); $width (negedge RESETNeg, tpw_RESETNeg_negedge); $width (posedge WENeg, tpw_WENeg_posedge); $width (negedge WENeg, tpw_WENeg_negedge); $width (posedge CENeg, tpw_CENeg_posedge); $width (negedge CENeg, tpw_CENeg_negedge); $width (negedge A0, tpw_A0_negedge);//ok $width (negedge A1, tpw_A0_negedge);//ok $width (negedge A2, tpw_A0_negedge);//ok $width (negedge A3, tpw_A0_negedge);//ok $width (negedge A4, tpw_A0_negedge);//ok $width (negedge A5, tpw_A0_negedge);//ok $width (negedge A6, tpw_A0_negedge);//ok $width (negedge A7, tpw_A0_negedge);//ok $width (negedge A8, tpw_A0_negedge);//ok $width (negedge A9, tpw_A0_negedge);//ok $width (negedge A10, tpw_A0_negedge);//ok $width (negedge A11, tpw_A0_negedge);//ok $width (negedge A12, tpw_A0_negedge);//ok $width (negedge A13, tpw_A0_negedge);//ok $width (negedge A14, tpw_A0_negedge);//ok $width (negedge A15, tpw_A0_negedge);//ok $width (negedge A16, tpw_A0_negedge);//ok $width (negedge A17, tpw_A0_negedge);//ok $width (negedge A18, tpw_A0_negedge);//ok $width (negedge A19, tpw_A0_negedge);//ok $width (negedge A20, tpw_A0_negedge);//ok $width (negedge A21, tpw_A0_negedge);//ok $width (posedge A0, tpw_A0_posedge);//ok $width (posedge A1, tpw_A0_posedge);//ok $width (posedge A2, tpw_A0_posedge);//ok $width (posedge A3, tpw_A0_posedge);//ok $width (posedge A4, tpw_A0_posedge);//ok $width (posedge A5, tpw_A0_posedge);//ok $width (posedge A6, tpw_A0_posedge);//ok $width (posedge A7, tpw_A0_posedge);//ok $width (posedge A8, tpw_A0_posedge);//ok $width (posedge A9, tpw_A0_posedge);//ok $width (posedge A10, tpw_A0_posedge);//ok $width (posedge A11, tpw_A0_posedge);//ok $width (posedge A12, tpw_A0_posedge);//ok $width (posedge A13, tpw_A0_posedge);//ok $width (posedge A14, tpw_A0_posedge);//ok $width (posedge A15, tpw_A0_posedge);//ok $width (posedge A16, tpw_A0_posedge);//ok $width (posedge A17, tpw_A0_posedge);//ok $width (posedge A18, tpw_A0_posedge);//ok $width (posedge A19, tpw_A0_posedge);//ok $width (posedge A20, tpw_A0_posedge);//ok $width (posedge A21, tpw_A0_posedge);//ok endspecify // FSM states parameter RESET =6'd0; parameter Z001 =6'd1; parameter PREL_SETBWB =6'd2; parameter PREL_ULBYPASS =6'd3; parameter PREL_ULBYPASS_RESET =6'd4; parameter AS =6'd5; parameter AS_Z001 =6'd6; parameter AS_Z002 =6'd7; parameter A0SEEN =6'd8; parameter OTP =6'd9; parameter OTP_Z001 =6'd10; parameter OTP_PREL =6'd11; parameter OTP_A0SEEN =6'd12; parameter OTP_OW_PREL =6'd13; parameter OTP_OW_Z001 =6'd14; parameter OTP_OW_PGMS =6'd15; parameter OTP_OW_STAT =6'd16; parameter OTP_EXIT =6'd17; parameter C8 =6'd18; parameter C8_Z001 =6'd19; parameter C8_PREL =6'd20; parameter ERS =6'd21; parameter SERS =6'd22; parameter ESPS =6'd23; parameter SERS_EXEC =6'd24; parameter ESP =6'd25; parameter ESP_Z001 =6'd26; parameter ESP_PREL =6'd27; parameter ESP_A0SEEN =6'd28; parameter PGMS =6'd29; parameter CFI =6'd30; reg [5:0] current_state; reg [5:0] next_state; reg sector_prot [0:SecNum]; reg deq; always @(DIn, DOut) begin if (DIn==DOut) deq=1'b1; else deq=1'b0; end // check when data is generated from model to avoid setuphold check in // those occasion assign deg =deq; //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// time elapsed, duration, start; integer Data, DataLo,DataHi, AddrCom; reg abc = 0; reg[7:0] temp; reg oe = 0; reg ER_FLAG = 0; reg PR_FLAG = 0; reg INITIAL = 0; reg rising_edge_AVDNeg, falling_edge_AVDNeg; event oe_event; reg rising_edge_gWE_n, falling_edge_gWE_n,falling_edge_reseted; reg rising_edge_gCE_n, falling_edge_gCE_n; reg rising_edge_CENeg, falling_edge_CENeg; reg falling_edge_OENeg, A_event, BYTENeg_event; reg rising_edge_RESETNeg,faling_edge_RST,falling_edge_RESETNeg; reg rising_edge_START_in, rising_edge_read, falling_edge_read; reg rising_edge_reseted, rising_edge_PSTART; reg rising_edge_PSUSP, rising_edge_PRES; reg rising_edge_ESTART, rising_edge_ESUSP, rising_edge_ERES; reg rising_edge_WENeg; reg falling_edge_write, rising_edge_CEDONE,falling_edge_EERR; reg rising_edge_EDONE = 0; reg rising_edge_PDONE; reg rising_edge_START_T1_out = 0; reg rising_edge_START_out, falling_edge_RST; reg rising_edge_OENeg; reg next_state_event; // Power Up time tVCS is 30 us initial begin : PowerupTime PoweredUp = 1'b0; #100 PoweredUp = 1'b1; sgsaT[0] = 30'h000000; sgsaT[1] = 30'h7F0000; sgsaB[0] = 30'h000000; sgsaB[1] = 30'h00FFFF; end // initialize memory and load preoload files if any initial begin: InitMemory integer secsi[0:8'hFF]; tmp_timing = TimingModel; i = 19; while ((i >= 0) && (found != 1'b1))//search for first non null character begin //i keeps position of first non null character j = 7; while ((j >= 0) && (found != 1'b1)) begin if (tmp_timing[i*8+j] != 1'd0) found = 1'b1; else j = j-1; end i = i - 1; end if (found)//if non null character is found begin for (j=0;j<=7;j=j+1) begin tmp_char[j] = tmp_timing[(i-9)*8+j]; tmp_char1[j] = tmp_timing[(i-8)*8+j]; end end for (i=0;i<=8'hFF;i=i+1) begin secsi[i]=MaxData; end for (i=0;i<=MemSize;i=i+1) begin Memory[i]=MaxData; end for (i=0;i<=SecNum;i=i+1) begin sector_prot[i]=0; end if (UserPreload && !(mem_file_name == "none")) begin $readmemh(mem_file_name,Memory); end if (UserPreload && !(secsi_file_name == "none")) begin $readmemh(secsi_file_name,secsi); end if (UserPreload && prot_file_name != "none") begin $readmemb(prot_file_name,sector_prot); end //SecSi Preload for (i=0;i<=8'hFF;i=i+1) begin SecSiMem[i] = secsi[i]; end for (i=0;i<=SecNum;i=i+1) begin Sec_Prot[i] = sector_prot[i]; end if (tmp_char1 == "T" || tmp_char1 == "t") begin iter = 4; while (iter < 121) begin Sec_Prot[iter] = Sec_Prot[iter] || Sec_Prot[iter+1] || Sec_Prot[iter+2] || Sec_Prot[iter+3]; Sec_Prot[iter+1] = Sec_Prot[iter]; Sec_Prot[iter+2] = Sec_Prot[iter]; Sec_Prot[iter+3] = Sec_Prot[iter]; iter = iter + 4; end Sec_Prot[124] = Sec_Prot[124] || Sec_Prot[125] || Sec_Prot[126]; end else if (tmp_char1 == "B" || tmp_char1 == "b") begin Sec_Prot[8] = Sec_Prot[8] || Sec_Prot[9] || Sec_Prot[10]; iter = 11; while (iter < 128) begin Sec_Prot[iter] = Sec_Prot[iter] || Sec_Prot[iter+1] || Sec_Prot[iter+2] || Sec_Prot[iter+3]; Sec_Prot[iter+1] = Sec_Prot[iter]; Sec_Prot[iter+2] = Sec_Prot[iter]; Sec_Prot[iter+3] = Sec_Prot[iter]; iter = iter + 4; end end else if (tmp_char1 == "H" || tmp_char1 == "h" || tmp_char1 == "L" || tmp_char1 == "l") begin iter = 0; while (iter < 61) begin Sec_Prot[iter] = Sec_Prot[iter] || Sec_Prot[iter+1] || Sec_Prot[iter+2] || Sec_Prot[iter+3]; Sec_Prot[iter+1] = Sec_Prot[iter]; Sec_Prot[iter+2] = Sec_Prot[iter]; Sec_Prot[iter+3] = Sec_Prot[iter]; iter = iter + 4; end end end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(posedge START_T1_in) begin:TESTARTT1r #tdevice_START_T1 START_T1 = START_T1_in; end always @(negedge START_T1_in) begin:TESTARTT1f #1 START_T1 = START_T1_in; end always @(negedge OENeg) begin OENeg_event = $time; end always @(negedge CENeg) begin CENeg_event = $time; end always @(posedge OENeg) begin OENeg_posEvent = $time; end always @(posedge CENeg) begin CENeg_posEvent = $time; end always @(RESETNeg) begin RST <= #499 RESETNeg; end always @(A) begin ADDR_event = $time; end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(DOut_zd) begin : OutputGen if (DOut_zd[0] !== 1'bz) begin CEDQ_t = CENeg_event + CEDQ_01; OEDQ_t = OENeg_event + OEDQ_01; ADDRDQ_t = ADDR_event + ADDRDQ; FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time)); FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time)); FROMADDR = 1'b1; if ((ADDRDQ_t > $time) && (((ADDRDQ_t>OEDQ_t) && FROMOE) || ((ADDRDQ_t>CEDQ_t) && FROMCE))) begin TempData = DOut_zd; FROMADDR = 1'b0; DOut_Pass[15:8] = 8'bx; DOut_Pass[7:0] = 8'bx; DOut_Pass <= #(ADDRDQ_t - $time) TempData; end else begin DOut_Pass = DOut_zd; end end end always @(DOut_zd) begin if (DOut_zd[0] === 1'bz) begin disable OutputGen; FROMCE = 1'b1; FROMOE = 1'b1; FROMADDR = 1'b0; DOut_Pass = DOut_zd; end end always @(posedge CTMOUT_in) begin:TCTMOUTr #(tdevice_CTMOUT-5) CTMOUT = CTMOUT_in; end always @(negedge CTMOUT_in) begin:TCTMOUTf #1 CTMOUT = CTMOUT_in; end //////////////////////////////////////////////////////////////////////////// //// sequential process for reset control and FSM state transition //////////////////////////////////////////////////////////////////////////// always @(negedge RST) begin ESP_ACT = 1'b0; ULBYPASS = 1'b0; OTP_ACT = 1'b0; end // sequential process for reset control and FSM state transition always @(next_state_event, RST, PoweredUp,falling_edge_RESETNeg, rising_edge_RESETNeg,RESETNeg,read) begin: StateTransition if (PoweredUp) begin if (RESETNeg) begin if (next_state_event) #1 current_state = next_state; reseted = 1; end else if (~RST) begin // no state transition while RESETNeg is low current_state = RESET; reseted = 0; end end else begin current_state = RESET; reseted = 0; end end // ///////////////////////////////////////////////////////////////////////// // //Glitch Protection: Inertial Delay does not propagate pulses <5ns // ///////////////////////////////////////////////////////////////////////// assign #5 gWE_n = WENeg_ipd; assign #5 gCE_n = CENeg_ipd; assign #5 gOE_n = OENeg_ipd; /////////////////////////////////////////////////////////////////////////// //Process that reports warning when changes on signals WE#, CE#, OE# are //discarded /////////////////////////////////////////////////////////////////////////// always @(WENeg) begin: PulseWatch1 if (gWE_n == WENeg) $display("Glitch on WE#"); end always @(CENeg) begin: PulseWatch2 if (gCE_n == CENeg) $display("Glitch on CE#"); end always @(OENeg) begin: PulseWatch3 if (gOE_n == OENeg) $display("Glitch on OE#"); end //latch address on rising edge and data on falling edge of write always @(gWE_n or gCE_n or gOE_n ) begin: write_dc if (RESETNeg!=1'b0) begin if (~gWE_n && ~gCE_n && gOE_n) write = 1'b1; else write = 1'b0; end if (gWE_n && ~gCE_n && ~gOE_n) read = 1'b1; else read = 1'b0; end //------------------------------------------------------------------------- // --Latch address on falling edge of WE# or CE# what ever comes later // --Latches data on rising edge of WE# or CE# what ever comes first // -- also write cycle decode // ------------------------------------------------------------------------- integer AddressLatched ; integer WrAddressLatched; integer new_int,old_int; integer FinalAddress; integer READCYCLE; integer LATCHED; integer A_tmp ; integer A_tmp1 ; integer SA_tmp ; integer Mem_tmp; integer AS_addr; reg CE; always @(WENeg_ipd) begin if (reseted) begin if (~WENeg_ipd && ~CENeg_ipd && OENeg_ipd ) begin A_tmp = A; A_tmp1 = { A[HiAddrBit:0],1'b0}; SA_tmp = ReturnSectorID(A_tmp1); Address = A_tmp1; Addr = A_tmp; end else if (WENeg_ipd && write) begin end end end always @(CENeg_ipd) begin if (reseted) begin if (~CENeg_ipd && (WENeg_ipd != OENeg_ipd) ) begin Addr = A; A_tmp1 = { A[HiAddrBit:0],1'b0}; SecAddr = ReturnSectorID(A_tmp1); Address = A_tmp1; end else if (CENeg_ipd && write) begin end end end always @(negedge OENeg_ipd ) begin if (reseted) begin if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd) begin A_tmp = A; A_tmp1 = { A[HiAddrBit:0],1'b0}; SA_tmp = ReturnSectorID(A_tmp1); Address = A_tmp1; Addr = A_tmp; end if (~OENeg_ipd) begin SecAddr = SA_tmp; Address = A_tmp1; CE = CENeg; Addr = A_tmp; end end end // ///////////////////////////////////////////////////////////////////////// // // Timing control for the Program/ write Buffer Program Operations // // start/ suspend/ resume // ///////////////////////////////////////////////////////////////////////// integer cnt_write = 0; time duration_write ; event pdone_event; always @(posedge reseted) begin PDONE = 1'b1; end always @(reseted or PSTART) begin if (reseted) begin if (PSTART && PDONE) begin if ((Sec_Prot[SA] == 1'b0) && (Ers_queue[SA] == 1'b0)) begin duration_write = tdevice_POW; PDONE = 1'b0; ->pdone_event; end else begin PERR = 1'b1; PERR <= #1000 1'b0; end end end end always @(pdone_event) begin:pdone_process PDONE = 1'b0; #duration_write PDONE = 1'b1; end // ///////////////////////////////////////////////////////////////////////// // // Timing control for the Erase Operations // ///////////////////////////////////////////////////////////////////////// integer cnt_erase = 0; // 0 - SecNum+SubSecNum time elapsed_erase; time duration_erase; time start_erase; always @(posedge reseted) begin disable edone_process; EDONE = 1'b1; end event edone_event; always @(reseted or ESTART) begin: erase integer i; if (reseted) begin if (ESTART && EDONE) begin cnt_erase = 0; for (i=0;i<=SecNum;i=i+1) begin if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]==1'b0)) cnt_erase = cnt_erase + 1; end if (cnt_erase>0) begin elapsed_erase = 0; duration_erase = cnt_erase* tdevice_SEO; ->edone_event; start_erase = $time; end else begin EERR = 1'b1; EERR <= #1000 1'b0; end end end end always @(edone_event) begin : edone_process EDONE = 1'b0; #duration_erase EDONE = 1'b1; end always @(reseted or ESUSP) begin if (reseted) if (ESUSP && ~EDONE) begin disable edone_process; elapsed_erase = $time - start_erase; duration_erase = duration_erase - elapsed_erase; EDONE = 1'b0; end end always @(reseted or ERES) begin if (reseted) if (ERES && ~EDONE) begin start_erase = $time; EDONE = 1'b0; ->edone_event; end end // ///////////////////////////////////////////////////////////////////////// // // Main Behavior Process // // combinational process for next state generation // ///////////////////////////////////////////////////////////////////////// reg PATTERN_1 = 1'b0; reg PATTERN_2 = 1'b0; reg A_PAT_1 = 1'b0; always @(negedge write) begin if (~write) begin DataLo = DIn[7:0]; DataHi = DIn[15:8]; PATTERN_1 = (Addr==16'h555) && (DataLo==8'hAA) ; PATTERN_2 = (Addr==16'h2AA) && (DataLo==8'h55) ; A_PAT_1 = (Addr==16'h555); end end // always @(negedge(write) or reseted or PERR or EERR or oe) always @(falling_edge_write or reseted or PERR or EERR or oe) begin: StateGen1 if (reseted!=1'b1) next_state = current_state; else case (current_state) RESET : begin if (falling_edge_write) begin if (PATTERN_1) next_state = Z001; else if ((Addr==16'h555) && (DataLo==8'h98)) next_state = CFI; else next_state = RESET; end end Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = PREL_SETBWB; else next_state = RESET; end end CFI : begin if (falling_edge_write) begin if (DataLo==16'hF0) begin next_state = CFI; if ((ESP_ACT == 1'b1) && (AS_ACT == 1'b0)) next_state = ESP; else if (AS_ACT == 1'b1) next_state = AS; else next_state = RESET; end else next_state = CFI; end end PREL_SETBWB : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h20)) next_state = PREL_ULBYPASS; else if (A_PAT_1 && (DataLo==16'h90)) next_state = AS; else if (A_PAT_1 && (DataLo==16'h88)) next_state = OTP; else if (A_PAT_1 && (DataLo==16'hA0)) next_state = A0SEEN; else if (A_PAT_1 && (DataLo==16'h80)) next_state = C8; else//? next_state = RESET; end end PREL_ULBYPASS : begin if (falling_edge_write) begin if (DataLo==16'h90) next_state = PREL_ULBYPASS_RESET; else if (A_PAT_1 && (DataLo==16'hA0)) next_state = A0SEEN; else if (A_PAT_1 && (DataLo==16'h80)) next_state = C8_PREL; else next_state = PREL_ULBYPASS; end end PREL_ULBYPASS_RESET : begin if (falling_edge_write) begin if (DataLo==16'h00) begin if (ESP_ACT == 1'b1) next_state = ESP; else next_state = RESET; end else next_state = PREL_ULBYPASS; end end AS : begin if (oe) begin if (Addr%16'h100 == 16'h01) if (tmp_char1 == "B" || tmp_char1 == "b" || tmp_char1 == "T" || tmp_char1 == "b") next_state <= AS_Z001; else next_state <= AS; end else if (falling_edge_write) begin if (DataLo==16'hF0) begin if (ESP_ACT == 1'b1) next_state = ESP; else next_state = RESET; end else if ((Addr == 16'h555) && (DataLo == 16'h98)) next_state = CFI; else next_state = AS; end end AS_Z001 : begin if (oe) begin if (Addr%16'h100 == 16'h0E) next_state <= AS_Z002; else next_state <= AS; end else if (falling_edge_write) begin if (DataLo==16'hF0) begin if (ESP_ACT == 1'b1) next_state = ESP; else next_state = RESET; end else next_state = AS; end end AS_Z002 : begin if (falling_edge_write) begin if (DataLo==16'hF0) begin if (ESP_ACT == 1'b1) next_state = ESP; else next_state = RESET; end else next_state = AS; end else if (oe) begin next_state = AS; end end A0SEEN : begin if (falling_edge_write) next_state = PGMS; end OTP : begin if (falling_edge_write) begin if (PATTERN_1) next_state = OTP_Z001; else next_state = OTP; end end OTP_Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = OTP_PREL; else next_state = OTP; end end OTP_PREL : begin if (falling_edge_write) begin if (Addr == 16'h555 && DataLo == 16'h60) next_state = OTP_OW_PREL; else if ((Addr == 16'h555) && (DataLo == 16'h90)) next_state = OTP_EXIT; else next_state = OTP; end end OTP_EXIT : begin if (falling_edge_write) begin if ( DataLo == 16'h00) begin if (ESP_ACT == 1'b1) next_state = ESP; else next_state = RESET; end else next_state = OTP; end end OTP_OW_PREL : begin if (falling_edge_write) begin if ((Addr == 16'h1A) && (DataLo == 16'h48)) next_state = OTP_OW_STAT; else next_state = OTP; end end OTP_OW_STAT : begin if (oe) next_state = OTP; end C8 : begin if (falling_edge_write) begin if (PATTERN_1) next_state = C8_Z001; else next_state = RESET; end end C8_Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = C8_PREL; else next_state = RESET; end end C8_PREL : begin if (falling_edge_write) begin if ((Addr == 16'h555) && (DataLo == 16'h10)) next_state = ERS; else if ((DataLo == 16'h30)) next_state = SERS; else next_state = RESET; end end ERS : begin if (EDONE || EERR) begin if (ULBYPASS == 1'b1) next_state = PREL_ULBYPASS; else next_state = RESET; end end SERS : begin if (CTMOUT) next_state <= SERS_EXEC; else if (falling_edge_write) begin if (DataLo == 16'hB0) next_state = ESP; // ESP else if (DataLo==16'h30) next_state = SERS; else if (ULBYPASS) next_state = PREL_ULBYPASS; else next_state = RESET; end end SERS_EXEC : begin end ESP : begin if (falling_edge_write) begin if (DataLo == 16'h30) next_state = SERS_EXEC; else begin if (PATTERN_1) next_state = ESP_Z001; else if (Addr == 16'h555 && DataLo == 8'h98) next_state = CFI; end end end ESP_Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = ESP_PREL; else next_state = ESP; end end ESP_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && DataLo == 16'hA0) next_state = A0SEEN; else if (A_PAT_1 && DataLo == 16'h20) next_state <= PREL_ULBYPASS; else if (A_PAT_1 && DataLo == 16'h88) next_state <= OTP; else if (A_PAT_1 && DataLo == 16'h90) next_state = AS; else next_state = ESP; end end PGMS : begin end endcase end always @(posedge PDONE or negedge PERR) begin: StateGen6 if (reseted!=1'b1) next_state = current_state; else begin if (current_state==PGMS && ULBYPASS) next_state = PREL_ULBYPASS; else if (current_state==PGMS && OTP_ACT) next_state = OTP; else if (current_state==PGMS && ESP_ACT) next_state = ESP; else if (current_state==PGMS) next_state = RESET; end end always @(posedge EDONE or negedge EERR) begin: StateGen2 if (reseted!=1'b1) next_state = current_state; else begin if ((current_state==ERS) || (current_state==SERS_EXEC)) next_state = RESET; end end always @(negedge write or reseted) begin: StateGen7 //ok integer i,j; if (reseted!=1'b1) next_state = current_state; else begin if (current_state==SERS_EXEC && (write==1'b0) && (EERR!=1'b1)) if (DataLo==16'hB0) begin next_state = ESPS; ESUSP = 1'b1; ESUSP <= #1 1'b0; end end end always @(CTMOUT or reseted) begin: StateGen4 if (reseted!=1'b1) next_state = current_state; else begin if (current_state==SERS && CTMOUT) next_state = SERS_EXEC; end end always @(posedge START_T1 or reseted) begin: StateGen5 if (reseted!=1'b1) next_state = current_state; else if (current_state==ESPS && START_T1) #1 next_state = ESP; end /////////////////////////////////////////////////////////////////////////// //FSM Output generation and general functionality /////////////////////////////////////////////////////////////////////////// always @(posedge read) begin ->oe_event; end always @(Address or SecAddr) begin if (read) ->oe_event; end always @(oe_event) begin oe = 1'b1; #1 oe = 1'b0; end always @(oe or reseted or current_state or PDONE or rising_edge_EDONE or falling_edge_write or PERR or rising_edge_START_T1_out) begin if (reseted) begin case (current_state) RESET : begin ESP_ACT = 1'b0; OTP_ACT = 1'b0; ULBYPASS = 1'b0; CTMOUT_in = 1'b0; if (oe) begin if (Memory[Address] == -1) DOut_zd[7:0] = 8'bx; else DOut_zd[7:0] = Memory[Address]; if (Memory[Address + 1] == -1) DOut_zd[15:8] = 8'bx; else DOut_zd[15:8] = Memory[Address + 1]; end end CFI : begin if (oe) begin DOut_zd[15:0] = 16'bZ; if ((Address/2 >=16'h10)&&(Address/2 <=16'h50)) begin DOut_zd[15:8] = 0; DOut_zd[7:0] = CFI_array[Address/2]; end else $display ("Invalid CFI query address"); end end PREL_SETBWB : begin if (falling_edge_write) begin if ((Addr ==16'h555)&&(DataLo ==16'h20)) ULBYPASS = 1'b1; else ULBYPASS = 1'b0; end end PREL_ULBYPASS_RESET: begin if (falling_edge_write) begin if (DataLo ==16'h00) ULBYPASS = 1'b0; end end AS : begin if (falling_edge_write) begin AS_ACT = 1'b1; if (DataLo == 16'hF0) begin AS_ACT = 1'b0; ULBYPASS = 1'b0; end end if (oe) begin if (Address%16'h100 == 0) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'h22; if (Addr%16'h100 == 0) begin DOut_zd[7:0] = 1; end else if (Addr%16'h100 == 1) begin if ((tmp_char1 == "B" || tmp_char1 == "b")) DOut_zd[7:0] = 8'h7E; else if((tmp_char1 == "T" || tmp_char1 == "t")) DOut_zd[7:0] = 8'h7E; else if((tmp_char1 == "L" || tmp_char1 == "l")) DOut_zd[7:0] = 8'hD7; else if((tmp_char1 == "H" || tmp_char1 == "h")) DOut_zd[7:0] = 8'hD7; end else if (Addr%16'h100 == 2) begin DOut_zd[7:1] = 7'b0; if (Sec_Prot[SecAddr] == 1'b1) DOut_zd[0] = 1'b1; else DOut_zd[0] = 1'b0; end end end AS_Z001 : begin DOut_zd[15:8] = 16'h22; if ((tmp_char1 == "B" || tmp_char1 == "b" || tmp_char1 == "T" || tmp_char1 == "t") && (Addr% 16'h100 == 16'h0E)) DOut_zd[7:0] = 16'h0F; end AS_Z002: begin DOut_zd[15:8] = 16'h22; if ((tmp_char1 == "B" || tmp_char1 == "b") && (Addr% 16'h100 == 16'h0F)) DOut_zd[7:0] = 16'h00; else if ((tmp_char1 == "T" || tmp_char1 == "t") && (Addr% 16'h100 == 16'h0F)) DOut_zd[7:0] = 16'h01; end A0SEEN : begin if (falling_edge_write) begin PSTART = 1'b1; PSTART <= #1 1'b0; if (Viol!=1'b0) begin WData[0] = -1; WData[1] = -1; Viol=1'b0;//? end else begin WData[0] = DataLo; WData[1] = DataHi; end WAddr[0] = Address;// % 32; SA = SecAddr; temp = DataLo; Status[7] = ~temp[7]; WAddr[1] = WAddr[0] +1; PR_FLAG = 1'b0; end end OTP: begin OTP_ACT = 1'b1; if (oe) begin SecSiAddr = Address%(SecSiSize + 1); DOut_zd[7:0] = 8'bX; if ((tmp_char1 == "T" || tmp_char1 == "t") && ((Address >= 25'h7FFF00) && (Address <= 25'h7FFFFF) && (SecAddr == 134))) begin DOut_zd[7:0] = SecSiMem[SecSiAddr]; DOut_zd[15:8] = 8'bX; if (SecSiMem[SecSiAddr + 1] != -1) DOut_zd[15:8] = SecSiMem[SecSiAddr + 1]; end else if ((tmp_char1 == "B" || tmp_char1 == "b") && ((Address >= 25'h000000) && (Address <= 25'h0000FF) && (SecAddr == 0))) begin DOut_zd[7:0] = SecSiMem[SecSiAddr]; DOut_zd[15:8] = 8'bX; if (SecSiMem[SecSiAddr + 1] != -1) DOut_zd[15:8] = SecSiMem[SecSiAddr + 1]; end else if ((tmp_char1 == "L" || tmp_char1 == "l") && ((Address >= 25'h000000) && (Address <= 25'h0000FF) && (SecAddr == 0))) begin DOut_zd[7:0] = SecSiMem[SecSiAddr]; DOut_zd[15:8] = 8'hX; if (SecSiMem[SecSiAddr + 1] != -1) DOut_zd[15:8] = SecSiMem[SecSiAddr + 1]; end else if ((tmp_char1 == "H" || tmp_char1 == "h") && ((Address >= 25'h7FFF00) && (Address <= 25'h7FFFFF) && (SecAddr == 127))) begin DOut_zd[7:0] = SecSiMem[SecSiAddr]; DOut_zd[15:8] = 8'bX; if (SecSiMem[SecSiAddr + 1] != -1) DOut_zd[15:8] = SecSiMem[SecSiAddr + 1]; end else $display("Invalid address in SecSi region. "); end end OTP_OW_STAT : begin if (oe) if (Addr%16'h100 == 16'h1A) DOut_zd[0] = ProtBit; end C8_PREL : begin if (falling_edge_write) begin SA_ERS = SecAddr; if (A_PAT_1 && DataLo == 16'h10) begin //--Start Chip Erase ESTART = 1'b1; ESTART <= #1000 1'b0; ESUSP = 1'b0; ERES = 1'b0; for (i=0;i<=SecNum;i=i+1) begin if (Sec_Prot[i] == 1'b0) Ers_queue[i] = 1'b1; else Ers_queue[i] = 1'b0; end ER_FLAG = 1'b0; end else if (DataLo == 16'h30) begin ER_FLAG = 1'b0; //put selected sector to sec. ers. queue //start timeout for(i=0;i<=SecNum;i=i+1) begin Ers_queue[i] = 1'b0; end Ers_queue[SecAddr] = 1'b1; CTMOUT_in = 1'b0; CTMOUT_in <= #1 1'b1; end end end ERS : begin if (oe) begin //-------------------------------------------------------- //-- read status / embeded erase algorithm - Chip Erase //-------------------------------------------------------- Status[7] = 1'b0; Status[6] = ~Status[6]; //--toggle Status[5] = 1'b0; Status[3] = 1'b1; Status[2] = ~Status[2];// --toggle DOut_zd[7:0] = Status[7:0]; end end SERS : begin if (CTMOUT == 1'b1) begin CTMOUT_in = 1'b0; START_T1_in = 1'b0; ESTART = 1'b1; ESTART <= #1 1'b0; ESUSP = 1'b0; ERES = 1'b0; end else if (falling_edge_write) begin if (DataLo == 16'hB0) begin //--need to start erase process prior to suspend ESTART = 1'b1; ESTART <= #1 1'b0; ERES = 1'b0; //-- CTMOUT reset CTMOUT_in = 1'b0; ESUSP = 1'b1; ESUSP <= #1 1'b0; end else if (DataLo == 16'h30) begin CTMOUT_in = 1'b0; CTMOUT_in = #1000 1'b1; Ers_queue[SecAddr] = 1'b1; end else CTMOUT_in = 1'b0; end else if (oe) begin // --------------------------------------------------------- // --read status - sector erase timeout // --------------------------------------------------------- Status[3] = 1'b0; Status[7] = 1'b1; DOut_zd[7:0] = Status[7:0]; end end ESPS : begin if (rising_edge_START_T1_out) begin ESP_ACT = 1'b1; START_T1_in = 1'b0; end else if (oe) begin // --------------------------------------------------------- // --read status / erase suspend timeout - stil erasing // --------------------------------------------------------- if (Ers_queue[SecAddr]== 1'b1) begin Status[7] = 1'b0; Status[2] = ~Status[2];// --toggle end else Status[7] = 1'b1; Status[6] = ~Status[6];// --toggle Status[5] = 1'b0; Status[3] = 1'b1; DOut_zd[7:0] = Status[7:0]; end end SERS_EXEC: //ok begin if (oe) begin // --------------------------------------------------------- // --read status Erase Busy // --------------------------------------------------------- if (Ers_queue[SecAddr] == 1'b1) begin Status[7] = 1'b0; Status[2] = ~Status[2];// --toggle end else begin Status[7] = 1'b1; end Status[6] = ~Status[6];// --toggle Status[5] = 1'b0; Status[3] = 1'b1; DOut_zd[7:0] = Status[7:0]; end if (falling_edge_write) //ok begin if (DataLo == 16'hB0) begin START_T1_in = 1'b1; ESUSP = 1'b1; ESUSP <= #1000 1'b0; end end end ESP : begin if (OTP_ACT == 1'b1) OTP_ACT = 1'b0; if (falling_edge_write) begin if (DataLo == 16'h30) begin //--resume erase ERES = 1'b1; ERES <= #1000 1'b0; end end else if (oe) begin if ((Ers_queue[SecAddr] == 1'b1) && (Sec_Prot[SecAddr] != 1'b1)) begin // ----------------------------------------------------- // --read status // ----------------------------------------------------- Status[7] = 1'b1; // -- Status(6) No toggle Status[5] = 1'b0; Status[2] = ~Status[2];// --toggle DOut_zd[7:0] = Status[7:0]; end else begin // ----------------------------------------------------- // --read // ----------------------------------------------------- if (Memory[Address] == -1) DOut_zd[7:0] = 8'bX; else DOut_zd[7:0] = Memory[Address]; if (Memory[Address + 1] == -1) DOut_zd[15:8] = 8'bX; else DOut_zd[15:8] = Memory[Address + 1]; end end end ESP_PREL : begin if (falling_edge_write) if (Addr == 16'h555 && DataLo == 16'h20) ULBYPASS = 1'b1; end PGMS : begin if (oe) begin Status[7] = ~DataLo[7]; // --------------------------------------------------------- // --read status // --------------------------------------------------------- Status[6] = ~Status[6];// --toggle Status[5] = 1'b0; // --Status[2] no toggle Status[1] = 1'b0; DOut_zd[7:0] = Status[7:0]; end end endcase end end always @(gOE_n or RESETNeg or RST or oe) begin //Output Disable Control if (gOE_n || (~RESETNeg))// && ~RST DOut_zd = 16'bZ; end always @(EERR or EDONE or current_state) begin : ERS2 integer i; integer j; if (current_state==ERS) begin if (tmp_char1 == "H" || tmp_char1 == "h" || tmp_char1 == "L" || tmp_char1 == "l") SecNum_ers = 127; else SecNum_ers = 134; if (~EERR) begin if (~ER_FLAG) begin ER_FLAG = 1'b1; for (i=0;i<=SecNum_ers;i=i+1) begin if (Sec_Prot[i] == 1'b0) begin SA_ERS = i; if (~((tmp_char1 == "H" || tmp_char1 == "h") || (tmp_char1 == "L" || tmp_char1 == "l"))) begin if ((SA_ERS <= 7) && (tmp_char1 == "B" || tmp_char1 == "b")) begin for (j=(SA_ERS*(SecSize8+1) + sgsaB[0]); j<(SA_ERS*(SecSize8+1) + sgsaB[0]+SecSize8);j=j+1) begin Memory[j] = -1; end end else if (tmp_char1 == "B" || tmp_char1 == "b") begin for( j=((SA_ERS-8)*(SecSize64+1) + sgsaB[1]); j< ((SA_ERS-8)*(SecSize64+1) + sgsaB[1]+SecSize64);j=j+1) begin Memory[j] = -1; end end else if ((SA_ERS < SecNum-7) && (tmp_char1 == "T" || tmp_char1 == "t")) begin for (j=(SA_ERS*(SecSize64+1) + sgsaT[0]); j<(SA_ERS*(SecSize64+1) + sgsaT[0]+SecSize64);j=j+1) begin Memory[j] = -1; end end else begin for(j = (SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]; j<((SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]+SecSize8);j=j+1) begin Memory[j] = -1; end end end else begin for(j=(SA_ERS*(SecSize64+1)); j<(SA_ERS*(SecSize64+1)+SecSize64);j=j+1) begin Memory[j] = -1; end end end end end end if (rising_edge_EDONE) begin for (i=0;i<=SecNum_ers;i=i+1) begin if (Sec_Prot[i] == 1'b0) begin SA_ERS = i; if (~((tmp_char1 == "H" || tmp_char1 == "h") || (tmp_char1 == "L" || tmp_char1 == "l"))) begin if ((SA_ERS <= 7) && (tmp_char1 == "B" || tmp_char1 == "b")) begin for (j=(SA_ERS*(SecSize8+1) + sgsaB[0]); j<(SA_ERS*(SecSize8+1) + sgsaB[0]+SecSize8);j=j+1) begin Memory[j] = MaxData; end end else if (tmp_char1 == "B" || tmp_char1 == "b") begin for( j=((SA_ERS-8)*(SecSize64+1) + sgsaB[1]); j< ((SA_ERS-8)*(SecSize64+1) + sgsaB[1]+SecSize64);j=j+1) begin Memory[j] = MaxData; end end else if ((SA_ERS < SecNum-7) && (tmp_char1 == "T" || tmp_char1 == "t")) begin for (j=(SA_ERS*(SecSize64+1) + sgsaT[0]); j<(SA_ERS*(SecSize64+1) + sgsaT[0]+SecSize64);j=j+1) begin Memory[j] = MaxData; end end else begin for(j = (SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]; j<((SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]+SecSize8);j=j+1) begin Memory[j] = MaxData; end end end else begin for(j=(SA_ERS*(SecSize64+1)); j<(SA_ERS*(SecSize64+1)+SecSize64);j=j+1) begin Memory[j] = MaxData; end end end end for(i=0;i<=SecNum_ers;i=i+1) begin if (Ers_queue[i] == 1'b1 && Sec_Prot[i] == 1'b0) begin Ers_queue[i] = 1'b0; end end Status[7] = 1'b1; end end end always @(CTMOUT or current_state) begin : SERS2 if (current_state==SERS) begin if (CTMOUT) begin CTMOUT_in = 1'b0; START_T1_in = 1'b0; ESTART = 1'b1; ESTART <= #1 1'b0; ESUSP = 1'b0; ERES = 1'b0; end end end always @(current_state or EERR or EDONE) begin: SERS_EXEC2 integer i,j; if (current_state==SERS_EXEC) begin if (tmp_char1 == "H" || tmp_char1 == "h" || tmp_char1 == "L" || tmp_char1 == "l") SecNum_ers = 127; else SecNum_ers = 134; if (EERR != 1'b1) begin if (~ER_FLAG) begin ER_FLAG = 1'b1; for (i=0;i<=SecNum_ers;i=i+1) begin if ((Ers_queue[i] == 1'b1) &&(Sec_Prot[i] == 1'b0)) begin SA_ERS = i; if (~((tmp_char1 == "H" || tmp_char1 == "h") || (tmp_char1 == "L" || tmp_char1 == "l"))) begin if ((SA_ERS <= 7) && (tmp_char1 == "B" || tmp_char1 == "b")) begin for (j=(SA_ERS*(SecSize8+1) + sgsaB[0]); j<(SA_ERS*(SecSize8+1) + sgsaB[0]+SecSize8);j=j+1) begin Memory[j] = -1; end end else if (tmp_char1 == "B" || tmp_char1 == "b") begin for( j=((SA_ERS-8)*(SecSize64+1) + sgsaB[1]); j< ((SA_ERS-8)*(SecSize64+1) + sgsaB[1]+SecSize64);j=j+1) begin Memory[j] = -1; end end else if ((SA_ERS < SecNum-7) && (tmp_char1 == "T" || tmp_char1 == "t")) begin for (j=(SA_ERS*(SecSize64+1) + sgsaT[0]); j<(SA_ERS*(SecSize64+1) + sgsaT[0]+SecSize64);j=j+1) begin Memory[j] = -1; end end else begin for(j = (SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]; j<((SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]+SecSize8);j=j+1) begin Memory[j] = -1; end end end else begin for(j=(SA_ERS*(SecSize64+1)); j<(SA_ERS*(SecSize64+1)+SecSize64);j=j+1) begin Memory[j] = -1; end end end end end end if (rising_edge_EDONE) begin for (i=0;i<=SecNum_ers;i=i+1) begin if ((Ers_queue[i] == 1'b1) &&(Sec_Prot[i] == 1'b0)) begin SA_ERS = i; if (~((tmp_char1 == "H" || tmp_char1 == "h") || (tmp_char1 == "L" || tmp_char1 == "l"))) begin if ((SA_ERS <= 7) && (tmp_char1 == "B" || tmp_char1 == "b")) begin for (j=(SA_ERS*(SecSize8+1) + sgsaB[0]); j<(SA_ERS*(SecSize8+1) + sgsaB[0]+SecSize8);j=j+1) begin Memory[j] = MaxData; end end else if (tmp_char1 == "B" || tmp_char1 == "b") begin for( j=((SA_ERS-8)*(SecSize64+1) + sgsaB[1]); j< ((SA_ERS-8)*(SecSize64+1) + sgsaB[1]+SecSize64);j=j+1) begin Memory[j] = MaxData; end end else if ((SA_ERS < SecNum-7) && (tmp_char1 == "T" || tmp_char1 == "t")) begin for (j=(SA_ERS*(SecSize64+1) + sgsaT[0]); j<(SA_ERS*(SecSize64+1) + sgsaT[0]+SecSize64);j=j+1) begin Memory[j] = MaxData; end end else begin for(j = (SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]; j<((SA_ERS-(SecNum-7))*(SecSize8+1)+sgsaT[1]+SecSize8);j=j+1) begin Memory[j] = MaxData; end end end else begin for(j=(SA_ERS*(SecSize64+1)); j<(SA_ERS*(SecSize64+1)+SecSize64);j=j+1) begin Memory[j] = MaxData; end end end end for(i= 0;i<=SecNum_ers;i=i+1) begin if (Ers_queue[i] == 1'b1 && Sec_Prot[i] == 1'b0) begin Ers_queue[i] = 1'b0; end end Status[7] = 1'b1; end end end always @(current_state or posedge PDONE) // or PERR or PDONE) begin: PGMS2 integer i,j; if (current_state==PGMS) begin if (WAddr[1] < 1'b0) wr_cnt = 1'b0;// --if any of WAddr is equal to -1, else //--here is where this problem is handled wr_cnt = 1'b1;// --no need to handle it separately! if (Sec_Prot[SA] == 1'b0) begin if (~PR_FLAG) begin PR_FLAG = 1'b1; if (PERR!=1'b1) begin for( i=0;i<=wr_cnt;i=i+1) begin new_int = WData[i]; old_int=Memory[WAddr[i]]; if (new_int>-1) begin new_bit=new_int; if (old_int>-1) begin old_bit = old_int; for(j=0;j<=7;j=j+1) begin if (old_bit[j] == 1'b0) new_bit[j]=1'b0; end new_int=new_bit; end WData[i]= new_int; end else WData[i]= -1; end for(i=0;i<=wr_cnt;i=i+1) begin Memory[WAddr[i]] = -1; end end end end //--busy signal active if ((PDONE == 1'b1) && (~PSTART)) begin for(i=0;i<=wr_cnt;i=i+1) begin Memory[WAddr[i]] = WData[i]; WData[i] = -1; end end end end always@(WPNeg) begin : WPProtect if (tmp_char1 == "T" || tmp_char1 == "t") begin if (WPNeg == 1'b0) begin Sec_Prot[133] = 1'b1; Sec_Prot[134] = 1'b1; end else begin Sec_Prot[133] = 1'b0; Sec_Prot[134] = 1'b0; end end else if (tmp_char1 == "B" || tmp_char1 == "b") begin if (WPNeg == 1'b0) begin Sec_Prot[0] = 1'b1; Sec_Prot[1] = 1'b1; end else begin Sec_Prot[0] = 1'b0; Sec_Prot[1] = 1'b0; end end else if (tmp_char1 == "H" || tmp_char1 == "h") begin if (WPNeg == 1'b0) Sec_Prot[127] = 1'b1; else Sec_Prot[127] = 1'b0; end else if (tmp_char1 == "L" || tmp_char1 == "l") begin if (WPNeg == 1'b0) Sec_Prot[0] = 1'b1; else Sec_Prot[0] = 1'b0; end end initial begin : CFIPreload // //////////////////////////////////////////////////////////////////// // //CFI array data // //////////////////////////////////////////////////////////////////// // // //CFI query identification string for (i=16;i<92;i=i+1) begin CFI_array[i] = -1; end //// --CFI query identification string CFI_array[16'h10] = 16'h51; CFI_array[16'h11] = 16'h52; CFI_array[16'h12] = 16'h59; CFI_array[16'h13] = 16'h02; CFI_array[16'h14] = 16'h00; CFI_array[16'h15] = 16'h40; CFI_array[16'h16] = 16'h00; CFI_array[16'h17] = 16'h00; CFI_array[16'h18] = 16'h00; CFI_array[16'h19] = 16'h00; CFI_array[16'h1A] = 16'h00; // --system interface string CFI_array[16'h1B] = 16'h27; CFI_array[16'h1C] = 16'h36; CFI_array[16'h1D] = 16'h00; CFI_array[16'h1E] = 16'h00; CFI_array[16'h1F] = 16'h03; CFI_array[16'h20] = 16'h00; CFI_array[16'h21] = 16'h09; CFI_array[16'h22] = 16'h00; CFI_array[16'h23] = 16'h05; CFI_array[16'h24] = 16'h00; CFI_array[16'h25] = 16'h04; CFI_array[16'h26] = 16'h00; // --device geometry definition CFI_array[16'h27] = 16'h17; CFI_array[16'h28] = 16'h01; CFI_array[16'h29] = 16'h00; CFI_array[16'h2A] = 16'h00; CFI_array[16'h2B] = 16'h00; if ((tmp_char1 == "H") || (tmp_char1 == "h") || (tmp_char1 == "L") || (tmp_char1 == "l")) CFI_array[16'h2C] = 16'h01; else CFI_array[16'h2C] = 16'h02; if ((tmp_char1 == "H") || (tmp_char1 == "h") || (tmp_char1 == "L") || (tmp_char1 == "l")) begin CFI_array[16'h2D] = 16'h01; CFI_array[16'h2E] = 16'h00; CFI_array[16'h2F] = 16'h00; CFI_array[16'h30] = 16'h7F; end else begin CFI_array[16'h2D] = 16'h00; CFI_array[16'h2E] = 16'h20; CFI_array[16'h2F] = 16'h00; CFI_array[16'h30] = 16'h07; end if ((tmp_char1 == "H") || (tmp_char1 == "h") || (tmp_char1 == "L") || (tmp_char1 == "l")) begin CFI_array[16'h31] = 16'h00; CFI_array[16'h32] = 16'h00; CFI_array[16'h33] = 16'h00; CFI_array[16'h34] = 16'h00; end else begin CFI_array[16'h31] = 16'h01; CFI_array[16'h32] = 16'h00; CFI_array[16'h33] = 16'h00; CFI_array[16'h34] = 16'h7E; end CFI_array[16'h35] = 16'h00; CFI_array[16'h36] = 16'h00; CFI_array[16'h37] = 16'h00; CFI_array[16'h38] = 16'h00; CFI_array[16'h39] = 16'h00; CFI_array[16'h3A] = 16'h00; CFI_array[16'h3B] = 16'h00; CFI_array[16'h3C] = 16'h00; // --primary vendor-specific extended query CFI_array[16'h40] = 16'h50; CFI_array[16'h41] = 16'h52; CFI_array[16'h42] = 16'h49; CFI_array[16'h43] = 16'h31; CFI_array[16'h44] = 16'h33; CFI_array[16'h45] = 16'h01; CFI_array[16'h46] = 16'h02; CFI_array[16'h47] = 16'h04; CFI_array[16'h48] = 16'h01; CFI_array[16'h49] = 16'h04; CFI_array[16'h4A] = 16'h00; CFI_array[16'h4B] = 16'h00; CFI_array[16'h4C] = 16'h00; CFI_array[16'h4D] = 16'hB5; CFI_array[16'h4E] = 16'hC5; if ((tmp_char1 == "H") || (tmp_char1 == "h")) CFI_array[16'h4F] = 16'h05; else if ((tmp_char1 == "L") || (tmp_char1 == "l")) CFI_array[16'h4F] = 16'h04; else if ((tmp_char1 == "B") || (tmp_char1 == "b")) CFI_array[16'h4F] = 16'h02; else if ((tmp_char1 == "T") || (tmp_char1 == "t")) CFI_array[16'h4F] = 16'h03; CFI_array[16'h50] = 16'h00; end always @(posedge gWE_n) begin rising_edge_gWE_n = 1; #1 rising_edge_gWE_n = 0; end always @(negedge gWE_n) begin falling_edge_gWE_n = 1; #1 falling_edge_gWE_n = 0; end always @(posedge gCE_n) begin rising_edge_gCE_n = 1; #1 rising_edge_gCE_n = 0; end always @(negedge gCE_n) begin falling_edge_gCE_n = 1; #1 falling_edge_gCE_n = 0; end always @(posedge CENeg) begin rising_edge_CENeg = 1; #1 rising_edge_CENeg = 0; end always @(negedge CENeg) begin falling_edge_CENeg = 1; #1 falling_edge_CENeg = 0; end always @(negedge OENeg) begin falling_edge_OENeg = 1; #1 falling_edge_OENeg = 0; end always @(A) begin A_event = 1; #1 A_event = 0; end always @(posedge RESETNeg) begin rising_edge_RESETNeg = 1; #1 rising_edge_RESETNeg = 0; end always @(negedge RESETNeg) begin falling_edge_RESETNeg = 1; #1 falling_edge_RESETNeg = 0; end always @(posedge START_in) begin rising_edge_START_in = 1; #1 rising_edge_START_in = 0; end always @(posedge read) begin rising_edge_read =1; #1 rising_edge_read = 0; end always @(negedge read) begin falling_edge_read =1; #1 falling_edge_read = 0; end always @(posedge reseted) begin rising_edge_reseted = 1; #1 rising_edge_reseted = 0; end always @(negedge reseted) begin falling_edge_reseted = 1; #1 falling_edge_reseted = 0; end always @(posedge PSTART) begin rising_edge_PSTART = 1; #1 rising_edge_PSTART = 0; end always @(posedge PSUSP) begin rising_edge_PSUSP = 1; #1 rising_edge_PSUSP = 0; end always @(posedge PRES) begin rising_edge_PRES = 1; #1 rising_edge_PRES = 0; end always @(posedge ESTART) begin rising_edge_ESTART = 1; #1 rising_edge_ESTART = 0; end always @(posedge ESUSP) begin rising_edge_ESUSP = 1; #1 rising_edge_ESUSP = 0; end always @(posedge ERES) begin rising_edge_ERES = 1; #1 rising_edge_ERES = 0; end always @(negedge write) begin falling_edge_write = 1; #1 falling_edge_write = 0; end always @(posedge START_T1) begin rising_edge_START_T1_out = 1; #1 rising_edge_START_T1_out = 0; end always @(posedge EDONE) begin rising_edge_EDONE = 1; #1 rising_edge_EDONE = 0; end always @(negedge EERR) begin falling_edge_EERR = 1; #1 falling_edge_EERR = 0; end always @(posedge PDONE) begin rising_edge_PDONE = 1; #1 rising_edge_PDONE = 0; end always @(posedge START_out) begin rising_edge_START_out = 1; #1 rising_edge_START_out = 0; end always @(negedge RST) begin falling_edge_RST = 1; #1 falling_edge_RST = 0; end always @(posedge OENeg) begin rising_edge_OENeg = 1; #1 rising_edge_OENeg = 0; end always @(posedge WENeg) begin rising_edge_WENeg = 1; #1 rising_edge_WENeg = 0; end always @(posedge CENeg) begin rising_edge_CENeg = 1; #1 rising_edge_CENeg = 0; end always @(next_state) begin next_state_event = 1; #1 next_state_event = 0; end function integer ReturnSectorID; input integer ADDR; integer conv; begin conv = ADDR / (SecSize64+1); if (~(tmp_char1 == "H" || tmp_char1 == "h" || tmp_char1 == "L" || tmp_char1 == "l")) begin if (conv == 0 && (tmp_char1 == "B" || tmp_char1 == "b")) ReturnSectorID = (ADDR - sgsaB[0]) / (SecSize8+1); else if (tmp_char1 == "B" || tmp_char1 == "b") ReturnSectorID = 7+conv; else if (conv == (SecNum-7) && (tmp_char1=="T" || tmp_char1=="t")) ReturnSectorID = SecNum - 7 + (ADDR - sgsaT[1])/(SecSize8+1); else ReturnSectorID = conv; end else ReturnSectorID = conv; end endfunction reg BuffInOE, BuffInCE, BuffInADDR; wire BuffOutOE, BuffOutCE, BuffOutADDR; BUFFER BUFOE (BuffOutOE, BuffInOE); BUFFER BUFCE (BuffOutCE, BuffInCE); BUFFER BUFADDR (BuffOutADDR, BuffInADDR); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInADDR = 1'b1; end always @(posedge BuffOutOE) begin OEDQ_01 = $time; end always @(posedge BuffOutCE) begin CEDQ_01 = $time; end always @(posedge BuffOutADDR) begin ADDRDQ_01 = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule