////////////////////////////////////////////////////////////////////////////// // File name : s29al008j.v ////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY : // // version: | author: | date: | changes made: // V1.0 I.Milutinovic 07 Mar 30 Initial release // ////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // // Library: FLASH // Technology: Flash Memory // Part: S29AL008J // // Description: 8 Megabit Floating Gate NOR Boot Sector Flash Memory // Boot sector determined by TimingModel generic // ////////////////////////////////////////////////////////////////////////////// // Known Bugs: // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module s29al008j ( A18 , A17 , A16 , A15 , A14 , A13 , A12 , A11 , A10 , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 , DQ15 , DQ14 , DQ13 , DQ12 , DQ11 , DQ10 , DQ9 , DQ8 , DQ7 , DQ6 , DQ5 , DQ4 , DQ3 , DQ2 , DQ1 , DQ0 , CENeg , OENeg , WENeg , RESETNeg , BYTENeg , WPNeg , RY ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input A18 ; input A17 ; input A16 ; input A15 ; input A14 ; input A13 ; input A12 ; input A11 ; input A10 ; input A9 ; input A8 ; input A7 ; input A6 ; input A5 ; input A4 ; input A3 ; input A2 ; input A1 ; input A0 ; inout DQ15 ; inout DQ14 ; inout DQ13 ; inout DQ12 ; inout DQ11 ; inout DQ10 ; inout DQ9 ; inout DQ8 ; inout DQ7 ; inout DQ6 ; inout DQ5 ; inout DQ4 ; inout DQ3 ; inout DQ2 ; inout DQ1 ; inout DQ0 ; input CENeg ; input OENeg ; input WENeg ; input WPNeg ; input RESETNeg ; input BYTENeg ; output RY ; // interconnect path delay signals wire A18_ipd ; wire A17_ipd ; wire A16_ipd ; wire A15_ipd ; wire A14_ipd ; wire A13_ipd ; wire A12_ipd ; wire A11_ipd ; wire A10_ipd ; wire A9_ipd ; wire A8_ipd ; wire A7_ipd ; wire A6_ipd ; wire A5_ipd ; wire A4_ipd ; wire A3_ipd ; wire A2_ipd ; wire A1_ipd ; wire A0_ipd ; wire [18 : 0] A; assign A = { A18_ipd, A17_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire DQ15_ipd ; wire DQ14_ipd ; wire DQ13_ipd ; wire DQ12_ipd ; wire DQ11_ipd ; wire DQ10_ipd ; wire DQ9_ipd ; wire DQ8_ipd ; wire DQ7_ipd ; wire DQ6_ipd ; wire DQ5_ipd ; wire DQ4_ipd ; wire DQ3_ipd ; wire DQ2_ipd ; wire DQ1_ipd ; wire DQ0_ipd ; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire CENeg_ipd ; wire OENeg_ipd ; wire WENeg_ipd ; wire WPNeg_ipd ; wire RESETNeg_ipd ; wire BYTENeg_ipd ; // internal delays reg START_T1 ; // Start TimeOut reg START_T1_in ; reg CTMOUT ; // Sector Erase TimeOut reg CTMOUT_in ; reg READY_in ; reg READY ; // Device ready after reset wire DQ15_zd ; wire DQ14_zd ; wire DQ13_zd ; wire DQ12_zd ; wire DQ11_zd ; wire DQ10_zd ; wire DQ9_zd ; wire DQ8_zd ; wire DQ7_zd ; wire DQ6_zd ; wire DQ5_zd ; wire DQ4_zd ; wire DQ3_zd ; wire DQ2_zd ; wire DQ1_zd ; wire DQ0_zd ; reg [15 : 0] DOut_zd; assign {DQ15_zd, DQ14_zd, DQ13_zd, DQ12_zd, DQ11_zd, DQ10_zd, DQ9_zd, DQ8_zd, DQ7_zd, DQ6_zd, DQ5_zd, DQ4_zd, DQ3_zd, DQ2_zd, DQ1_zd, DQ0_zd } = DOut_zd; wire DQ15_Pass ; wire DQ14_Pass ; wire DQ13_Pass ; wire DQ12_Pass ; wire DQ11_Pass ; wire DQ10_Pass ; wire DQ9_Pass ; wire DQ8_Pass ; wire DQ7_Pass ; wire DQ6_Pass ; wire DQ5_Pass ; wire DQ4_Pass ; wire DQ3_Pass ; wire DQ2_Pass ; wire DQ1_Pass ; wire DQ0_Pass ; reg [15 : 0] DOut_Pass; assign {DQ15_Pass, DQ14_Pass, DQ13_Pass, DQ12_Pass, DQ11_Pass, DQ10_Pass, DQ9_Pass, DQ8_Pass, DQ7_Pass, DQ6_Pass, DQ5_Pass, DQ4_Pass, DQ3_Pass, DQ2_Pass, DQ1_Pass, DQ0_Pass } = DOut_Pass; reg RY_zd; parameter TimingChecksOn = 1'b1; //Should be =1'b1 when SDF is used parameter UserPreload = 1'b0; parameter mem_file_name = "none"; parameter prot_file_name = "none"; parameter secsi_file_name = "none"; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "s29al008j"; parameter MaxData = 255; parameter SecSize = 65535; parameter SecSiSize = 255; parameter SecNum = 15; parameter SubSecNum = 3; parameter HiAddrBit = 18; parameter MemSize = (SecNum+1) *(SecSize+1)-1; // If speedsimulation is needed uncomment following line // `define SPEEDSIM; //varaibles to resolve if bottom or top architecture is used reg [20*8-1:0] tmp_timing;//stores copy of TimingModel reg [20*8-1:0] tmp1_timing;//stores copy of TimingModel reg [7:0] tmp_char;//stores "t" or "b" character integer found = 1'b0; // powerup reg PoweredUp; //FSM control signals reg ULBYPASS ; ////Unlock Bypass Active reg ESP_ACT ; ////Erase Suspend reg OTP_ACT ; //Enter SecSi reg PDONE ; ////Prog. Done reg PSTART ; ////Start Programming reg PERR ;//Program location is in protected sector reg EDONE ; ////Ers. Done reg ESTART ; ////Start Erase reg ESUSP ; ////Suspend Erase reg ERES ; ////Resume Erase //All sectors selected for erasure are protected reg EERR ; //Sectors selected for erasure reg [SecNum:0] Ers_queue; // = SecNum'b0; reg [SubSecNum:0] Ers_Sub_queue; //Command Register reg write ; reg read ; //Sector Address integer SecAddr = 0; // 0 - SecNum integer SubSect = 0; // 0 - SubSecNum integer SA = 0; // 0 TO SecNum integer SSA = 0; // 0 TO SubSecNum //Address within sector integer Address = 0; // 0 - SecSize //A19:A11 Don't Care integer Addr ; //0 TO 16'h7FF# //glitch protection wire gWE_n ; wire gCE_n ; wire gOE_n ; reg RST ; reg reseted ; integer Mem[0:MemSize]; //Sector Protection Status reg [SecNum:0] Sec_Prot; //= SecNum'b0; //Sector Protection for first 4 sectors //or last 4, depending on chosen model reg [SubSecNum:0] SubSec_Prot; integer CFI_array[16:90]; integer SecSi[0:SecSiSize]; // timing check violation reg Viol = 1'b0; //Address of variable size sector (bottom or top boot sector) integer VarSect = -1; reg vs; integer WBData[0:1]; integer WBAddr[0:1]; reg oe = 1'b0; event oe_event; reg rd = 1'b0; event rd_event; //Status reg. reg[7:0] Status = 8'b0; reg[7:0] old_bit, new_bit; integer old_int, new_int; integer wr_cnt; integer S_ind = 0; integer ind = 0; reg[7:0] temp; reg FactoryProt; integer i,j,k; //TPD_XX_DATA time OEDQ_t; time CEDQ_t; time OENeg_event; time CENeg_event; time ADDR_event; time ADDRDQ_t; reg FROMOE; reg FROMCE; reg FROMADDR; integer OEDQ_01; integer CEDQ_01; integer ADDRDQ; reg [15:0] TempData; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (A18_ipd, A18); buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (CENeg_ipd , CENeg ); buf (OENeg_ipd , OENeg ); buf (WENeg_ipd , WENeg ); buf (WPNeg_ipd , WPNeg ); buf (RESETNeg_ipd , RESETNeg ); buf (BYTENeg_ipd , BYTENeg ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_Pass , 1); nmos (DQ14, DQ14_Pass , 1); nmos (DQ13, DQ13_Pass , 1); nmos (DQ12, DQ12_Pass , 1); nmos (DQ11, DQ11_Pass , 1); nmos (DQ10, DQ10_Pass , 1); nmos (DQ9 , DQ9_Pass , 1); nmos (DQ8 , DQ8_Pass , 1); nmos (DQ7 , DQ7_Pass , 1); nmos (DQ6 , DQ6_Pass , 1); nmos (DQ5 , DQ5_Pass , 1); nmos (DQ4 , DQ4_Pass , 1); nmos (DQ3 , DQ3_Pass , 1); nmos (DQ2 , DQ2_Pass , 1); nmos (DQ1 , DQ1_Pass , 1); nmos (DQ0 , DQ0_Pass , 1); nmos (RY , 1'b0 , ~RY_zd); wire deg; wire deg1; wire Check; assign Check = TimingChecksOn; wire CENeg_Check; assign CENeg_Check = TimingChecksOn & CENeg; wire OENeg_Check; assign OENeg_Check = TimingChecksOn & OENeg; wire WENeg_Check; assign WENeg_Check = TimingChecksOn & WENeg; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_A0_DQ0 =1; specparam tpd_CENeg_DQ0 =1; specparam tpd_OENeg_DQ0 =1; specparam tpd_BYTENeg_DQ15 =1; specparam tpd_RESETNeg_DQ0 =1; specparam tpd_WENeg_RY =1; //tBUSY // tsetup values: setup time specparam tsetup_A0_CENeg =1; //tAS edge \ specparam tsetup_DQ0_CENeg =1; //tDS edge / specparam tsetup_CENeg_WENeg =1; //0 ns / // thold values: hold times specparam thold_A0_CENeg =1; //tAH edge \ specparam thold_DQ0_CENeg =1; //tDH edge / specparam thold_OENeg_WENeg =1; //tOEH edge / specparam thold_CENeg_WENeg =1; //tCH edge / specparam thold_CENeg_RESETNeg =1; //tRH edge / specparam thold_BYTENeg_CENeg =1; //telfh, tehfl \ specparam thold_WENeg_OENeg =1; //tGHWL edge / // tpw values: pulse width specparam tpw_RESETNeg_negedge =1; //tRP specparam tpw_WENeg_negedge =1; //tWP specparam tpw_WENeg_posedge =1; //tWPH specparam tpw_A0_negedge =1; //tWC tRC // tdevice values `ifdef SPEEDSIM //Sector Erase Operation tWHWH2 specparam tdevice_SEO = 10000; //* 1000 = 10 ms; specparam tdevice_POB = 7500; //7.5 us; specparam tdevice_POW = 15000; //15 us; `else //Sector Erase Operation tWHWH2 specparam tdevice_SEO = 10000000; //* 1000 = 10 sec; specparam tdevice_POB = 75000; //75 us; specparam tdevice_POW = 150000; //150 us; `endif //SPEEDSIM //program/erase suspend timeout specparam tdevice_START_T1 = 20000; //20 us; //sector erase command sequence timeout specparam tdevice_CTMOUT = 50000; //50 us; //device ready after Hardware reset(during embeded algorithm) specparam tdevice_READY = 20000; //20 us; //tReady /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// (CENeg => RY) = tpd_WENeg_RY; (WENeg => RY) = tpd_WENeg_RY; if (FROMCE) (CENeg *> DQ0) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ1) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ2) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ3) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ4) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ5) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ6) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ7) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ8) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ9) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ10) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ11) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ12) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ13) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ14) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ15) = tpd_CENeg_DQ0; if (FROMOE) (OENeg *> DQ0) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ1) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ2) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ3) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ4) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ5) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ6) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ7) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ8) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ9) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ10) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ11) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ12) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ13) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ14) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ15) = tpd_OENeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ0) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ1) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ2) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ3) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ4) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ5) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ6) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ7) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ8) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ9) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ10) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ11) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ12) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ13) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ14) = tpd_RESETNeg_DQ0; if (~RESETNeg) (RESETNeg *> DQ15) = tpd_RESETNeg_DQ0; (A0 *> DQ0) = tpd_A0_DQ0; (A0 *> DQ1) = tpd_A0_DQ0; (A0 *> DQ2) = tpd_A0_DQ0; (A0 *> DQ3) = tpd_A0_DQ0; (A0 *> DQ4) = tpd_A0_DQ0; (A0 *> DQ5) = tpd_A0_DQ0; (A0 *> DQ6) = tpd_A0_DQ0; (A0 *> DQ7) = tpd_A0_DQ0; (A0 *> DQ8) = tpd_A0_DQ0; (A0 *> DQ9) = tpd_A0_DQ0; (A0 *> DQ10) = tpd_A0_DQ0; (A0 *> DQ11) = tpd_A0_DQ0; (A0 *> DQ12) = tpd_A0_DQ0; (A0 *> DQ13) = tpd_A0_DQ0; (A0 *> DQ14) = tpd_A0_DQ0; (A0 *> DQ15) = tpd_A0_DQ0; (A1 *> DQ0) = tpd_A0_DQ0; (A1 *> DQ1) = tpd_A0_DQ0; (A1 *> DQ2) = tpd_A0_DQ0; (A1 *> DQ3) = tpd_A0_DQ0; (A1 *> DQ4) = tpd_A0_DQ0; (A1 *> DQ5) = tpd_A0_DQ0; (A1 *> DQ6) = tpd_A0_DQ0; (A1 *> DQ7) = tpd_A0_DQ0; (A1 *> DQ8) = tpd_A0_DQ0; (A1 *> DQ9) = tpd_A0_DQ0; (A1 *> DQ10) = tpd_A0_DQ0; (A1 *> DQ11) = tpd_A0_DQ0; (A1 *> DQ12) = tpd_A0_DQ0; (A1 *> DQ13) = tpd_A0_DQ0; (A1 *> DQ14) = tpd_A0_DQ0; (A1 *> DQ15) = tpd_A0_DQ0; (A2 *> DQ0) = tpd_A0_DQ0; (A2 *> DQ1) = tpd_A0_DQ0; (A2 *> DQ2) = tpd_A0_DQ0; (A2 *> DQ3) = tpd_A0_DQ0; (A2 *> DQ4) = tpd_A0_DQ0; (A2 *> DQ5) = tpd_A0_DQ0; (A2 *> DQ6) = tpd_A0_DQ0; (A2 *> DQ7) = tpd_A0_DQ0; (A2 *> DQ8) = tpd_A0_DQ0; (A2 *> DQ9) = tpd_A0_DQ0; (A2 *> DQ10) = tpd_A0_DQ0; (A2 *> DQ11) = tpd_A0_DQ0; (A2 *> DQ12) = tpd_A0_DQ0; (A2 *> DQ13) = tpd_A0_DQ0; (A2 *> DQ14) = tpd_A0_DQ0; (A2 *> DQ15) = tpd_A0_DQ0; (A3 *> DQ0) = tpd_A0_DQ0; (A3 *> DQ1) = tpd_A0_DQ0; (A3 *> DQ2) = tpd_A0_DQ0; (A3 *> DQ3) = tpd_A0_DQ0; (A3 *> DQ4) = tpd_A0_DQ0; (A3 *> DQ5) = tpd_A0_DQ0; (A3 *> DQ6) = tpd_A0_DQ0; (A3 *> DQ7) = tpd_A0_DQ0; (A3 *> DQ8) = tpd_A0_DQ0; (A3 *> DQ9) = tpd_A0_DQ0; (A3 *> DQ10) = tpd_A0_DQ0; (A3 *> DQ11) = tpd_A0_DQ0; (A3 *> DQ12) = tpd_A0_DQ0; (A3 *> DQ13) = tpd_A0_DQ0; (A3 *> DQ14) = tpd_A0_DQ0; (A3 *> DQ15) = tpd_A0_DQ0; (A4 *> DQ0) = tpd_A0_DQ0; (A4 *> DQ1) = tpd_A0_DQ0; (A4 *> DQ2) = tpd_A0_DQ0; (A4 *> DQ3) = tpd_A0_DQ0; (A4 *> DQ4) = tpd_A0_DQ0; (A4 *> DQ5) = tpd_A0_DQ0; (A4 *> DQ6) = tpd_A0_DQ0; (A4 *> DQ7) = tpd_A0_DQ0; (A4 *> DQ8) = tpd_A0_DQ0; (A4 *> DQ9) = tpd_A0_DQ0; (A4 *> DQ10) = tpd_A0_DQ0; (A4 *> DQ11) = tpd_A0_DQ0; (A4 *> DQ12) = tpd_A0_DQ0; (A4 *> DQ13) = tpd_A0_DQ0; (A4 *> DQ14) = tpd_A0_DQ0; (A4 *> DQ15) = tpd_A0_DQ0; (A5 *> DQ0) = tpd_A0_DQ0; (A5 *> DQ1) = tpd_A0_DQ0; (A5 *> DQ2) = tpd_A0_DQ0; (A5 *> DQ3) = tpd_A0_DQ0; (A5 *> DQ4) = tpd_A0_DQ0; (A5 *> DQ5) = tpd_A0_DQ0; (A5 *> DQ6) = tpd_A0_DQ0; (A5 *> DQ7) = tpd_A0_DQ0; (A5 *> DQ8) = tpd_A0_DQ0; (A5 *> DQ9) = tpd_A0_DQ0; (A5 *> DQ10) = tpd_A0_DQ0; (A5 *> DQ11) = tpd_A0_DQ0; (A5 *> DQ12) = tpd_A0_DQ0; (A5 *> DQ13) = tpd_A0_DQ0; (A5 *> DQ14) = tpd_A0_DQ0; (A5 *> DQ15) = tpd_A0_DQ0; (A6 *> DQ0) = tpd_A0_DQ0; (A6 *> DQ1) = tpd_A0_DQ0; (A6 *> DQ2) = tpd_A0_DQ0; (A6 *> DQ3) = tpd_A0_DQ0; (A6 *> DQ4) = tpd_A0_DQ0; (A6 *> DQ5) = tpd_A0_DQ0; (A6 *> DQ6) = tpd_A0_DQ0; (A6 *> DQ7) = tpd_A0_DQ0; (A6 *> DQ8) = tpd_A0_DQ0; (A6 *> DQ9) = tpd_A0_DQ0; (A6 *> DQ10) = tpd_A0_DQ0; (A6 *> DQ11) = tpd_A0_DQ0; (A6 *> DQ12) = tpd_A0_DQ0; (A6 *> DQ13) = tpd_A0_DQ0; (A6 *> DQ14) = tpd_A0_DQ0; (A6 *> DQ15) = tpd_A0_DQ0; (A7 *> DQ0) = tpd_A0_DQ0; (A7 *> DQ1) = tpd_A0_DQ0; (A7 *> DQ2) = tpd_A0_DQ0; (A7 *> DQ3) = tpd_A0_DQ0; (A7 *> DQ4) = tpd_A0_DQ0; (A7 *> DQ5) = tpd_A0_DQ0; (A7 *> DQ6) = tpd_A0_DQ0; (A7 *> DQ7) = tpd_A0_DQ0; (A7 *> DQ8) = tpd_A0_DQ0; (A7 *> DQ9) = tpd_A0_DQ0; (A7 *> DQ10) = tpd_A0_DQ0; (A7 *> DQ11) = tpd_A0_DQ0; (A7 *> DQ12) = tpd_A0_DQ0; (A7 *> DQ13) = tpd_A0_DQ0; (A7 *> DQ14) = tpd_A0_DQ0; (A7 *> DQ15) = tpd_A0_DQ0; (A8 *> DQ0) = tpd_A0_DQ0; (A8 *> DQ1) = tpd_A0_DQ0; (A8 *> DQ2) = tpd_A0_DQ0; (A8 *> DQ3) = tpd_A0_DQ0; (A8 *> DQ4) = tpd_A0_DQ0; (A8 *> DQ5) = tpd_A0_DQ0; (A8 *> DQ6) = tpd_A0_DQ0; (A8 *> DQ7) = tpd_A0_DQ0; (A8 *> DQ8) = tpd_A0_DQ0; (A8 *> DQ9) = tpd_A0_DQ0; (A8 *> DQ10) = tpd_A0_DQ0; (A8 *> DQ11) = tpd_A0_DQ0; (A8 *> DQ12) = tpd_A0_DQ0; (A8 *> DQ13) = tpd_A0_DQ0; (A8 *> DQ14) = tpd_A0_DQ0; (A8 *> DQ15) = tpd_A0_DQ0; (A9 *> DQ0) = tpd_A0_DQ0; (A9 *> DQ1) = tpd_A0_DQ0; (A9 *> DQ2) = tpd_A0_DQ0; (A9 *> DQ3) = tpd_A0_DQ0; (A9 *> DQ4) = tpd_A0_DQ0; (A9 *> DQ5) = tpd_A0_DQ0; (A9 *> DQ6) = tpd_A0_DQ0; (A9 *> DQ7) = tpd_A0_DQ0; (A9 *> DQ8) = tpd_A0_DQ0; (A9 *> DQ9) = tpd_A0_DQ0; (A9 *> DQ10) = tpd_A0_DQ0; (A9 *> DQ11) = tpd_A0_DQ0; (A9 *> DQ12) = tpd_A0_DQ0; (A9 *> DQ13) = tpd_A0_DQ0; (A9 *> DQ14) = tpd_A0_DQ0; (A9 *> DQ15) = tpd_A0_DQ0; (A10 *> DQ0) = tpd_A0_DQ0; (A10 *> DQ1) = tpd_A0_DQ0; (A10 *> DQ2) = tpd_A0_DQ0; (A10 *> DQ3) = tpd_A0_DQ0; (A10 *> DQ4) = tpd_A0_DQ0; (A10 *> DQ5) = tpd_A0_DQ0; (A10 *> DQ6) = tpd_A0_DQ0; (A10 *> DQ7) = tpd_A0_DQ0; (A10 *> DQ8) = tpd_A0_DQ0; (A10 *> DQ9) = tpd_A0_DQ0; (A10 *> DQ10) = tpd_A0_DQ0; (A10 *> DQ11) = tpd_A0_DQ0; (A10 *> DQ12) = tpd_A0_DQ0; (A10 *> DQ13) = tpd_A0_DQ0; (A10 *> DQ14) = tpd_A0_DQ0; (A10 *> DQ15) = tpd_A0_DQ0; (A11 *> DQ0) = tpd_A0_DQ0; (A11 *> DQ1) = tpd_A0_DQ0; (A11 *> DQ2) = tpd_A0_DQ0; (A11 *> DQ3) = tpd_A0_DQ0; (A11 *> DQ4) = tpd_A0_DQ0; (A11 *> DQ5) = tpd_A0_DQ0; (A11 *> DQ6) = tpd_A0_DQ0; (A11 *> DQ7) = tpd_A0_DQ0; (A11 *> DQ8) = tpd_A0_DQ0; (A11 *> DQ9) = tpd_A0_DQ0; (A11 *> DQ10) = tpd_A0_DQ0; (A11 *> DQ11) = tpd_A0_DQ0; (A11 *> DQ12) = tpd_A0_DQ0; (A11 *> DQ13) = tpd_A0_DQ0; (A11 *> DQ14) = tpd_A0_DQ0; (A11 *> DQ15) = tpd_A0_DQ0; (A12 *> DQ0) = tpd_A0_DQ0; (A12 *> DQ1) = tpd_A0_DQ0; (A12 *> DQ2) = tpd_A0_DQ0; (A12 *> DQ3) = tpd_A0_DQ0; (A12 *> DQ4) = tpd_A0_DQ0; (A12 *> DQ5) = tpd_A0_DQ0; (A12 *> DQ6) = tpd_A0_DQ0; (A12 *> DQ7) = tpd_A0_DQ0; (A12 *> DQ8) = tpd_A0_DQ0; (A12 *> DQ9) = tpd_A0_DQ0; (A12 *> DQ10) = tpd_A0_DQ0; (A12 *> DQ11) = tpd_A0_DQ0; (A12 *> DQ12) = tpd_A0_DQ0; (A12 *> DQ13) = tpd_A0_DQ0; (A12 *> DQ14) = tpd_A0_DQ0; (A12 *> DQ15) = tpd_A0_DQ0; (A13 *> DQ0) = tpd_A0_DQ0; (A13 *> DQ1) = tpd_A0_DQ0; (A13 *> DQ2) = tpd_A0_DQ0; (A13 *> DQ3) = tpd_A0_DQ0; (A13 *> DQ4) = tpd_A0_DQ0; (A13 *> DQ5) = tpd_A0_DQ0; (A13 *> DQ6) = tpd_A0_DQ0; (A13 *> DQ7) = tpd_A0_DQ0; (A13 *> DQ8) = tpd_A0_DQ0; (A13 *> DQ9) = tpd_A0_DQ0; (A13 *> DQ10) = tpd_A0_DQ0; (A13 *> DQ11) = tpd_A0_DQ0; (A13 *> DQ12) = tpd_A0_DQ0; (A13 *> DQ13) = tpd_A0_DQ0; (A13 *> DQ14) = tpd_A0_DQ0; (A13 *> DQ15) = tpd_A0_DQ0; (A14 *> DQ0) = tpd_A0_DQ0; (A14 *> DQ1) = tpd_A0_DQ0; (A14 *> DQ2) = tpd_A0_DQ0; (A14 *> DQ3) = tpd_A0_DQ0; (A14 *> DQ4) = tpd_A0_DQ0; (A14 *> DQ5) = tpd_A0_DQ0; (A14 *> DQ6) = tpd_A0_DQ0; (A14 *> DQ7) = tpd_A0_DQ0; (A14 *> DQ8) = tpd_A0_DQ0; (A14 *> DQ9) = tpd_A0_DQ0; (A14 *> DQ10) = tpd_A0_DQ0; (A14 *> DQ11) = tpd_A0_DQ0; (A14 *> DQ12) = tpd_A0_DQ0; (A14 *> DQ13) = tpd_A0_DQ0; (A14 *> DQ14) = tpd_A0_DQ0; (A14 *> DQ15) = tpd_A0_DQ0; (A15 *> DQ0) = tpd_A0_DQ0; (A15 *> DQ1) = tpd_A0_DQ0; (A15 *> DQ2) = tpd_A0_DQ0; (A15 *> DQ3) = tpd_A0_DQ0; (A15 *> DQ4) = tpd_A0_DQ0; (A15 *> DQ5) = tpd_A0_DQ0; (A15 *> DQ6) = tpd_A0_DQ0; (A15 *> DQ7) = tpd_A0_DQ0; (A15 *> DQ8) = tpd_A0_DQ0; (A15 *> DQ9) = tpd_A0_DQ0; (A15 *> DQ10) = tpd_A0_DQ0; (A15 *> DQ11) = tpd_A0_DQ0; (A15 *> DQ12) = tpd_A0_DQ0; (A15 *> DQ13) = tpd_A0_DQ0; (A15 *> DQ14) = tpd_A0_DQ0; (A15 *> DQ15) = tpd_A0_DQ0; (A16 *> DQ0) = tpd_A0_DQ0; (A16 *> DQ1) = tpd_A0_DQ0; (A16 *> DQ2) = tpd_A0_DQ0; (A16 *> DQ3) = tpd_A0_DQ0; (A16 *> DQ4) = tpd_A0_DQ0; (A16 *> DQ5) = tpd_A0_DQ0; (A16 *> DQ6) = tpd_A0_DQ0; (A16 *> DQ7) = tpd_A0_DQ0; (A16 *> DQ8) = tpd_A0_DQ0; (A16 *> DQ9) = tpd_A0_DQ0; (A16 *> DQ10) = tpd_A0_DQ0; (A16 *> DQ11) = tpd_A0_DQ0; (A16 *> DQ12) = tpd_A0_DQ0; (A16 *> DQ13) = tpd_A0_DQ0; (A16 *> DQ14) = tpd_A0_DQ0; (A16 *> DQ15) = tpd_A0_DQ0; (A17 *> DQ0) = tpd_A0_DQ0; (A17 *> DQ1) = tpd_A0_DQ0; (A17 *> DQ2) = tpd_A0_DQ0; (A17 *> DQ3) = tpd_A0_DQ0; (A17 *> DQ4) = tpd_A0_DQ0; (A17 *> DQ5) = tpd_A0_DQ0; (A17 *> DQ6) = tpd_A0_DQ0; (A17 *> DQ7) = tpd_A0_DQ0; (A17 *> DQ8) = tpd_A0_DQ0; (A17 *> DQ9) = tpd_A0_DQ0; (A17 *> DQ10) = tpd_A0_DQ0; (A17 *> DQ11) = tpd_A0_DQ0; (A17 *> DQ12) = tpd_A0_DQ0; (A17 *> DQ13) = tpd_A0_DQ0; (A17 *> DQ14) = tpd_A0_DQ0; (A17 *> DQ15) = tpd_A0_DQ0; (A18 *> DQ0) = tpd_A0_DQ0; (A18 *> DQ1) = tpd_A0_DQ0; (A18 *> DQ2) = tpd_A0_DQ0; (A18 *> DQ3) = tpd_A0_DQ0; (A18 *> DQ4) = tpd_A0_DQ0; (A18 *> DQ5) = tpd_A0_DQ0; (A18 *> DQ6) = tpd_A0_DQ0; (A18 *> DQ7) = tpd_A0_DQ0; (A18 *> DQ8) = tpd_A0_DQ0; (A18 *> DQ9) = tpd_A0_DQ0; (A18 *> DQ10) = tpd_A0_DQ0; (A18 *> DQ11) = tpd_A0_DQ0; (A18 *> DQ12) = tpd_A0_DQ0; (A18 *> DQ13) = tpd_A0_DQ0; (A18 *> DQ14) = tpd_A0_DQ0; (A18 *> DQ15) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ0 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ1 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ2 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ3 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ4 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ5 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ6 ) = tpd_A0_DQ0; if (~BYTENeg)( DQ15 *> DQ7 ) = tpd_A0_DQ0; if (BYTENeg)( BYTENeg *> DQ8 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ9 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ10 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ11 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ12 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ13 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ14 ) = tpd_BYTENeg_DQ15; if (BYTENeg)( BYTENeg *> DQ15 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ8 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ9 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ10 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ11 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ12 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ13 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ14 ) = tpd_BYTENeg_DQ15; if (~BYTENeg)( BYTENeg *> DQ15 ) = tpd_BYTENeg_DQ15; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// $setup ( A0 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A1 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A2 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A3 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A4 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A5 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A6 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A7 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A8 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A9 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A10 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A11 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A12 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A13 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A14 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A15 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A16 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A17 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A18 , negedge CENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A0 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A1 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A2 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A3 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A4 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A5 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A6 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A7 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A8 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A9 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A10 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A11 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A12 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A13 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A14 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A15 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A16 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A17 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( A18 , negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $setup ( DQ0 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge CENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ0 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge WENeg &&& deg1, tsetup_DQ0_CENeg, Viol); $setup ( WENeg , negedge CENeg &&& Check, tsetup_CENeg_WENeg, Viol); $setup ( CENeg , negedge WENeg &&& Check, tsetup_CENeg_WENeg, Viol); $setup ( BYTENeg, negedge WENeg &&& Check, tsetup_A0_CENeg, Viol); $hold ( posedge RESETNeg &&& CENeg_Check, CENeg,thold_CENeg_RESETNeg,Viol); $hold ( posedge RESETNeg &&& OENeg_Check, OENeg,thold_CENeg_RESETNeg,Viol); $hold ( posedge RESETNeg &&& WENeg_Check, WENeg,thold_CENeg_RESETNeg,Viol); $hold ( posedge OENeg &&& Check, WENeg, thold_WENeg_OENeg, Viol); $hold ( posedge CENeg &&& Check, WENeg , thold_CENeg_WENeg, Viol); $hold ( posedge WENeg &&& Check, OENeg , thold_OENeg_WENeg, Viol); $hold ( posedge WENeg &&& Check, CENeg , thold_CENeg_WENeg, Viol); $hold ( negedge CENeg &&& Check, BYTENeg, thold_BYTENeg_CENeg, Viol); $hold ( negedge WENeg &&& Check, BYTENeg, thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A0 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A1 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A2 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A3 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A4 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A5 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A6 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A7 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A8 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A9 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A10 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A11 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A12 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A13 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A14 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A15 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A16 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A17 , thold_A0_CENeg, Viol); $hold ( negedge CENeg &&& (WENeg===0), A18 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A0 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A1 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A2 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A3 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A4 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A5 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A6 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A7 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A8 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A9 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A10 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A11 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A12 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A13 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A14 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A15 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A16 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A17 , thold_A0_CENeg, Viol); $hold ( negedge WENeg &&& Check, A18 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ1 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ2 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ3 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ4 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ5 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ6 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ7 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ8 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ9 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ10, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ11, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ12, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ13, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ14, thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& deg1, DQ15, thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ1 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ2 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ3 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ4 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ5 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ6 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ7 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ8 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ9 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ10 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ11 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ12 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ13 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ14 , thold_DQ0_CENeg, Viol); $hold ( posedge WENeg &&& deg1, DQ15 , thold_DQ0_CENeg, Viol); $width (negedge RESETNeg &&& Check, tpw_RESETNeg_negedge); $width (posedge WENeg &&& Check, tpw_WENeg_posedge); $width (negedge WENeg &&& Check, tpw_WENeg_negedge); $width (posedge CENeg &&& Check, tpw_WENeg_posedge); $width (negedge CENeg &&& Check, tpw_WENeg_negedge); $width (negedge A0 &&& Check, tpw_A0_negedge); $width (posedge A0 &&& Check, tpw_A0_negedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// // FSM states parameter RESET =6'd0; parameter Z001 =6'd1; parameter PREL_SETBWB =6'd2; parameter PREL_ULBYPASS =6'd3; parameter PREL_ULBYPASS_Z001 =6'd4; parameter CFI =6'd5; parameter AS =6'd6; parameter OTP =6'd7; parameter OTP_Z001 =6'd8; parameter OTP_PREL =6'd9; parameter OTP_AS =6'd10; parameter OTP_A0SEEN =6'd11; parameter A0SEEN =6'd12; parameter C8 =6'd13; parameter C8_Z001 =6'd14; parameter C8_PREL =6'd15; parameter ERS =6'd16; parameter SERS =6'd17; parameter ESPS =6'd18; parameter SERS_EXEC =6'd19; parameter ESP =6'd20; parameter ESP_Z001 =6'd21; parameter ESP_PREL =6'd22; parameter ESP_CFI =6'd23; parameter ESP_A0SEEN =6'd24; parameter ESP_AS =6'd25; parameter PGMS =6'd26; reg [5:0] current_state; reg [5:0] next_state; reg rising_edge_WENeg; reg rising_edge_CENeg; reg rising_edge_write; reg rising_edge_EDONE; reg rising_edge_CTMOUT_out; reg rising_edge_START_T1_out; reg rising_edge_PDONE; reg rising_edge_WPNeg; reg falling_edge_WENeg; reg falling_edge_CENeg; reg falling_edge_OENeg; reg falling_edge_write; reg falling_edge_EERR; reg falling_edge_PERR; reg falling_edge_WPNeg; reg A_event; reg DIn_15_event; reg BYTENeg_event; reg rising_edge_RESETNeg = 1'b0; reg falling_edge_RESETNeg = 1'b0; reg deq; integer tmp1,tmp2,tmp3; integer sector_preload[0:MemSize]; reg sector_prot[0:SecNum+SubSecNum+1]; always @(DIn, DOut) begin if (DIn==DOut) deq=1'b1; else deq=1'b0; end // check when data is generated from model to avoid setuphold check in // those occasion assign deg=deq; assign deg1= deq && Check; // find which 4 sectors have variable size initial begin //TOP OR BOTTOM arch model is used //assumptions: //1. TimingModel has format as //"s29al008j" //2. TimingModel does not have more then 20 characters tmp_timing = TimingModel;//copy of TimingModel i = 19; while ((i >= 0) && (found != 1'b1))//search for first non null character begin //i keeps position of first non null character j = 7; while ((j >= 0) && (found != 1'b1)) begin if (tmp_timing[i*8+j] != 1'd0) found = 1'b1; else j = j-1; end i = i - 1; end i = i +1; if (found)//if non null character is found begin for (j=0;j<=7;j=j+1) begin tmp_char[j] = TimingModel[(i-9)*8+j];//bottom/top character is 10 end //characters right from first end if (tmp_char == "T") begin VarSect = SecNum; vs = 1'b1; end else begin VarSect = 0; vs = 1'b0; end // initialize memory and load preoload files if any for (i=0;i<(SecSize+1)*(SecNum+1);i=i+1) Mem[i]=MaxData; for (i=0;i<=SecSiSize;i=i+1) SecSi[i]=MaxData; for (i=0;i<=SecNum+SubSecNum+1;i=i+1) begin sector_prot[i]=0; end for (i=0;i<=SubSecNum;i=i+1) begin SubSec_Prot[i] = 0; Ers_Sub_queue[i] = 0; end for (i=0;i<=SecNum;i=i+1) begin Sec_Prot[i] = 0; Ers_queue[i] = 0; end if (UserPreload && prot_file_name != "none") begin //s29al008j_prot sector protect file // // - comment // @aaa - stands for sector address // (aaaa is incremented at every load) // b - is 1 for protected sector , 0 for unprotect. $readmemb(prot_file_name,sector_prot); end if (UserPreload && secsi_file_name != "none") begin // Secure Silicon Sector Region preload // s29al008j_secsi memory file // // - comment // @aa - stands for address within last defined sector // dd -
is byte to be written at SecSi(aa++) // (aa is incremented at every load) $readmemh(secsi_file_name,SecSi); end if (UserPreload && mem_file_name != "none") begin //s29al008j.mem, memory preload file // @aaaaaa - stands for address within last defined sector // dd -
is byte to be written at Mem(nn)(aaaaaa++) // (aaaaaa is incremented at every load) $readmemh(mem_file_name,Mem); end FactoryProt = sector_prot[SecNum+SubSecNum+1]; if ( VarSect == 0 ) begin tmp2 = SubSecNum+1; tmp3 = SubSecNum; end else begin tmp2 = 0; tmp3 = 0; end //subsector protect for (i=0;i<=SubSecNum;i=i+1) begin SubSec_Prot[i] = sector_prot[i+VarSect]; end //sector protect for (i=tmp2;i= sssa(vs, i) && A_tmp1 <= ssea(vs, i)) begin SubSect = i; end end Addr = A_tmp; end end end ///////////////////////////////////////////////////////////////////////// // Timing control for the Program Operation start ///////////////////////////////////////////////////////////////////////// integer cnt_write = 0; time duration_write ; event pdone_event; always @(posedge reseted) begin PDONE = 1'b1; end always @(reseted or PSTART) begin : programming if (reseted) begin if (PSTART && PDONE) begin if ( (SA != VarSect && ~Sec_Prot[SA] && (~Ers_queue[SA] || ~ESP_ACT ) && (FactoryProt == 0 || ~OTP_ACT ) ) || ( SA == VarSect && ~SubSec_Prot[SSA] && (~Ers_Sub_queue[SSA] || ~ESP_ACT) && (FactoryProt == 0 || ~OTP_ACT) ) ) begin if (BYTENeg) duration_write = tdevice_POW; else duration_write = tdevice_POB; PDONE = 1'b0; ->pdone_event; end else begin PERR = 1'b1; PERR <= #1000 1'b0; end end end end always @(pdone_event) begin:pdone_process PDONE = 1'b0; #duration_write PDONE = 1'b1; end ///////////////////////////////////////////////////////////////////////// // Timing control for the Erase Operations ///////////////////////////////////////////////////////////////////////// integer cnt_erase = 0; // 0 - SecNum+SubSecNum time elapsed_erase; time duration_erase; time start_erase; always @(posedge reseted) begin disable edone_process; EDONE = 1'b1; end event edone_event; always @(reseted or ESTART) begin: erase integer i; time tdevice_SEO1; if (reseted) begin if (ESTART && EDONE) begin cnt_erase = 0; for (i=0;i<=SecNum;i=i+1) begin if ( i == VarSect ) begin for(j=0;j<=SubSecNum;j=j+1) begin if ((Ers_Sub_queue[j]==1'b1) && (~SubSec_Prot[j])) cnt_erase = cnt_erase + 1; end end else begin if ((Ers_queue[i]==1'b1) && (Sec_Prot[i]!=1'b1)) cnt_erase = cnt_erase + 1; end end if (cnt_erase>0) begin elapsed_erase = 0; tdevice_SEO1 = tdevice_SEO * 1000; duration_erase = cnt_erase* tdevice_SEO1; ->edone_event; start_erase = $time; end else begin EERR = 1'b1; EERR <= #100000 1'b0; end end end end always @(edone_event) begin : edone_process EDONE = 1'b0; #duration_erase EDONE = 1'b1; end always @(reseted or ESUSP) begin if (reseted) if (ESUSP && ~EDONE) begin disable edone_process; elapsed_erase = $time - start_erase; duration_erase = duration_erase - elapsed_erase; EDONE = 1'b0; end end always @(reseted or ERES) begin if (reseted) if (ERES && ~EDONE) begin start_erase = $time; EDONE = 1'b0; ->edone_event; end end ///////////////////////////////////////////////////////////////////////// // Main Behavior Process // combinational process for next state generation ///////////////////////////////////////////////////////////////////////// reg PATTERN_1 = 1'b0; reg PATTERN_2 = 1'b0; reg A_PAT_1 = 1'b0; //DATA High Byte integer DataHi ; //DATA Low Byte integer DataLo ; always @(falling_edge_write or rising_edge_EDONE or falling_edge_EERR or rising_edge_CTMOUT_out or rising_edge_START_T1_out or reseted or falling_edge_EERR or rising_edge_PDONE or falling_edge_PERR ) begin : Next_State if (falling_edge_write) begin DataLo = DIn[7:0]; if (BYTENeg) DataHi = DIn[15:8]; PATTERN_1 = (Addr==16'h555) && (DataLo==8'hAA) ; PATTERN_2 = (Addr==16'h2AA) && (DataLo==8'h55) ; A_PAT_1 = ((Addr==16'h555) && ~ULBYPASS) || ULBYPASS; end if (reseted!=1'b1) next_state = current_state; else case (current_state) RESET : begin if (falling_edge_write) begin if (PATTERN_1) next_state = Z001; else if ((Addr==8'h55) && (DataLo==8'h98)) next_state = CFI; else next_state = RESET; end end Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = PREL_SETBWB; else next_state = RESET; end end PREL_SETBWB : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h20)) next_state = PREL_ULBYPASS; else if (A_PAT_1 && (DataLo==16'h90)) next_state = AS; else if (A_PAT_1 && (DataLo==16'hA0)) #1 next_state = A0SEEN; else if (A_PAT_1 && (DataLo==16'h80)) next_state = C8; else if (A_PAT_1 && (DataLo==16'h88)) next_state = OTP; else next_state = RESET; end end PREL_ULBYPASS : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h90)) next_state = PREL_ULBYPASS_Z001; else if (A_PAT_1 && (DataLo==16'hA0)) next_state = A0SEEN; else if (A_PAT_1 && (DataLo==16'h80)) next_state = C8_PREL; else next_state = PREL_ULBYPASS; end end PREL_ULBYPASS_Z001 : begin if (falling_edge_write) begin if (DataLo == 8'h00) begin if (ESP_ACT) next_state = ESP; else next_state = RESET; end else next_state = PREL_ULBYPASS; end end CFI : begin if (falling_edge_write) begin if ( DataLo==16'hF0 ) next_state = RESET; else next_state = CFI; end end AS : begin if (falling_edge_write) begin if (DataLo==16'hF0) next_state = RESET; else if ( Addr == 8'h55 && DataLo == 8'h98 ) next_state = CFI; else next_state = AS; end end A0SEEN : begin if (falling_edge_write) next_state = PGMS; else next_state = A0SEEN; end OTP : begin if (falling_edge_write) begin if (PATTERN_1) next_state = OTP_Z001; else next_state = OTP; end end OTP_Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = OTP_PREL; else next_state = OTP; end end OTP_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo == 8'h90)) next_state = OTP_AS; else if (A_PAT_1 && (DataLo == 8'hA0)) next_state = OTP_A0SEEN; else next_state = OTP; end end OTP_AS : begin if (falling_edge_write) if (DataLo==16'h00) begin if (ESP_ACT) next_state = ESP; else next_state = RESET; end else if (DataLo==16'hF0) next_state = OTP; else next_state = OTP_AS; end OTP_A0SEEN : begin if (falling_edge_write) begin if ((vs == 1 && SecAddr == VarSect && Address >= 16'hFF00 && Address <= 16'hFFFF) || (vs == 0 && SecAddr == 16'h00 && Address >= 16'h0000 && Address <= 16'h00FF)) next_state = PGMS; else next_state = OTP; end end C8 : begin if (falling_edge_write) begin if (PATTERN_1) next_state = C8_Z001; else next_state = RESET; end end C8_Z001 : begin if (falling_edge_write) begin if (PATTERN_2) next_state = C8_PREL; else next_state = RESET; end end C8_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h10)) next_state = ERS; else if (DataLo==16'h30) next_state = SERS; else if (ULBYPASS) next_state = PREL_ULBYPASS; else next_state = RESET; end end ERS : begin if (rising_edge_EDONE || falling_edge_EERR) begin if (ULBYPASS) next_state = PREL_ULBYPASS; else next_state = RESET; end end SERS : begin if (rising_edge_CTMOUT_out) next_state = SERS_EXEC; else if (falling_edge_write) begin if (DataLo == 16'hB0) next_state = ESP; else if (DataLo==16'h30) next_state = SERS; else if (ULBYPASS) next_state = PREL_ULBYPASS; else next_state = RESET; end end ESPS : begin if (rising_edge_START_T1_out) next_state = ESP; end SERS_EXEC : begin if (rising_edge_EDONE || falling_edge_EERR) begin if (ULBYPASS) next_state = PREL_ULBYPASS; else next_state = RESET; end else if (EERR != 1'b1) begin if (falling_edge_write) if (DataLo == 16'hB0) next_state = ESPS; end end ESP : begin if (falling_edge_write) begin if (DataLo == 16'h30) next_state = SERS_EXEC; else if (A_PAT_1 && (DataLo == 16'h90)) next_state = ESP_AS; if ((Addr == 16'h55) && (DataLo == 16'h98)) next_state = ESP_CFI; else if (PATTERN_1) next_state = ESP_Z001; end end ESP_Z001 : begin if (falling_edge_write) if (PATTERN_2) next_state = ESP_PREL; else next_state = ESP; end ESP_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo == 16'h20)) next_state = PREL_ULBYPASS ; else if (A_PAT_1 && DataLo == 16'hA0) next_state = ESP_A0SEEN; else if (A_PAT_1 && DataLo == 16'h88) next_state = OTP; else if (A_PAT_1 && DataLo == 16'h90) next_state = ESP_AS; else next_state = ESP; end end ESP_CFI : begin if (falling_edge_write) begin if ((Addr == 16'h55) && (DataLo == 16'h98)) begin end else if (DataLo == 16'hF0) next_state = ESP; else next_state = ESP_CFI; end end ESP_A0SEEN : begin if (falling_edge_write) next_state = PGMS; end ESP_AS : begin if (falling_edge_write) if (DataLo == 16'hF0) next_state = ESP; end PGMS : begin if (rising_edge_PDONE || falling_edge_PERR) begin if (ESP_ACT) next_state = ESP; else if (ULBYPASS) next_state = PREL_ULBYPASS; else if (OTP_ACT) next_state = OTP; else next_state = RESET; end end endcase end /////////////////////////////////////////////////////////////////////////// //FSM Output generation and general funcionality /////////////////////////////////////////////////////////////////////////// reg corrupt = 1'b0; always @(falling_edge_write or reseted or current_state or rising_edge_EDONE or oe or rd or rising_edge_CTMOUT_out or rising_edge_START_T1_out or rising_edge_PDONE ) begin : Functional if (reseted) begin case (current_state) RESET : begin ESP_ACT = 0; OTP_ACT = 0; ULBYPASS = 0; CTMOUT_in = 0; if (oe || rd) begin MemRead(DOut_zd[15:0]); end RY_zd = 1'b1; end Z001 : begin end PREL_SETBWB : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h20)) ULBYPASS = 1'b1; else if (A_PAT_1 && (DataLo==16'h90)) ULBYPASS = 1'b0; else if (A_PAT_1 && (DataLo==16'h88)) begin ULBYPASS = 1'b0; OTP_ACT = 1'b1; end end end PREL_ULBYPASS : begin if (falling_edge_write) begin if (DataLo==16'h20) ULBYPASS = 1'b1; else if (A_PAT_1 && (DataLo==16'h90)) begin ULBYPASS = 1'b0; ESP_ACT = 1'b0; end end //ready signal active RY_zd = 1'b1; end PREL_ULBYPASS_Z001 : begin if (falling_edge_write) begin if (DataLo == 16'h00) ULBYPASS = 0; end RY_zd = 1; end CFI : begin if (falling_edge_write) begin if (DataLo == 16'hF0) ULBYPASS = 0; end else if (oe) begin DOut_zd[15:0] = 16'b0; if ((Addr>=16'h10) && (Addr<=16'h50)) DOut_zd[7:0] = CFI_array[Addr]; else $display ("Invalid CFI query address"); end end AS : begin if (oe || rd) ASRead(DOut_zd); end A0SEEN : begin if (falling_edge_write) begin WBData[0] = -1; WBData[1] = -1; if (Viol == 1'b0) begin WBData[0] = DataLo; WBData[1] = DataHi; end Viol = 1'b0; WBAddr[0] = Address; SA = SecAddr; SSA = SubSect; PSTART = 1'b1; PSTART <= #1 1'b0; temp = DataLo; Status[7] = ~temp[7]; if (BYTENeg) WBAddr[1] = WBAddr[0] +1; else WBAddr[1] = -1; end end OTP : begin OTP_ACT = 1; if (oe || rd) begin //read SecSi Sector Region if (((vs == 1) && (SecAddr == VarSect) && ((Address >= 16'hFF00) && (Address <= 16'hFFFF))) || ((vs == 0) && (SecAddr == VarSect) && ((Address >= 16'h0000) && (Address <= 16'h00FF)))) begin if (SecSi[(Address % (SecSiSize + 1))]==-1) DOut_zd[7:0] = 8'bx; else DOut_zd[7:0] = SecSi[(Address % (SecSiSize + 1))]; if (BYTENeg) if (SecSi[(Address % (SecSiSize + 1))+1]==-1) DOut_zd[15:8]= 8'bx; else DOut_zd[15:8] = SecSi[(Address % (SecSiSize + 1))+1]; end else $display("Invalid address in SecSi mode"); end RY_zd = 1; end OTP_Z001 : begin end OTP_PREL : begin end OTP_AS : begin if (falling_edge_write) if (DataLo == 16'h00) OTP_ACT = 0; end OTP_A0SEEN : begin if (falling_edge_write) begin OTP_ACT = 1'b1; if (((vs == 1) && (SecAddr == VarSect) && ((Address >= 16'hFF00) && (Address <= 16'hFFFF))) || ((vs == 0) && (SecAddr == VarSect) && ((Address >= 16'h0000) && (Address <= 16'h00FF)))) begin PSTART = 1'b1; PSTART <= #1 1'b0; end WBData[0] = -1; WBData[1] = -1; if (Viol==1'b0) begin WBData[0] = DataLo; WBData[1] = DataHi; end Viol = 1'b0; WBAddr[0] = (Address % (SecSiSize + 1)) ; SA = SecAddr; SSA = SubSect; temp = DataLo; Status[7] = ~temp[7]; if (BYTENeg) WBAddr[1] = WBAddr[0] +1; else WBAddr[1] = -1; end end C8 : begin end C8_Z001 : begin end C8_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && (DataLo==16'h10)) begin //Start Chip Erase ESTART = 1'b1; ESTART <= #1 1'b0; ESUSP = 1'b0; ERES = 1'b0; Ers_queue = ~(0); Ers_Sub_queue = ~(0); Status = 8'b00001000; end else if (DataLo==16'h30) begin //put selected sector to sec. ers. queue //start timeout Ers_queue = 0; Ers_Sub_queue = 0; if ( SecAddr == VarSect ) Ers_Sub_queue[SubSect] = 1'b1; else Ers_queue[SecAddr] = 1'b1; disable TCTMOUTr; CTMOUT_in = 1'b0; #1 CTMOUT_in <= 1'b1; end end end ERS : begin if (oe || rd) begin /////////////////////////////////////////////////////////// // read status / embeded erase algorithm - Chip Erase /////////////////////////////////////////////////////////// Status[7] = 1'b0; Status[6] = ~Status[6]; //toggle Status[5] = 1'b0; Status[3] = 1'b1; Status[2] = ~Status[2]; //toggle DOut_zd[7:0] = Status; end if (EERR!=1'b1 ) begin if (~corrupt) begin for (i=0;i<=SecNum;i=i+1) begin if (i == VarSect) begin for( j=0;j<=SubSecNum;j=j+1) if (SubSec_Prot[j]!=1'b1) begin for(k=sssa(vs, j);k<=ssea(vs, j);k=k+1) Mem[sa(i)+k] = -1; end end else begin if (Sec_Prot[i]!=1'b1) for (j=0;j<=SecSize;j=j+1) begin Mem[sa(i)+j] = -1; end end corrupt = 1; end end if (rising_edge_EDONE && corrupt) begin corrupt = 0; for (i=0;i<=SecNum;i=i+1) begin if ( i == VarSect ) begin for( j=0;j<=SubSecNum;j=j+1) if ( SubSec_Prot[j]!=1'b1 ) for(k=sssa(vs, j);k<=ssea(vs, j);k=k+1) Mem[sa(i)+k] = MaxData; end else begin if (Sec_Prot[i]!=1'b1) for (j=0;j<=SecSize;j=j+1) begin Mem[sa(i)+j] = MaxData; end end end end end // busy signal active RY_zd = 1'b0; end SERS : begin if (oe || rd) begin /////////////////////////////////////////////////////////// //read status - sector erase timeout /////////////////////////////////////////////////////////// Status[3] = 1'b0; DOut_zd[7:0] = Status; end if (rising_edge_CTMOUT_out) begin CTMOUT_in = 0; START_T1_in = 0; ESTART = 1; ESTART <= #1 0; ESUSP = 0; ERES = 0; end if (falling_edge_write) begin if (DataLo == 16'hB0) begin ESTART = 1'b1; ESTART <= #1 1'b0; // must start erase prior to suspend // for edone_event ESUSP = 1'b1; ESUSP <= #1 1'b0; ERES = 1'b0; ESP_ACT = 1'b1; end else if (DataLo==16'h30) begin disable TCTMOUTr; CTMOUT_in = 1'b0; #1 CTMOUT_in <= 1'b1; if ( SecAddr == VarSect ) Ers_Sub_queue[SubSect] = 1'b1; else Ers_queue[SecAddr] = 1'b1; end end //ready signal active RY_zd = 1'b0; end ESPS : begin ESUSP = 1; if (rising_edge_START_T1_out) begin ESP_ACT = 1'b1; START_T1_in = 1'b0; end if (oe || rd) begin /////////////////////////////////////////////////////////// //read status / erase suspend timeout - stil erasing /////////////////////////////////////////////////////////// //read is modified so status 2 toggles only if sector // selected for erasure is read // if sector that is not selected for erasure is read // Status 2 stays does not change vaule if (( SecAddr != VarSect && Ers_queue[SecAddr]==1'b1) || ( SecAddr == VarSect && Ers_Sub_queue[SubSect]==1'b1)) Status[2] = ~Status[2]; //toggle Status[7] = 1'b0; Status[6] = ~Status[6]; //toggle Status[5] = 1'b0; Status[3] = 1'b1; DOut_zd[7:0] = Status; end //busy signal active RY_zd = 1'b0; end SERS_EXEC: begin if (oe || rd) begin /////////////////////////////////////////////////// //read status erase /////////////////////////////////////////////////// //read is modified so status 2 toggles only if sector // selected for erasure is read // if sector that is not selected for erasure is read // Status 2 stays does not change vaule if (( SecAddr != VarSect && Ers_queue[SecAddr]==1'b1) || ( SecAddr == VarSect && Ers_Sub_queue[SubSect]==1'b1)) Status[2] = ~Status[2]; //toggle Status[7] = 1'b0; Status[6] = ~Status[6]; //toggle Status[5] = 1'b0; Status[3] = 1'b1; DOut_zd[7:0] = Status; end if (falling_edge_write) begin if (DataLo==16'hB0) START_T1_in = 1'b1; end if (EERR!=1'b1 && ~oe && ~rd) begin if (~rising_edge_EDONE) begin for (i=0;i<=SecNum;i=i+1) begin if ( i == VarSect) begin for( j=0;j<=SubSecNum;j=j+1) if (SubSec_Prot[j]!=1'b1 && Ers_Sub_queue[j]==1'b1) for(k=sssa(vs,j);k<=ssea(vs,j);k=k+1) Mem[sa(i)+k] = -1; end else begin if (Sec_Prot[i]!=1'b1 && Ers_queue[i]) for (j=0;j<=SecSize;j=j+1) Mem[sa(i)+j] = -1; end end end if (rising_edge_EDONE) begin for (i=0;i<=SecNum;i=i+1) begin if ( i == VarSect ) begin for( j=0;j<=SubSecNum;j=j+1) if (SubSec_Prot[j]!=1'b1 && Ers_Sub_queue[j]) for(k=sssa(vs,j);k<=ssea(vs,j);k=k+1) Mem[sa(i)+k] = MaxData; end else begin if (Sec_Prot[i]!=1'b1 && Ers_queue[i]) for (j=0;j<=SecSize;j=j+1) begin Mem[sa(i)+j] = MaxData; end end end end end //busy signal active RY_zd = 1'b0; end ESP : begin ESUSP = 1'b0; if (falling_edge_write) begin if (DataLo == 16'h30) begin //resume erase ERES = 1'b1; ERES <= #1 1'b0; ESP_ACT = 0; end end if (oe || rd) begin /////////////////////////////////////////////////////////// //read /////////////////////////////////////////////////////////// if (( SecAddr != VarSect && Ers_queue[SecAddr]!=1'b1) || ( SecAddr == VarSect && Ers_Sub_queue[SubSect]!=1'b1)) MemRead(DOut_zd[15:0]); else begin /////////////////////////////////////////////////////// //read status /////////////////////////////////////////////////////// Status[7] = 1'b1; // Status[6) No toggle Status[5] = 1'b0; Status[2] = ~Status[2]; //toggle DOut_zd[7:0] = Status; end end RY_zd = 1; end ESP_Z001 : begin end ESP_PREL : begin if (falling_edge_write) begin if (A_PAT_1 && DataLo == 8'h20) ULBYPASS = 1; end end ESP_CFI : begin if (oe) begin DOut_zd[15:0] = 16'b0; if ((Addr>=16'h10)&&(Addr<=16'h50)) DOut_zd[7:0] = CFI_array[Addr]; else $display("Invalid CFI query address"); end end ESP_A0SEEN : begin if (falling_edge_write) begin ESP_ACT = 1'b1; PSTART = 1'b1; PSTART <= #1 1'b0; WBData[0] = -1; WBData[1] = -1; if (Viol==1'b0) begin WBData[0] = DataLo; WBData[1] = DataHi; end Viol = 1'b0; WBAddr[0] = Address; SA = SecAddr; SSA = SubSect; temp = DataLo; Status[7] = ~temp[7]; if (BYTENeg) WBAddr[1] = WBAddr[0] +1; else WBAddr[1] = -1; end end ESP_AS : begin if (falling_edge_write) begin if (DataLo == 16'hF0) ULBYPASS = 0; end if (oe || rd) ASRead(DOut_zd); end PGMS : begin if (oe || rd) begin /////////////////////////////////////////////////////////// //read status /////////////////////////////////////////////////////////// Status[6] = ~Status[6]; //toggle Status[5] = 1'b0; //Status[2) no toggle Status[1] = 1'b0; DOut_zd[7:0] = Status; end RY_zd = 1'b0; if (PERR!=1'b1 && ~falling_edge_PERR) begin //Word/Byte program wr_cnt = 0; if (WBAddr[1] > -1 ) wr_cnt =1; for (i=wr_cnt;i>=0;i=i-1) begin new_int= WBData[i]; if (~OTP_ACT) old_int=Mem[sa(SA)+WBAddr[i]]; else old_int=SecSi[WBAddr[i]]; if (new_int>-1) begin new_bit = new_int; if (old_int>-1) begin old_bit = old_int; for(j=0;j<=7;j=j+1) if (~old_bit[j]) new_bit[j]=1'b0; new_int=new_bit; end WBData[i]= new_int; end else WBData[i]= -1; end for (i=wr_cnt;i>=0;i=i-1) begin if (~OTP_ACT) Mem[sa(SA)+WBAddr[i]] = -1; else SecSi[WBAddr[i]] = -1; end if (rising_edge_PDONE && ~PERR) begin for (i=wr_cnt;i>=0;i=i-1) begin if (~OTP_ACT) Mem[sa(SA)+WBAddr[i]] = WBData[i]; else SecSi[WBAddr[i]] = WBData[i]; WBData[i]= -1; end end end end endcase end end always @(gOE_n or RESETNeg or RST or BYTENeg) begin : Output_Disable //Output Disable Control if (gOE_n || (~RESETNeg && ~RST)) DOut_zd = 16'bZ; else if (~BYTENeg) DOut_zd[15:8] = 8'bZ; end reg Sec_Prot1_reg; reg Sec_Prot0_reg; always @(WPNeg ) begin : WP_CTRL // Hardware write protection if (~WPNeg && PoweredUp) begin Sec_Prot1_reg = SubSec_Prot[vs*SubSecNum]; Sec_Prot0_reg = SubSec_Prot[vs*(SubSecNum-2) +1]; SubSec_Prot[vs*SubSecNum] = 1; SubSec_Prot[vs* (SubSecNum-2) +1 ] = 1; end else if (WPNeg && PoweredUp) begin SubSec_Prot[vs*SubSecNum] = Sec_Prot1_reg; SubSec_Prot[vs*(SubSecNum-2) +1] = Sec_Prot0_reg; end end always @(DOut_zd) begin : OutputGen if (DOut_zd[0] !== 1'bz) begin CEDQ_t = CENeg_event + CEDQ_01; OEDQ_t = OENeg_event + OEDQ_01; ADDRDQ_t = ADDR_event + ADDRDQ; FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time)); FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time)); FROMADDR = 1'b1; if ((ADDRDQ_t > $time) && (((ADDRDQ_t>OEDQ_t) && FROMOE) || ((ADDRDQ_t>CEDQ_t) && FROMCE))) begin TempData = DOut_zd; FROMADDR = 1'b0; if (~BYTENeg) DOut_Pass[15:8] = 8'bz; else DOut_Pass[15:8] = 8'bx; DOut_Pass[7:0] = 8'bx; DOut_Pass <= #(ADDRDQ_t - $time) TempData; end else begin DOut_Pass = DOut_zd; end end end always @(DOut_zd) begin if (DOut_zd[0] === 1'bz) begin disable OutputGen; FROMCE = 1'b1; FROMOE = 1'b1; FROMADDR = 1'b0; DOut_Pass = DOut_zd; end end initial begin : CFI_preload /////////////////////////////////////////////////////////////////////// //CFI array data /////////////////////////////////////////////////////////////////////// for(i=16; i<=90; i=i+1) CFI_array[i] = 16'h0; //CFI query identification string CFI_array[16'h10] = 16'h51; CFI_array[16'h11] = 16'h52; CFI_array[16'h12] = 16'h59; CFI_array[16'h13] = 16'h02; CFI_array[16'h14] = 16'h00; CFI_array[16'h15] = 16'h40; CFI_array[16'h16] = 16'h00; CFI_array[16'h17] = 16'h00; CFI_array[16'h18] = 16'h00; CFI_array[16'h19] = 16'h00; CFI_array[16'h1A] = 16'h00; //system interface string CFI_array[16'h1B] = 16'h27; CFI_array[16'h1C] = 16'h36; CFI_array[16'h1D] = 16'h00; CFI_array[16'h1E] = 16'h00; CFI_array[16'h1F] = 16'h03; CFI_array[16'h20] = 16'h00; CFI_array[16'h21] = 16'h09; CFI_array[16'h22] = 16'h00; CFI_array[16'h23] = 16'h05; CFI_array[16'h24] = 16'h00; CFI_array[16'h25] = 16'h04; CFI_array[16'h26] = 16'h00; //device geometry definition CFI_array[16'h27] = 16'h14; // 8Mb CFI_array[16'h28] = 16'h02; CFI_array[16'h29] = 16'h02; CFI_array[16'h2A] = 16'h00; CFI_array[16'h2B] = 16'h00; CFI_array[16'h2C] = 16'h02; CFI_array[16'h2D] = 16'h00; CFI_array[16'h2E] = 16'h00; CFI_array[16'h2F] = 16'h40; CFI_array[16'h30] = 16'h00; CFI_array[16'h31] = 16'h01; CFI_array[16'h32] = 16'h00; CFI_array[16'h33] = 16'h20; CFI_array[16'h34] = 16'h00; CFI_array[16'h35] = 16'h00; CFI_array[16'h36] = 16'h00; CFI_array[16'h37] = 16'h80; CFI_array[16'h38] = 16'h00; CFI_array[16'h39] = 16'h0D; // 8 Mb CFI_array[16'h3A] = 16'h00; CFI_array[16'h3B] = 16'h00; CFI_array[16'h3C] = 16'h01; //primary vendor-specific extended query CFI_array[16'h40] = 16'h50; CFI_array[16'h41] = 16'h52; CFI_array[16'h42] = 16'h49; CFI_array[16'h43] = 16'h31; CFI_array[16'h44] = 16'h33; CFI_array[16'h45] = 16'h0C; CFI_array[16'h46] = 16'h02; CFI_array[16'h47] = 16'h01; CFI_array[16'h48] = 16'h01; CFI_array[16'h49] = 16'h04; CFI_array[16'h4A] = 16'h00; CFI_array[16'h4B] = 16'h00; CFI_array[16'h4C] = 16'h00; CFI_array[16'h4D] = 16'h04; CFI_array[16'h4E] = 16'h00; if (tmp_char == "T") CFI_array[16'h4F] = 16'h03; else if (tmp_char == "B") CFI_array[16'h4F] = 16'h02; CFI_array[16'h50] = 16'h00; end function integer sa; input integer sect; begin sa = sect * (SecSize + 1); end endfunction function integer sssa; input integer vs; input integer subsect; begin if (vs == 0) //bottom begin if (subsect == 0) sssa=16'h0000; else if (subsect == 1) sssa=16'h4000; else if (subsect == 2) sssa=16'h6000; else if (subsect == 3) sssa=16'h8000; end else//vs == 1 begin if (subsect == 0) sssa=16'h0000; else if (subsect == 1) sssa=16'h8000; else if (subsect == 2) sssa=16'hA000; else if (subsect == 3) sssa=16'hC000; end end endfunction function integer ssea; input integer vs; input integer subsect; begin if (vs == 0) //bottom begin if (subsect == 0) ssea=16'h3FFF; else if (subsect == 1) ssea=16'h5FFF; else if (subsect == 2) ssea=16'h7FFF; else if (subsect == 3) ssea=16'hFFFF; end else //vs == 1 begin if (subsect == 0) ssea=16'h7FFF; else if (subsect == 1) ssea=16'h9FFF; else if (subsect == 2) ssea=16'hBFFF; else if (subsect == 3) ssea=16'hFFFF; end end endfunction task MemRead; inout [15:0] DOut_zd; begin if (Mem[sa(SecAddr)+Address]==-1) DOut_zd[7:0] = 8'bx; else DOut_zd[7:0] = Mem[sa(SecAddr)+Address]; if (BYTENeg) if (Mem[sa(SecAddr)+Address+1]==-1) DOut_zd[15:8]= 8'bx; else DOut_zd[15:8] = Mem[sa(SecAddr)+Address+1]; end endtask /////////////Read AS Code task ASRead; inout [15:0] DOut_zd; begin if (BYTENeg) if (Address == 0) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'h22; else DOut_zd[15:8] = 8'bZ; if (Addr == 0) DOut_zd[7:0] = 1; else if (Addr == 1) begin if (vs == 1) DOut_zd[7:0] = 8'hDA; else DOut_zd[7:0] = 8'h5B; end else if (Addr == 2) begin DOut_zd[7:1] = 7'b0; if ( SecAddr == VarSect ) DOut_zd[0] = SubSec_Prot[SubSect]; else DOut_zd[0] = Sec_Prot[SecAddr]; end else if (Addr == 3) begin if (VarSect > 0) begin DOut_zd[7:0] = 16'h0E; if (FactoryProt == 1'b1) DOut_zd[7] = 1; end else begin DOut_zd[7:0] = 16'h16; if (FactoryProt == 1'b1) DOut_zd[7] = 1; end end end endtask always @(negedge WENeg) begin falling_edge_WENeg = 1; #1 falling_edge_WENeg = 0; end always @(negedge CENeg) begin falling_edge_CENeg = 1; #1 falling_edge_CENeg = 0; end always @(negedge OENeg) begin falling_edge_OENeg = 1; #1 falling_edge_OENeg = 0; end always @(posedge WENeg) begin rising_edge_WENeg = 1; #1 rising_edge_WENeg = 0; end always @(posedge CENeg) begin rising_edge_CENeg = 1; #1 rising_edge_CENeg = 0; end always @(posedge write) begin rising_edge_write = 1; #1 rising_edge_write = 0; end always @(negedge write) begin falling_edge_write = 1; #1 falling_edge_write = 0; end always @(posedge EDONE) begin rising_edge_EDONE = 1; #1 rising_edge_EDONE = 0; end always @(negedge EERR) begin falling_edge_EERR = 1; #1 falling_edge_EERR = 0; end always @(posedge CTMOUT) begin rising_edge_CTMOUT_out = 1; #1 rising_edge_CTMOUT_out = 0; end always @(posedge START_T1) begin rising_edge_START_T1_out = 1; #1 rising_edge_START_T1_out = 0; end always @(posedge PDONE) begin rising_edge_PDONE = 1; #1 rising_edge_PDONE = 0; end always @(negedge PERR) begin falling_edge_PERR = 1; #1 falling_edge_PERR = 0; end always @(A) begin A_event = 1; #1 A_event = 0; end always @(DIn[15]) begin DIn_15_event = 1; #1 DIn_15_event = 0; end always @(BYTENeg) begin BYTENeg_event = 1; #1 BYTENeg_event = 0; end always @(posedge read) begin ->oe_event; end always @(Address or SecAddr or BYTENeg) begin if (read) ->rd_event; end always @(oe_event) begin oe = 1'b1; #1 oe = 1'b0; end always @(rd_event) begin rd = 1'b1; #1 rd = 1'b0; end always @(posedge RESETNeg) begin rising_edge_RESETNeg = 1'b1; #1 rising_edge_RESETNeg = 1'b0; end always @(negedge RESETNeg) begin falling_edge_RESETNeg = 1'b1; #1 falling_edge_RESETNeg = 1'b0; end reg BuffInOE, BuffInCE, BuffInADDR; wire BuffOutOE, BuffOutCE, BuffOutADDR; BUFFER BUFOE (BuffOutOE, BuffInOE); BUFFER BUFCE (BuffOutCE, BuffInCE); BUFFER BUFADDR (BuffOutADDR, BuffInADDR); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInADDR = 1'b1; end always @(posedge BuffOutOE) begin OEDQ_01 = $time; end always @(posedge BuffOutCE) begin CEDQ_01 = $time; end always @(posedge BuffOutADDR) begin ADDRDQ = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule