//////////////////////////////////////////////////////////////////////////////// // File name : mt28f800b5.v //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // MODIFICATION HISTORY : // // version: | author: | mod date: | changes made: // V1.0 D.Komaromi 04 Sep 27 Initial //////////////////////////////////////////////////////////////////////////////// // PART DESCRIPTION: // // Library: FLASH // Technology: Flash Memory // Part: mt28f800b5 // // Description: 8Mbit(1M x 8-Bit/0.5 M x 16-Bit) 5 Boot Block Flash Memory // Boot sector determined by TimingModel generic // //////////////////////////////////////////////////////////////////////////////// // Known Bugs: // //////////////////////////////////////////////////////////////////////////////// // Note: // Protection against over-erasure and optimization of the write margin to each // cell is not implemented, since the maximum number of erase and write cycles // executed by the ISM without a successful verification is not given in the // datasheet.Also, the method of verification is not explained //////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module mt28f800b5 ( A18 , A17 , A16 , A15 , A14 , A13 , A12 , A11 , A10 , A9 , A8 , A7 , A6 , A5 , A4 , A3 , A2 , A1 , A0 , DQ15 , DQ14 , DQ13 , DQ12 , DQ11 , DQ10 , DQ9 , DQ8 , DQ7 , DQ6 , DQ5 , DQ4 , DQ3 , DQ2 , DQ1 , DQ0 , CENeg , OENeg , WENeg , RPNeg , WPNeg , BYTENeg , VPP ); //////////////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations // //////////////////////////////////////////////////////////////////////////////// input A18 ; input A17 ; input A16 ; input A15 ; input A14 ; input A13 ; input A12 ; input A11 ; input A10 ; input A9 ; input A8 ; input A7 ; input A6 ; input A5 ; input A4 ; input A3 ; input A2 ; input A1 ; input A0 ; inout DQ15 ; inout DQ14 ; inout DQ13 ; inout DQ12 ; inout DQ11 ; inout DQ10 ; inout DQ9 ; inout DQ8 ; inout DQ7 ; inout DQ6 ; inout DQ5 ; inout DQ4 ; inout DQ3 ; inout DQ2 ; inout DQ1 ; inout DQ0 ; input CENeg ; input OENeg ; input WENeg ; input RPNeg ; input WPNeg ; input BYTENeg ; input VPP ; // interconnect path delay signals wire A18_ipd ; wire A17_ipd ; wire A16_ipd ; wire A15_ipd ; wire A14_ipd ; wire A13_ipd ; wire A12_ipd ; wire A11_ipd ; wire A10_ipd ; wire A9_ipd ; wire A8_ipd ; wire A7_ipd ; wire A6_ipd ; wire A5_ipd ; wire A4_ipd ; wire A3_ipd ; wire A2_ipd ; wire A1_ipd ; wire A0_ipd ; wire [18 : 0] A; assign A = { A18_ipd, A17_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd }; wire DQ15_ipd ; wire DQ14_ipd ; wire DQ13_ipd ; wire DQ12_ipd ; wire DQ11_ipd ; wire DQ10_ipd ; wire DQ9_ipd ; wire DQ8_ipd ; wire DQ7_ipd ; wire DQ6_ipd ; wire DQ5_ipd ; wire DQ4_ipd ; wire DQ3_ipd ; wire DQ2_ipd ; wire DQ1_ipd ; wire DQ0_ipd ; wire [15 : 0 ] DIn; assign DIn = {DQ15_ipd, DQ14_ipd, DQ13_ipd, DQ12_ipd, DQ11_ipd, DQ10_ipd, DQ9_ipd, DQ8_ipd, DQ7_ipd, DQ6_ipd, DQ5_ipd, DQ4_ipd, DQ3_ipd, DQ2_ipd, DQ1_ipd, DQ0_ipd }; wire [15 : 0 ] DOut; assign DOut = {DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0 }; wire CENeg_ipd ; wire OENeg_ipd ; wire WENeg_ipd ; wire RPNeg_ipd ; wire WPNeg_ipd ; wire BYTENeg_ipd ; wire VPP_ipd ; reg BUSY_in ; reg BUSY_out ; reg READY_in ; reg READY_out ; reg REL_in ; reg REL_out ; wire DQ15_zd ; wire DQ14_zd ; wire DQ13_zd ; wire DQ12_zd ; wire DQ11_zd ; wire DQ10_zd ; wire DQ9_zd ; wire DQ8_zd ; wire DQ7_zd ; wire DQ6_zd ; wire DQ5_zd ; wire DQ4_zd ; wire DQ3_zd ; wire DQ2_zd ; wire DQ1_zd ; wire DQ0_zd ; reg [15 : 0] DOut_zd; assign {DQ15_zd, DQ14_zd, DQ13_zd, DQ12_zd, DQ11_zd, DQ10_zd, DQ9_zd, DQ8_zd, DQ7_zd, DQ6_zd, DQ5_zd, DQ4_zd, DQ3_zd, DQ2_zd, DQ1_zd, DQ0_zd } = DOut_zd; wire DQ15_Pass ; wire DQ14_Pass ; wire DQ13_Pass ; wire DQ12_Pass ; wire DQ11_Pass ; wire DQ10_Pass ; wire DQ9_Pass ; wire DQ8_Pass ; wire DQ7_Pass ; wire DQ6_Pass ; wire DQ5_Pass ; wire DQ4_Pass ; wire DQ3_Pass ; wire DQ2_Pass ; wire DQ1_Pass ; wire DQ0_Pass ; reg [15 : 0] DOut_Pass; assign {DQ15_Pass, DQ14_Pass, DQ13_Pass, DQ12_Pass, DQ11_Pass, DQ10_Pass, DQ9_Pass, DQ8_Pass, DQ7_Pass, DQ6_Pass, DQ5_Pass, DQ4_Pass, DQ3_Pass, DQ2_Pass, DQ1_Pass, DQ0_Pass } = DOut_Pass; parameter UserPreload = 1'b0; parameter mem_file_name = "none"; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "mt28f800b5"; parameter MaxData = 255; parameter SecSize = 131071; parameter SecNum = 8; parameter SubSecNum = 4; parameter HiAddrBit = 18; parameter MemSize = (SecSize + 1) * (SecNum) -1; // FSM states parameter READ_ARRAY =4'd0; parameter READ_IDENT =4'd1; parameter READ_STATUS =4'd2; parameter CLR_STATUS =4'd3; parameter W_SETUP =4'd4; parameter WRITE_T =4'd5; parameter WRITE_EX =4'd6; parameter E_SETUP =4'd7; parameter ERS_T =4'd8; parameter ERS_EX =4'd9; parameter SERS_T =4'd10; parameter SERS =4'd11; parameter SERS_RA =4'd12; parameter SERS_RS =4'd13; parameter RES_T =4'd14; reg [4:0] current_state; reg [4:0] next_state; // powerup reg PoweredUp; //ISM control signals reg PDONE ; ////Prog. Done reg PSTART ; ////Start Programming //Program location is in protected sector reg PERR ; reg EDONE ; ////Ers. Done reg ESTART ; ////Start Erase reg ESUSP ; ////Suspend Erase reg ERES ; ////Resume Erase reg EERR ; //Command Register reg write ; reg read ; //Sector Address integer SA = 0; integer SubSect = 0; integer ErsSec = 0; integer ErsSubSec = 0; //Address within sector integer Address = 0; integer SA_tmp =-1; integer A_tmp1 =-1; reg IDAddr; integer D_tmp0 ; integer D_tmp1; //DATA Low Byte integer DataLo ; integer DataHi ; integer WData[0:1]; integer WAddr[0:1]; integer WSec = 0; integer WSubSec = 0; reg RST ; reg reseted ; reg OK_to_l = 1'b1; integer Mem[0:MemSize]; //Sector Protection Status reg Boot_Prot = 1'b1; // timing check violation reg Viol = 1'b0; //Address of variable size sector (bottom or top boot sector) integer VarSect = -1; reg vs; reg oe = 1'b0; event oe_event; //Status reg. reg[7:0] StatusReg = 8'b0; reg[7:0] old_bit, new_bit; integer old_int, new_int; integer wr_cnt; reg[7:0] temp; integer i,j,k; //TPD_XX_DATA time OEDQ_t; time CEDQ_t; time ADDRDQ_t; time OENeg_event; time CENeg_event; time ADDR_event; reg FROMOE; reg FROMCE; reg[15:0] TempData; integer OEDQ_01; integer CEDQ_01; integer ADDRDQ_01; /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_Pass , 1); nmos (DQ14, DQ14_Pass , 1); nmos (DQ13, DQ13_Pass , 1); nmos (DQ12, DQ12_Pass , 1); nmos (DQ11, DQ11_Pass , 1); nmos (DQ10, DQ10_Pass , 1); nmos (DQ9 , DQ9_Pass , 1); nmos (DQ8 , DQ8_Pass , 1); nmos (DQ7 , DQ7_Pass , 1); nmos (DQ6 , DQ6_Pass , 1); nmos (DQ5 , DQ5_Pass , 1); nmos (DQ4 , DQ4_Pass , 1); nmos (DQ3 , DQ3_Pass , 1); nmos (DQ2 , DQ2_Pass , 1); nmos (DQ1 , DQ1_Pass , 1); nmos (DQ0 , DQ0_Pass , 1); //////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section // //////////////////////////////////////////////////////////////////////////////// buf (A18_ipd, A18); buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (DQ15_ipd, DQ15); buf (DQ14_ipd, DQ14); buf (DQ13_ipd, DQ13); buf (DQ12_ipd, DQ12); buf (DQ11_ipd, DQ11); buf (DQ10_ipd, DQ10); buf (DQ9_ipd , DQ9 ); buf (DQ8_ipd , DQ8 ); buf (DQ7_ipd , DQ7 ); buf (DQ6_ipd , DQ6 ); buf (DQ5_ipd , DQ5 ); buf (DQ4_ipd , DQ4 ); buf (DQ3_ipd , DQ3 ); buf (DQ2_ipd , DQ2 ); buf (DQ1_ipd , DQ1 ); buf (DQ0_ipd , DQ0 ); buf (CENeg_ipd , CENeg ); buf (OENeg_ipd , OENeg ); buf (WENeg_ipd , WENeg ); buf (RPNeg_ipd , RPNeg ); buf (WPNeg_ipd , WPNeg ); buf (BYTENeg_ipd , BYTENeg ); buf (VPP_ipd , VPP ); //////////////////////////////////////////////////////////////////////////////// // Propagation delay Section // //////////////////////////////////////////////////////////////////////////////// nmos (DQ15, DQ15_zd , 1); nmos (DQ14, DQ14_zd , 1); nmos (DQ13, DQ13_zd , 1); nmos (DQ12, DQ12_zd , 1); nmos (DQ11, DQ11_zd , 1); nmos (DQ10, DQ10_zd , 1); nmos (DQ9 , DQ9_zd , 1); nmos (DQ8 , DQ8_zd , 1); nmos (DQ7 , DQ7_zd , 1); nmos (DQ6 , DQ6_zd , 1); nmos (DQ5 , DQ5_zd , 1); nmos (DQ4 , DQ4_zd , 1); nmos (DQ3 , DQ3_zd , 1); nmos (DQ2 , DQ2_zd , 1); nmos (DQ1 , DQ1_zd , 1); nmos (DQ0 , DQ0_zd , 1); wire deg; wire WR_cyc; assign WR_cyc = write; wire WR_cyc_deg; assign WR_cyc_deg = write && deg; wire VPP_Chk; assign VPP_Chk = VPP && (current_state == W_SETUP || current_state == E_SETUP); specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_A0_DQ0 =1; specparam tpd_A0_DQ1 =1; specparam tpd_A0_DQ2 =1; specparam tpd_A0_DQ3 =1; specparam tpd_A0_DQ4 =1; specparam tpd_A0_DQ5 =1; specparam tpd_A0_DQ6 =1; specparam tpd_A0_DQ7 =1; specparam tpd_A0_DQ8 =1; specparam tpd_A0_DQ9 =1; specparam tpd_A0_DQ10 =1; specparam tpd_A0_DQ11 =1; specparam tpd_A0_DQ12 =1; specparam tpd_A0_DQ13 =1; specparam tpd_A0_DQ14 =1; specparam tpd_A0_DQ15 =1; specparam tpd_A1_DQ0 =1; specparam tpd_A1_DQ1 =1; specparam tpd_A1_DQ2 =1; specparam tpd_A1_DQ3 =1; specparam tpd_A1_DQ4 =1; specparam tpd_A1_DQ5 =1; specparam tpd_A1_DQ6 =1; specparam tpd_A1_DQ7 =1; specparam tpd_A1_DQ8 =1; specparam tpd_A1_DQ9 =1; specparam tpd_A1_DQ10 =1; specparam tpd_A1_DQ11 =1; specparam tpd_A1_DQ12 =1; specparam tpd_A1_DQ13 =1; specparam tpd_A1_DQ14 =1; specparam tpd_A1_DQ15 =1; specparam tpd_A2_DQ0 =1; specparam tpd_A2_DQ1 =1; specparam tpd_A2_DQ2 =1; specparam tpd_A2_DQ3 =1; specparam tpd_A2_DQ4 =1; specparam tpd_A2_DQ5 =1; specparam tpd_A2_DQ6 =1; specparam tpd_A2_DQ7 =1; specparam tpd_A2_DQ8 =1; specparam tpd_A2_DQ9 =1; specparam tpd_A2_DQ10 =1; specparam tpd_A2_DQ11 =1; specparam tpd_A2_DQ12 =1; specparam tpd_A2_DQ13 =1; specparam tpd_A2_DQ14 =1; specparam tpd_A2_DQ15 =1; specparam tpd_A3_DQ0 =1; specparam tpd_A3_DQ1 =1; specparam tpd_A3_DQ2 =1; specparam tpd_A3_DQ3 =1; specparam tpd_A3_DQ4 =1; specparam tpd_A3_DQ5 =1; specparam tpd_A3_DQ6 =1; specparam tpd_A3_DQ7 =1; specparam tpd_A3_DQ8 =1; specparam tpd_A3_DQ9 =1; specparam tpd_A3_DQ10 =1; specparam tpd_A3_DQ11 =1; specparam tpd_A3_DQ12 =1; specparam tpd_A3_DQ13 =1; specparam tpd_A3_DQ14 =1; specparam tpd_A3_DQ15 =1; specparam tpd_A4_DQ0 =1; specparam tpd_A4_DQ1 =1; specparam tpd_A4_DQ2 =1; specparam tpd_A4_DQ3 =1; specparam tpd_A4_DQ4 =1; specparam tpd_A4_DQ5 =1; specparam tpd_A4_DQ6 =1; specparam tpd_A4_DQ7 =1; specparam tpd_A4_DQ8 =1; specparam tpd_A4_DQ9 =1; specparam tpd_A4_DQ10 =1; specparam tpd_A4_DQ11 =1; specparam tpd_A4_DQ12 =1; specparam tpd_A4_DQ13 =1; specparam tpd_A4_DQ14 =1; specparam tpd_A4_DQ15 =1; specparam tpd_A5_DQ0 =1; specparam tpd_A5_DQ1 =1; specparam tpd_A5_DQ2 =1; specparam tpd_A5_DQ3 =1; specparam tpd_A5_DQ4 =1; specparam tpd_A5_DQ5 =1; specparam tpd_A5_DQ6 =1; specparam tpd_A5_DQ7 =1; specparam tpd_A5_DQ8 =1; specparam tpd_A5_DQ9 =1; specparam tpd_A5_DQ10 =1; specparam tpd_A5_DQ11 =1; specparam tpd_A5_DQ12 =1; specparam tpd_A5_DQ13 =1; specparam tpd_A5_DQ14 =1; specparam tpd_A5_DQ15 =1; specparam tpd_A6_DQ0 =1; specparam tpd_A6_DQ1 =1; specparam tpd_A6_DQ2 =1; specparam tpd_A6_DQ3 =1; specparam tpd_A6_DQ4 =1; specparam tpd_A6_DQ5 =1; specparam tpd_A6_DQ6 =1; specparam tpd_A6_DQ7 =1; specparam tpd_A6_DQ8 =1; specparam tpd_A6_DQ9 =1; specparam tpd_A6_DQ10 =1; specparam tpd_A6_DQ11 =1; specparam tpd_A6_DQ12 =1; specparam tpd_A6_DQ13 =1; specparam tpd_A6_DQ14 =1; specparam tpd_A6_DQ15 =1; specparam tpd_A7_DQ0 =1; specparam tpd_A7_DQ1 =1; specparam tpd_A7_DQ2 =1; specparam tpd_A7_DQ3 =1; specparam tpd_A7_DQ4 =1; specparam tpd_A7_DQ5 =1; specparam tpd_A7_DQ6 =1; specparam tpd_A7_DQ7 =1; specparam tpd_A7_DQ8 =1; specparam tpd_A7_DQ9 =1; specparam tpd_A7_DQ10 =1; specparam tpd_A7_DQ11 =1; specparam tpd_A7_DQ12 =1; specparam tpd_A7_DQ13 =1; specparam tpd_A7_DQ14 =1; specparam tpd_A7_DQ15 =1; specparam tpd_A8_DQ0 =1; specparam tpd_A8_DQ1 =1; specparam tpd_A8_DQ2 =1; specparam tpd_A8_DQ3 =1; specparam tpd_A8_DQ4 =1; specparam tpd_A8_DQ5 =1; specparam tpd_A8_DQ6 =1; specparam tpd_A8_DQ7 =1; specparam tpd_A8_DQ8 =1; specparam tpd_A8_DQ9 =1; specparam tpd_A8_DQ10 =1; specparam tpd_A8_DQ11 =1; specparam tpd_A8_DQ12 =1; specparam tpd_A8_DQ13 =1; specparam tpd_A8_DQ14 =1; specparam tpd_A8_DQ15 =1; specparam tpd_A9_DQ0 =1; specparam tpd_A9_DQ1 =1; specparam tpd_A9_DQ2 =1; specparam tpd_A9_DQ3 =1; specparam tpd_A9_DQ4 =1; specparam tpd_A9_DQ5 =1; specparam tpd_A9_DQ6 =1; specparam tpd_A9_DQ7 =1; specparam tpd_A9_DQ8 =1; specparam tpd_A9_DQ9 =1; specparam tpd_A9_DQ10 =1; specparam tpd_A9_DQ11 =1; specparam tpd_A9_DQ12 =1; specparam tpd_A9_DQ13 =1; specparam tpd_A9_DQ14 =1; specparam tpd_A9_DQ15 =1; specparam tpd_A10_DQ0 =1; specparam tpd_A10_DQ1 =1; specparam tpd_A10_DQ2 =1; specparam tpd_A10_DQ3 =1; specparam tpd_A10_DQ4 =1; specparam tpd_A10_DQ5 =1; specparam tpd_A10_DQ6 =1; specparam tpd_A10_DQ7 =1; specparam tpd_A10_DQ8 =1; specparam tpd_A10_DQ9 =1; specparam tpd_A10_DQ10 =1; specparam tpd_A10_DQ11 =1; specparam tpd_A10_DQ12 =1; specparam tpd_A10_DQ13 =1; specparam tpd_A10_DQ14 =1; specparam tpd_A10_DQ15 =1; specparam tpd_A11_DQ0 =1; specparam tpd_A11_DQ1 =1; specparam tpd_A11_DQ2 =1; specparam tpd_A11_DQ3 =1; specparam tpd_A11_DQ4 =1; specparam tpd_A11_DQ5 =1; specparam tpd_A11_DQ6 =1; specparam tpd_A11_DQ7 =1; specparam tpd_A11_DQ8 =1; specparam tpd_A11_DQ9 =1; specparam tpd_A11_DQ10 =1; specparam tpd_A11_DQ11 =1; specparam tpd_A11_DQ12 =1; specparam tpd_A11_DQ13 =1; specparam tpd_A11_DQ14 =1; specparam tpd_A11_DQ15 =1; specparam tpd_A12_DQ0 =1; specparam tpd_A12_DQ1 =1; specparam tpd_A12_DQ2 =1; specparam tpd_A12_DQ3 =1; specparam tpd_A12_DQ4 =1; specparam tpd_A12_DQ5 =1; specparam tpd_A12_DQ6 =1; specparam tpd_A12_DQ7 =1; specparam tpd_A12_DQ8 =1; specparam tpd_A12_DQ9 =1; specparam tpd_A12_DQ10 =1; specparam tpd_A12_DQ11 =1; specparam tpd_A12_DQ12 =1; specparam tpd_A12_DQ13 =1; specparam tpd_A12_DQ14 =1; specparam tpd_A12_DQ15 =1; specparam tpd_A13_DQ0 =1; specparam tpd_A13_DQ1 =1; specparam tpd_A13_DQ2 =1; specparam tpd_A13_DQ3 =1; specparam tpd_A13_DQ4 =1; specparam tpd_A13_DQ5 =1; specparam tpd_A13_DQ6 =1; specparam tpd_A13_DQ7 =1; specparam tpd_A13_DQ8 =1; specparam tpd_A13_DQ9 =1; specparam tpd_A13_DQ10 =1; specparam tpd_A13_DQ11 =1; specparam tpd_A13_DQ12 =1; specparam tpd_A13_DQ13 =1; specparam tpd_A13_DQ14 =1; specparam tpd_A13_DQ15 =1; specparam tpd_A14_DQ0 =1; specparam tpd_A14_DQ1 =1; specparam tpd_A14_DQ2 =1; specparam tpd_A14_DQ3 =1; specparam tpd_A14_DQ4 =1; specparam tpd_A14_DQ5 =1; specparam tpd_A14_DQ6 =1; specparam tpd_A14_DQ7 =1; specparam tpd_A14_DQ8 =1; specparam tpd_A14_DQ9 =1; specparam tpd_A14_DQ10 =1; specparam tpd_A14_DQ11 =1; specparam tpd_A14_DQ12 =1; specparam tpd_A14_DQ13 =1; specparam tpd_A14_DQ14 =1; specparam tpd_A14_DQ15 =1; specparam tpd_A15_DQ0 =1; specparam tpd_A15_DQ1 =1; specparam tpd_A15_DQ2 =1; specparam tpd_A15_DQ3 =1; specparam tpd_A15_DQ4 =1; specparam tpd_A15_DQ5 =1; specparam tpd_A15_DQ6 =1; specparam tpd_A15_DQ7 =1; specparam tpd_A15_DQ8 =1; specparam tpd_A15_DQ9 =1; specparam tpd_A15_DQ10 =1; specparam tpd_A15_DQ11 =1; specparam tpd_A15_DQ12 =1; specparam tpd_A15_DQ13 =1; specparam tpd_A15_DQ14 =1; specparam tpd_A15_DQ15 =1; specparam tpd_A16_DQ0 =1; specparam tpd_A16_DQ1 =1; specparam tpd_A16_DQ2 =1; specparam tpd_A16_DQ3 =1; specparam tpd_A16_DQ4 =1; specparam tpd_A16_DQ5 =1; specparam tpd_A16_DQ6 =1; specparam tpd_A16_DQ7 =1; specparam tpd_A16_DQ8 =1; specparam tpd_A16_DQ9 =1; specparam tpd_A16_DQ10 =1; specparam tpd_A16_DQ11 =1; specparam tpd_A16_DQ12 =1; specparam tpd_A16_DQ13 =1; specparam tpd_A16_DQ14 =1; specparam tpd_A16_DQ15 =1; specparam tpd_A17_DQ0 =1; specparam tpd_A17_DQ1 =1; specparam tpd_A17_DQ2 =1; specparam tpd_A17_DQ3 =1; specparam tpd_A17_DQ4 =1; specparam tpd_A17_DQ5 =1; specparam tpd_A17_DQ6 =1; specparam tpd_A17_DQ7 =1; specparam tpd_A17_DQ8 =1; specparam tpd_A17_DQ9 =1; specparam tpd_A17_DQ10 =1; specparam tpd_A17_DQ11 =1; specparam tpd_A17_DQ12 =1; specparam tpd_A17_DQ13 =1; specparam tpd_A17_DQ14 =1; specparam tpd_A17_DQ15 =1; specparam tpd_A18_DQ0 =1; specparam tpd_A18_DQ1 =1; specparam tpd_A18_DQ2 =1; specparam tpd_A18_DQ3 =1; specparam tpd_A18_DQ4 =1; specparam tpd_A18_DQ5 =1; specparam tpd_A18_DQ6 =1; specparam tpd_A18_DQ7 =1; specparam tpd_A18_DQ8 =1; specparam tpd_A18_DQ9 =1; specparam tpd_A18_DQ10 =1; specparam tpd_A18_DQ11 =1; specparam tpd_A18_DQ12 =1; specparam tpd_A18_DQ13 =1; specparam tpd_A18_DQ14 =1; specparam tpd_A18_DQ15 =1; specparam tpd_DQ15_DQ0 =1; specparam tpd_DQ15_DQ1 =1; specparam tpd_DQ15_DQ2 =1; specparam tpd_DQ15_DQ3 =1; specparam tpd_DQ15_DQ4 =1; specparam tpd_DQ15_DQ5 =1; specparam tpd_DQ15_DQ6 =1; specparam tpd_DQ15_DQ7 =1; specparam tpd_CENeg_DQ0 =1; specparam tpd_CENeg_DQ1 =1; specparam tpd_CENeg_DQ2 =1; specparam tpd_CENeg_DQ3 =1; specparam tpd_CENeg_DQ4 =1; specparam tpd_CENeg_DQ5 =1; specparam tpd_CENeg_DQ6 =1; specparam tpd_CENeg_DQ7 =1; specparam tpd_CENeg_DQ8 =1; specparam tpd_CENeg_DQ9 =1; specparam tpd_CENeg_DQ10 =1; specparam tpd_CENeg_DQ11 =1; specparam tpd_CENeg_DQ12 =1; specparam tpd_CENeg_DQ13 =1; specparam tpd_CENeg_DQ14 =1; specparam tpd_CENeg_DQ15 =1; specparam tpd_OENeg_DQ0 =1; specparam tpd_OENeg_DQ1 =1; specparam tpd_OENeg_DQ2 =1; specparam tpd_OENeg_DQ3 =1; specparam tpd_OENeg_DQ4 =1; specparam tpd_OENeg_DQ5 =1; specparam tpd_OENeg_DQ6 =1; specparam tpd_OENeg_DQ7 =1; specparam tpd_OENeg_DQ8 =1; specparam tpd_OENeg_DQ9 =1; specparam tpd_OENeg_DQ10 =1; specparam tpd_OENeg_DQ11 =1; specparam tpd_OENeg_DQ12 =1; specparam tpd_OENeg_DQ13 =1; specparam tpd_OENeg_DQ14 =1; specparam tpd_OENeg_DQ15 =1; specparam tpd_RPNeg_DQ0 =1; specparam tpd_RPNeg_DQ1 =1; specparam tpd_RPNeg_DQ2 =1; specparam tpd_RPNeg_DQ3 =1; specparam tpd_RPNeg_DQ4 =1; specparam tpd_RPNeg_DQ5 =1; specparam tpd_RPNeg_DQ6 =1; specparam tpd_RPNeg_DQ7 =1; specparam tpd_RPNeg_DQ8 =1; specparam tpd_RPNeg_DQ9 =1; specparam tpd_RPNeg_DQ10 =1; specparam tpd_RPNeg_DQ11 =1; specparam tpd_RPNeg_DQ12 =1; specparam tpd_RPNeg_DQ13 =1; specparam tpd_RPNeg_DQ14 =1; specparam tpd_RPNeg_DQ15 =1; // tsetup values: setup time specparam tsetup_A0_CENeg =1; //tAS edge / specparam tsetup_A0_WENeg =1; //tAS edge / specparam tsetup_DQ0_CENeg =1; //tDS edge / specparam tsetup_DQ0_WENeg =1; //tDS edge / specparam tsetup_WENeg_CENeg =1; //0 edge / specparam tsetup_CENeg_WENeg =1; //0 ns / specparam tsetup_VPP_CENeg =1; //tVPS1 edge/ specparam tsetup_VPP_WENeg =1; //tVPS1 edge/ specparam tsetup_WPNeg_CENeg =1; //tRHS edge/ specparam tsetup_WPNeg_WENeg =1; //tRHS edge/ // thold values: hold times specparam thold_A0_CENeg =1; //tAH edge / specparam thold_A0_WENeg =1; //tAH edge / specparam thold_DQ0_CENeg =1; //tDH edge / specparam thold_DQ0_WENeg =1; //0 ns edge / specparam thold_CENeg_WENeg =1; //0 ns edge / specparam thold_WENeg_CENeg =1; //0 ns edge / // tpw values: pulse width specparam tpw_RPNeg_negedge =1; //tRP specparam tpw_WENeg_negedge =1; //tWP specparam tpw_WENeg_posedge =1; //tWPH specparam tpw_CENeg_negedge =1; //tCP specparam tpw_CENeg_posedge =1; //tCEPH // tdevice values: values for internal delays //Write Operation specparam tdevice_POW = 13500; //Block Erase Operation //Boot Block specparam tdevice_BBEO = 300000000; //Parameter Block specparam tdevice_PBEO = 300000000; //Main Block specparam tdevice_MBEO = 1500000000; //WE#(CE#) to valid status tWB specparam tdevice_BUSY = 600; //Boot Block Relock Delay Time tREL specparam tdevice_REL = 100; //device ready after Hardware reset specparam tdevice_READY = 1000; //////////////////////////////////////////////////////////////////////////////// // Path delays // //////////////////////////////////////////////////////////////////////////////// //for DQ signals (A0 *> DQ0) = tpd_A0_DQ0; (A0 *> DQ1) = tpd_A0_DQ1; (A0 *> DQ2) = tpd_A0_DQ2; (A0 *> DQ3) = tpd_A0_DQ3; (A0 *> DQ4) = tpd_A0_DQ4; (A0 *> DQ5) = tpd_A0_DQ5; (A0 *> DQ6) = tpd_A0_DQ6; (A0 *> DQ7) = tpd_A0_DQ7; (A0 *> DQ8) = tpd_A0_DQ8; (A0 *> DQ9) = tpd_A0_DQ9; (A0 *> DQ10) = tpd_A0_DQ10; (A0 *> DQ11) = tpd_A0_DQ11; (A0 *> DQ12) = tpd_A0_DQ12; (A0 *> DQ13) = tpd_A0_DQ13; (A0 *> DQ14) = tpd_A0_DQ14; (A0 *> DQ15) = tpd_A0_DQ15; (A1 *> DQ0) = tpd_A1_DQ0; (A1 *> DQ1) = tpd_A1_DQ1; (A1 *> DQ2) = tpd_A1_DQ2; (A1 *> DQ3) = tpd_A1_DQ3; (A1 *> DQ4) = tpd_A1_DQ4; (A1 *> DQ5) = tpd_A1_DQ5; (A1 *> DQ6) = tpd_A1_DQ6; (A1 *> DQ7) = tpd_A1_DQ7; (A1 *> DQ8) = tpd_A1_DQ8; (A1 *> DQ9) = tpd_A1_DQ9; (A1 *> DQ10) = tpd_A1_DQ10; (A1 *> DQ11) = tpd_A1_DQ11; (A1 *> DQ12) = tpd_A1_DQ12; (A1 *> DQ13) = tpd_A1_DQ13; (A1 *> DQ14) = tpd_A1_DQ14; (A1 *> DQ15) = tpd_A1_DQ15; (A2 *> DQ0) = tpd_A2_DQ0; (A2 *> DQ1) = tpd_A2_DQ1; (A2 *> DQ2) = tpd_A2_DQ2; (A2 *> DQ3) = tpd_A2_DQ3; (A2 *> DQ4) = tpd_A2_DQ4; (A2 *> DQ5) = tpd_A2_DQ5; (A2 *> DQ6) = tpd_A2_DQ6; (A2 *> DQ7) = tpd_A2_DQ7; (A2 *> DQ8) = tpd_A2_DQ8; (A2 *> DQ9) = tpd_A2_DQ9; (A2 *> DQ10) = tpd_A2_DQ10; (A2 *> DQ11) = tpd_A2_DQ11; (A2 *> DQ12) = tpd_A2_DQ12; (A2 *> DQ13) = tpd_A2_DQ13; (A2 *> DQ14) = tpd_A2_DQ14; (A2 *> DQ15) = tpd_A2_DQ15; (A3 *> DQ0) = tpd_A3_DQ0; (A3 *> DQ1) = tpd_A3_DQ1; (A3 *> DQ2) = tpd_A3_DQ2; (A3 *> DQ3) = tpd_A3_DQ3; (A3 *> DQ4) = tpd_A3_DQ4; (A3 *> DQ5) = tpd_A3_DQ5; (A3 *> DQ6) = tpd_A3_DQ6; (A3 *> DQ7) = tpd_A3_DQ7; (A3 *> DQ8) = tpd_A3_DQ8; (A3 *> DQ9) = tpd_A3_DQ9; (A3 *> DQ10) = tpd_A3_DQ10; (A3 *> DQ11) = tpd_A3_DQ11; (A3 *> DQ12) = tpd_A3_DQ12; (A3 *> DQ13) = tpd_A3_DQ13; (A3 *> DQ14) = tpd_A3_DQ14; (A3 *> DQ15) = tpd_A3_DQ15; (A4 *> DQ0) = tpd_A4_DQ0; (A4 *> DQ1) = tpd_A4_DQ1; (A4 *> DQ2) = tpd_A4_DQ2; (A4 *> DQ3) = tpd_A4_DQ3; (A4 *> DQ4) = tpd_A4_DQ4; (A4 *> DQ5) = tpd_A4_DQ5; (A4 *> DQ6) = tpd_A4_DQ6; (A4 *> DQ7) = tpd_A4_DQ7; (A4 *> DQ8) = tpd_A4_DQ8; (A4 *> DQ9) = tpd_A4_DQ9; (A4 *> DQ10) = tpd_A4_DQ10; (A4 *> DQ11) = tpd_A4_DQ11; (A4 *> DQ12) = tpd_A4_DQ12; (A4 *> DQ13) = tpd_A4_DQ13; (A4 *> DQ14) = tpd_A4_DQ14; (A4 *> DQ15) = tpd_A4_DQ15; (A5 *> DQ0) = tpd_A5_DQ0; (A5 *> DQ1) = tpd_A5_DQ1; (A5 *> DQ2) = tpd_A5_DQ2; (A5 *> DQ3) = tpd_A5_DQ3; (A5 *> DQ4) = tpd_A5_DQ4; (A5 *> DQ5) = tpd_A5_DQ5; (A5 *> DQ6) = tpd_A5_DQ6; (A5 *> DQ7) = tpd_A5_DQ7; (A5 *> DQ8) = tpd_A5_DQ8; (A5 *> DQ9) = tpd_A5_DQ9; (A5 *> DQ10) = tpd_A5_DQ10; (A5 *> DQ11) = tpd_A5_DQ11; (A5 *> DQ12) = tpd_A5_DQ12; (A5 *> DQ13) = tpd_A5_DQ13; (A5 *> DQ14) = tpd_A5_DQ14; (A5 *> DQ15) = tpd_A5_DQ15; (A6 *> DQ0) = tpd_A6_DQ0; (A6 *> DQ1) = tpd_A6_DQ1; (A6 *> DQ2) = tpd_A6_DQ2; (A6 *> DQ3) = tpd_A6_DQ3; (A6 *> DQ4) = tpd_A6_DQ4; (A6 *> DQ5) = tpd_A6_DQ5; (A6 *> DQ6) = tpd_A6_DQ6; (A6 *> DQ7) = tpd_A6_DQ7; (A6 *> DQ8) = tpd_A6_DQ8; (A6 *> DQ9) = tpd_A6_DQ9; (A6 *> DQ10) = tpd_A6_DQ10; (A6 *> DQ11) = tpd_A6_DQ11; (A6 *> DQ12) = tpd_A6_DQ12; (A6 *> DQ13) = tpd_A6_DQ13; (A6 *> DQ14) = tpd_A6_DQ14; (A6 *> DQ15) = tpd_A6_DQ15; (A7 *> DQ0) = tpd_A7_DQ0; (A7 *> DQ1) = tpd_A7_DQ1; (A7 *> DQ2) = tpd_A7_DQ2; (A7 *> DQ3) = tpd_A7_DQ3; (A7 *> DQ4) = tpd_A7_DQ4; (A7 *> DQ5) = tpd_A7_DQ5; (A7 *> DQ6) = tpd_A7_DQ6; (A7 *> DQ7) = tpd_A7_DQ7; (A7 *> DQ8) = tpd_A7_DQ8; (A7 *> DQ9) = tpd_A7_DQ9; (A7 *> DQ10) = tpd_A7_DQ10; (A7 *> DQ11) = tpd_A7_DQ11; (A7 *> DQ12) = tpd_A7_DQ12; (A7 *> DQ13) = tpd_A7_DQ13; (A7 *> DQ14) = tpd_A7_DQ14; (A7 *> DQ15) = tpd_A7_DQ15; (A8 *> DQ0) = tpd_A8_DQ0; (A8 *> DQ1) = tpd_A8_DQ1; (A8 *> DQ2) = tpd_A8_DQ2; (A8 *> DQ3) = tpd_A8_DQ3; (A8 *> DQ4) = tpd_A8_DQ4; (A8 *> DQ5) = tpd_A8_DQ5; (A8 *> DQ6) = tpd_A8_DQ6; (A8 *> DQ7) = tpd_A8_DQ7; (A8 *> DQ8) = tpd_A8_DQ8; (A8 *> DQ9) = tpd_A8_DQ9; (A8 *> DQ10) = tpd_A8_DQ10; (A8 *> DQ11) = tpd_A8_DQ11; (A8 *> DQ12) = tpd_A8_DQ12; (A8 *> DQ13) = tpd_A8_DQ13; (A8 *> DQ14) = tpd_A8_DQ14; (A8 *> DQ15) = tpd_A8_DQ15; (A9 *> DQ0) = tpd_A9_DQ0; (A9 *> DQ1) = tpd_A9_DQ1; (A9 *> DQ2) = tpd_A9_DQ2; (A9 *> DQ3) = tpd_A9_DQ3; (A9 *> DQ4) = tpd_A9_DQ4; (A9 *> DQ5) = tpd_A9_DQ5; (A9 *> DQ6) = tpd_A9_DQ6; (A9 *> DQ7) = tpd_A9_DQ7; (A9 *> DQ8) = tpd_A9_DQ8; (A9 *> DQ9) = tpd_A9_DQ9; (A9 *> DQ10) = tpd_A9_DQ10; (A9 *> DQ11) = tpd_A9_DQ11; (A9 *> DQ12) = tpd_A9_DQ12; (A9 *> DQ13) = tpd_A9_DQ13; (A9 *> DQ14) = tpd_A9_DQ14; (A9 *> DQ15) = tpd_A9_DQ15; (A10 *> DQ0) = tpd_A10_DQ0; (A10 *> DQ1) = tpd_A10_DQ1; (A10 *> DQ2) = tpd_A10_DQ2; (A10 *> DQ3) = tpd_A10_DQ3; (A10 *> DQ4) = tpd_A10_DQ4; (A10 *> DQ5) = tpd_A10_DQ5; (A10 *> DQ6) = tpd_A10_DQ6; (A10 *> DQ7) = tpd_A10_DQ7; (A10 *> DQ8) = tpd_A10_DQ8; (A10 *> DQ9) = tpd_A10_DQ9; (A10 *> DQ10) = tpd_A10_DQ10; (A10 *> DQ11) = tpd_A10_DQ11; (A10 *> DQ12) = tpd_A10_DQ12; (A10 *> DQ13) = tpd_A10_DQ13; (A10 *> DQ14) = tpd_A10_DQ14; (A10 *> DQ15) = tpd_A10_DQ15; (A11 *> DQ0) = tpd_A11_DQ0; (A11 *> DQ1) = tpd_A11_DQ1; (A11 *> DQ2) = tpd_A11_DQ2; (A11 *> DQ3) = tpd_A11_DQ3; (A11 *> DQ4) = tpd_A11_DQ4; (A11 *> DQ5) = tpd_A11_DQ5; (A11 *> DQ6) = tpd_A11_DQ6; (A11 *> DQ7) = tpd_A11_DQ7; (A11 *> DQ8) = tpd_A11_DQ8; (A11 *> DQ9) = tpd_A11_DQ9; (A11 *> DQ10) = tpd_A11_DQ10; (A11 *> DQ11) = tpd_A11_DQ11; (A11 *> DQ12) = tpd_A11_DQ12; (A11 *> DQ13) = tpd_A11_DQ13; (A11 *> DQ14) = tpd_A11_DQ14; (A11 *> DQ15) = tpd_A11_DQ15; (A12 *> DQ0) = tpd_A12_DQ0; (A12 *> DQ1) = tpd_A12_DQ1; (A12 *> DQ2) = tpd_A12_DQ2; (A12 *> DQ3) = tpd_A12_DQ3; (A12 *> DQ4) = tpd_A12_DQ4; (A12 *> DQ5) = tpd_A12_DQ5; (A12 *> DQ6) = tpd_A12_DQ6; (A12 *> DQ7) = tpd_A12_DQ7; (A12 *> DQ8) = tpd_A12_DQ8; (A12 *> DQ9) = tpd_A12_DQ9; (A12 *> DQ10) = tpd_A12_DQ10; (A12 *> DQ11) = tpd_A12_DQ11; (A12 *> DQ12) = tpd_A12_DQ12; (A12 *> DQ13) = tpd_A12_DQ13; (A12 *> DQ14) = tpd_A12_DQ14; (A12 *> DQ15) = tpd_A12_DQ15; (A13 *> DQ0) = tpd_A13_DQ0; (A13 *> DQ1) = tpd_A13_DQ1; (A13 *> DQ2) = tpd_A13_DQ2; (A13 *> DQ3) = tpd_A13_DQ3; (A13 *> DQ4) = tpd_A13_DQ4; (A13 *> DQ5) = tpd_A13_DQ5; (A13 *> DQ6) = tpd_A13_DQ6; (A13 *> DQ7) = tpd_A13_DQ7; (A13 *> DQ8) = tpd_A13_DQ8; (A13 *> DQ9) = tpd_A13_DQ9; (A13 *> DQ10) = tpd_A13_DQ10; (A13 *> DQ11) = tpd_A13_DQ11; (A13 *> DQ12) = tpd_A13_DQ12; (A13 *> DQ13) = tpd_A13_DQ13; (A13 *> DQ14) = tpd_A13_DQ14; (A13 *> DQ15) = tpd_A13_DQ15; (A14 *> DQ0) = tpd_A14_DQ0; (A14 *> DQ1) = tpd_A14_DQ1; (A14 *> DQ2) = tpd_A14_DQ2; (A14 *> DQ3) = tpd_A14_DQ3; (A14 *> DQ4) = tpd_A14_DQ4; (A14 *> DQ5) = tpd_A14_DQ5; (A14 *> DQ6) = tpd_A14_DQ6; (A14 *> DQ7) = tpd_A14_DQ7; (A14 *> DQ8) = tpd_A14_DQ8; (A14 *> DQ9) = tpd_A14_DQ9; (A14 *> DQ10) = tpd_A14_DQ10; (A14 *> DQ11) = tpd_A14_DQ11; (A14 *> DQ12) = tpd_A14_DQ12; (A14 *> DQ13) = tpd_A14_DQ13; (A14 *> DQ14) = tpd_A14_DQ14; (A14 *> DQ15) = tpd_A14_DQ15; (A15 *> DQ0) = tpd_A15_DQ0; (A15 *> DQ1) = tpd_A15_DQ1; (A15 *> DQ2) = tpd_A15_DQ2; (A15 *> DQ3) = tpd_A15_DQ3; (A15 *> DQ4) = tpd_A15_DQ4; (A15 *> DQ5) = tpd_A15_DQ5; (A15 *> DQ6) = tpd_A15_DQ6; (A15 *> DQ7) = tpd_A15_DQ7; (A15 *> DQ8) = tpd_A15_DQ8; (A15 *> DQ9) = tpd_A15_DQ9; (A15 *> DQ10) = tpd_A15_DQ10; (A15 *> DQ11) = tpd_A15_DQ11; (A15 *> DQ12) = tpd_A15_DQ12; (A15 *> DQ13) = tpd_A15_DQ13; (A15 *> DQ14) = tpd_A15_DQ14; (A15 *> DQ15) = tpd_A15_DQ15; (A16 *> DQ0) = tpd_A16_DQ0; (A16 *> DQ1) = tpd_A16_DQ1; (A16 *> DQ2) = tpd_A16_DQ2; (A16 *> DQ3) = tpd_A16_DQ3; (A16 *> DQ4) = tpd_A16_DQ4; (A16 *> DQ5) = tpd_A16_DQ5; (A16 *> DQ6) = tpd_A16_DQ6; (A16 *> DQ7) = tpd_A16_DQ7; (A16 *> DQ8) = tpd_A16_DQ8; (A16 *> DQ9) = tpd_A16_DQ9; (A16 *> DQ10) = tpd_A16_DQ10; (A16 *> DQ11) = tpd_A16_DQ11; (A16 *> DQ12) = tpd_A16_DQ12; (A16 *> DQ13) = tpd_A16_DQ13; (A16 *> DQ14) = tpd_A16_DQ14; (A16 *> DQ15) = tpd_A16_DQ15; (A17 *> DQ0) = tpd_A17_DQ0; (A17 *> DQ1) = tpd_A17_DQ1; (A17 *> DQ2) = tpd_A17_DQ2; (A17 *> DQ3) = tpd_A17_DQ3; (A17 *> DQ4) = tpd_A17_DQ4; (A17 *> DQ5) = tpd_A17_DQ5; (A17 *> DQ6) = tpd_A17_DQ6; (A17 *> DQ7) = tpd_A17_DQ7; (A17 *> DQ8) = tpd_A17_DQ8; (A17 *> DQ9) = tpd_A17_DQ9; (A17 *> DQ10) = tpd_A17_DQ10; (A17 *> DQ11) = tpd_A17_DQ11; (A17 *> DQ12) = tpd_A17_DQ12; (A17 *> DQ13) = tpd_A17_DQ13; (A17 *> DQ14) = tpd_A17_DQ14; (A17 *> DQ15) = tpd_A17_DQ15; (A18 *> DQ0) = tpd_A18_DQ0; (A18 *> DQ1) = tpd_A18_DQ1; (A18 *> DQ2) = tpd_A18_DQ2; (A18 *> DQ3) = tpd_A18_DQ3; (A18 *> DQ4) = tpd_A18_DQ4; (A18 *> DQ5) = tpd_A18_DQ5; (A18 *> DQ6) = tpd_A18_DQ6; (A18 *> DQ7) = tpd_A18_DQ7; (A18 *> DQ8) = tpd_A18_DQ8; (A18 *> DQ9) = tpd_A18_DQ9; (A18 *> DQ10) = tpd_A18_DQ10; (A18 *> DQ11) = tpd_A18_DQ11; (A18 *> DQ12) = tpd_A18_DQ12; (A18 *> DQ13) = tpd_A18_DQ13; (A18 *> DQ14) = tpd_A18_DQ14; (A18 *> DQ15) = tpd_A18_DQ15; if (~BYTENeg) (DQ15 *> DQ0) = tpd_DQ15_DQ0; if (~BYTENeg) (DQ15 *> DQ1) = tpd_DQ15_DQ1; if (~BYTENeg) (DQ15 *> DQ2) = tpd_DQ15_DQ2; if (~BYTENeg) (DQ15 *> DQ3) = tpd_DQ15_DQ3; if (~BYTENeg) (DQ15 *> DQ4) = tpd_DQ15_DQ4; if (~BYTENeg) (DQ15 *> DQ5) = tpd_DQ15_DQ5; if (~BYTENeg) (DQ15 *> DQ6) = tpd_DQ15_DQ6; if (~BYTENeg) (DQ15 *> DQ7) = tpd_DQ15_DQ7; if (FROMCE) (CENeg *> DQ0) = tpd_CENeg_DQ0; if (FROMCE) (CENeg *> DQ1) = tpd_CENeg_DQ1; if (FROMCE) (CENeg *> DQ2) = tpd_CENeg_DQ2; if (FROMCE) (CENeg *> DQ3) = tpd_CENeg_DQ3; if (FROMCE) (CENeg *> DQ4) = tpd_CENeg_DQ4; if (FROMCE) (CENeg *> DQ5) = tpd_CENeg_DQ5; if (FROMCE) (CENeg *> DQ6) = tpd_CENeg_DQ6; if (FROMCE) (CENeg *> DQ7) = tpd_CENeg_DQ7; if (FROMCE) (CENeg *> DQ8) = tpd_CENeg_DQ8; if (FROMCE) (CENeg *> DQ9) = tpd_CENeg_DQ9; if (FROMCE) (CENeg *> DQ10) = tpd_CENeg_DQ10; if (FROMCE) (CENeg *> DQ11) = tpd_CENeg_DQ11; if (FROMCE) (CENeg *> DQ12) = tpd_CENeg_DQ12; if (FROMCE) (CENeg *> DQ13) = tpd_CENeg_DQ13; if (FROMCE) (CENeg *> DQ14) = tpd_CENeg_DQ14; if (FROMCE) (CENeg *> DQ15) = tpd_CENeg_DQ15; if (FROMOE) (OENeg *> DQ0) = tpd_OENeg_DQ0; if (FROMOE) (OENeg *> DQ1) = tpd_OENeg_DQ1; if (FROMOE) (OENeg *> DQ2) = tpd_OENeg_DQ2; if (FROMOE) (OENeg *> DQ3) = tpd_OENeg_DQ3; if (FROMOE) (OENeg *> DQ4) = tpd_OENeg_DQ4; if (FROMOE) (OENeg *> DQ5) = tpd_OENeg_DQ5; if (FROMOE) (OENeg *> DQ6) = tpd_OENeg_DQ6; if (FROMOE) (OENeg *> DQ7) = tpd_OENeg_DQ7; if (FROMOE) (OENeg *> DQ8) = tpd_OENeg_DQ8; if (FROMOE) (OENeg *> DQ9) = tpd_OENeg_DQ9; if (FROMOE) (OENeg *> DQ10) = tpd_OENeg_DQ10; if (FROMOE) (OENeg *> DQ11) = tpd_OENeg_DQ11; if (FROMOE) (OENeg *> DQ12) = tpd_OENeg_DQ12; if (FROMOE) (OENeg *> DQ13) = tpd_OENeg_DQ13; if (FROMOE) (OENeg *> DQ14) = tpd_OENeg_DQ14; if (FROMOE) (OENeg *> DQ15) = tpd_OENeg_DQ15; if (RPNeg) (RPNeg *> DQ0) = tpd_RPNeg_DQ0; if (RPNeg) (RPNeg *> DQ1) = tpd_RPNeg_DQ1; if (RPNeg) (RPNeg *> DQ2) = tpd_RPNeg_DQ2; if (RPNeg) (RPNeg *> DQ3) = tpd_RPNeg_DQ3; if (RPNeg) (RPNeg *> DQ4) = tpd_RPNeg_DQ4; if (RPNeg) (RPNeg *> DQ5) = tpd_RPNeg_DQ5; if (RPNeg) (RPNeg *> DQ6) = tpd_RPNeg_DQ6; if (RPNeg) (RPNeg *> DQ7) = tpd_RPNeg_DQ7; if (RPNeg) (RPNeg *> DQ8) = tpd_RPNeg_DQ8; if (RPNeg) (RPNeg *> DQ9) = tpd_RPNeg_DQ9; if (RPNeg) (RPNeg *> DQ10) = tpd_RPNeg_DQ10; if (RPNeg) (RPNeg *> DQ11) = tpd_RPNeg_DQ11; if (RPNeg) (RPNeg *> DQ12) = tpd_RPNeg_DQ12; if (RPNeg) (RPNeg *> DQ13) = tpd_RPNeg_DQ13; if (RPNeg) (RPNeg *> DQ14) = tpd_RPNeg_DQ14; if (RPNeg) (RPNeg *> DQ15) = tpd_RPNeg_DQ15; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// //tas $setup ( A0 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A1 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A2 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A3 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A4 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A5 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A6 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A7 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A8 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A9 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A10 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A11 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A12 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A13 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A14 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A15 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A16 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A17 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A18 , posedge CENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A0 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A1 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A2 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A3 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A4 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A5 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A6 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A7 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A8 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A9 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A10 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A11 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A12 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A13 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A14 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A15 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A16 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A17 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); $setup ( A18 , posedge WENeg &&& WR_cyc, tsetup_A0_CENeg, Viol); //tds $setup ( DQ0 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ1 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ2 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ3 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ4 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ5 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ6 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ7 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ8 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ9 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ10 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ11 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ12 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ13 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ14 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ15 , posedge CENeg &&& WR_cyc_deg, tsetup_DQ0_CENeg, Viol); $setup ( DQ0 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ1 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ2 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ3 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ4 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ5 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ6 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ7 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ8 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ9 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ10 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ11 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ12 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ13 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ14 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( DQ15 , posedge WENeg &&& WR_cyc_deg, tsetup_DQ0_WENeg, Viol); $setup ( CENeg , negedge WENeg , tsetup_CENeg_WENeg, Viol); $setup ( WENeg , negedge CENeg , tsetup_WENeg_CENeg, Viol); $setup ( WPNeg , posedge CENeg , tsetup_WPNeg_CENeg, Viol); $setup ( WPNeg , posedge WENeg , tsetup_WPNeg_WENeg, Viol); $setup ( VPP , posedge CENeg &&& VPP_Chk , tsetup_VPP_CENeg , Viol); $setup ( VPP , posedge WENeg &&& VPP_Chk , tsetup_VPP_WENeg , Viol); $hold ( posedge CENeg, WENeg , thold_CENeg_WENeg, Viol); $hold ( posedge WENeg, CENeg , thold_WENeg_CENeg, Viol); //tah $hold ( posedge CENeg &&& WR_cyc, A0 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A1 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A2 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A3 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A4 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A5 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A6 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A7 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A8 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A9 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A10 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A11 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A12 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A13 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A14 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A15 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A16 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A17 , thold_A0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, A18 , thold_A0_CENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A0 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A1 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A2 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A3 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A4 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A5 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A6 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A7 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A8 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A9 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A10 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A11 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A12 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A13 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A14 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A15 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A16 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A17 , thold_A0_WENeg, Viol); $hold ( posedge WENeg &&& WR_cyc, A18 , thold_A0_WENeg, Viol); //tdh $hold ( posedge CENeg &&& WR_cyc, DQ0 , thold_DQ0_CENeg, Viol); $hold ( posedge CENeg &&& WR_cyc, DQ1 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ2 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ3 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ4 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ5 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ6 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ7 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ8 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ9 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ10 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ11 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ12 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ13 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ14 , thold_DQ0_CENeg,Viol); $hold ( posedge CENeg &&& WR_cyc, DQ15 , thold_DQ0_CENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ0 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ1 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ2 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ3 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ4 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ5 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ6 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ7 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ8 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ9 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ10 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ11 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ12 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ13 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ14 , thold_DQ0_WENeg,Viol); $hold ( posedge WENeg &&& WR_cyc, DQ15 , thold_DQ0_WENeg,Viol); $width (negedge RPNeg, tpw_RPNeg_negedge); $width (posedge WENeg, tpw_WENeg_posedge); $width (negedge WENeg, tpw_WENeg_negedge); $width (posedge CENeg, tpw_CENeg_posedge); $width (negedge CENeg, tpw_CENeg_negedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// reg deq; integer sector_preload[0:MemSize]; always @(DIn, DOut) begin if (DIn==DOut) deq=1'b1; else deq=1'b0; end // check when data is generated from model to avoid setuphold check in // those occasion assign deg=deq; reg [7:0] tmp_char;//stores "T" or "B" character reg [20*8-1:0] tmp_timing;//stores copy of TimingModel integer found = 1'b0; // find which 4 sectors have variable size initial //TOP OR BOTTOM arch model is used //assumptions: //1. TimingModel has format as //"mt28f800b5wp-8 B" //it is important that 16-th character from first one is "T" or "B" //2. TimingModel does not have more then 20 characters begin tmp_timing = TimingModel;//copy of TimingModel i = 19; while ((i >= 0) && (found != 1'b1))//search for first non null character begin //i keeps position of //first non null character j = 7; while ((j >= 0) && (found != 1'b1)) begin if (tmp_timing[i*8+j] != 1'd0) found = 1'b1; else j = j-1; end i = i - 1; end if (found)//if non null character is found begin for (j=0;j<=7;j=j+1) begin tmp_char[j] = TimingModel[(i-14)*8+j];//bottom/top character is 16 end //characters right from first ("m") end if (tmp_char == "T") begin VarSect = SecNum-1; vs = 1'b1; end else if (tmp_char == "B") begin VarSect = 0; vs = 1'b0; end // initialize memory and load preoload files if any for (i=0;i<=MemSize;i=i+1) begin sector_preload[i]=MaxData; end if (UserPreload && mem_file_name != "none") begin //mt28f800b5.mem, memory preload file // @aaaaa - stands for address within last defined sector // dd -
is byte to be written at Mem(nn)(aaaaa++) // (aaaaa is incremented at every load) $readmemh(mem_file_name,sector_preload); end //memory load for (j=0;j<=MemSize;j=j+1) begin Mem[j]=sector_preload[j]; end Boot_Prot = 1'b1; for (i=0;i<=1;i=i+1) begin WData[i] = 0; WAddr[i] = -1; end end initial begin PoweredUp = 1'b0; #100 PoweredUp = 1'b1; end always @(RPNeg) begin RST <= #60 RPNeg; end initial begin write = 1'b0; read = 1'b0; PDONE = 1'b1; PSTART = 1'b0; PERR = 1'b0; EDONE = 1'b1; ESTART = 1'b0; ESUSP = 1'b0; ERES = 1'b0; EERR = 1'b0; READY_in = 1'b0; OENeg_event = 0; CENeg_event = 0; end always @(posedge BUSY_in) begin:TBUSYr #(tdevice_BUSY) BUSY_out = BUSY_in; end always @(negedge BUSY_in) begin:TBUSYf #1 BUSY_out = BUSY_in; end always @(posedge REL_in) begin:TRELr #tdevice_REL REL_out= REL_in; end always @(negedge REL_in) begin:TRELf #1 REL_out = REL_in; end always @(posedge READY_in) begin:TREADYr #tdevice_READY READY_out = READY_in; end always @(negedge READY_in) begin:TREADYf #1 READY_out = READY_in; end //////////////////////////////////////////////////////////////////////////////// //// sequential process for reset control and FSM state transition // //////////////////////////////////////////////////////////////////////////////// reg R; always @(posedge RPNeg) begin if (PoweredUp) //Hardware reset timing control if (RST==1'b1) begin READY_in = 1'b0; R = 1'b0; end else begin READY_in = 1'b1; R = 1'b1; reseted = 1'b0; end end always @(posedge READY_out) begin R = 1'b0; end always @(next_state or negedge RPNeg or posedge READY_out or RST or PoweredUp) begin: StateTransition if(PoweredUp) begin if(RPNeg && (~R || READY_out)) begin current_state = next_state; READY_in = 1'b0; reseted = 1'b1; end else if ((~RPNeg && ~RST)|| ( ~RPNeg && ~RST && ~READY_out)|| ( RPNeg && ~RST && ~READY_out)|| ( RPNeg && RST && ~READY_out)) begin current_state = READ_ARRAY; reseted = 1'b0; end end else begin current_state = READ_ARRAY; reseted = 1'b0; end end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(DOut_zd) begin : OutputGen if (DOut_zd[0] !== 1'bz) begin CEDQ_t = CENeg_event + CEDQ_01; OEDQ_t = OENeg_event + OEDQ_01; ADDRDQ_t = ADDR_event + ADDRDQ_01; FROMCE = ((CEDQ_t >= OEDQ_t) && ( CEDQ_t >= $time)); FROMOE = ((OEDQ_t >= CEDQ_t) && ( OEDQ_t >= $time)); if ((ADDRDQ_t > $time )&& (((ADDRDQ_t>OEDQ_t)&&FROMOE) || ((ADDRDQ_t>CEDQ_t)&&FROMCE))) begin TempData = DOut_zd; if(~ BYTENeg) begin DOut_Pass[7:0]=8'bx; DOut_Pass[15:8]=8'bz; end else DOut_Pass = 16'bx; DOut_Pass <= #( ADDRDQ_t - $time ) TempData; end else DOut_Pass = DOut_zd; end end always @(DOut_zd) begin if (DOut_zd[0] === 1'bz) begin disable OutputGen; FROMCE = 1'b1; FROMOE = 1'b1; DOut_Pass = DOut_zd; end end always @(WENeg or CENeg or OENeg or RPNeg) begin: write_dc if (RPNeg!=1'b0) begin if (~WENeg && ~CENeg && OENeg) write = 1'b1; else write = 1'b0 ; end if (WENeg && ~CENeg && ~OENeg) read = 1'b1; else read = 1'b0; end //////////////////////////////////////////////////////////////////////////////// //Latch address on falling edge of WE# or CE# what ever comes later //Latches data on rising edge of WE# or CE# what ever comes first // also Write cycle decode //////////////////////////////////////////////////////////////////////////////// always @(posedge WENeg_ipd) begin if (reseted) begin if (WENeg_ipd && ~CENeg_ipd && OENeg_ipd ) begin SA_tmp = A[HiAddrBit:16]; if (~BYTENeg) A_tmp1 = { A[15:0],DIn[15] }; else A_tmp1 = { A[15:0],1'b0}; SA = SA_tmp; Address = A_tmp1; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end D_tmp0 = DIn[7:0]; if (BYTENeg) D_tmp1 = DIn[15:8]; end end end always @(posedge CENeg_ipd) begin if (reseted) begin if (CENeg_ipd && ~WENeg_ipd && OENeg_ipd ) begin SA_tmp = A[HiAddrBit:16]; if (~BYTENeg) A_tmp1 = { A[15:0],DIn[15] }; else A_tmp1 = { A[15:0],1'b0}; SA = SA_tmp; Address = A_tmp1; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end D_tmp0 = DIn[7:0]; if (BYTENeg) D_tmp1 = DIn[15:8]; end end end always @(negedge OENeg_ipd ) begin if (reseted) begin if (~OENeg_ipd && WENeg_ipd && ~CENeg_ipd) begin SA_tmp = A[HiAddrBit:16]; IDAddr = A[0]; if (~BYTENeg) A_tmp1 = { A[15:0],DIn[15] }; else A_tmp1 = { A[15:0],1'b0}; SA = SA_tmp; Address = A_tmp1; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end end end end always @(negedge CENeg_ipd ) begin if (reseted) begin if (~CENeg_ipd && WENeg_ipd && ~OENeg_ipd) begin SA_tmp = A[HiAddrBit:16]; IDAddr = A[0]; if (~BYTENeg) A_tmp1 = { A[15:0],DIn[15] }; else A_tmp1 = { A[15:0],1'b0}; SA = SA_tmp; Address = A_tmp1; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end end end end always @(A) begin ADDR_event = $time; if (WENeg_ipd && ~OENeg_ipd && ~CENeg_ipd) begin SA_tmp = A[HiAddrBit:16]; IDAddr = A[0]; if (~BYTENeg) A_tmp1 = { A[15:0],DIn[15] }; else A_tmp1 = { A[15:0],1'b0}; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end SA = SA_tmp; Address = A_tmp1; end end always @(DIn) begin if (~BYTENeg && ~deg) ADDR_event = $time; if (WENeg_ipd && ~OENeg_ipd && ~CENeg_ipd && ~BYTENeg && ~deg) begin SA_tmp = A[HiAddrBit:16]; IDAddr = A[0]; A_tmp1 = { A[15:0],DIn[15] }; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end SA = SA_tmp; Address = A_tmp1; for(i=0;i<=SubSecNum-1;i=i+1) begin if ( A_tmp1 >= sssa(vs,i) && A_tmp1 <= ssea(vs,i) ) begin SubSect = i; end end end end //////////////////////////////////////////////////////////////////////////////// // Timing control for the Program/ Write Buffer Program Operations // start/ suspend/ resume //////////////////////////////////////////////////////////////////////////////// integer cnt_write = 0; time duration_write ; event pdone_event; always @(posedge reseted) begin PDONE = 1'b1; StatusReg[7]=1'b1; end always @(reseted or PSTART) begin if (reseted) begin if (PSTART && PDONE) begin if ((WSec != VarSect || (WSec == VarSect && ((vs==1 && (WSubSec!=3 || (WSubSec==3 && Boot_Prot==1'b0))) ||(vs==0 &&(WSubSec!=0 ||(WSubSec==0 && Boot_Prot==1'b0)))))) && StatusReg[3]==1'b0) begin PDONE = 1'b0; ->pdone_event; duration_write = tdevice_POW; end end end end always @(pdone_event) begin:pdone_process PDONE = 1'b0; #(duration_write) PDONE = 1'b1; end //////////////////////////////////////////////////////////////////////////////// //// Timing control for the Erase Operations // //////////////////////////////////////////////////////////////////////////////// time elapsed_erase; time duration_erase; time start_erase; always @(posedge reseted) begin disable edone_process; EDONE = 1'b1; StatusReg[7]=1'b1; end event edone_event; always @(reseted or ESTART) begin: erase if (reseted) begin if (ErsSec== VarSect) case (ErsSubSec) 0: if (vs== 0) duration_erase= tdevice_BBEO; else duration_erase= tdevice_MBEO; 1: duration_erase = tdevice_PBEO; 2: duration_erase = tdevice_PBEO; 3: if (vs== 1) duration_erase= tdevice_BBEO; else duration_erase= tdevice_MBEO; endcase else duration_erase= tdevice_MBEO; if (ESTART && EDONE) begin if((ErsSec != VarSect || (ErsSec == VarSect && ((vs==1 &&(ErsSubSec!=3 ||(ErsSubSec==3 && Boot_Prot==1'b0))) ||(vs==0 &&(ErsSubSec!=0 ||(ErsSubSec==0 && Boot_Prot==1'b0))))))&& StatusReg[3]==1'b0) begin elapsed_erase = 0; EDONE= 1'b0; ->edone_event; start_erase = $time; end end end end always @(edone_event) begin : edone_process EDONE = 1'b0; #(duration_erase) EDONE = 1'b1; end always @(reseted or ESUSP) begin if (reseted) if (ESUSP && ~EDONE) begin disable edone_process; elapsed_erase = $time - start_erase; duration_erase = duration_erase - elapsed_erase; end end always @(reseted or ERES) begin if (reseted) if (ERES && ~EDONE) begin start_erase = $time; if (current_state != SERS_T) begin duration_erase= duration_erase + tdevice_BUSY; end // deassign EDONE; EDONE = 1'b0; ->edone_event; end end always @(posedge REL_out) begin REL_in = 1'b0; OK_to_l=1'b1; end always @(PDONE or EDONE) begin :rel_ctrl if (reseted &&((PDONE && WSec==VarSect && ((vs==0 && WSubSec==0) || (vs==1 && WSubSec==3))) || (EDONE && ErsSec==VarSect && ((vs==0 && ErsSubSec==0) || (vs==1 && ErsSubSec==3))))) begin REL_in = 1'b1; OK_to_l=1'b0; end end always @(WPNeg) begin :WP_ctrl if (WPNeg) Boot_Prot = 1'b0; else if (~WPNeg) if (OK_to_l) Boot_Prot = 1'b1; else begin $display(" Boot block relock delay time has not elapsed"); $display("simulation may be inaccurate due to timing violations"); end end //////////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////////// always @(negedge OENeg) begin OENeg_event = $time; end always @(negedge CENeg) begin CENeg_event = $time; end //////////////////////////////////////////////////////////////////////////////// // Main Behavior Process // combinational process for next state generation //////////////////////////////////////////////////////////////////////////////// always @(negedge write) begin DataLo = D_tmp0; if (BYTENeg) DataHi = D_tmp1; end always @(negedge write or reseted) begin: StateGen1 if (reseted!=1'b1) next_state = current_state; else case (current_state) READ_ARRAY : begin if (DataLo== 8'h90) next_state = READ_IDENT; else if (DataLo== 8'h70) next_state = READ_STATUS; else if (DataLo== 8'h50) next_state = CLR_STATUS; else if (DataLo== 8'h20) next_state = E_SETUP; else if (DataLo==8'h10 || DataLo==8'h40) next_state = W_SETUP; end READ_IDENT : begin if (DataLo== 8'hFF) next_state = READ_ARRAY; else if (DataLo== 8'h70) next_state = READ_STATUS; else if (DataLo== 8'h50) next_state = CLR_STATUS; else if (DataLo== 8'h20) next_state = E_SETUP; else if (DataLo==8'h10 || DataLo==8'h40) next_state = W_SETUP; end READ_STATUS: begin if (DataLo== 8'hFF) next_state = READ_ARRAY; else if (DataLo== 8'h90) next_state = READ_IDENT; else if (DataLo== 8'h50) next_state = CLR_STATUS; else if (DataLo== 8'h20) next_state = E_SETUP; else if (DataLo== 8'h10 || DataLo== 8'h40) next_state = W_SETUP; end CLR_STATUS: begin if (DataLo== 8'hFF) next_state = READ_ARRAY; else if (DataLo== 8'h90) next_state = READ_IDENT; else if (DataLo== 8'h70) next_state = READ_STATUS; else if (DataLo== 8'h20) next_state = E_SETUP; else if (DataLo== 8'h10 || DataLo== 8'h40) next_state = W_SETUP; end W_SETUP: begin if(VPP==1'b1 && StatusReg[3]==1'b0 &&(SA != VarSect ||(SA ==VarSect && ((vs==1 && (SubSect!=3 || ( SubSect==3 && Boot_Prot==1'b0))) || (vs==0 && (SubSect!=0 || ( SubSect==0 && Boot_Prot==1'b0))))))) next_state = WRITE_T; else next_state = READ_STATUS; end E_SETUP: begin if(VPP==1'b1 && (DataLo== 8'hD0) && StatusReg[3]==1'b0 && (SA != VarSect ||(SA ==VarSect && ((vs==1 && (SubSect!=3 || ( SubSect==3 && Boot_Prot==1'b0))) || (vs==0 && (SubSect!=0 || ( SubSect==0 && Boot_Prot==1'b0))))))) next_state = ERS_T; else next_state = READ_STATUS; end ERS_EX: begin if( EERR != 1'b1 && DataLo == 8'hB0 && VPP==1'b1) next_state = SERS_T; end SERS_T: begin if(DataLo == 8'hD0) next_state = ERS_EX; end SERS: begin if (DataLo== 8'hFF) next_state = SERS_RA; else if (DataLo== 8'h70) next_state = SERS_RS; else if (DataLo== 8'hD0) next_state = RES_T; end SERS_RA : begin if (DataLo== 8'hD0 ) next_state = RES_T; else if (DataLo== 8'h70 ) next_state = SERS_RS; end SERS_RS : begin if (DataLo== 8'hD0 ) next_state = RES_T; else if (DataLo== 8'hFF ) next_state = SERS_RA; end endcase end always @(negedge VPP) begin: StateGen2 case (current_state) W_SETUP: next_state =READ_STATUS; WRITE_T: next_state =READ_STATUS; WRITE_EX: next_state =READ_STATUS; E_SETUP: next_state =READ_STATUS; ERS_T: next_state =READ_STATUS; ERS_EX: next_state =READ_STATUS; SERS_T: next_state =READ_STATUS; SERS: next_state =READ_STATUS; SERS_RA: next_state =READ_STATUS; SERS_RS: next_state =READ_STATUS; RES_T: next_state =READ_STATUS; endcase end always @(posedge BUSY_out) begin: StateGen3 case (current_state) WRITE_T: next_state =WRITE_EX; ERS_T: next_state =ERS_EX; SERS_T: next_state =SERS; RES_T: next_state =ERS_EX; endcase end always @(posedge PDONE) begin: StateGen4 begin if (current_state==WRITE_EX) next_state = READ_STATUS; end end always @(posedge EDONE) begin: StateGen5 begin if (current_state==ERS_EX) next_state = READ_STATUS; end end //////////////////////////////////////////////////////////////////////////////// //FSM Output generation and general funcionality // //////////////////////////////////////////////////////////////////////////////// always @(posedge read) begin ->oe_event; end always @(Address or SA) begin if (read) ->oe_event; end always @(oe_event) begin oe = 1'b1; #1 oe = 1'b0; end always @(oe or reseted or current_state) begin if (reseted) begin case (current_state) READ_ARRAY : begin if (oe) begin MemRead(DOut_zd); end end READ_IDENT : begin if (oe) begin IDRead(DOut_zd); end end READ_STATUS: begin if (oe) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end end WRITE_EX : begin if (oe) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end end ERS_EX: begin if (oe) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end end SERS: begin if (oe) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end end SERS_RA: begin if (oe) begin if (SA==ErsSec || (SubSect==ErsSubSec && SA== VarSect)) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end else MemRead(DOut_zd); end end SERS_RS: begin if (oe) begin DOut_zd[7:0] = StatusReg; if (BYTENeg) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'bz; end end endcase end end always @(negedge VPP) begin case (current_state) W_SETUP: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; PERR =1'b1; end WRITE_T: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; PERR =1'b1; BUSY_in=1'b0; end WRITE_EX: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; PERR =1'b1; end E_SETUP: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; end ERS_T: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; BUSY_in=1'b0; end ERS_EX: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; end SERS_T: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; BUSY_in=1'b0; end SERS: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; end SERS_RA: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; end SERS_RS: begin StatusReg[3]=1'b1; StatusReg[7]=1'b1; EERR =1'b1; end RES_T: begin StatusReg[3]=1'b1; StatusReg[6]=1'b0; StatusReg[7]=1'b1; EERR =1'b1; BUSY_in=1'b0; end endcase end always @(negedge write or reseted) begin : Output_generation if (reseted) begin case (current_state) READ_ARRAY : begin PERR =1'b0; EERR =1'b0; end CLR_STATUS: StatusReg[5:3]= 3'b0; W_SETUP: begin if (VPP==1'b1 && StatusReg[3]==1'b0 && (SA != VarSect ||(SA ==VarSect && ((vs==1 &&(SubSect!=3 ||(SubSect==3 && Boot_Prot==1'b0))) ||(vs==0 && (SubSect!=0 || (SubSect==0 && Boot_Prot==1'b0))))))) begin WData[0] = -1; WData[1] = -1; if (Viol == 1'b0) begin WData[0] = DataLo; WData[1] = DataHi; end WAddr[0] = Address; WSec = SA; WSubSec = SubSect; if (BYTENeg) WAddr[1] = WAddr[0] + 1; else WAddr[1] = -1; BUSY_in = 1'b1; PSTART = 1'b1; PSTART =#1 1'b0; end else begin StatusReg[7]=1'b1; PERR =1'b1; StatusReg[4]=1'b1; end end E_SETUP: begin if(VPP==1'b1 && (DataLo== 8'hD0) && StatusReg[3]==1'b0 && (SA != VarSect ||(SA ==VarSect && ((vs==1 && (SubSect!=3 || ( SubSect==3 && Boot_Prot==1'b0))) || (vs==0 && (SubSect!=0 || ( SubSect==0 && Boot_Prot==1'b0))))))) begin ErsSec = SA; ErsSubSec = SubSect; BUSY_in = 1'b1; ESTART = 1'b1; ESTART =#1 1'b0; ESUSP = 1'b0; ERES = 1'b0; end else begin StatusReg[4]=1'b1; StatusReg[5]=1'b1; end end ERS_EX: begin if( EERR != 1'b1 && DataLo == 8'hB0 && VPP==1'b1) begin BUSY_in = 1'b1; ESUSP = 1'b1; ESUSP =#1 1'b0; end end SERS_T: begin if( DataLo == 8'hD0) begin BUSY_in = 1'b0; ERES = 1'b1; ERES =#1 1'b0; StatusReg[7]=1'b0; StatusReg[6]=1'b0; end end SERS: begin if( DataLo == 8'hD0) begin BUSY_in = 1'b1; ERES = 1'b1; ERES =#1 1'b0; end end SERS_RA: begin if( DataLo == 8'hD0) begin BUSY_in = 1'b1; ERES = 1'b1; ERES =#1 1'b0; end end SERS_RS: begin if( DataLo == 8'hD0) begin BUSY_in = 1'b1; ERES = 1'b1; ERES =#1 1'b0; end end endcase end end always @(posedge BUSY_out) begin case (current_state) WRITE_T: begin BUSY_in=1'b0; StatusReg[7]=1'b0; end ERS_T: begin BUSY_in=1'b0; StatusReg[7]=1'b0; end SERS_T: begin BUSY_in=1'b0; StatusReg[7]=1'b1; StatusReg[6]=1'b1; end RES_T: begin BUSY_in=1'b0; StatusReg[7]=1'b0; StatusReg[6]=1'b0; end endcase end always @(current_state or posedge PDONE) begin: WEX integer i,j; if (current_state == WRITE_EX) begin if (PDONE) StatusReg[7]=1'b1; if (~PERR) begin if (WAddr[1] < 0) wr_cnt = 0; else wr_cnt = 1; for (i=wr_cnt;i>=0;i=i-1) begin new_int= WData[i]; if (WAddr[i] >= 0) old_int=Mem[sa(WSec)+WAddr[i]]; WData[i]= -1; if (new_int>-1) begin new_bit = new_int; if (old_int>-1) begin old_bit = old_int; for(j=0;j<=7;j=j+1) if (~old_bit[j]) new_bit[j]=1'b0; new_int=new_bit; end WData[i]= new_int; end end for (i=wr_cnt;i>=0;i=i-1) begin Mem[sa(WSec)+WAddr[i]] = -1; end if (PDONE && ~PSTART) for (i=wr_cnt;i>=0;i=i-1) begin if (WAddr[i]> -1) Mem[sa(WSec)+WAddr[i]] = WData[i]; WData[i]= -1; end end end end always @(posedge EDONE or current_state) begin: EEX integer i,j; if (current_state==ERS_EX) begin if(EDONE) StatusReg[7]=1'b1; if (~EERR) begin if( ErsSec == VarSect) begin if((vs==1 &&((ErsSubSec==3 && Boot_Prot==1'b0) || ErsSubSec!=3)) || (vs==0 &&((ErsSubSec==0 && Boot_Prot==1'b0)|| ErsSubSec!=0))) for(k=sssa(vs,ErsSubSec);k<=ssea(vs,ErsSubSec);k=k+1) Mem[sa(ErsSec)+k] = -1; end else begin for (j=0;j<=SecSize;j=j+1) Mem[sa(ErsSec)+j] = -1; end if(EDONE) if(ErsSec == VarSect) for(k=sssa(vs,ErsSubSec);k<=ssea(vs,ErsSubSec);k=k+1) Mem[sa(ErsSec)+k] = MaxData; else for (j=0;j<=SecSize;j=j+1) Mem[sa(ErsSec)+j] = MaxData; end end end always @(OENeg or RPNeg or RST or BYTENeg) begin //Output Disable Control if (OENeg || (~RPNeg && ~RST)) DOut_zd = 16'bZ; else if (~BYTENeg) DOut_zd[15:8] = 8'bZ; end //////////////// //PROCEDURES /////////////// function integer sa; input integer sect; begin sa = sect * (SecSize + 1); end endfunction task MemRead; inout [15:0] DOut_zd; begin if (Mem[sa(SA)+Address]==-1) DOut_zd[7:0] = 8'bx; else begin DOut_zd[7:0] = Mem[sa(SA)+Address]; end if (BYTENeg) begin if (Mem[sa(SA)+Address+1]==-1) DOut_zd[15:8]= 8'bx; else DOut_zd[15:8] = Mem[sa(SA)+Address+1]; end end endtask task IDRead; inout [15:0] DOut_zd; begin if (BYTENeg) if (~IDAddr) DOut_zd[15:8] = 0; else DOut_zd[15:8] = 8'h88; else DOut_zd[15:8] = 8'bZ; if (~IDAddr) DOut_zd[7:0] =8'h89; else begin if (vs == 1) DOut_zd[7:0] = 8'h9C; else DOut_zd[7:0] = 8'h9D; end end endtask function integer sssa; input integer vs; input integer subsect; begin if (subsect == 0) sssa=20'h00000; else if (subsect == 1) sssa=vs ? 20'h18000 : 20'h04000 ; else if (subsect == 2) sssa=vs ? 20'h1A000 : 20'h06000; else sssa=vs ? 20'h1C000 : 20'h08000; end endfunction function integer ssea; input integer vs; input integer subsect; begin if (subsect == 0) ssea=vs ? 20'h17FFF : 20'h03FFF; else if (subsect == 1) ssea=vs ? 20'h19FFF : 20'h05FFF; else if (subsect == 2) ssea=vs ? 20'h1BFFF : 20'h07FFF; else ssea=20'h1FFFF; end endfunction reg BuffInOE, BuffInCE,BuffInADDR; wire BuffOutOE, BuffOutCE,BuffOutADDR; BUFFER BUFOE (BuffOutOE, BuffInOE); BUFFER BUFCE (BuffOutCE, BuffInCE); BUFFER BUFADDR (BuffOutADDR, BuffInADDR); initial begin BuffInOE = 1'b1; BuffInCE = 1'b1; BuffInADDR = 1'b1; end always @(posedge BuffOutOE) begin OEDQ_01 = $time; end always @(posedge BuffOutCE) begin CEDQ_01 = $time; end always @(posedge BuffOutADDR) begin ADDRDQ_01 = $time; end endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule