/* -------------------------------------------------------------------------------- -- File Name: idt72t54242.v -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Gmitrovic 05 Dec 12 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: Library: FIFO Technology: CMOS Part: IDT72T54242 Description: 32,768x10x4/16,384x20x2 QUAD/DUAL TeraSync DDR/SDR FIFO ------------------------------------------------------------------------------*/ ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ps/1 ps //////////////////////////////////////////////// // Top level module, 4 FIFO instances //////////////////////////////////////////////// module idt72t54242 ( D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, D32, D33, D34, D35, D36, D37, D38, D39, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, MD, EF0Neg, EF1Neg, EF2Neg, EF3Neg, ERCLK0, ERCLK1, ERCLK2, ERCLK3, EREN0Neg, EREN1Neg, EREN2Neg, EREN3Neg, FF0Neg, FF1Neg, FF2Neg, FF3Neg, FSEL0, FSEL1, FWFT, IOSEL, IW, PDNeg, MRSNeg, OE0Neg, OE1Neg, OE2Neg, OE3Neg, OW, PAE0Neg, PAE1Neg, PAE2Neg, PAE3Neg, PAF0Neg, PAF1Neg, PAF2Neg, PAF3Neg, PRSNeg, RCLK0, RCLK1, RCLK2, RCLK3, RCS0Neg, RCS1Neg, RCS2Neg, RCS3Neg, REN0Neg, REN1Neg, REN2Neg, REN3Neg, RDDR, PFM, SCLK, SWENNeg, SRENNeg, SI, SDO, WCLK0, WCLK1, WCLK2, WCLK3, WCS0Neg, WCS1Neg, WCS2Neg, WCS3Neg, WEN0Neg, WEN1Neg, WEN2Neg, WEN3Neg, WDDR ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input D0; input D1; input D2; input D3; input D4; input D5; input D6; input D7; input D8; input D9; input D10; input D11; input D12; input D13; input D14; input D15; input D16; input D17; input D18; input D19; input D20; input D21; input D22; input D23; input D24; input D25; input D26; input D27; input D28; input D29; input D30; input D31; input D32; input D33; input D34; input D35; input D36; input D37; input D38; input D39; output Q0; output Q1; output Q2; output Q3; output Q4; output Q5; output Q6; output Q7; output Q8; output Q9; output Q10; output Q11; output Q12; output Q13; output Q14; output Q15; output Q16; output Q17; output Q18; output Q19; output Q20; output Q21; output Q22; output Q23; output Q24; output Q25; output Q26; output Q27; output Q28; output Q29; output Q30; output Q31; output Q32; output Q33; output Q34; output Q35; output Q36; output Q37; output Q38; output Q39; input MD; input FSEL0; input FSEL1; input FWFT; input IOSEL; input IW; input PDNeg; input MRSNeg; input OE0Neg; input OE1Neg; input OE2Neg; input OE3Neg; input OW; input PRSNeg; input RCLK0; input RCLK1; input RCLK2; input RCLK3; input RCS1Neg; input RCS2Neg; input RCS3Neg; input RCS0Neg; input REN0Neg; input REN1Neg; input REN2Neg; input REN3Neg; input RDDR; input PFM; input SCLK; input SWENNeg; input SRENNeg; input SI; input WCLK0; input WCLK1; input WCLK2; input WCLK3; input WCS0Neg; input WCS1Neg; input WCS2Neg; input WCS3Neg; input WEN0Neg; input WEN1Neg; input WEN2Neg; input WEN3Neg; input WDDR; output EF0Neg; output EF1Neg; output EF2Neg; output EF3Neg; output ERCLK0; output ERCLK1; output ERCLK2; output ERCLK3; output EREN0Neg; output EREN1Neg; output EREN2Neg; output EREN3Neg; output FF0Neg; output FF1Neg; output FF2Neg; output FF3Neg; output PAE0Neg; output PAE1Neg; output PAE2Neg; output PAE3Neg; output PAF0Neg; output PAF1Neg; output PAF2Neg; output PAF3Neg; output SDO; wire D0; wire D1; wire D2; wire D3; wire D4; wire D5; wire D6; wire D7; wire D8; wire D9; wire D10; wire D11; wire D12; wire D13; wire D14; wire D15; wire D16; wire D17; wire D18; wire D19; wire D20; wire D21; wire D22; wire D23; wire D24; wire D25; wire D26; wire D27; wire D28; wire D29; wire D30; wire D31; wire D32; wire D33; wire D34; wire D35; wire D36; wire D37; wire D38; wire D39; wire Q0; wire Q1; wire Q2; wire Q3; wire Q4; wire Q5; wire Q6; wire Q7; wire Q8; wire Q9; wire Q10; wire Q11; wire Q12; wire Q13; wire Q14; wire Q15; wire Q16; wire Q17; wire Q18; wire Q19; wire Q20; wire Q21; wire Q22; wire Q23; wire Q24; wire Q25; wire Q26; wire Q27; wire Q28; wire Q29; wire Q30; wire Q31; wire Q32; wire Q33; wire Q34; wire Q35; wire Q36; wire Q37; wire Q38; wire Q39; wire MD; wire FSEL0; wire FSEL1; wire FWFT; wire IOSEL; wire IW; wire PDNeg; wire MRSNeg; wire OE0Neg; wire OE1Neg; wire OE2Neg; wire OE3Neg; wire OW; wire PRSNeg; wire RCLK0; wire RCLK1; wire RCLK2; wire RCLK3; wire RCS0Neg; wire RCS1Neg; wire RCS2Neg; wire RCS3Neg; wire RENNeg; wire REN0Neg; wire REN1Neg; wire REN2Neg; wire REN3Neg; wire RDDR; wire PFM; wire SCLK; wire SWENNeg; wire SRENNeg; wire SI; wire WCLK0; wire WCLK1; wire WCLK2; wire WCLK3; wire WCS0Neg; wire WCS1Neg; wire WCS2Neg; wire WCS3Neg; wire WEN0Neg; wire WEN1Neg; wire WEN2Neg; wire WEN3Neg; wire WDDR; wire EF0Neg; wire EF1Neg; wire EF2Neg; wire EF3Neg; wire ERCLK0; wire ERCLK1; wire ERCLK2; wire ERCLK3; wire EREN0Neg; wire EREN1Neg; wire EREN2Neg; wire EREN3Neg; wire FF0Neg; wire FF1Neg; wire FF2Neg; wire FF3Neg; wire PAE0Neg; wire PAE1Neg; wire PAE2Neg; wire PAE3Neg; wire PAF0Neg; wire PAF1Neg; wire PAF2Neg; wire PAF3Neg; wire SDO; wire dummy; // parameter declaration parameter TimingModel = "defaulttimingmodel"; parameter FIFOnumber = 0; // Instance of FIFO0 idt72t54242_onefifo #(.TimingModel(TimingModel), .FIFOnumber(0)) FIFO0 ( .D0 (D0) , .D1 (D1) , .D2 (D2) , .D3 (D3) , .D4 (D4) , .D5 (D5) , .D6 (D6) , .D7 (D7) , .D8 (D8) , .D9 (D9) , .D10 (D10) , .D11 (D11) , .D12 (D12) , .D13 (D13) , .D14 (D14) , .D15 (D15) , .D16 (D16) , .D17 (D17) , .D18 (D18) , .D19 (D19) , .Q0 (Q0) , .Q1 (Q1) , .Q2 (Q2) , .Q3 (Q3) , .Q4 (Q4) , .Q5 (Q5) , .Q6 (Q6) , .Q7 (Q7) , .Q8 (Q8) , .Q9 (Q9) , .Q10 (Q10) , .Q11 (Q11) , .Q12 (Q12) , .Q13 (Q13) , .Q14 (Q14) , .Q15 (Q15) , .Q16 (Q16) , .Q17 (Q17) , .Q18 (Q18) , .Q19 (Q19) , .MD (MD) , .EFNeg (EF0Neg) , .ERCLK (ERCLK0) , .ERENNeg (EREN0Neg) , .FFNeg (FF0Neg) , .FSEL0 (FSEL0) , .FSEL1 (FSEL1) , .FWFT (FWFT) , .IOSEL (IOSEL) , .IW (IW) , .PDNeg (PDNeg) , .MRSNeg (MRSNeg) , .OENeg (OE0Neg) , .OW (OW) , .PAENeg (PAE0Neg) , .PAFNeg (PAF0Neg) , .PRSNeg (PRSNeg) , .RCLK (RCLK0) , .RCSNeg (RCS0Neg) , .RENNeg (REN0Neg) , .RDDR (RDDR) , .PFM (PFM) , .SCLK (SCLK) , .SWENNeg (SWENNeg) , .SRENNeg (SRENNeg) , .SI (SI) , .SDO (SDO) , .WCLK (WCLK0) , .WCSNeg (WCS0Neg) , .WENNeg (WEN0Neg) , .WDDR (WDDR)); // Instance of FIFO1 idt72t54242_onefifo #(.TimingModel(TimingModel), .FIFOnumber(1)) FIFO1 ( .D0 (D10) , .D1 (D11) , .D2 (D12) , .D3 (D13) , .D4 (D14) , .D5 (D15) , .D6 (D16) , .D7 (D17) , .D8 (D18) , .D9 (D19) , .D10 (dummy) , .D11 (dummy) , .D12 (dummy) , .D13 (dummy) , .D14 (dummy) , .D15 (dummy) , .D16 (dummy) , .D17 (dummy) , .D18 (dummy) , .D19 (dummy) , .Q0 (Q10) , .Q1 (Q11) , .Q2 (Q12) , .Q3 (Q13) , .Q4 (Q14) , .Q5 (Q15) , .Q6 (Q16) , .Q7 (Q17) , .Q8 (Q18) , .Q9 (Q19) , .Q10 (dummy) , .Q11 (dummy) , .Q12 (dummy) , .Q13 (dummy) , .Q14 (dummy) , .Q15 (dummy) , .Q16 (dummy) , .Q17 (dummy) , .Q18 (dummy) , .Q19 (dummy) , .MD (MD) , .EFNeg (EF1Neg) , .ERCLK (ERCLK1) , .ERENNeg (EREN1Neg) , .FFNeg (FF1Neg) , .FSEL0 (FSEL0) , .FSEL1 (FSEL1) , .FWFT (FWFT) , .IOSEL (IOSEL) , .IW (IW) , .PDNeg (PDNeg) , .MRSNeg (MRSNeg) , .OENeg (OE1Neg) , .OW (OW) , .PAENeg (PAE1Neg) , .PAFNeg (PAF1Neg) , .PRSNeg (PRSNeg) , .RCLK (RCLK1) , .RCSNeg (RCS1Neg) , .RENNeg (REN1Neg) , .RDDR (RDDR) , .PFM (PFM) , .SCLK (SCLK) , .SWENNeg (SWENNeg) , .SRENNeg (SRENNeg) , .SI (SI) , .SDO (dummy) , .WCLK (WCLK1) , .WCSNeg (WCS1Neg) , .WENNeg (WEN1Neg) , .WDDR (WDDR)); // Instance of FIFO2 idt72t54242_onefifo #(.TimingModel(TimingModel), .FIFOnumber(2)) FIFO2 ( .D0 (D20) , .D1 (D21) , .D2 (D22) , .D3 (D23) , .D4 (D24) , .D5 (D25) , .D6 (D26) , .D7 (D27) , .D8 (D28) , .D9 (D29) , .D10 (D30) , .D11 (D31) , .D12 (D32) , .D13 (D33) , .D14 (D34) , .D15 (D35) , .D16 (D36) , .D17 (D37) , .D18 (D38) , .D19 (D39) , .Q0 (Q20) , .Q1 (Q21) , .Q2 (Q22) , .Q3 (Q23) , .Q4 (Q24) , .Q5 (Q25) , .Q6 (Q26) , .Q7 (Q27) , .Q8 (Q28) , .Q9 (Q29) , .Q10 (Q30) , .Q11 (Q31) , .Q12 (Q32) , .Q13 (Q33) , .Q14 (Q34) , .Q15 (Q35) , .Q16 (Q36) , .Q17 (Q37) , .Q18 (Q38) , .Q19 (Q39) , .MD (MD) , .EFNeg (EF2Neg) , .ERCLK (ERCLK2) , .ERENNeg (EREN2Neg) , .FFNeg (FF2Neg) , .FSEL0 (FSEL0) , .FSEL1 (FSEL1) , .FWFT (FWFT) , .IOSEL (IOSEL) , .IW (IW) , .PDNeg (PDNeg) , .MRSNeg (MRSNeg) , .OENeg (OE2Neg) , .OW (OW) , .PAENeg (PAE2Neg) , .PAFNeg (PAF2Neg) , .PRSNeg (PRSNeg) , .RCLK (RCLK2) , .RCSNeg (RCS2Neg) , .RENNeg (REN2Neg) , .RDDR (RDDR) , .PFM (PFM) , .SCLK (SCLK) , .SWENNeg (SWENNeg) , .SRENNeg (SRENNeg) , .SI (SI) , .SDO (SDO) , .WCLK (WCLK2) , .WCSNeg (WCS2Neg) , .WENNeg (WEN2Neg) , .WDDR (WDDR)); // Instance of FIFO3 idt72t54242_onefifo #(.TimingModel(TimingModel), .FIFOnumber(3)) FIFO3 ( .D0 (D30) , .D1 (D31) , .D2 (D32) , .D3 (D33) , .D4 (D34) , .D5 (D35) , .D6 (D36) , .D7 (D37) , .D8 (D38) , .D9 (D39) , .D10 (dummy) , .D11 (dummy) , .D12 (dummy) , .D13 (dummy) , .D14 (dummy) , .D15 (dummy) , .D16 (dummy) , .D17 (dummy) , .D18 (dummy) , .D19 (dummy) , .Q0 (Q30) , .Q1 (Q31) , .Q2 (Q32) , .Q3 (Q33) , .Q4 (Q34) , .Q5 (Q35) , .Q6 (Q36) , .Q7 (Q37) , .Q8 (Q38) , .Q9 (Q39) , .Q10 (Dummy) , .Q11 (Dummy) , .Q12 (Dummy) , .Q13 (Dummy) , .Q14 (Dummy) , .Q15 (Dummy) , .Q16 (Dummy) , .Q17 (Dummy) , .Q18 (Dummy) , .Q19 (Dummy) , .MD (MD) , .EFNeg (EF3Neg) , .ERCLK (ERCLK3) , .ERENNeg (EREN3Neg) , .FFNeg (FF3Neg) , .FSEL0 (FSEL0) , .FSEL1 (FSEL1) , .FWFT (FWFT) , .IOSEL (IOSEL) , .IW (IW) , .PDNeg (PDNeg) , .MRSNeg (MRSNeg) , .OENeg (OE3Neg) , .OW (OW) , .PAENeg (PAE3Neg) , .PAFNeg (PAF3Neg) , .PRSNeg (PRSNeg) , .RCLK (RCLK3) , .RCSNeg (RCS3Neg) , .RENNeg (REN3Neg) , .RDDR (RDDR) , .PFM (PFM) , .SCLK (SCLK) , .SWENNeg (SWENNeg) , .SRENNeg (SRENNeg) , .SI (SI) , .SDO (dummy) , .WCLK (WCLK3) , .WCSNeg (WCS3Neg) , .WENNeg (WEN3Neg) , .WDDR (WDDR)); endmodule //////////////////////////////////////////////////// // Timing model single FIFO component //////////////////////////////////////////////////// module idt72t54242_onefifo ( D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, MD, EFNeg, ERCLK, ERENNeg, FFNeg, FSEL0, FSEL1, FWFT, IOSEL, IW, PDNeg, MRSNeg, OENeg, OW, PAENeg, PAFNeg, PRSNeg, RCLK, RCSNeg, RENNeg, RDDR, PFM, SCLK, SWENNeg, SRENNeg, SI, SDO, WCLK, WCSNeg, WENNeg, WDDR ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input D0; input D1; input D2; input D3; input D4; input D5; input D6; input D7; input D8; input D9; input D10; input D11; input D12; input D13; input D14; input D15; input D16; input D17; input D18; input D19; output Q0; output Q1; output Q2; output Q3; output Q4; output Q5; output Q6; output Q7; output Q8; output Q9; output Q10; output Q11; output Q12; output Q13; output Q14; output Q15; output Q16; output Q17; output Q18; output Q19; input MD; input FSEL0; input FSEL1; input FWFT; input IOSEL; input IW; input PDNeg; input MRSNeg; input OENeg; input OW; input PRSNeg; input RCLK; input RCSNeg; input RENNeg; input RDDR; input PFM; input SCLK; input SWENNeg; input SRENNeg; input SI; input WCLK; input WCSNeg; input WENNeg; input WDDR; output EFNeg; output ERCLK; output ERENNeg; output FFNeg; output PAENeg; output PAFNeg; output SDO; // interconnect path delay signals wire D0_ipd ; wire D1_ipd ; wire D2_ipd ; wire D3_ipd ; wire D4_ipd ; wire D5_ipd ; wire D6_ipd ; wire D7_ipd ; wire D8_ipd ; wire D9_ipd ; wire D10_ipd ; wire D11_ipd ; wire D12_ipd ; wire D13_ipd ; wire D14_ipd ; wire D15_ipd ; wire D16_ipd ; wire D17_ipd ; wire D18_ipd ; wire D19_ipd ; wire [19:0] DIn; assign DIn ={D19_ipd , D18_ipd , D17_ipd , D16_ipd , D15_ipd , D14_ipd , D13_ipd , D12_ipd , D11_ipd , D10_ipd , D9_ipd , D8_ipd , D7_ipd , D6_ipd , D5_ipd , D4_ipd , D3_ipd , D2_ipd , D1_ipd , D0_ipd }; wire MD_ipd ; wire FSEL0_ipd ; wire FSEL1_ipd ; wire FWFT_ipd ; wire IOSEL_ipd ; wire IW_ipd ; wire PDNeg_ipd ; wire MRSNeg_ipd ; wire OENeg_ipd ; wire OW_ipd ; wire PRSNeg_ipd ; wire RCLK_ipd ; wire RCSNeg_ipd ; wire RENNeg_ipd ; wire RDDR_ipd ; wire PFM_ipd ; wire SCLK_ipd ; wire SENNeg_ipd ; wire SRENNeg_ipd ; wire SI_ipd ; wire WCLK_ipd ; wire WCSNeg_ipd ; wire WENNeg_ipd ; wire WDDR_ipd ; // internal delays reg [19 : 0] QOut_zd; wire Q19_Pass ; wire Q18_Pass ; wire Q17_Pass ; wire Q16_Pass ; wire Q15_Pass ; wire Q14_Pass ; wire Q13_Pass ; wire Q12_Pass ; wire Q11_Pass ; wire Q10_Pass ; wire Q9_Pass ; wire Q8_Pass ; wire Q7_Pass ; wire Q6_Pass ; wire Q5_Pass ; wire Q4_Pass ; wire Q3_Pass ; wire Q2_Pass ; wire Q1_Pass ; wire Q0_Pass ; reg [19 : 0] QOut_Pass; assign {Q19_Pass, Q18_Pass, Q17_Pass, Q16_Pass, Q15_Pass, Q14_Pass, Q13_Pass, Q12_Pass, Q11_Pass, Q10_Pass, Q9_Pass, Q8_Pass, Q7_Pass, Q6_Pass, Q5_Pass, Q4_Pass, Q3_Pass, Q2_Pass, Q1_Pass, Q0_Pass } = QOut_Pass; parameter FIFOnumber = 0; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "idt72t54242"; parameter MemorySize = 32768; parameter MaxData = 1023; parameter HiDBit = 19; integer tSKEW1; integer tSKEW2; integer tSKEW3; integer OE_t; integer RCLK_t; reg mreset = 1'b0; reg time_flag_for_OE = 1'b0; reg FROMOE = 1'b0; reg FROMPD = 1'b0; reg FROMRCLK = 1'b0; integer offsetps[3:0]; reg wrote_in = 1'b0; reg read_out = 1'b0; reg Viol = 1'b0; reg EFNeg_zd; reg FFNeg_zd; reg PAFNeg_zd; reg PAFNeg_dly; reg PAENeg_zd; reg PAENeg_dly; reg ERCLK_zd; reg ERENNeg_zd; reg[19:0] Qreg = 40'b0; reg[19:0] Qreg_tmp = 40'b0; reg SDO_zd; integer fwftmod = 1'b0; integer iw = 1'b0; integer ow = 1'b0; integer memA[0:MemorySize + 1]; integer memB[0:MemorySize + 1]; parameter normal = 5'd11; parameter mapped = 5'd12; reg[4:0] memory_model; integer rdptr = 1'b0; integer wrptr = 1'b0; integer rdptr_next = 1'b0; integer wrptr_next = 1'b0; integer paeoff; //pae offset integer pafoff; //paf offset integer opi; //offset preset index integer count; integer fwftcnt; // fwft RCLK counter integer fwftcnt1; // fwft output integer fwftvar = 1'b0; // fwft flag for outreg integer fwft_eren = 1'b0; integer do_fw = 1'b0; integer fw_done = 1'b0; integer fwcnt; reg[1:0] opireg; reg[39:0] outreg; reg[39:0] outtmp; integer rd_upd_flg = 1'b0; integer wr_upd_flg = 1'b0; integer Eflagcnt = 1'd0; integer PAEflagcnt = 1'd0; integer PAFflagcnt = 1'd0; integer Fflagcnt = 1'd0; integer TotalLoc = MemorySize; integer TotalLoc1 = MemorySize; integer count_rcycle; integer count_wcycle; time tRCLKposedge = 0; time tWCLKposedge = 0; time tRCLKnegedge = 0; time tWCLKnegedge = 0; time OENeg_event = 0; integer minskew1RW = 1'b1; integer minskew2RW = 1'b1; integer minskew3RW = 1'b1; integer minskew1WR = 1'b1; integer minskew2WR = 1'b1; integer minskew3WR = 1'b1; parameter write = 5'd8; parameter read = 5'd9; parameter none = 5'd10; reg[4:0] last_done = none; reg flag_FF = 1'b0; reg flag_EF = 1'b0; reg flag_PAF = 1'b0; reg flag_PAE = 1'b0; integer pass_EF = 1'b0; integer pass_FF = 1'b0; integer pass_PAE = 1'b0; integer pass_PAF = 1'b0; reg[2:0] bm_reg; integer bm_Incnt = 1'd0; integer bm_Outcnt = 1'd0; integer fs_Incnt = 1'd0; reg[119:0] tmp_ser_in =119'b0; parameter SDR = 2'd0; parameter DDR = 2'd1; reg[4:0] mode_wr; reg[4:0] mode_rd; parameter DDR20 = 5'd1; parameter DDR10 = 5'd2; parameter SDR20 = 5'd4; parameter SDR10 = 5'd5; reg[4:0] in_mode; reg[4:0] out_mode; reg[4:0] device_mode; reg[4:0] PFM_mode; parameter sync = 5'd0; parameter async = 5'd1; parameter QUAD = 5'd0; parameter DUAL = 5'd1; integer Data1 = 0; integer Data2 = 0; integer write_clk_paf = 1'b0; integer read_clk_pae = 1'b0; integer delayed_pae = 1'b0; integer delayed_paf = 1'b0; integer WCLK_1 = 1'b0; integer update_EFNeg_fwft = 1'b0; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (D19_ipd, D19); buf (D18_ipd, D18); buf (D17_ipd, D17); buf (D16_ipd, D16); buf (D15_ipd, D15); buf (D14_ipd, D14); buf (D13_ipd, D13); buf (D12_ipd, D12); buf (D11_ipd, D11); buf (D10_ipd, D10); buf (D9_ipd , D9 ); buf (D8_ipd , D8 ); buf (D7_ipd , D7 ); buf (D6_ipd , D6 ); buf (D5_ipd , D5 ); buf (D4_ipd , D4 ); buf (D3_ipd , D3 ); buf (D2_ipd , D2 ); buf (D1_ipd , D1 ); buf (D0_ipd , D0 ); buf (MD_ipd , MD ); buf (FSEL0_ipd , FSEL0 ); buf (FSEL1_ipd , FSEL1 ); buf (FWFT_ipd , FWFT ); buf (IOSEL_ipd , IOSEL ); buf (IW_ipd , IW ); buf (PDNeg_ipd , PDNeg ); buf (MRSNeg_ipd , MRSNeg ); buf (OENeg_ipd , OENeg ); buf (OW_ipd , OW ); buf (PRSNeg_ipd , PRSNeg ); buf (RCLK_ipd , RCLK ); buf (RCSNeg_ipd , RCSNeg ); buf (RENNeg_ipd , RENNeg ); buf (RDDR_ipd , RDDR ); buf (PFM_ipd , PFM ); buf (SCLK_ipd , SCLK ); buf (SWENNeg_ipd, SWENNeg ); buf (SRENNeg_ipd, SRENNeg ); buf (SI_ipd , SI ); buf (WCLK_ipd , WCLK ); buf (WCSNeg_ipd , WCSNeg ); buf (WENNeg_ipd , WENNeg ); buf (WDDR_ipd , WDDR ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (Q19, Q19_Pass , 1); nmos (Q18, Q18_Pass , 1); nmos (Q17, Q17_Pass , 1); nmos (Q16, Q16_Pass , 1); nmos (Q15, Q15_Pass , 1); nmos (Q14, Q14_Pass , 1); nmos (Q13, Q13_Pass , 1); nmos (Q12, Q12_Pass , 1); nmos (Q11, Q11_Pass , 1); nmos (Q10, Q10_Pass , 1); nmos (Q9 , Q9_Pass , 1); nmos (Q8 , Q8_Pass , 1); nmos (Q7 , Q7_Pass , 1); nmos (Q6 , Q6_Pass , 1); nmos (Q5 , Q5_Pass , 1); nmos (Q4 , Q4_Pass , 1); nmos (Q3 , Q3_Pass , 1); nmos (Q2 , Q2_Pass , 1); nmos (Q1 , Q1_Pass , 1); nmos (Q0 , Q0_Pass , 1); nmos (EFNeg, EFNeg_zd, 1); nmos (PAENeg, PAENeg_zd, 1); nmos (PAFNeg, PAFNeg_zd, 1); nmos (FFNeg, FFNeg_zd, 1); nmos (ERCLK, ERCLK_zd, 1); nmos (SDO, SDO_zd, 1); nmos (ERENNeg, ERENNeg_zd, 1); // Needed for TimingChecks // VHDL CheckEnable Equivalent wire PFMsyncR; assign PFMsyncR = (PFM_mode == sync) && RCLK; wire PFMsyncW; assign PFMsyncW = (PFM_mode == sync) && WCLK; wire PFMasyncR; assign PFMasyncR = (PFM_mode == async) && RCLK; wire PFMasyncW; assign PFMasyncW = (PFM_mode == async) && WCLK; wire D_WCLK_check_pos; assign D_WCLK_check_pos = ~WENNeg && ~WCSNeg; // Based on generic FIFOnumber fifo 1 and 3 will work wire fifoworks; assign fifoworks = ((MD == 1'b1) || ((MD == 1'b0) && ((FIFOnumber == 0) || (FIFOnumber == 2)))); wire D_WCLK_check_neg; assign D_WCLK_check_neg = ~WENNeg && ~WCSNeg && (mode_wr == DDR) && fifoworks; wire RENNeg_RCLK_check; assign RENNeg_RCLK_check = ~RENNeg && ~RCSNeg && fifoworks; wire WENNeg_WCLK_check; assign WENNeg_WCLK_check = ~WENNeg && ~WCSNeg && fifoworks; wire SWENNeg_SCLK_check; assign SWENNeg_SCLK_check = ~SWENNeg && fifoworks; wire SRENNeg_SCLK_check; assign SRENNeg_SCLK_check = ~SRENNeg && fifoworks; wire RCLK1_period_check; assign RCLK1_period_check = ((mode_rd == SDR) && mreset) && fifoworks; wire WCLK1_period_check; assign WCLK1_period_check = ((mode_wr == SDR) && mreset) && fifoworks; wire RCLK2_period_check; assign RCLK2_period_check = ((mode_rd == DDR) && mreset) && fifoworks; wire WCLK2_period_check; assign WCLK2_period_check = ((mode_wr == DDR) && mreset)&& fifoworks; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_RCLK_Q0 = 1;//tA, tASO, tRCSLZ, tRCSHZ specparam tpd_OENeg_Q0 = 1;//tOLZ, tOHZ, tOE specparam tpd_PDNeg_Q0 = 1;//tPDLZ, tPDHZ specparam tpd_MRSNeg_EFNeg = 1;//tRSF specparam tpd_WCLK_FFNeg = 1;//tWFF specparam tpd_RCLK_EFNeg = 1;//tREF specparam tpd_WCLK_PAFNeg = 1;//tPAFS specparam tpd_RCLK_PAENeg = 1;//tPAES specparam tpd_RCLK_ERCLK = 1;//tERCLK specparam tpd_RCLK_ERENNeg = 1;//tCLKEN //tsetup values specparam tsetup_D0_WCLK = 1;//tDS specparam tsetup_RENNeg_RCLK = 1;//tENS edge/ specparam tsetup_WCSNeg_WCLK = 1;//tWCSS edge/ specparam tsetup_SI_SCLK = 1;//tSDS / specparam tsetup_SWENNeg_SCLK = 1;//tSENS / specparam tsetup_RENNeg_MRSNeg = 1;//tRSS edge\ specparam tsetup_HSTL_MRSNeg = 1;//tHRSS edge\ //thold values specparam thold_D0_WCLK = 1;//tDH specparam thold_RENNeg_RCLK = 1;//tENH edge / specparam thold_WCSNeg_WCLK = 1;//tWCSH edge / specparam thold_SI_SCLK = 1;//tSDH edge / specparam thold_SWENNeg_SCLK = 1;//tSENH edge / specparam thold_PDNeg_RENNeg = 1;// //tpw values specparam tpw_MRSNeg_negedge = 1; //tRS specparam tpw_PDNeg_negedge = 1; //tRS specparam tpw_RCLK1_negedge = 1; //tCLKL1 specparam tpw_RCLK1_posedge = 1; //tCLKH1 specparam tpw_WCLK1_negedge = 1; //tCLKL1 specparam tpw_WCLK1_posedge = 1; //tCLKH1 specparam tpw_RCLK2_negedge = 1; //tCLKL2 specparam tpw_RCLK2_posedge = 1; //tCLKH2 specparam tpw_WCLK2_negedge = 1; //tCLKL2 specparam tpw_WCLK2_posedge = 1; //tCLKH2 specparam tpw_SCLK_negedge = 1; //tSCKL specparam tpw_SCLK_posedge = 1; //tSCKH //period values specparam tperiod_RCLK1_posedge = 1; //tCLK1 specparam tperiod_WCLK1_posedge = 1; //tCLK1 specparam tperiod_RCLK2_posedge = 1; //tCLK2 specparam tperiod_WCLK2_posedge = 1; //tCLK2 specparam tperiod_SCLK_posedge = 1; //tSCLK //trecovery values specparam trecovery_RENNeg_MRSNeg = 1; //tRSR //tdevice values: values for internal delays specparam tdevice_SKEW1 = 3.5; specparam tdevice_SKEW2 = 3.5; specparam tdevice_SKEW3 = 4; /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// // Data ouptut paths if (FROMRCLK) ( RCLK => Q0 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q1 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q2 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q3 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q4 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q5 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q6 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q7 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q8 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q9 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q10 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q11 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q12 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q13 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q14 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q15 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q16 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q17 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q18 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q19 ) = tpd_RCLK_Q0; if (FROMOE) ( OENeg => Q0 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q1 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q2 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q3 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q4 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q5 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q6 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q7 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q8 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q9 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q10 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q11 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q12 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q13 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q14 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q15 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q16 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q17 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q18 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q19 ) = tpd_OENeg_Q0; if (~MRSNeg) ( MRSNeg => Q0 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q1 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q2 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q3 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q4 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q5 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q6 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q7 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q8 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q9 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q10 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q11 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q12 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q13 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q14 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q15 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q16 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q17 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q18 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q19 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q0 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q1 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q2 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q3 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q4 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q5 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q6 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q7 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q8 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q9 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q10 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q11 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q12 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q13 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q14 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q15 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q16 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q17 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q18 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q19 ) = tpd_MRSNeg_EFNeg; if (FROMPD) ( PDNeg => Q0 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q1 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q2 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q3 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q4 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q5 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q6 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q7 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q8 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q9 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q10 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q11 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q12 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q13 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q14 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q15 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q16 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q17 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q18 ) = tpd_PDNeg_Q0; if (FROMPD) ( PDNeg => Q19 ) = tpd_PDNeg_Q0; if (RCLK) ( RCLK => EFNeg ) = tpd_RCLK_EFNeg; if (WCLK) ( WCLK => FFNeg ) = tpd_WCLK_FFNeg; if (PFMsyncR) ( RCLK => PAENeg ) = tpd_RCLK_PAENeg; if (PFMasyncR) ( RCLK => PAENeg ) = tpd_RCLK_PAENeg; if (PFMasyncW) ( WCLK => PAENeg ) = tpd_RCLK_PAENeg; if (PFMsyncW) ( WCLK => PAFNeg ) = tpd_WCLK_PAFNeg; if (PFMasyncW) ( WCLK => PAFNeg ) = tpd_WCLK_PAFNeg; if (PFMasyncR) ( RCLK => PAFNeg ) = tpd_WCLK_PAFNeg; if (~MRSNeg) ( MRSNeg => EFNeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => PAENeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => PAFNeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => FFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => EFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => PAENeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => PAFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => FFNeg ) = tpd_MRSNeg_EFNeg; if (PDNeg) ( RCLK => ERCLK ) = tpd_RCLK_ERCLK; if (~PDNeg) ( PDNeg => ERCLK ) = tpd_RCLK_ERCLK; ( SCLK => SDO ) = tpd_RCLK_Q0; if (PDNeg) ( RCLK => ERENNeg ) = tpd_RCLK_ERENNeg; if (~PDNeg) ( PDNeg => ERENNeg ) = tpd_RCLK_ERENNeg; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// $setup ( D0 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D1 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D2 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D3 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D4 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D5 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D6 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D7 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D8 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D9 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D10 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D11 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D12 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D13 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D14 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D15 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D16 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D17 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D18 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D19 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D0 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D1 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D2 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D3 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D4 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D5 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D6 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D7 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D8 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D9 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D10 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D11 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D12 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D13 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D14 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D15 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D16 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D17 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D18 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D19 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( RENNeg , posedge RCLK &&& RENNeg_RCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( WENNeg , posedge WCLK &&& WENNeg_WCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( RCSNeg , posedge RCLK &&& RENNeg_RCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( WCSNeg , posedge WCLK &&& WENNeg_WCLK_check, tsetup_WCSNeg_WCLK,Viol); $setup ( SI , posedge SCLK &&& fifoworks, tsetup_SI_SCLK,Viol); $setup ( SWENNeg , posedge SCLK &&& SWENNeg_SCLK_check, tsetup_SWENNeg_SCLK,Viol); $setup ( SRENNeg , posedge SCLK &&& SRENNeg_SCLK_check, tsetup_SWENNeg_SCLK,Viol); $setup ( RENNeg , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( WENNeg , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( SWENNeg , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( SRENNeg , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( FWFT , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( FSEL0 , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( FSEL1 , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( MD , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( OW , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( IW , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( WDDR , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( RDDR , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( PFM , negedge MRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( IOSEL , negedge MRSNeg &&& fifoworks, tsetup_HSTL_MRSNeg,Viol); $setup ( RENNeg , negedge PRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( WENNeg , negedge PRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( SWENNeg , negedge PRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $setup ( SRENNeg , negedge PRSNeg &&& fifoworks, tsetup_RENNeg_MRSNeg,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D0, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D1, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D2, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D3, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D4, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D5, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D6, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D7, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D8, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D9, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D10, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D11, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D12, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D13, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D14, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D15, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D16, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D17, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D18, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D19, thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D0, thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D1 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D2 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D3 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D4 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D5 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D6 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D7 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D8 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D9 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D10 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D11 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D12 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D13 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D14 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D15 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D16 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D17 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D18 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D19 , thold_D0_WCLK,Viol); $hold ( posedge RCLK &&& RENNeg_RCLK_check, RENNeg, thold_RENNeg_RCLK,Viol); $hold ( posedge WCLK &&& WENNeg_WCLK_check, WENNeg, thold_RENNeg_RCLK,Viol); $hold ( posedge RCLK &&& RENNeg_RCLK_check, RCSNeg , thold_RENNeg_RCLK,Viol); $hold ( posedge WCLK &&& WENNeg_WCLK_check, WCSNeg , thold_WCSNeg_WCLK,Viol); $hold ( posedge SCLK &&& fifoworks, SI , thold_SI_SCLK,Viol); $hold ( posedge SCLK &&& SWENNeg_SCLK_check, SWENNeg , thold_SWENNeg_SCLK,Viol); $hold ( posedge SCLK &&& SRENNeg_SCLK_check, SRENNeg , thold_SWENNeg_SCLK,Viol); $hold ( posedge MRSNeg &&& fifoworks, RENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge MRSNeg &&& fifoworks, WENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge PDNeg &&& fifoworks, RENNeg , thold_PDNeg_RENNeg,Viol); $hold ( posedge PRSNeg &&& fifoworks, RENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge PRSNeg &&& fifoworks, WENNeg , trecovery_RENNeg_MRSNeg,Viol); $width (negedge MRSNeg &&& fifoworks, tpw_MRSNeg_negedge); $width (negedge PRSNeg &&& fifoworks, tpw_MRSNeg_negedge); $width (posedge RCLK &&& RCLK1_period_check, tpw_RCLK1_posedge); $width (negedge RCLK &&& RCLK1_period_check, tpw_RCLK1_negedge); $width (posedge WCLK &&& WCLK1_period_check, tpw_WCLK1_posedge); $width (negedge WCLK &&& WCLK1_period_check, tpw_WCLK1_negedge); $width (posedge RCLK &&& RCLK2_period_check, tpw_RCLK2_posedge); $width (negedge RCLK &&& RCLK2_period_check, tpw_RCLK2_negedge); $width (posedge WCLK &&& WCLK2_period_check, tpw_WCLK2_posedge); $width (negedge WCLK &&& WCLK2_period_check, tpw_WCLK2_negedge); $width (posedge SCLK &&& fifoworks, tpw_SCLK_posedge); $width (negedge SCLK &&& fifoworks, tpw_SCLK_negedge); $width (negedge PDNeg, tpw_PDNeg_negedge); $period(posedge RCLK &&& RCLK1_period_check, tperiod_RCLK1_posedge); $period(posedge WCLK &&& WCLK1_period_check, tperiod_WCLK1_posedge); $period(posedge RCLK &&& RCLK2_period_check, tperiod_RCLK2_posedge); $period(posedge WCLK &&& WCLK2_period_check, tperiod_WCLK2_posedge); $period(posedge SCLK &&& fifoworks, tperiod_SCLK_posedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// initial begin memory_model = normal; mode_wr = SDR; mode_rd = SDR; in_mode = SDR10; out_mode = SDR10; device_mode = DUAL; PFM_mode = sync; TotalLoc = MemorySize; TotalLoc1 = MemorySize; offsetps[0] = 8'd7; offsetps[1] = 8'd127; offsetps[2] = 8'd63; offsetps[3] = 8'd255; end always @(PDNeg) begin if ((~PDNeg) && (fifoworks)) begin if ((count_rcycle >= 4) && (count_wcycle >= 4)) begin if ((MD == 1'b0) && (OW == 1'b1)) QOut_zd[19:0] = 20'bz; else QOut_zd[9:0] = 10'bz; ERENNeg_zd = 1'bz; ERCLK_zd = 1'bz; FROMPD = 1'b1; FROMPD <= #1 1'b0; end else begin $display ("4 read and write cycles "); $display ("must pass before asserting PDNeg"); end end else if ((PDNeg) && (fifoworks)) QOut_zd = Qreg; end always @(posedge RENNeg) begin if (fifoworks) if (RENNeg) count_rcycle = 0; end always @(posedge WENNeg) begin if (fifoworks) if (WENNeg) count_wcycle = 0; end always @(posedge WCLK) begin if (fifoworks) if ((WENNeg) && (WCLK)) count_wcycle = count_wcycle+1; end always @(posedge RCLK) begin if (fifoworks) if ((RENNeg) && (RCLK)) count_rcycle = count_rcycle+1; end always @(negedge MRSNeg) begin if (fifoworks) master_reset; else QOut_Pass = 40'bZ; end always @(negedge PRSNeg) begin if (fifoworks) partial_reset; end always @(WCLK) // for violation registering begin if (fifoworks) #10 WCLK_1 <= WCLK; end always @(WCLK_1) begin if ((mreset == 1'b1) && (PDNeg == 1'b1)) begin if ((((FFNeg_zd == 1'b1) && (fwftmod == 1'b0)) || ((FFNeg_zd == 1'b0 && fwftmod == 1'b1))) || (bm_Incnt != 1'b0)) begin case (in_mode) DDR20 : begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 1'b0)) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt = bm_Incnt + 1; if ((count==0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[39:30] = Data2; outtmp[29:20] = Data1; fwcnt = 1; end end else if (bm_Incnt == 1'b1) begin write_input; memA[wrptr_next + TotalLoc/2] = Data2; memB[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt = 0; if ((fwcnt == 1) && (fwftmod == 1'b1)&& (fw_done==1'b0)) begin outtmp[19:10] = Data2; outtmp[9:0] = Data1; do_fw = 1'b1; fwcnt = 0; end end end SDR20 : begin if (out_mode == DDR20) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 1'b0) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt = bm_Incnt + 1; if ((count ==0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[39:30] = Data2; outtmp[29:20] = Data1; do_fw = 1'b1; fwcnt = 1; end end else if (bm_Incnt == 1) begin write_input; memA[wrptr_next + TotalLoc/2] = Data2; memB[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt = 0; if ((fwcnt == 1) && (fwftmod == 1'b1)) begin outtmp[19:10] = Data2; outtmp[9:0] = Data1; fwcnt = 0; end end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; last_done = write; if ((count == 0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[19:10] = Data2; outtmp[9:0] = Data1; do_fw = 1'b1; end end end end DDR10 : begin if (out_mode == DDR20) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; if ((count == 0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[39:30] = Data1; fwcnt = 1; end end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; if ((fwcnt == 1) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[29:20] = Data1; fwcnt = 2; do_fw = 1'b1; end end else if (bm_Incnt == 2) begin write_input; memA[wrptr_next + TotalLoc/2] = Data1; bm_Incnt = bm_Incnt + 1; if ((fwcnt == 2) && (fwftmod == 1'b1)) begin outtmp[19:10] = Data1; fwcnt = 3; end end else if (bm_Incnt == 3) begin write_input; memB[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt=0; if ((fwcnt == 3) && (fwftmod == 1'b1)) begin outtmp[9:0] = Data1; fwcnt = 0; end end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; if ((count == 0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[19:10] = Data1; fwcnt = 1; end end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=0; last_done = write; if ((fwcnt == 1) && (fwftmod == 1'b1)&& (fw_done==1'b0)) begin outtmp[9:0] = Data1; fwcnt = 0; do_fw = 1'b1; end end end end SDR10 : begin if (out_mode == DDR20) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; if ((count == 0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin outtmp[39:30] = Data1; do_fw = 1'b1; fwcnt = 1; end end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; if ((fwcnt == 1) && (fwftmod == 1'b1)) begin outtmp[29:20] = Data1; fwcnt = 2; end end else if (bm_Incnt == 2) begin write_input; memA[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; if ((fwcnt == 2) && (fwftmod == 1'b1)) begin outtmp[19:10] = Data1; fwcnt = 3; end end else if (bm_Incnt == 3) begin write_input; memB[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt = 0; if ((fwcnt == 3) && (fwftmod == 1'b1)) begin outtmp[9:0] = Data1; fwcnt = 0; end end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; last_done = write; bm_Incnt=bm_Incnt + 1; if ((count == 0) && (fwftmod == 1'b1) && (fw_done==1'b0)) begin if (out_mode == SDR10) outtmp[9:0] = Data1; else outtmp[19:10] = Data1; do_fw = 1'b1; fwcnt = 1; end end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; if (out_mode == SDR10) wrote_in = 1'b1; last_done = write; bm_Incnt=0; if ((fwcnt == 1) && (fwftmod == 1'b1)&& (fw_done==1'b0)) begin outtmp[9:0] = Data1; fwcnt = 0; if (out_mode == SDR10) do_fw = 1'b1; end end end end endcase end if (wrote_in == 1'b1) begin wrote_in = 1'b0; if (((fwftmod == 1'b1) && (FFNeg_zd == 1'b0)) || // not full ((fwftmod == 1'b0) && (FFNeg_zd == 1'b1))) //write pointer begin if ((wrptr < TotalLoc1 - 1) && ~((in_mode==SDR10) && (out_mode == SDR10))) wrptr = wrptr + 1; else if ((wrptr >= TotalLoc1 - 1) && ~((in_mode==SDR10) && (out_mode == SDR10))) wrptr = 0; else if ( (in_mode==SDR10) && (out_mode==SDR10) && (wrptr < TotalLoc1/2 - 1) && (bm_Incnt == 0)) wrptr = wrptr + 1; else if ( (in_mode==SDR10) && (out_mode==SDR10) && (wrptr >= TotalLoc1/2 - 1) && (bm_Incnt == 0)) wrptr = 0; //counter count = count + 1; if (count == TotalLoc1) begin if (fwftmod == 1'b1) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; end //PAF sync updating if (pafoff <= count) begin PAFNeg_dly = 1'b0; delayed_paf = 1'b1; end else PAFNeg_dly = 1'b1; if (PFM_mode == sync) // flags for EFNeg and PAENeg updating if (((count == 1) && (fwftmod == 1'b0)) || (count == paeoff + 1)) wr_upd_flg = 1'b1; else wr_upd_flg = 1'b0; else if (count == paeoff + 1) PAENeg_zd = 1'b1; else if ((count == 1) && (fwftmod == 1'b0)) wr_upd_flg = 1'b1; else wr_upd_flg = 1'b0; end end if (WCLK_1) begin //FFNeg updating when reading active if (mode_rd == DDR) begin if ((minskew2RW == 1'b0) && (flag_FF == 1'b1)) if (Fflagcnt < 1) Fflagcnt = Fflagcnt + 1; else begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end else if ((minskew2RW == 1'b1) && (flag_FF == 1'b1)) begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end end else begin if ((minskew1RW == 1'b0) && (flag_FF == 1'b1)) if (Fflagcnt < 1) Fflagcnt = Fflagcnt + 1; else begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end else if ((minskew1RW==1'b1) && (flag_FF == 1'b1)) begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end end //PAFNeg updating when write active if (((write_clk_paf == 2) && (delayed_paf == 1'b1) && (PFM_mode == sync)) || ((delayed_paf == 1'b1) && (PFM_mode == async))) begin PAFNeg_zd = PAFNeg_dly; write_clk_paf = 1'b0; delayed_paf = 1'b0; end else if (delayed_paf == 1'b1) write_clk_paf = write_clk_paf + 1; //PAFNeg updating when read active if ((minskew3RW == 1'b0) && (flag_PAF == 1'b1)) if (PAFflagcnt < 1) PAFflagcnt = PAFflagcnt + 1; else begin PAFNeg_zd = 1'b1; PAFflagcnt = 0; flag_PAF = 1'b0; end else if ((minskew3RW==1'b1) && (flag_PAF == 1'b1)) begin PAFNeg_zd = 1'b1; PAFflagcnt = 0; flag_PAF = 1'b0; end // FFNeg updating when read active if ((rd_upd_flg==1'b1) && (count == TotalLoc1 - 1)) begin pass_FF = 1'b1; rd_upd_flg = 1'b0; end if ((last_done == read) && (pass_FF==1'b1)) begin flag_FF = 1'b1; pass_FF = 1'b0; end if ((rd_upd_flg==1'b1) && (count == pafoff - 1)) begin pass_PAF = 1'b1; rd_upd_flg = 1'b0; end if ((last_done == read) && (pass_PAF==1'b1)) begin flag_PAF = 1'b1; pass_PAF = 1'b0; end end end end always @(RCLK) begin if (fifoworks) begin if (RCLK) ERCLK_zd = 1'b1; else if (~RCLK) ERCLK_zd = 1'b0; end end // First Word Fall Through always @(RCLK) begin if (fifoworks) begin if ((fwftmod == 1'b1) && (PDNeg == 1'b1)) if (RCLK) if ((do_fw == 1'b1) && (fwftcnt == 0) && (EFNeg_zd == 1'b1)) begin fwftcnt = fwftcnt + 1; if ((out_mode==SDR10) && (in_mode == SDR10)) begin bm_Outcnt = 1; rdptr_next = 0; end else rdptr = rdptr + 1; fw_done = 1'b1; count = count - 1; end else if ((do_fw == 1'b1) && (fwftcnt == 1)) fwftcnt = fwftcnt + 1; else if ((do_fw == 1'b1) && (fwftcnt == 2)) if (((minskew1WR == 1'b1) && (mode_wr == SDR)) || ((minskew2WR == 1'b1) && (mode_wr == DDR))) begin fwftvar = 1'b1; fwft_eren = 1'b1; EFNeg_zd = 1'b0; fwftcnt = 0; fwftcnt1 = 0; FROMOE = 1'b0; FROMRCLK = 1'b1; outreg = outtmp; do_fw = 1'b0; end else fwftcnt = fwftcnt + 1; else if ((do_fw == 1'b1) && (fwftcnt == 3)) begin fwftvar = 1'b1; fwft_eren = 1'b1; EFNeg_zd = 1'b0; fwftcnt = 0; fwftcnt1 = 0; FROMOE = 1'b0; FROMRCLK = 1'b1; outreg = outtmp; do_fw = 1'b0; end if ((fwftvar == 1'b1) && (mode_rd == DDR)) begin if (out_mode == DDR20) begin if (fwftcnt1 == 0) begin Qreg[19:0] = outreg[39:20]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[19:0] = outreg[19:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else if (out_mode == DDR10) begin if (in_mode == DDR20) begin if (fwftcnt1 == 0) begin Qreg[9:0] = outreg[39:30]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[9:0] = outreg[29:20]; fwftcnt1 = 2; end else if (fwftcnt1 == 2) begin Qreg[9:0] = outreg[19:10]; fwftcnt1 = 3; end else if (fwftcnt1 == 3) begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else begin if (fwftcnt1 == 0) begin Qreg[9:0] = outreg[19:10]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end end end else if ((fwftvar == 1'b1) && (mode_rd == SDR) && (RCLK)) begin if (out_mode == SDR20) begin if (in_mode == DDR20) begin if (fwftcnt1 == 0) begin Qreg[19:0] = outreg[39:20]; fwftcnt1 = 1; end else begin Qreg[19:0] = outreg[19:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else begin Qreg[19:0] = outreg[19:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else if (out_mode == SDR10) begin if (in_mode == DDR20) begin if (fwftcnt1 == 0) begin Qreg[9:0] = outreg[39:30]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[9:0] = outreg[29:20]; fwftcnt1 = 2; end else if (fwftcnt1 == 2) begin Qreg[9:0] = outreg[19:10]; fwftcnt1 = 3; end else if (fwftcnt1 == 3) begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else if (in_mode == SDR10) begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end else begin if (fwftcnt1 == 0) begin Qreg[9:0] = outreg[19:10]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end end end end end always @(RCLK) begin if ((fifoworks) && (mreset == 1'b1)) begin // empty fifo in fwft mode if ((RCLK) && (count == 0) && (EFNeg_zd == 1'b0) && (fwftmod == 1'b1) && (update_EFNeg_fwft == 1'b1) &&(RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin EFNeg_zd = 1'b1; update_EFNeg_fwft = 1'b0; end if (( ( ((EFNeg_zd==1'b1) && (fwftmod==1'b0)) || ((EFNeg_zd==1'b0) && (fwftmod==1'b1)) ) && (RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) ) || ((fwft_eren == 1'b1) && (fwftmod == 1'b1) && (RCSNeg == 1'b1))) begin ERENNeg_zd = 1'b0; fwft_eren = 1'b0; end else if (((RCLK) && (last_done == read)) || ((RCLK) && (RENNeg == 1'b1)) || ((RCLK) && (RCSNeg ==1'b1))) ERENNeg_zd = 1'b1; // at the end of the reading cycle // or if RENNeg inactive // read from fifo if ( (count > 0) && (((EFNeg_zd == 1'b1) && (fwftmod==1'b0)) || ((EFNeg_zd == 1'b0) && (fwftmod==1'b1))) || (bm_Outcnt != 0) ) begin case (out_mode) DDR20: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next + TotalLoc/2); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end SDR20: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) ) begin if (in_mode == DDR20) begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next + TotalLoc/2); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end else begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end end end DDR10: begin if (in_mode == DDR20) begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[19:10]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; read_out = 1'b1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end else begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[19:10]; read_out = 1'b1; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =0; last_done = read; end end end SDR10: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin if (in_mode == DDR20) begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[19:10]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =0; read_out = 1'b1; last_done = read; end end else begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[19:10]; if (in_mode == SDR10) begin read_out = 1'b1; last_done = read; end rdptr_next = rdptr; bm_Outcnt = bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =0; read_out = 1'b1; last_done = read; end end end end endcase end // flag ctrl if (read_out == 1'b1) begin read_out = 1'b0; if (((fwftmod==1'b1) && (EFNeg_zd == 1'b0)) || ((fwftmod == 1'b0) && (EFNeg_zd == 1'b1))) //not empty begin //read pointer if ((rdptr < TotalLoc1 - 1) && ~((in_mode==SDR10) && (out_mode == SDR10))) rdptr = rdptr + 1; else if ((rdptr >= TotalLoc1 - 1) && ~((in_mode==SDR10) && (out_mode == SDR10))) rdptr = 0; else if ( (in_mode==SDR10) && (out_mode==SDR10) && (rdptr < TotalLoc1/2 - 1) && (bm_Outcnt == 0)) rdptr = rdptr + 1; else if ( (in_mode==SDR10) && (out_mode==SDR10) && (rdptr >= TotalLoc1/2 - 1) && (bm_Outcnt == 0)) rdptr = 0; //counter count = count - 1; //update PAENeg, delayed if (count == 0) fw_done = 1'b0; if (count <= paeoff) begin PAENeg_dly = 1'b0; delayed_pae = 1'b1; end else PAENeg_dly = 1'b1; //update EFNeg, for idt standard mode only if ((count == 0) && (fwftmod == 1'b0)) EFNeg_zd = 1'b0; //update EFNeg, for fwft mode only if ((count == 0) && (fwftmod == 1'b1)) #1 update_EFNeg_fwft <= 1'b1; if (PFM_mode == sync) begin // for updating PAFNeg and FFNeg if ((count == TotalLoc1 -1) || (count == pafoff - 1)) rd_upd_flg = 1'b1; else rd_upd_flg = 1'b0; end else begin if (count == pafoff - 1) PAFNeg_zd = 1'b1; else if (count == TotalLoc1 -1) rd_upd_flg = 1'b1; else rd_upd_flg = 1'b0; end end end if (RCLK) begin if (mode_wr == DDR) begin if ((minskew2WR==1'b0) && (flag_EF == 1'b1)) begin if (Eflagcnt < 1) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end else if ((minskew2WR==1'b1) && (flag_EF == 1'b1)) begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end else begin if ((minskew1WR==1'b0) && (flag_EF == 1'b1)) begin if (fwftmod==1'b0) begin if (Eflagcnt < 1) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end end else if ((minskew1WR==1'b1) && (flag_EF == 1'b1)) begin if (fwftmod==1'b0) begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end end //PAENeg updating when writing - delayed if (((read_clk_pae == 2) && (delayed_pae == 1'b1) && (PFM_mode == sync)) || ((delayed_pae == 1'b1) &&(PFM_mode==async))) begin PAENeg_zd = PAENeg_dly; read_clk_pae = 0; delayed_pae = 1'b0; end else if (delayed_pae == 1'b1) begin read_clk_pae = read_clk_pae + 1; end //PAENeg updating when write active if ((minskew3WR==1'b0) && (flag_PAE == 1'b1)) begin if (PAEflagcnt < 1) PAEflagcnt = PAEflagcnt + 1; else begin PAENeg_zd = 1'b1; PAEflagcnt = 0; flag_PAE = 1'b0; end end else if ((minskew3WR==1'b1) && (flag_PAE == 1'b1)) begin PAENeg_zd = 1'b1; PAEflagcnt = 0; flag_PAE = 1'b0; end //EFNeg updating when reading active if ((wr_upd_flg == 1'b1) && (count == 1)) begin pass_EF = 1'b1; wr_upd_flg = 1'b0; end if ((last_done == write) && (pass_EF == 1'b1)) begin flag_EF = 1'b1; pass_EF = 1'b0; end //PAENeg updating when write active if ((wr_upd_flg == 1'b1) && (count == paeoff + 1)) begin pass_PAE = 1'b1; wr_upd_flg = 1'b0; end if ((last_done == write) && (pass_PAE == 1'b1)) begin flag_PAE = 1'b1; pass_PAE = 1'b0; end end end end always @(posedge SWENNeg or posedge SRENNeg) begin if ((PDNeg == 1'b1) && (fifoworks)) fs_Incnt = 0; end always @(posedge SCLK) begin if ((mreset == 1'b1) && (~SWENNeg) && (PDNeg == 1'b1) && (fifoworks)) //write to registers write_register; end always @(posedge SCLK) begin if ((mreset == 1'b1) && (~SRENNeg) && (PDNeg == 1'b1)&& (fifoworks)) //read from registers read_register; end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(QOut_zd) begin : OutputGen if ((QOut_zd[0] !== 1'bz) && (fifoworks)) QOut_Pass = QOut_zd; end always @(QOut_zd) begin if ((QOut_zd[0] === 1'bz) && (fifoworks)) begin disable OutputGen; FROMOE = 1'b1; QOut_Pass = QOut_zd; end end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(negedge OENeg) begin if (fifoworks) begin OENeg_event = $time; FROMOE = 1'b0; if (time_flag_for_OE == 1'b1) begin if ((RCLK_t - (OENeg_event - tRCLKposedge)) >= OE_t) begin FROMOE = 1'b0; FROMRCLK = 1'b1; if ((OW == 1'b1) && (MD == 1'b0)) QOut_zd = Qreg; else begin QOut_zd[9:0] = Qreg[9:0]; QOut_zd[19:10] = 10'bZ; end end else begin FROMOE = 1'b1; FROMRCLK = 1'b0; if ((OW == 1'b1) && (MD == 1'b0)) QOut_zd = Qreg; else begin QOut_zd[9:0] = Qreg[9:0]; QOut_zd[19:10] = 10'bZ; end end end else begin FROMOE = 1'b1; FROMRCLK = 1'b0; if ((OW == 1'b1) && (MD == 1'b0)) QOut_zd = Qreg; else begin QOut_zd[9:0] = Qreg[9:0]; QOut_zd[19:10] = 10'bZ; end end end end ////////////////////////////////////////////////////////////////////////// // Clock active edges ////////////////////////////////////////////////////////////////////////// always @(posedge RCLK) begin if (fifoworks) begin tRCLKposedge = $time; if ((tRCLKposedge - tWCLKposedge) > tSKEW1) minskew1WR = 1'b1; else minskew1WR = 1'b0; if ((tRCLKposedge - tWCLKnegedge) > tSKEW2) minskew2WR = 1'b1; else minskew2WR = 1'b0; if ((tRCLKposedge - tWCLKposedge) > tSKEW3) minskew3WR = 1'b1; else minskew3WR = 1'b0; end end always @(negedge RCLK) begin if (fifoworks) tRCLKnegedge = $time; end always @(posedge WCLK) begin if (fifoworks) begin tWCLKposedge = $time; if ((tWCLKposedge - tRCLKposedge) > tSKEW1) minskew1RW = 1'b1; else minskew1RW = 1'b0; if ((tWCLKposedge - tRCLKnegedge) > tSKEW2) minskew2RW = 1'b1; else minskew2RW = 1'b0; if ((tWCLKposedge - tRCLKposedge) > tSKEW3) minskew3RW = 1'b1; else minskew3RW = 1'b0; end end always @(negedge WCLK) begin if (fifoworks) tWCLKnegedge = $time; end //Output Disable Control always @(posedge OENeg or posedge RCSNeg) begin if (fifoworks) QOut_zd = 40'bz; end always @(Qreg) begin if ((fifoworks) && (OENeg == 1'b0)) if ((OW == 1'b1) && (MD == 1'b0)) QOut_zd = Qreg; else begin QOut_zd[9:0] = Qreg[9:0]; QOut_zd[19:10] = 10'bZ; end end //Master Reset always @(negedge MRSNeg) begin if ((~MRSNeg) && (fifoworks)) begin QOut_zd = 40'b0; end end reg BuffInOE, BuffInRCLK; reg BuffInSkew1, BuffInSkew2, BuffInSkew3; wire BuffOutOE, BuffOutRCLK; wire BuffOutSkew1, BuffOutSkew2, BuffOutSkew3; BUFFER BUFOE (BuffOutOE , BuffInOE); BUFFER BUFRCLK (BuffOutRCLK , BuffInRCLK); BUFFER SKEW1 (BuffOutSkew1, BuffInSkew1); BUFFER SKEW2 (BuffOutSkew2, BuffInSkew2); BUFFER SKEW3 (BuffOutSkew3, BuffInSkew3); initial begin BuffInSkew1 = 1'b1; BuffInSkew2 = 1'b1; BuffInSkew3 = 1'b1; BuffInOE = 1'b1; BuffInRCLK = 1'b1; end always @(posedge BuffOutOE) begin OE_t = $time; end always @(posedge BuffOutRCLK) begin RCLK_t = $time; end always @(posedge BuffOutSkew1) begin tSKEW1 = $time; end always @(posedge BuffOutSkew2) begin tSKEW2 = $time; end always @(posedge BuffOutSkew3) begin tSKEW3 = $time; end task write_input; begin if (~Viol) begin if (DIn[19] !== 1'bZ) Data2 = DIn[19:10]; if (DIn[9] !== 1'bZ) Data1 = DIn[9:0]; end else begin Data2 = -1; Data1 = -1; Viol = 1'b0; end end endtask task generate_output; input pointer; integer pointer; begin if (RCLK == 1'b1) begin time_flag_for_OE = 1'b1; time_flag_for_OE <= #RCLK_t 1'b0; if (OENeg == 1'b0) begin FROMRCLK = 1'b1; FROMOE = 1'b0; end else begin FROMRCLK = 1'b0; FROMOE = 1'b1; end end if (memA[pointer] >= 0) Qreg_tmp[19:10] = memA[pointer]; else Qreg_tmp[19:10] = 10'bX; if (memB[pointer] >= 0) Qreg_tmp[9:0] = memB[pointer]; else Qreg_tmp[9:0] = 10'bX; end endtask task master_reset; begin mreset = 1'b0; mreset <= #200000 1'b1; fwftcnt = 1'b0; PAENeg_zd = 1'b0; PAFNeg_zd = 1'b1; PAENeg_dly = 1'b0; PAFNeg_dly = 1'b1; TotalLoc1 = TotalLoc; rdptr = 1'b0; wrptr = 1'b0; count = 1'b0; fw_done = 1'b0; last_done = none; count_rcycle = 0; count_wcycle = 0; Viol = 1'b0; // configuration section if (FWFT) begin fwftmod = 1'b1; // fwft mode EFNeg_zd = 1'b1; FFNeg_zd = 1'b0; end else begin fwftmod = 1'b0; //idt standard mode EFNeg_zd = 1'b0; FFNeg_zd = 1'b1; end if (~MD) device_mode = DUAL; else if (MD) device_mode = QUAD; if (PFM) PFM_mode = sync; else if (~PFM) PFM_mode = async; //bus matching byte order bm_Incnt = 1'b0; bm_Outcnt = 1'b0; if (~WDDR) mode_wr = SDR; else mode_wr = DDR; if (~RDDR) mode_rd = SDR; else mode_rd = DDR; opireg[1] = FSEL1; opireg[0] = FSEL0; opi = opireg; paeoff = offsetps[opi]; if ((device_mode == QUAD) || ((device_mode == DUAL) && (IW == 1'b0) && (OW == 1'b0) )) begin if (mode_wr == SDR) in_mode = SDR10; else in_mode = DDR10; if (mode_rd == SDR) out_mode = SDR10; else out_mode = DDR10; end else if ((device_mode == DUAL) && (IW == 1'b1) && (OW == 1'b0) ) begin if (mode_wr == SDR) in_mode = SDR20; else in_mode = DDR20; if (mode_rd == SDR) out_mode = SDR10; else out_mode = DDR10; end else if ((device_mode == DUAL) && (IW == 1'b0) && (OW == 1'b1) ) begin if (mode_wr == SDR) in_mode = SDR10; else in_mode = DDR10; if (mode_rd == SDR) out_mode = SDR20; else out_mode = DDR20; end else if ((device_mode == DUAL) && (IW == 1'b1) && (OW == 1'b1) ) begin if (mode_wr == SDR) in_mode = SDR20; else in_mode = DDR20; if (mode_rd == SDR) out_mode = SDR20; else out_mode = DDR20; end if ((in_mode == SDR10) && (out_mode == SDR10)) begin memory_model = normal; TotalLoc1 = TotalLoc; end else if ( ((in_mode == DDR10) && (out_mode != DDR20)) || ((in_mode == SDR10) && (out_mode != DDR20)) || ((in_mode != DDR20) && (out_mode == SDR10)) || ((in_mode != DDR20) && (out_mode == SDR20)) || ((in_mode == SDR20) && (out_mode != DDR20)) ) begin memory_model = mapped; TotalLoc1 = TotalLoc/2; paeoff = (paeoff - 1)/2; end else begin memory_model = mapped; TotalLoc1 = TotalLoc/4; paeoff = (paeoff - 1)/4; end pafoff = TotalLoc1 - paeoff; outreg = 40'b0; Qreg = 40'b0; end endtask task partial_reset; begin mreset = 1'b0; mreset <= #200000 1'b1; fwftcnt = 1'b0; PAENeg_zd = 1'b0; PAFNeg_zd = 1'b1; PAENeg_dly = 1'b0; PAFNeg_dly = 1'b1; rdptr = 1'b0; wrptr = 1'b0; count = 1'b0; last_done = none; fw_done = 1'b0; last_done = none; count_rcycle = 0; count_wcycle = 0; Viol = 1'b0; if (fwftmod == 1'b1) begin EFNeg_zd = 1'b1; FFNeg_zd = 1'b0; end else begin EFNeg_zd = 1'b0; FFNeg_zd = 1'b1; end Qreg = 40'b0; bm_Incnt = 1'b0; bm_Outcnt= 1'b0; end endtask task write_register; begin if (device_mode == QUAD) begin tmp_ser_in[118:0] = tmp_ser_in[119:1]; tmp_ser_in[119] = SI; if (FIFOnumber == 0) begin pafoff= tmp_ser_in[119:105]; paeoff= tmp_ser_in[104:90]; end else if (FIFOnumber == 1) begin pafoff= tmp_ser_in[89:75]; paeoff= tmp_ser_in[74:60]; end else if (FIFOnumber == 2) begin pafoff= tmp_ser_in[59:45]; paeoff= tmp_ser_in[44:30]; end else begin pafoff= tmp_ser_in[29:15]; paeoff= tmp_ser_in[14:0]; end end else if ((device_mode == DUAL) && (IW == 1'b0) && (OW == 1'b0)) begin tmp_ser_in[58:0] = tmp_ser_in[59:1]; tmp_ser_in[59] = SI; if (FIFOnumber == 0) begin pafoff= tmp_ser_in[59:45]; paeoff= tmp_ser_in[44:30]; end else if (FIFOnumber == 2) begin pafoff= tmp_ser_in[29:15]; paeoff= tmp_ser_in[14:0]; end end else if ((device_mode == DUAL) && (IW == 1'b1) && (OW == 1'b1)) begin tmp_ser_in[54:0] = tmp_ser_in[55:1]; tmp_ser_in[55] = SI; if (FIFOnumber == 0) begin pafoff= tmp_ser_in[55:42]; paeoff= tmp_ser_in[41:28]; end else if (FIFOnumber == 2) begin pafoff= tmp_ser_in[27:14]; paeoff= tmp_ser_in[13:0]; end end if ((mode_wr == DDR) || (mode_rd == DDR)) begin if (memory_model == mapped) begin pafoff = pafoff /2; paeoff = paeoff /2; pafoff = TotalLoc1-pafoff; end end else begin if (memory_model == mapped) pafoff = TotalLoc1-pafoff; else pafoff = TotalLoc-pafoff; end end endtask task read_register; begin if (device_mode == QUAD) begin if (fs_Incnt < 120) begin SDO_zd = tmp_ser_in[fs_Incnt]; fs_Incnt=fs_Incnt+1; end if (fs_Incnt >= 119) fs_Incnt=0; end else if ((device_mode == DUAL) && (IW == 1'b0) && (OW == 1'b0)) begin if (fs_Incnt < 60) begin SDO_zd = tmp_ser_in[fs_Incnt]; fs_Incnt=fs_Incnt+1; end if (fs_Incnt >= 59) fs_Incnt=0; end else if ((device_mode == DUAL) && (IW == 1'b1) && (OW == 1'b1)) begin if (fs_Incnt < 56) begin SDO_zd = tmp_ser_in[fs_Incnt]; fs_Incnt=fs_Incnt+1; end if (fs_Incnt >= 55) fs_Incnt=0; end end endtask endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule