/*------------------------------------------------------------------------------ -------------------------------------------------------------------------------- -- File Name: idt72t40118.v -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.freemodelfoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- 1.0 D.Vukicevic 05 Dec 12 initial version -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH MEMORY -- Technology: CMOS -- Part: IDT72T40118 -- -- Description: 128K x 40 High-speed TeraSync DDR/SDR Fifo -- -------------------------------------------------------------------------------- ------------------------------------------------------------------------------*/ ////////////////////////////////////////////////////////////////////////////// // Comments : // For precise simulation results, simulator resolution should // be set to 1ps ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module idt72t40118 ( D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D31, D32, D33, D34, D35, D36, D37, D38, D39, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, BM, EFNeg, ERCLK, ERENNeg, FFNeg, FSEL0, FSEL1, FWFT, HSTL, IW, MARK, MRSNeg, OENeg, OW, PAENeg, PAFNeg, PRSNeg, RCLK, RCSNeg, RENNeg, RSDRNeg, RTNeg, SCLK, SENNeg, SRENNeg, SI, SO, WCLK, WCSNeg, WENNeg, WSDRNeg ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input D0; input D1; input D2; input D3; input D4; input D5; input D6; input D7; input D8; input D9; input D10; input D11; input D12; input D13; input D14; input D15; input D16; input D17; input D18; input D19; input D20; input D21; input D22; input D23; input D24; input D25; input D26; input D27; input D28; input D29; input D30; input D31; input D32; input D33; input D34; input D35; input D36; input D37; input D38; input D39; output Q0; output Q1; output Q2; output Q3; output Q4; output Q5; output Q6; output Q7; output Q8; output Q9; output Q10; output Q11; output Q12; output Q13; output Q14; output Q15; output Q16; output Q17; output Q18; output Q19; output Q20; output Q21; output Q22; output Q23; output Q24; output Q25; output Q26; output Q27; output Q28; output Q29; output Q30; output Q31; output Q32; output Q33; output Q34; output Q35; output Q36; output Q37; output Q38; output Q39; input BM; input FSEL0; input FSEL1; input FWFT; input HSTL; input IW; input MARK; input MRSNeg; input OENeg; input OW; input PRSNeg; input RCLK; input RCSNeg; input RENNeg; input RSDRNeg; input RTNeg; input SCLK; input SENNeg; input SRENNeg; input SI; input WCLK; input WCSNeg; input WENNeg; input WSDRNeg; output EFNeg; output ERCLK; output ERENNeg; output FFNeg; output PAENeg; output PAFNeg; output SO; // interconnect path delay signals wire D0_ipd ; wire D1_ipd ; wire D2_ipd ; wire D3_ipd ; wire D4_ipd ; wire D5_ipd ; wire D6_ipd ; wire D7_ipd ; wire D8_ipd ; wire D9_ipd ; wire D10_ipd ; wire D11_ipd ; wire D12_ipd ; wire D13_ipd ; wire D14_ipd ; wire D15_ipd ; wire D16_ipd ; wire D17_ipd ; wire D18_ipd ; wire D19_ipd ; wire D20_ipd ; wire D21_ipd ; wire D22_ipd ; wire D23_ipd ; wire D24_ipd ; wire D25_ipd ; wire D26_ipd ; wire D27_ipd ; wire D28_ipd ; wire D29_ipd ; wire D30_ipd ; wire D31_ipd ; wire D32_ipd ; wire D33_ipd ; wire D34_ipd ; wire D35_ipd ; wire D36_ipd ; wire D37_ipd ; wire D38_ipd ; wire D39_ipd ; wire [39:0] DIn; assign DIn ={D39_ipd, D38_ipd , D37_ipd , D36_ipd , D35_ipd , D34_ipd , D33_ipd , D32_ipd , D31_ipd , D30_ipd , D29_ipd , D28_ipd , D27_ipd , D26_ipd , D25_ipd , D24_ipd , D23_ipd , D22_ipd , D21_ipd , D20_ipd , D19_ipd , D18_ipd , D17_ipd , D16_ipd , D15_ipd , D14_ipd , D13_ipd , D12_ipd , D11_ipd , D10_ipd , D9_ipd , D8_ipd , D7_ipd , D6_ipd , D5_ipd , D4_ipd , D3_ipd , D2_ipd , D1_ipd , D0_ipd }; wire BM_ipd ; wire FSEL0_ipd ; wire FSEL1_ipd ; wire FWFT_ipd ; wire HSTL_ipd ; wire IW_ipd ; wire MARK_ipd ; wire MRSNeg_ipd ; wire OENeg_ipd ; wire OW_ipd ; wire PRSNeg_ipd ; wire RCLK_ipd ; wire RCSNeg_ipd ; wire RENNeg_ipd ; wire RSDRNeg_ipd ; wire RTNeg_ipd ; wire SCLK_ipd ; wire SENNeg_ipd ; wire SRENNeg_ipd ; wire SI_ipd ; wire WCLK_ipd ; wire WCSNeg_ipd ; wire WENNeg_ipd ; wire WSDRNeg_ipd ; // internal delays reg [39 : 0] QOut_zd; wire Q39_Pass ; wire Q38_Pass ; wire Q37_Pass ; wire Q36_Pass ; wire Q35_Pass ; wire Q34_Pass ; wire Q33_Pass ; wire Q32_Pass ; wire Q31_Pass ; wire Q30_Pass ; wire Q29_Pass ; wire Q28_Pass ; wire Q27_Pass ; wire Q26_Pass ; wire Q25_Pass ; wire Q24_Pass ; wire Q23_Pass ; wire Q22_Pass ; wire Q21_Pass ; wire Q20_Pass ; wire Q19_Pass ; wire Q18_Pass ; wire Q17_Pass ; wire Q16_Pass ; wire Q15_Pass ; wire Q14_Pass ; wire Q13_Pass ; wire Q12_Pass ; wire Q11_Pass ; wire Q10_Pass ; wire Q9_Pass ; wire Q8_Pass ; wire Q7_Pass ; wire Q6_Pass ; wire Q5_Pass ; wire Q4_Pass ; wire Q3_Pass ; wire Q2_Pass ; wire Q1_Pass ; wire Q0_Pass ; reg [39 : 0] QOut_Pass; assign {Q39_Pass, Q38_Pass, Q37_Pass, Q36_Pass, Q35_Pass, Q34_Pass, Q33_Pass, Q32_Pass, Q31_Pass, Q30_Pass, Q29_Pass, Q28_Pass, Q27_Pass, Q26_Pass, Q25_Pass, Q24_Pass, Q23_Pass, Q22_Pass, Q21_Pass, Q20_Pass, Q19_Pass, Q18_Pass, Q17_Pass, Q16_Pass, Q15_Pass, Q14_Pass, Q13_Pass, Q12_Pass, Q11_Pass, Q10_Pass, Q9_Pass, Q8_Pass, Q7_Pass, Q6_Pass, Q5_Pass, Q4_Pass, Q3_Pass, Q2_Pass, Q1_Pass, Q0_Pass } = QOut_Pass; parameter TimingModel = "DefaultTimingModel"; parameter PartID = "idt72t40118"; parameter MemorySize = 131072; parameter MaxData = 1023; parameter HiDBit = 39; integer tSKEW1; integer tSKEW2; integer tSKEW3; reg mreset = 1'b0; reg time_flag_for_OE = 1'b0; reg FROMOE = 1'b0; reg FROMRCLK = 1'b0; integer offsetps[3:0]; reg wrote_in = 1'b0; reg read_out = 1'b0; reg Viol = 1'b0; reg EFNeg_zd; reg FFNeg_zd; reg PAFNeg_zd; reg PAFNeg_dly; reg PAENeg_zd; reg PAENeg_dly; reg ERCLK_zd; reg ERENNeg_zd; reg[39:0] Qreg = 40'b0; reg[39:0] Qreg_tmp = 40'b0; reg[39:0] rtreg = 40'b0; reg SO_zd; integer fwftmod = 1'b0; integer bm = 1'b0; integer iw = 1'b0; integer ow = 1'b0; integer memA[0:MemorySize + 1]; integer memB[0:MemorySize + 1]; integer memC[0:MemorySize + 1]; integer memD[0:MemorySize + 1]; parameter normal = 5'd11; parameter mapped = 5'd12; reg[4:0] memory_model; integer rdptr = 1'b0; integer wrptr = 1'b0; integer rdptr_next = 1'b0; integer wrptr_next = 1'b0; integer rtrdptr = 1'b0; integer paeoff; //pae offset integer pafoff; //paf offset integer opi; //offset preset index integer count; integer fwftcnt; // fwft RCLK counter integer fwftcnt1; // fwft output integer fwftvar = 1'b0; // fwft flag for outreg reg[1:0] opireg; reg[39:0] outreg; reg[39:0] outtmp; integer rd_upd_flg = 1'b0; integer wr_upd_flg = 1'b0; integer Eflagcnt = 1'd0; integer PAEflagcnt = 1'd0; integer PAFflagcnt = 1'd0; integer Fflagcnt = 1'd0; integer TotalLoc = MemorySize; integer TotalLoc1 = MemorySize; time tRCLKposedge = 0; time tWCLKposedge = 0; time tRCLKnegedge = 0; time tWCLKnegedge = 0; time OENeg_event = 0; integer minskew1RW = 1'b1; integer minskew2RW = 1'b1; integer minskew3RW = 1'b1; integer minskew1WR = 1'b1; integer minskew2WR = 1'b1; integer minskew3WR = 1'b1; parameter write = 5'd8; parameter read = 5'd9; parameter none = 5'd10; reg[4:0] last_done = none; reg flag_FF = 1'b0; reg flag_EF = 1'b0; reg flag_PAF = 1'b0; reg flag_PAE = 1'b0; integer pass_EF = 1'b0; integer pass_FF = 1'b0; integer pass_PAE = 1'b0; integer pass_PAF = 1'b0; reg[2:0] bm_reg; integer bm_Incnt = 1'd0; integer bm_Outcnt = 1'd0; integer fs_Incnt = 1'd0; reg[33:0] tmp_ser_in =34'b0; parameter SDR = 2'd0; parameter DDR = 2'd1; reg[4:0] mode_wr; reg[4:0] mode_rd; parameter DDR40 = 5'd0; parameter DDR20 = 5'd1; parameter DDR10 = 5'd2; parameter SDR40 = 5'd3; parameter SDR20 = 5'd4; parameter SDR10 = 5'd5; reg[4:0] in_mode; reg[4:0] out_mode; integer Data1 = 0; integer Data2 = 0; integer Data3 = 0; integer Data4 = 0; reg rt_mode = 1'b0; reg rtrdptr_set = 1'b0; reg rdptr_set = 1'b0; integer write_clk_paf = 1'b0; integer read_clk_pae = 1'b0; integer delayed_pae = 1'b0; integer delayed_paf = 1'b0; integer WCLK_1 = 1'b0; integer update_EFNeg_fwft = 1'b0; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (D39_ipd, D39); buf (D38_ipd, D38); buf (D37_ipd, D37); buf (D36_ipd, D36); buf (D35_ipd, D35); buf (D34_ipd, D34); buf (D33_ipd, D33); buf (D32_ipd, D32); buf (D31_ipd, D31); buf (D30_ipd, D30); buf (D29_ipd, D29); buf (D28_ipd, D28); buf (D27_ipd, D27); buf (D26_ipd, D26); buf (D25_ipd, D25); buf (D24_ipd, D24); buf (D23_ipd, D23); buf (D22_ipd, D22); buf (D21_ipd, D21); buf (D20_ipd, D20); buf (D19_ipd, D19); buf (D18_ipd, D18); buf (D17_ipd, D17); buf (D16_ipd, D16); buf (D15_ipd, D15); buf (D14_ipd, D14); buf (D13_ipd, D13); buf (D12_ipd, D12); buf (D11_ipd, D11); buf (D10_ipd, D10); buf (D9_ipd , D9 ); buf (D8_ipd , D8 ); buf (D7_ipd , D7 ); buf (D6_ipd , D6 ); buf (D5_ipd , D5 ); buf (D4_ipd , D4 ); buf (D3_ipd , D3 ); buf (D2_ipd , D2 ); buf (D1_ipd , D1 ); buf (D0_ipd , D0 ); buf (BM_ipd , BM ); buf (FSEL0_ipd , FSEL0 ); buf (FSEL1_ipd , FSEL1 ); buf (FWFT_ipd , FWFT ); buf (HSTL_ipd , HSTL ); buf (IW_ipd , IW ); buf (MARK_ipd , MARK ); buf (MRSNeg_ipd , MRSNeg ); buf (OENeg_ipd , OENeg ); buf (OW_ipd , OW ); buf (PRSNeg_ipd , PRSNeg ); buf (RCLK_ipd , RCLK ); buf (RCSNeg_ipd , RCSNeg ); buf (RENNeg_ipd , RENNeg ); buf (RSDRNeg_ipd, RSDRNeg ); buf (RTNeg_ipd , RTNeg ); buf (SCLK_ipd , SCLK ); buf (SENNeg_ipd , SENNeg ); buf (SRENNeg_ipd, SRENNeg ); buf (SI_ipd , SI ); buf (WCLK_ipd , WCLK ); buf (WCSNeg_ipd , WCSNeg ); buf (WENNeg_ipd , WENNeg ); buf (WSDRNeg_ipd, WSDRNeg ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (Q39, Q39_Pass , 1); nmos (Q38, Q38_Pass , 1); nmos (Q37, Q37_Pass , 1); nmos (Q36, Q36_Pass , 1); nmos (Q35, Q35_Pass , 1); nmos (Q34, Q34_Pass , 1); nmos (Q33, Q33_Pass , 1); nmos (Q32, Q32_Pass , 1); nmos (Q31, Q31_Pass , 1); nmos (Q30, Q30_Pass , 1); nmos (Q29, Q29_Pass , 1); nmos (Q28, Q28_Pass , 1); nmos (Q27, Q27_Pass , 1); nmos (Q26, Q26_Pass , 1); nmos (Q25, Q25_Pass , 1); nmos (Q24, Q24_Pass , 1); nmos (Q23, Q23_Pass , 1); nmos (Q22, Q22_Pass , 1); nmos (Q21, Q21_Pass , 1); nmos (Q20, Q20_Pass , 1); nmos (Q19, Q19_Pass , 1); nmos (Q18, Q18_Pass , 1); nmos (Q17, Q17_Pass , 1); nmos (Q16, Q16_Pass , 1); nmos (Q15, Q15_Pass , 1); nmos (Q14, Q14_Pass , 1); nmos (Q13, Q13_Pass , 1); nmos (Q12, Q12_Pass , 1); nmos (Q11, Q11_Pass , 1); nmos (Q10, Q10_Pass , 1); nmos (Q9 , Q9_Pass , 1); nmos (Q8 , Q8_Pass , 1); nmos (Q7 , Q7_Pass , 1); nmos (Q6 , Q6_Pass , 1); nmos (Q5 , Q5_Pass , 1); nmos (Q4 , Q4_Pass , 1); nmos (Q3 , Q3_Pass , 1); nmos (Q2 , Q2_Pass , 1); nmos (Q1 , Q1_Pass , 1); nmos (Q0 , Q0_Pass , 1); nmos (EFNeg, EFNeg_zd, 1); nmos (PAENeg, PAENeg_zd, 1); nmos (PAFNeg, PAFNeg_zd, 1); nmos (FFNeg, FFNeg_zd, 1); nmos (ERCLK, ERCLK_zd, 1); nmos (SO, SO_zd, 1); nmos (ERENNeg, ERENNeg_zd, 1); // Needed for TimingChecks // VHDL CheckEnable Equivalent wire D_WCLK_check_pos; assign D_WCLK_check_pos = ~WENNeg && ~WCSNeg; wire D_WCLK_check_neg; assign D_WCLK_check_neg = ~WENNeg && ~WCSNeg && (mode_wr == DDR); wire RENNeg_RCLK_check; assign RENNeg_RCLK_check = ~RENNeg && ~RCSNeg; wire WENNeg_WCLK_check; assign WENNeg_WCLK_check = ~WENNeg && ~WCSNeg; wire SENNeg_SCLK_check; assign SENNeg_SCLK_check = ~SENNeg; wire SRENNeg_SCLK_check; assign SRENNeg_SCLK_check = ~SRENNeg; wire RCLK1_period_check; assign RCLK1_period_check = ((mode_rd == SDR) && mreset); wire WCLK1_period_check; assign WCLK1_period_check = ((mode_wr == SDR) && mreset); wire RCLK2_period_check; assign RCLK2_period_check = ((mode_rd == DDR) && mreset); wire WCLK2_period_check; assign WCLK2_period_check = ((mode_wr == DDR) && mreset); specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_RCLK_Q0 = 1;//tA, tASO, tRCSLZ, tRCSHZ specparam tpd_OENeg_Q0 = 1;//tOLZ, tOHZ, tOE specparam tpd_MRSNeg_EFNeg = 1;//tRSF specparam tpd_WCLK_FFNeg = 1;//tWFF specparam tpd_RCLK_EFNeg = 1;//tREF specparam tpd_WCLK_PAFNeg = 1;//tPAFS specparam tpd_RCLK_PAENeg = 1;//tPAES specparam tpd_RCLK_ERCLK = 1;//tERCLK specparam tpd_RCLK_ERENNeg = 1;//tCLKEN //tsetup values specparam tsetup_D0_WCLK = 1;//tDS specparam tsetup_RENNeg_RCLK = 1;//tENS edge/ specparam tsetup_WCSNeg_WCLK = 1;//tWCSS edge/ specparam tsetup_SI_SCLK = 1;//tSDS / specparam tsetup_SENNeg_SCLK = 1;//tSENS / specparam tsetup_RENNeg_MRSNeg = 1;//tRSS edge\ specparam tsetup_HSTL_MRSNeg = 1;//tHRSS edge\ //thold values specparam thold_D0_WCLK = 1;//tDH specparam thold_RENNeg_RCLK = 1;//tENH edge / specparam thold_WCSNeg_WCLK = 1;//tWCSH edge / specparam thold_SI_SCLK = 1;//tSDH edge / specparam thold_SENNeg_SCLK = 1;//tSENH edge / //tpw values specparam tpw_MRSNeg_negedge = 1; //tRS specparam tpw_RCLK1_negedge = 1; //tCLKL1 specparam tpw_RCLK1_posedge = 1; //tCLKH1 specparam tpw_WCLK1_negedge = 1; //tCLKL1 specparam tpw_WCLK1_posedge = 1; //tCLKH1 specparam tpw_RCLK2_negedge = 1; //tCLKL2 specparam tpw_RCLK2_posedge = 1; //tCLKH2 specparam tpw_WCLK2_negedge = 1; //tCLKL2 specparam tpw_WCLK2_posedge = 1; //tCLKH2 specparam tpw_SCLK_negedge = 1; //tSCKL specparam tpw_SCLK_posedge = 1; //tSCKH //period values specparam tperiod_RCLK1_posedge = 1; //tCLK1 specparam tperiod_WCLK1_posedge = 1; //tCLK1 specparam tperiod_RCLK2_posedge = 1; //tCLK2 specparam tperiod_WCLK2_posedge = 1; //tCLK2 specparam tperiod_SCLK_posedge = 1; //tSCLK //trecovery values specparam trecovery_RENNeg_MRSNeg = 1; //tRSR //tdevice values: values for internal delays specparam tdevice_SKEW1 = 3.5; specparam tdevice_SKEW2 = 3.5; specparam tdevice_SKEW3 = 4; /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// // Data ouptut paths if (FROMRCLK) ( RCLK => Q0 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q1 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q2 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q3 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q4 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q5 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q6 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q7 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q8 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q9 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q10 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q11 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q12 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q13 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q14 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q15 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q16 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q17 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q18 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q19 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q20 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q21 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q22 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q23 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q24 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q25 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q26 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q27 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q28 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q29 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q30 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q31 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q32 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q33 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q34 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q35 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q36 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q37 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q38 ) = tpd_RCLK_Q0; if (FROMRCLK) ( RCLK => Q39 ) = tpd_RCLK_Q0; if (FROMOE) ( OENeg => Q0 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q1 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q2 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q3 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q4 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q5 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q6 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q7 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q8 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q9 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q10 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q11 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q12 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q13 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q14 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q15 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q16 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q17 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q18 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q19 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q20 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q21 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q22 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q23 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q24 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q25 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q26 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q27 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q28 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q29 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q30 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q31 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q32 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q33 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q34 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q35 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q36 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q37 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q38 ) = tpd_OENeg_Q0; if (FROMOE) ( OENeg => Q39 ) = tpd_OENeg_Q0; if (~MRSNeg) ( MRSNeg => Q0 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q1 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q2 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q3 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q4 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q5 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q6 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q7 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q8 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q9 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q10 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q11 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q12 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q13 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q14 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q15 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q16 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q17 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q18 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q19 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q20 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q21 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q22 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q23 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q24 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q25 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q26 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q27 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q28 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q29 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q30 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q31 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q32 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q33 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q34 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q35 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q36 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q37 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q38 ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => Q39 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q0 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q1 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q2 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q3 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q4 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q5 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q6 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q7 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q8 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q9 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q10 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q11 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q12 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q13 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q14 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q15 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q16 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q17 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q18 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q19 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q20 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q21 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q22 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q23 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q24 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q25 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q26 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q27 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q28 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q29 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q30 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q31 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q32 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q33 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q34 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q35 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q36 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q37 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q38 ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => Q39 ) = tpd_MRSNeg_EFNeg; if (RCLK) ( RCLK => EFNeg ) = tpd_RCLK_EFNeg; if (RCLK) ( RCLK => PAENeg ) = tpd_RCLK_PAENeg; if (WCLK) ( WCLK => PAFNeg ) = tpd_WCLK_PAFNeg; if (WCLK) ( WCLK => FFNeg ) = tpd_WCLK_FFNeg; if (~MRSNeg) ( MRSNeg => EFNeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => PAENeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => PAFNeg ) = tpd_MRSNeg_EFNeg; if (~MRSNeg) ( MRSNeg => FFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => EFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => PAENeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => PAFNeg ) = tpd_MRSNeg_EFNeg; if (~PRSNeg) ( PRSNeg => FFNeg ) = tpd_MRSNeg_EFNeg; ( RCLK => ERCLK ) = tpd_RCLK_ERCLK; ( SCLK => SO ) = tpd_RCLK_Q0; ( RCLK => ERENNeg ) = tpd_RCLK_ERENNeg; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// $setup ( D0 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D1 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D2 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D3 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D4 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D5 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D6 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D7 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D8 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D9 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D10 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D11 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D12 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D13 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D14 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D15 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D16 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D17 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D18 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D19 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D20 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D21 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D22 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D23 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D24 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D25 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D26 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D27 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D28 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D29 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D30 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D31 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D32 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D33 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D34 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D35 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D36 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D37 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D38 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D39 , posedge WCLK &&& D_WCLK_check_pos, tsetup_D0_WCLK,Viol); $setup ( D0 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D1 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D2 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D3 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D4 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D5 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D6 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D7 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D8 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D9 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D10 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D11 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D12 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D13 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D14 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D15 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D16 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D17 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D18 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D19 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D20 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D21 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D22 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D23 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D24 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D25 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D26 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D27 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D28 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D29 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D30 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D31 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D32 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D33 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D34 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D35 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D36 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D37 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D38 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( D39 , negedge WCLK &&& D_WCLK_check_neg, tsetup_D0_WCLK,Viol); $setup ( RENNeg , posedge RCLK &&& RENNeg_RCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( WENNeg , posedge WCLK &&& WENNeg_WCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( RCSNeg , posedge RCLK &&& RENNeg_RCLK_check, tsetup_RENNeg_RCLK,Viol); $setup ( RTNeg , posedge RCLK, tsetup_RENNeg_RCLK,Viol); $setup ( MARK , posedge RCLK, tsetup_RENNeg_RCLK,Viol); $setup ( WCSNeg , posedge WCLK &&& WENNeg_WCLK_check, tsetup_WCSNeg_WCLK,Viol); $setup ( SI , posedge SCLK, tsetup_SI_SCLK,Viol); $setup ( SENNeg , posedge SCLK &&& SENNeg_SCLK_check, tsetup_SENNeg_SCLK,Viol); $setup ( SRENNeg , posedge SCLK &&& SRENNeg_SCLK_check, tsetup_SENNeg_SCLK,Viol); $setup ( RENNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( WENNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( SENNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( SRENNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( FWFT , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( FSEL0 , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( FSEL1 , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( BM , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( OW , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( IW , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( WSDRNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( RSDRNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( RTNeg , negedge MRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( HSTL , negedge MRSNeg, tsetup_HSTL_MRSNeg,Viol); $setup ( RENNeg , negedge PRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( WENNeg , negedge PRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( SENNeg , negedge PRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( SRENNeg , negedge PRSNeg, tsetup_RENNeg_MRSNeg,Viol); $setup ( RTNeg , negedge PRSNeg, tsetup_RENNeg_MRSNeg,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D0, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D1, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D2, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D3, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D4, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D5, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D6, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D7, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D8, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D9, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D10, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D11, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D12, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D13, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D14, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D15, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D16, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D17, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D18, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D19, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D20, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D21, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D22, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D23, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D24, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D25, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D26, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D27, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D28, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D29, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D30, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D31, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D32, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D33, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D34, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D35, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D36, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D37, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D38, thold_D0_WCLK,Viol); $hold (posedge WCLK &&& D_WCLK_check_pos, D39, thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D0, thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D1 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D2 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D3 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D4 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D5 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D6 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D7 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D8 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D9 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D10 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D11 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D12 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D13 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D14 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D15 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D16 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D17 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D18 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D19 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D20 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D21 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D22 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D23 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D24 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D25 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D26 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D27 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D28 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D29 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D30 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D31 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D32 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D33 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D34 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D35 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D36 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D37 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D38 , thold_D0_WCLK,Viol); $hold (negedge WCLK &&& D_WCLK_check_neg, D39 , thold_D0_WCLK,Viol); $hold ( posedge RCLK &&& RENNeg_RCLK_check, RENNeg, thold_RENNeg_RCLK,Viol); $hold ( posedge WCLK &&& WENNeg_WCLK_check, WENNeg, thold_RENNeg_RCLK,Viol); $hold ( posedge RCLK &&& RENNeg_RCLK_check, RCSNeg , thold_RENNeg_RCLK,Viol); $hold ( posedge RCLK, RTNeg , thold_RENNeg_RCLK,Viol); $hold ( posedge RCLK, MARK , thold_RENNeg_RCLK,Viol); $hold ( posedge WCLK &&& WENNeg_WCLK_check, WCSNeg , thold_WCSNeg_WCLK,Viol); $hold ( posedge SCLK, SI , thold_SI_SCLK,Viol); $hold ( posedge SCLK &&& SENNeg_SCLK_check, SENNeg , thold_SENNeg_SCLK,Viol); $hold ( posedge SCLK &&& SRENNeg_SCLK_check, SRENNeg , thold_SENNeg_SCLK,Viol); $hold ( posedge MRSNeg, RENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge MRSNeg, WENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge MRSNeg, FWFT , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge MRSNeg, WSDRNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge MRSNeg, RSDRNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge PRSNeg, RENNeg , trecovery_RENNeg_MRSNeg,Viol); $hold ( posedge PRSNeg, WENNeg , trecovery_RENNeg_MRSNeg,Viol); $width (negedge MRSNeg, tpw_MRSNeg_negedge); $width (negedge PRSNeg, tpw_MRSNeg_negedge); $width (posedge RCLK &&& RCLK1_period_check, tpw_RCLK1_posedge); $width (negedge RCLK &&& RCLK1_period_check, tpw_RCLK1_negedge); $width (posedge WCLK &&& WCLK1_period_check, tpw_WCLK1_posedge); $width (negedge WCLK &&& WCLK1_period_check, tpw_WCLK1_negedge); $width (posedge RCLK &&& RCLK2_period_check, tpw_RCLK2_posedge); $width (negedge RCLK &&& RCLK2_period_check, tpw_RCLK2_negedge); $width (posedge WCLK &&& WCLK2_period_check, tpw_WCLK2_posedge); $width (negedge WCLK &&& WCLK2_period_check, tpw_WCLK2_negedge); $width (posedge SCLK, tpw_SCLK_posedge); $width (negedge SCLK, tpw_SCLK_negedge); $period(posedge RCLK &&& RCLK1_period_check, tperiod_RCLK1_posedge); $period(posedge WCLK &&& WCLK1_period_check, tperiod_WCLK1_posedge); $period(posedge RCLK &&& RCLK2_period_check, tperiod_RCLK2_posedge); $period(posedge WCLK &&& WCLK2_period_check, tperiod_WCLK2_posedge); $period(posedge SCLK, tperiod_SCLK_posedge); endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// initial begin memory_model = normal; mode_wr = SDR; mode_rd = SDR; in_mode = SDR40; out_mode = SDR40; TotalLoc = MemorySize; TotalLoc1 = MemorySize; offsetps[0] = 8'd7; offsetps[1] = 8'd127; offsetps[2] = 8'd63; offsetps[3] = 8'd255; end always @(negedge MRSNeg) begin master_reset; end always @(negedge PRSNeg) begin partial_reset; end always @(WCLK) // for violation registering begin #0.1 WCLK_1 <= WCLK; end always @(WCLK_1) begin if (mreset == 1'b1) begin if ((((FFNeg_zd == 1'b1) && (fwftmod == 1'b0)) || ((FFNeg_zd == 1'b0 && fwftmod == 1'b1))) || (bm_Incnt != 1'b0)) begin case (in_mode) DDR40 : begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 1'b0)) begin write_input; memA[wrptr] = Data4; memB[wrptr] = Data3; memC[wrptr] = Data2; memD[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 1'b1) begin write_input; memA[wrptr_next + TotalLoc/2] = Data4; memB[wrptr_next + TotalLoc/2] = Data3; memC[wrptr_next + TotalLoc/2] = Data2; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt = 0; end end DDR20 : begin if (out_mode == SDR40) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 1'b0)) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memC[wrptr_next] = Data2; memD[wrptr_next] = Data1; last_done = write; bm_Incnt = 0; end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memC[wrptr_next] = Data2; memD[wrptr_next] = Data1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memA[wrptr_next + TotalLoc/2] = Data2; memB[wrptr_next + TotalLoc/2] = Data1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memC[wrptr_next + TotalLoc/2] = Data2; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt = 0; end end end DDR10 : begin if (out_mode == SDR40) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memC[wrptr_next] = Data1; bm_Incnt = bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memD[wrptr_next] = Data1; last_done = write; bm_Incnt=0; end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0) && (bm_Incnt == 0)) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memC[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memD[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 4) begin write_input; memA[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 5) begin write_input; memB[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 6) begin write_input; memC[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 7) begin write_input; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt=0; end end end SDR40 : begin if (out_mode == DDR40) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data4; memB[wrptr] = Data3; memC[wrptr] = Data2; memD[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memA[wrptr_next + TotalLoc/2] = Data4; memB[wrptr_next + TotalLoc/2] = Data3; memC[wrptr_next + TotalLoc/2] = Data2; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt=0; end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) begin write_input; memA[wrptr] = Data4; memB[wrptr] = Data3; memC[wrptr] = Data2; memD[wrptr] = Data1; wrote_in = 1'b1; last_done = write; bm_Incnt=0; if ((count == 0) && (fwftmod == 1'b1)) begin outtmp[39:30] = Data4; outtmp[29:20] = Data3; outtmp[19:10] = Data2; outtmp[9:0] = Data1; end end end end SDR20 : begin if (out_mode == DDR40) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memC[wrptr_next] = Data2; memD[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memA[wrptr_next + TotalLoc/2] = Data2; memB[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memC[wrptr_next + TotalLoc/2] = Data2; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt=0; end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data2; memB[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; if ((count==0) && (fwftmod == 1'b1)) begin outtmp[39:30] = Data2; outtmp[29:20] = Data1; end end else if (bm_Incnt == 1) begin write_input; memC[wrptr_next] = Data2; memD[wrptr_next] = Data1; last_done = write; bm_Incnt=0; if ((count==1 && (fwftmod == 1'b1))) begin outtmp[19:10] = Data2; outtmp[9:0] = Data1; end end end end SDR10 : begin if (out_mode == DDR40) begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data1; wrptr_next = wrptr; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memC[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memD[wrptr_next] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 4) begin write_input; memA[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 5) begin write_input; memB[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 6) begin write_input; memC[wrptr_next + TotalLoc/2] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 7) begin write_input; memD[wrptr_next + TotalLoc/2] = Data1; last_done = write; bm_Incnt=0; end end else begin if ((WCLK_1) && (WENNeg == 1'b0) && (WCSNeg == 1'b0)) if (bm_Incnt == 0) begin write_input; memA[wrptr] = Data1; wrote_in = 1'b1; bm_Incnt=bm_Incnt + 1; wrptr_next = wrptr; if ((count==0) && (fwftmod==1'b1)) outtmp[39:30] = Data1; end else if (bm_Incnt == 1) begin write_input; memB[wrptr_next] = Data1; if ((count==1) && (fwftmod == 1'b1)) outtmp[29:20] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 2) begin write_input; memC[wrptr_next] = Data1; if ((count==1) && (fwftmod == 1'b1)) outtmp[19:10] = Data1; bm_Incnt=bm_Incnt + 1; end else if (bm_Incnt == 3) begin write_input; memD[wrptr_next] = Data1; if ((count==1) && (fwftmod == 1'b1)) outtmp[9:0] = Data1; last_done = write; bm_Incnt=0; end end end endcase end if (wrote_in == 1'b1) begin wrote_in = 1'b0; if (((fwftmod == 1'b1) && (FFNeg_zd == 1'b0)) || // not full ((fwftmod == 1'b0) && (FFNeg_zd == 1'b1))) //write pointer begin if (wrptr < TotalLoc1 - 1) begin if (rt_mode == 1'b0) wrptr = wrptr + 1; else begin if (wrptr != rtrdptr -1 ) wrptr = wrptr + 1; end end else wrptr = 0; //counter count = count + 1; if (count == TotalLoc1) begin if (fwftmod == 1'b1) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; end //PAF sync updating if (pafoff <= count) begin PAFNeg_dly = 1'b0; delayed_paf = 1'b1; end else PAFNeg_dly = 1'b1; // flags for EFNeg and PAENeg updating if ((count == 1) || (count == paeoff + 1)) wr_upd_flg = 1'b1; else wr_upd_flg = 1'b0; end end if (WCLK_1) begin //FFNeg updating when reading active if (mode_rd == DDR) begin if ((minskew2RW == 1'b0) && (flag_FF == 1'b1)) if (Fflagcnt < 1) Fflagcnt = Fflagcnt + 1; else begin FFNeg_zd = 1'b1; Fflagcnt = 0; flag_FF = 1'b0; end else if ((minskew2RW == 1'b1) && (flag_FF == 1'b1)) begin FFNeg_zd = 1'b1; Fflagcnt = 0; flag_FF = 1'b0; end end else begin if ((minskew1RW == 1'b0) && (flag_FF == 1'b1)) if (Fflagcnt < 1) Fflagcnt = Fflagcnt + 1; else begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end else if ((minskew1RW==1'b1) && (flag_FF == 1'b1)) begin if (fwftmod == 1'b0) FFNeg_zd = 1'b1; else FFNeg_zd = 1'b0; Fflagcnt = 0; flag_FF = 1'b0; end end //PAFNeg updating when write active if ((write_clk_paf == 2) && (delayed_paf == 1'b1)) begin PAFNeg_zd = PAFNeg_dly; write_clk_paf = 1'b0; delayed_paf = 1'b0; end else if (delayed_paf == 1'b1) write_clk_paf = write_clk_paf + 1; //PAFNeg updating when read active if ((minskew3RW == 1'b0) && (flag_PAF == 1'b1)) if (PAFflagcnt < 1) PAFflagcnt = PAFflagcnt + 1; else begin PAFNeg_zd = 1'b1; PAFflagcnt = 0; flag_PAF = 1'b0; end else if ((minskew3RW==1'b1) && (flag_PAF == 1'b1)) begin PAFNeg_zd = 1'b1; PAFflagcnt = 0; flag_PAF = 1'b0; end // FFNeg updating when read active if ((rd_upd_flg==1'b1) && (count == TotalLoc1 - 1)) begin pass_FF = 1'b1; rd_upd_flg = 1'b0; end if ((last_done == read) && (pass_FF==1'b1)) begin flag_FF = 1'b1; pass_FF = 1'b0; end if ((rd_upd_flg==1'b1) && (count == pafoff - 1)) begin pass_PAF = 1'b1; rd_upd_flg = 1'b0; end if ((last_done == read) && (pass_PAF==1'b1)) begin flag_PAF = 1'b1; pass_PAF = 1'b0; end end end end always @(RCLK) begin if (RCLK) ERCLK_zd = 1'b1; else if (~RCLK) ERCLK_zd = 1'b0; end // First Word Fall Through always @(RCLK) begin if ((RCLK) && (fwftmod == 1'b1)) begin if ((count == 1) && (fwftcnt == 0) && (last_done == write) && (EFNeg_zd == 1'b1)) begin fwftcnt = fwftcnt + 1; outreg = outtmp; rdptr = rdptr + 1; count = 0; end else if (fwftcnt == 1) fwftcnt = fwftcnt + 1; else if (fwftcnt == 2) begin fwftvar = 1'b1; EFNeg_zd = 1'b0; fwftcnt = 0; fwftcnt1 = 0; FROMOE = 1'b0; FROMRCLK = 1'b1; end if (fwftvar == 1'b1) begin if (out_mode == SDR40) begin Qreg = outreg; fwftvar = 1'b0; end else if (out_mode == SDR20) begin if (fwftcnt1 == 0) begin Qreg[19:0] = outreg[39:20]; fwftcnt1 = 1; end else begin Qreg[19:0] = outreg[19:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end else if (out_mode == SDR10) begin if (fwftcnt1 == 0) begin Qreg[9:0] = outreg[39:30]; fwftcnt1 = 1; end else if (fwftcnt1 == 1) begin Qreg[9:0] = outreg[29:20]; fwftcnt1 = 2; end else if (fwftcnt1 == 2) begin Qreg[9:0] = outreg[19:10]; fwftcnt1 = 3; end else begin Qreg[9:0] = outreg[9:0]; fwftcnt1 = 0; fwftvar = 1'b0; end end end end end // empty fifo in fwft mode always @(RCLK) begin if ((RCLK) && (count == 0) && (EFNeg_zd == 1'b0) && (fwftmod == 1'b1) && (update_EFNeg_fwft == 1'b1) &&(RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin EFNeg_zd = 1'b1; update_EFNeg_fwft = 1'b0; end end always @(RCLK) begin if (mreset == 1'b1) begin if ( ( ((EFNeg_zd==1'b1) && (fwftmod==1'b0)) || ((EFNeg_zd==1'b0) && (fwftmod==1'b1)) ) && (RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) ) ERENNeg_zd = 1'b0; else if (((RCLK) && (last_done == read)) || ((RCLK) && (RENNeg == 1'b1))) ERENNeg_zd = 1'b1; // at the end of the reading cycle // or if RENNeg inactive //retransmit if ((RCLK) && (MARK==1'b1) && (rt_mode==1'b0)) begin rt_mode = 1'b1; rtrdptr_set = 1'b0; rdptr_set = 1'b0; end else if ((RCLK) && (MARK == 1'b0) && (rt_mode==1'b1)) rt_mode = 1'b0; if ((RCLK) && (rt_mode == 1'b1)) begin if (fwftmod == 1'b1) begin if ((RENNeg==1'b0) && (RTNeg == 1'b1) && (count >= 32)) //retransmit setup begin if (rtrdptr_set == 1'b0) begin rtrdptr = rdptr; rtrdptr_set = 1'b1; rtreg = Qreg; end end else if ((RENNeg==1'b1) && (RTNeg == 1'b0) && (rtrdptr_set == 1'b1)) EFNeg_zd = 1'b1; else if ((RENNeg==1'b1) && (RTNeg == 1'b1) && (EFNeg_zd == 1'b1) && (rtrdptr_set==1'b1)) begin if (rdptr_set == 1'b0) begin EFNeg_zd = 1'b0; rdptr = rtrdptr; rdptr_set = 1'b1; Qreg = rtreg; end end end else begin if ((RENNeg==1'b0) && (RTNeg == 1'b1) && (((memory_model == mapped) && (count >= 16)) || ((memory_model == normal) && (count >= 32)))) //retransmit set begin if (rtrdptr_set == 1'b0) begin if (rdptr > 1) rtrdptr = rdptr-1; else rtrdptr = 0; rtrdptr_set = 1'b1; end end else if ((RENNeg==1'b1) && (RTNeg == 1'b0) && (rtrdptr_set == 1'b1)) EFNeg_zd = 1'b0; else if ((RENNeg==1'b1) && (RTNeg == 1'b1) && (EFNeg_zd == 1'b0) && (rtrdptr_set==1'b1)) begin if (rdptr_set == 1'b0) begin EFNeg_zd = 1'b1; rdptr = rtrdptr; rdptr_set = 1'b1; end end end end // read from fifo if ( (count > 0) && (((EFNeg_zd == 1'b1) && (fwftmod==1'b0)) || ((EFNeg_zd == 1'b0) && (fwftmod==1'b1))) || (bm_Outcnt != 0) ) begin case (out_mode) DDR40: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[39:30] = Qreg_tmp[39:30]; Qreg[29:20] = Qreg_tmp[29:20]; Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next + TotalLoc/2); Qreg[39:30] = Qreg_tmp[39:30]; Qreg[29:20] = Qreg_tmp[29:20]; Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end DDR20: begin if (in_mode == DDR40) begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[39:30]; Qreg[9:0] = Qreg_tmp[29:20]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next+TotalLoc/2); Qreg[19:10] =Qreg_tmp[39:30]; Qreg[9:0] =Qreg_tmp[29:20]; read_out = 1'b1; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next+TotalLoc/2); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end else begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[39:30]; Qreg[9:0] = Qreg_tmp[29:20]; read_out = 1'b1; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end end DDR10: begin if (in_mode == DDR40) begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[39:30]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 4) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[39:30]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 5) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 6) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[19:10]; read_out = 1'b1; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 7) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end else begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0) && (bm_Outcnt == 0)) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[39:30]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[19:10]; read_out = 1'b1; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; bm_Outcnt =0; end end end SDR40: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin if (in_mode == DDR40) begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[39:30] = Qreg_tmp[39:30]; Qreg[29:20] = Qreg_tmp[29:20]; Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next + TotalLoc/2); Qreg[39:30] = Qreg_tmp[39:30]; Qreg[29:20] = Qreg_tmp[29:20]; Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end else begin generate_output(rdptr); Qreg[39:30] = Qreg_tmp[39:30]; Qreg[29:20] = Qreg_tmp[29:20]; Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; last_done = read; read_out = 1'b1; bm_Outcnt =0; end end end SDR20: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin if (in_mode == DDR40) begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[19:10] = Qreg_tmp[39:30]; Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt = bm_Outcnt + 1; rdptr_next = rdptr; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt = bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next + TotalLoc/2); Qreg[19:10] = Qreg_tmp[39:30]; Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt = bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next + TotalLoc/2); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end else begin if (bm_Outcnt == 0) begin Qreg=40'b0; generate_output(rdptr); Qreg[19:10] = Qreg_tmp[39:30]; Qreg[9:0] = Qreg_tmp[29:20]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[19:10] = Qreg_tmp[19:10]; Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end end end SDR10: begin if ((RCLK) && (RENNeg == 1'b0) && (RCSNeg == 1'b0)) begin if (in_mode == DDR40) begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[39:30]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 4) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[39:30]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 5) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 6) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 7) begin generate_output(rdptr_next + TotalLoc/2); Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end else begin if (bm_Outcnt == 0) begin generate_output(rdptr); Qreg[9:0] = Qreg_tmp[39:30]; rdptr_next = rdptr; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 1) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[29:20]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 2) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[19:10]; bm_Outcnt =bm_Outcnt + 1; end else if (bm_Outcnt == 3) begin generate_output(rdptr_next); Qreg[9:0] = Qreg_tmp[9:0]; read_out = 1'b1; last_done = read; bm_Outcnt =0; end end end end endcase end // flag ctrl if (read_out == 1'b1) begin read_out = 1'b0; if (((fwftmod==1'b1) && (EFNeg_zd == 1'b0)) || ((fwftmod == 1'b0) && (EFNeg_zd == 1'b1))) //not empty begin //read pointer if (rdptr < TotalLoc1 - 1) rdptr = rdptr + 1; else rdptr = 0; //counter count = count - 1; //update PAENeg, delayed if (count <= paeoff) begin PAENeg_dly = 1'b0; delayed_pae = 1'b1; end else PAENeg_dly = 1'b1; //update EFNeg, for idt standard mode only if ((count == 0) && (fwftmod == 1'b0)) EFNeg_zd = 1'b0; //update EFNeg, for fwft mode only if ((count == 0) && (fwftmod == 1'b1)) #0.1 update_EFNeg_fwft <= 1'b1; // for updating PAFNeg and FFNeg if ((count == TotalLoc1 -1) || (count == pafoff - 1)) rd_upd_flg = 1'b1; else rd_upd_flg = 1'b0; end end if (RCLK) begin if (mode_wr == DDR) begin if ((minskew2WR==1'b0) && (flag_EF == 1'b1)) begin if (Eflagcnt < 1) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end else if ((minskew2WR==1'b1) && (flag_EF == 1'b1)) begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end else begin if ((minskew1WR==1'b0) && (flag_EF == 1'b1)) begin if (fwftmod==1'b0) begin if (Eflagcnt < 1) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end end else begin if (Eflagcnt < 2) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b0; Eflagcnt = 0; flag_EF = 1'b0; end end end else if ((minskew1WR==1'b1) && (flag_EF == 1'b1)) begin if (fwftmod==1'b0) begin EFNeg_zd = 1'b1; Eflagcnt = 0; flag_EF = 1'b0; end else begin if (Eflagcnt < 1) Eflagcnt = Eflagcnt + 1; else begin EFNeg_zd = 1'b0; Eflagcnt = 0; flag_EF = 1'b0; end end end end //PAENeg updating when writing - delayed if ((read_clk_pae == 2) && (delayed_pae == 1'b1)) begin PAENeg_zd = PAENeg_dly; read_clk_pae = 0; delayed_pae = 1'b0; end else if (delayed_pae == 1'b1) read_clk_pae = read_clk_pae + 1; //PAENeg updating when write active if ((minskew3WR==1'b0) && (flag_PAE == 1'b1)) begin if (PAEflagcnt < 1) PAEflagcnt = PAEflagcnt + 1; else begin PAENeg_zd = 1'b1; PAEflagcnt = 0; flag_PAE = 1'b0; end end else if ((minskew3WR==1'b1) && (flag_PAE == 1'b1)) begin PAENeg_zd = 1'b1; PAEflagcnt = 0; flag_PAE = 1'b0; end //EFNeg updating when reading active if ((wr_upd_flg == 1'b1) && (count == 1)) begin pass_EF = 1'b1; wr_upd_flg = 1'b0; end if ((last_done == write) && (pass_EF == 1'b1)) begin flag_EF = 1'b1; pass_EF = 1'b0; end //PAENeg updating when write active if ((wr_upd_flg == 1'b1) && (count == paeoff + 1)) begin pass_PAE = 1'b1; wr_upd_flg = 1'b0; end if ((last_done == write) && (pass_PAE == 1'b1)) begin flag_PAE = 1'b1; pass_PAE = 1'b0; end end end end always @(posedge SENNeg or posedge SRENNeg) begin fs_Incnt = 0; end always @(posedge SCLK) begin if ((mreset == 1'b1) && (~SENNeg)) //write to registers write_register; end always @(posedge SCLK) begin if ((mreset == 1'b1) && (~SRENNeg)) //read from registers read_register; end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(QOut_zd) begin : OutputGen if (QOut_zd[0] !== 1'bz) begin QOut_Pass = QOut_zd; end end always @(QOut_zd) begin if (QOut_zd[0] == 1'bz) begin disable OutputGen; FROMOE = 1'b1; QOut_Pass = QOut_zd; end end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(negedge OENeg) begin OENeg_event = $time; FROMOE = 1'b0; if (time_flag_for_OE == 1'b1) begin if ((tpd_RCLK_Q0 - (OENeg_event - tRCLKposedge)) >= tpd_OENeg_Q0) begin FROMOE = 1'b0; FROMRCLK = 1'b1; end else begin FROMOE = 1'b1; FROMRCLK = 1'b0; end end else begin FROMOE = 1'b1; FROMRCLK = 1'b0; end end ////////////////////////////////////////////////////////////////////////// // Clock active edges ////////////////////////////////////////////////////////////////////////// always @(posedge RCLK) begin tRCLKposedge = $time; if ((tRCLKposedge - tWCLKposedge) > tSKEW1) minskew1WR = 1'b1; else minskew1WR = 1'b0; if ((tRCLKposedge - tWCLKnegedge) > tSKEW2) minskew2WR = 1'b1; else minskew2WR = 1'b0; if ((tRCLKposedge - tWCLKposedge) > tSKEW3) minskew3WR = 1'b1; else minskew3WR = 1'b0; end always @(negedge RCLK) begin tRCLKnegedge = $time; end always @(posedge WCLK) begin tWCLKposedge = $time; if ((tWCLKposedge - tRCLKposedge) > tSKEW1) minskew1RW = 1'b1; else minskew1RW = 1'b0; if ((tWCLKposedge - tRCLKnegedge) > tSKEW2) minskew2RW = 1'b1; else minskew2RW = 1'b0; if ((tWCLKposedge - tRCLKposedge) > tSKEW3) minskew3RW = 1'b1; else minskew3RW = 1'b0; end always @(negedge WCLK) begin tWCLKnegedge = $time; end //Output Disable Control always @(posedge OENeg or posedge RCSNeg) begin QOut_zd = 40'bz; end always @(Qreg) begin QOut_zd = Qreg; end //Master Reset always @(negedge MRSNeg) begin if(~MRSNeg) begin QOut_zd = 40'b0; end end reg BuffInSkew1, BuffInSkew2, BuffInSkew3; wire BuffOutSkew1, BuffOutSkew2, BuffOutSkew3; BUFFER SKEW1 (BuffOutSkew1, BuffInSkew1); BUFFER SKEW2 (BuffOutSkew2, BuffInSkew2); BUFFER SKEW3 (BuffOutSkew3, BuffInSkew3); initial begin BuffInSkew1 = 1'b1; BuffInSkew2 = 1'b1; BuffInSkew3 = 1'b1; end always @(posedge BuffOutSkew1) begin tSKEW1 = $time; end always @(posedge BuffOutSkew2) begin tSKEW2 = $time; end always @(posedge BuffOutSkew3) begin tSKEW3 = $time; end task write_input; begin if (~Viol) begin if (DIn[39] !== 1'bZ) Data4 = DIn[39:30]; if (DIn[29] !== 1'bZ) Data3 = DIn[29:20]; if (DIn[19] !== 1'bZ) Data2 = DIn[19:10]; if (DIn[9] !== 1'bZ) Data1 = DIn[9:0]; end else begin Data4 = -1; Data3 = -1; Data2 = -1; Data1 = -1; Viol = 1'b0; end end endtask task generate_output; input pointer; integer pointer; begin if (RCLK == 1'b1) begin time_flag_for_OE = 1'b1; time_flag_for_OE <= #tpd_RCLK_Q0 1'b0; FROMRCLK = 1'b1; FROMOE = 1'b0; end if (memA[pointer] >= 0) Qreg_tmp[39:30] = memA[pointer]; else Qreg_tmp[39:30] = 10'bX; if (memB[pointer] >= 0) Qreg_tmp[29:20] = memB[pointer]; else Qreg_tmp[29:20] = 10'bX; if (memC[pointer] >= 0) Qreg_tmp[19:10] = memC[pointer]; else Qreg_tmp[19:10] = 10'bX; if (memD[pointer] >= 0) Qreg_tmp[9:0] = memD[pointer]; else Qreg_tmp[9:0] = 10'bX; end endtask task master_reset; begin mreset = 1'b0; mreset <= #30 1'b1; fwftcnt = 1'b0; PAENeg_zd = 1'b0; PAFNeg_zd = 1'b1; PAENeg_dly = 1'b0; PAFNeg_dly = 1'b1; TotalLoc1 = TotalLoc; rdptr = 1'b0; wrptr = 1'b0; count = 1'b0; last_done = none; rt_mode = 1'b0; Viol = 1'b0; // configuration section if (FWFT) begin fwftmod = 1'b1; // fwft mode EFNeg_zd = 1'b1; FFNeg_zd = 1'b0; end else begin fwftmod = 1'b0; //idt standard mode EFNeg_zd = 1'b0; FFNeg_zd = 1'b1; end if (~BM) bm = 1'b0; else if (BM) bm = 1'b1; else $display ("Warning - BM has unusable value"); if (~IW) iw = 1'b0; else if (IW) iw = 1'b1; else $display ("Warning - IW has unusable value"); if (~OW) ow = 1'b0; else if (OW) ow = 1'b1; else $display ("Warning - OW has unusable value"); //bus matching byte order bm_Incnt = 1'b0; bm_Outcnt = 1'b0; if (~WSDRNeg) mode_wr = SDR; else if (WSDRNeg) mode_wr = DDR; else $display ("Warning - WSDRNeg has unusable value"); if (~RSDRNeg) mode_rd = SDR; else if (RSDRNeg) mode_rd = DDR; else $display ("Warning - RSDRNeg has unusable value"); if (((mode_wr == DDR) || (mode_rd == DDR)) && (fwftmod == 1'b1)) $display ("FWFT mode is not acceptable for double data rate!"); opireg[1] = FSEL1; opireg[0] = FSEL0; opi = opireg; paeoff = offsetps[opi]; if ((bm == 1'b0) && (iw == 1'b0) && (ow == 1'b0)) begin if (mode_wr == SDR) in_mode = SDR40; else in_mode = DDR40; if (mode_rd == SDR) out_mode = SDR40; else out_mode = DDR40; end else if ((bm == 1'b1) && (iw == 1'b0) && (ow == 1'b0)) begin if (mode_wr == SDR) in_mode = SDR40; else in_mode = DDR40; if (mode_rd == SDR) out_mode = SDR20; else out_mode = DDR20; end else if ((bm == 1'b1) && (iw == 1'b0) && (ow == 1'b1)) begin if (mode_wr == SDR) in_mode = SDR40; else in_mode = DDR40; if (mode_rd == SDR) out_mode = SDR10; else out_mode = DDR10; end else if ((bm == 1'b1) && (iw == 1'b1) && (ow == 1'b0)) begin if (mode_wr == SDR) in_mode = SDR20; else in_mode = DDR20; if (mode_rd == SDR) out_mode = SDR40; else out_mode = DDR40; end else if ((bm == 1'b1) && (iw == 1'b1) && (ow == 1'b1)) begin if (mode_wr == SDR) in_mode = SDR10; else in_mode = DDR10; if (mode_rd == SDR) out_mode = SDR40; else out_mode = DDR40; end if ( (in_mode==DDR40) || ((in_mode == DDR20) && (out_mode != SDR40)) || ((in_mode == DDR10) && (out_mode != SDR40)) || ((in_mode == SDR40) && (out_mode == DDR40)) || ((in_mode == SDR20) && (out_mode == DDR40)) || ((in_mode == SDR10) && (out_mode == DDR40)) ) begin memory_model = mapped; TotalLoc1 = TotalLoc/2; paeoff = (paeoff - 1)/2; end else begin memory_model = normal; TotalLoc1 = TotalLoc; end pafoff = TotalLoc1 - paeoff; outreg = 40'b0; Qreg = 40'b0; end endtask task partial_reset; begin mreset = 1'b0; mreset <= #30 1'b1; fwftcnt = 1'b0; PAENeg_zd = 1'b0; PAFNeg_zd = 1'b1; PAENeg_dly = 1'b0; PAFNeg_dly = 1'b1; rdptr = 1'b0; wrptr = 1'b0; count = 1'b0; last_done = none; rt_mode = 1'b0; Viol = 1'b0; if (fwftmod == 1'b1) begin EFNeg_zd = 1'b1; FFNeg_zd = 1'b0; end else begin EFNeg_zd = 1'b0; FFNeg_zd = 1'b1; end Qreg = 40'b0; bm_Incnt = 1'b0; bm_Outcnt= 1'b0; end endtask task write_register; begin if (memory_model == mapped) begin if (fs_Incnt==0) tmp_ser_in = 34'b0; if (fs_Incnt<16) begin tmp_ser_in[fs_Incnt] = SI; fs_Incnt=fs_Incnt+1; paeoff= tmp_ser_in[15:0]; end else begin tmp_ser_in[fs_Incnt]= SI; fs_Incnt=fs_Incnt+1; pafoff= tmp_ser_in[31:16]; end if (fs_Incnt>31) begin fs_Incnt=0; pafoff=TotalLoc1-pafoff; end end else if (memory_model == normal) begin if (fs_Incnt==0) tmp_ser_in = 34'b0; if (fs_Incnt<17) begin tmp_ser_in[fs_Incnt]= SI; fs_Incnt=fs_Incnt+1; paeoff= tmp_ser_in[16:0]; end else begin tmp_ser_in[fs_Incnt]= SI; fs_Incnt=fs_Incnt+1; pafoff= tmp_ser_in[33:17]; end if (fs_Incnt>33) begin fs_Incnt=0; pafoff=TotalLoc-pafoff; end end end endtask task read_register; begin if (memory_model == mapped) begin if (fs_Incnt < 32) begin SO_zd = tmp_ser_in[fs_Incnt]; fs_Incnt=fs_Incnt+1; end if (fs_Incnt >= 32) fs_Incnt=0; end else if (memory_model == normal) begin if (fs_Incnt < 34) begin SO_zd = tmp_ser_in[fs_Incnt]; fs_Incnt=fs_Incnt+1; end if (fs_Incnt >= 34) fs_Incnt=0; end end endtask endmodule module BUFFER (OUT,IN); input IN; output OUT; buf ( OUT, IN); endmodule