//////////////////////////////////////////////////////////////////////////////
//  File name : idt72t36135m.v
//////////////////////////////////////////////////////////////////////////////
//  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
//
//  This program is free software; you can redistribute it and/or modify
//  it under the terms of the GNU General Public License version 2 as
//  published by the Free Software Foundation.
//
//  MODIFICATION HISTORY :
//
//  version: | author:    | mod date: | changes made:
//   V1.0      A.Anic       05 Dec 12   Initial release
//////////////////////////////////////////////////////////
//  PART DESCRIPTION:
//
//  Library:        FIFO
//  Technology:     CMOS
//  Part:        IDT72T36135M
//
//  Description: 2.5V 18M-BIT HIGH-SPEED FIFO 36-BIT CONFIGURATIONS 524,288x36
//
//////////////////////////////////////////////////////////////////////////////
//  Known Bugs:
//
//////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION                                                       //
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns

module idt72t36135m
    (
     D0      ,
     D1      ,
     D2      ,
     D3      ,
     D4      ,
     D5      ,
     D6      ,
     D7      ,
     D8      ,
     D9      ,
     D10     ,
     D11     ,
     D12     ,
     D13     ,
     D14     ,
     D15     ,
     D16     ,
     D17     ,
     D18     ,
     D19     ,
     D20     ,
     D21     ,
     D22     ,
     D23     ,
     D24     ,
     D25     ,
     D26     ,
     D27     ,
     D28     ,
     D29     ,
     D30     ,
     D31     ,
     D32     ,
     D33     ,
     D34     ,
     D35     ,

     ASYRNeg ,
     ASYWNeg ,
     FSEL0   ,
     FSEL1   ,
     FWFT    ,
     LDNeg   ,
     MARK    ,
     OENeg   ,
     MRSNeg  ,
     PFM     ,
     PRSNeg  ,
     RCLK    ,
     RENNeg  ,
     RCSNeg  ,
     RTNeg   ,
     SENNeg  ,
     SCLK    ,
     WCLK    ,
     WENNeg  ,
     WCSNeg  ,

     EF1Neg  ,
     EF2Neg  ,
     FF1Neg  ,
     FF2Neg  ,
     PAE1Neg ,
     PAE2Neg ,
     PAF1Neg ,
     PAF2Neg ,

     Q0      ,
     Q1      ,
     Q2      ,
     Q3      ,
     Q4      ,
     Q5      ,
     Q6      ,
     Q7      ,
     Q8      ,
     Q9      ,
     Q10     ,
     Q11     ,
     Q12     ,
     Q13     ,
     Q14     ,
     Q15     ,
     Q16     ,
     Q17     ,
     Q18     ,
     Q19     ,
     Q20     ,
     Q21     ,
     Q22     ,
     Q23     ,
     Q24     ,
     Q25     ,
     Q26     ,
     Q27     ,
     Q28     ,
     Q29     ,
     Q30     ,
     Q31     ,
     Q32     ,
     Q33     ,
     Q34     ,
     Q35

     );

    ////////////////////////////////////////////////////////////////////////
    // Port / Part Pin Declarations
    ////////////////////////////////////////////////////////////////////////

    input  D35  ;
    input  D34  ;
    input  D33  ;
    input  D32  ;
    input  D31  ;
    input  D30  ;
    input  D29  ;
    input  D28  ;
    input  D27  ;
    input  D26  ;
    input  D25  ;
    input  D24  ;
    input  D23  ;
    input  D22  ;
    input  D21  ;
    input  D20  ;
    input  D19  ;
    input  D18  ;
    input  D17  ;
    input  D16  ;
    input  D15  ;
    input  D14  ;
    input  D13  ;
    input  D12  ;
    input  D11  ;
    input  D10  ;
    input  D9   ;
    input  D8   ;
    input  D7   ;
    input  D6   ;
    input  D5   ;
    input  D4   ;
    input  D3   ;
    input  D2   ;
    input  D1   ;
    input  D0   ;

    input  ASYRNeg ;
    input  ASYWNeg ;
    input  FSEL0   ;
    input  FSEL1   ;
    input  FWFT    ;
    input  LDNeg   ;
    input  MARK    ;
    input  OENeg   ;
    input  MRSNeg  ;
    input  PFM     ;
    input  PRSNeg  ;
    input  RCLK    ;
    input  RENNeg  ;
    input  RCSNeg  ;
    input  RTNeg   ;
    input  SENNeg  ;
    input  SCLK    ;
    input  WCLK    ;
    input  WENNeg  ;
    input  WCSNeg  ;

    output  EF1Neg  ;
    output  EF2Neg  ;
    output  FF1Neg  ;
    output  FF2Neg  ;
    output  PAE1Neg ;
    output  PAE2Neg ;
    output  PAF1Neg ;
    output  PAF2Neg ;

    output  Q35  ;
    output  Q34  ;
    output  Q33  ;
    output  Q32  ;
    output  Q31  ;
    output  Q30  ;
    output  Q29  ;
    output  Q28  ;
    output  Q27  ;
    output  Q26  ;
    output  Q25  ;
    output  Q24  ;
    output  Q23  ;
    output  Q22  ;
    output  Q21  ;
    output  Q20  ;
    output  Q19  ;
    output  Q18  ;
    output  Q17  ;
    output  Q16  ;
    output  Q15  ;
    output  Q14  ;
    output  Q13  ;
    output  Q12  ;
    output  Q11  ;
    output  Q10  ;
    output  Q9   ;
    output  Q8   ;
    output  Q7   ;
    output  Q6   ;
    output  Q5   ;
    output  Q4   ;
    output  Q3   ;
    output  Q2   ;
    output  Q1   ;
    output  Q0   ;

    // interconnect path delay signals

    wire D0_ipd   ;
    wire D1_ipd   ;
    wire D2_ipd   ;
    wire D3_ipd   ;
    wire D4_ipd   ;
    wire D5_ipd   ;
    wire D6_ipd   ;
    wire D7_ipd   ;
    wire D8_ipd   ;
    wire D9_ipd   ;
    wire D10_ipd  ;
    wire D11_ipd  ;
    wire D12_ipd  ;
    wire D13_ipd  ;
    wire D14_ipd  ;
    wire D15_ipd  ;
    wire D16_ipd  ;
    wire D17_ipd  ;
    wire D18_ipd  ;
    wire D19_ipd  ;
    wire D20_ipd  ;
    wire D21_ipd  ;
    wire D22_ipd  ;
    wire D23_ipd  ;
    wire D24_ipd  ;
    wire D25_ipd  ;
    wire D26_ipd  ;
    wire D27_ipd  ;
    wire D28_ipd  ;
    wire D29_ipd  ;
    wire D30_ipd  ;
    wire D31_ipd  ;
    wire D32_ipd  ;
    wire D33_ipd  ;
    wire D34_ipd  ;
    wire D35_ipd  ;

    wire [35 : 0 ] DIn;
    assign        DIn = {D35_ipd ,
                         D34_ipd ,
                         D33_ipd ,
                         D32_ipd ,
                         D31_ipd ,
                         D30_ipd ,
                         D29_ipd ,
                         D28_ipd ,
                         D27_ipd ,
                         D26_ipd ,
                         D25_ipd ,
                         D24_ipd ,
                         D23_ipd ,
                         D22_ipd ,
                         D21_ipd ,
                         D20_ipd ,
                         D19_ipd ,
                         D18_ipd ,
                         D17_ipd ,
                         D16_ipd ,
                         D15_ipd ,
                         D14_ipd ,
                         D13_ipd ,
                         D12_ipd ,
                         D11_ipd ,
                         D10_ipd ,
                         D9_ipd ,
                         D8_ipd ,
                         D7_ipd ,
                         D6_ipd ,
                         D5_ipd ,
                         D4_ipd ,
                         D3_ipd ,
                         D2_ipd ,
                         D1_ipd ,
                         D0_ipd };

    wire ASYRNeg_ipd  ;
    wire ASYWNeg_ipd  ;
    wire FSEL0_ipd    ;
    wire FSEL1_ipd    ;
    wire FWFT_ipd     ;
    wire LDNeg_ipd    ;
    wire MARK_ipd     ;
    wire OENeg_ipd    ;
    wire MRSNeg_ipd   ;
    wire PFM_ipd      ;
    wire PRSNeg_ipd   ;
    wire RCLK_ipd     ;
    wire RENNeg_ipd   ;
    wire RCSNeg_ipd   ;
    wire RTNeg_ipd    ;
    wire SENNeg_ipd   ;
    wire SCLK_ipd     ;
    wire WCLK_ipd     ;
    wire WENNeg_ipd   ;
    wire WCSNeg_ipd   ;

    wire SCLK_d;
    wire WCLK_d;

    reg [35 : 0]   QOut_zd;

    reg [1:2]      EFNeg_zd;
    reg [1:2]      FFNeg_zd;
    reg [1:2]      PAENeg_zd;
    reg [1:2]      PAFNeg_zd;

    parameter     TimingModel = "DefaultTimingModel";
    parameter     PartID = "idt72t36135m";
    parameter     MaxData = 262143;
    parameter     TotalLoc  = 524287;
    parameter     DataWidth = 36;

    parameter      Synchronous   = 1'b0;
    parameter      Asynchronous  = 1'b1;

    parameter      no            = 1'b0;
    parameter      yes           = 1'b1;

    parameter      false         = 1'b0;
    parameter      true          = 1'b1;

    parameter      Serial        = 1'b0;
    parameter      Parallel      = 1'b1;

    parameter      IDTStandard   = 1'b0;
    parameter      FWFTMode      = 1'b1;

    parameter      LSBEmptyOffset   = 2'b00;
    parameter      MSBEmptyOffset   = 2'b01;
    parameter      LSBFullOffset    = 2'b10;
    parameter      MSBFullOffset    = 2'b11;

    parameter      marked     = 2'b00;
    parameter      initiated  = 2'b01;
    parameter      hold       = 2'b10;
    parameter      done       = 2'b11;

    parameter      Const0 = 1'b0;
    parameter      Const1 = 1'b1;

    reg            FlagForDelay;
    reg            FromRCLK;
    reg            FromOE;
    reg            Reset;
    reg            Enwrite;
    reg            PaLdEmptyOk;
    reg            PaLdEmptyEnd;
    reg            SerLdEnd;
    reg            SerLdOk;
    reg            ResetEF;
    reg            SetOR;
    reg            ResetFF;
    reg            SetPAF;
    reg            SetPAFabd;
    reg            SetPAF_1;
    reg            ResetPAFabd;
    reg            ResetPAF;
    reg            ResetPAF_1;
    reg            ResetOR;
    reg            SetIR;
    reg            ResetPAE;
    reg            ResetPAEabd;
    reg            ResetPAE_1;
    reg            SetPAE_1;
    reg            SetPAE;
    reg            SetPAEabd;
    reg            ResPAE_Ret;
    reg            SetPAE_Ret;
    reg            PaLdFullOk;
    reg            PaLdFullEnd;
    reg            FirstWord;
    reg            EnFirstWord;
    reg            EnReadOffs;
    reg            CondAbd;
    reg            FlagAbd;
    reg            FlagForOE;
    reg            FlagRCS;
    reg            FlagRCSNeg;
    reg            FlagRPE;

    reg            CopyEFNeg;
    reg            CopyFFNeg;
    reg            CopyPAF;
    reg            CopyPAE;

    reg            ProgFlagMode;
    reg            ProgramMode;
    reg            ReadOperation;
    reg            WriteOperation;
    reg            Mode;

    reg[0:1]       Retransmit;
    reg[0:1]       ByteOffset;
    reg[0:1]       ReadByteOffset;

    integer        MemDataLow [0:TotalLoc];
    integer        MemDataHigh[0:TotalLoc];

    integer        FullOffset;
    integer        EmptyOffset;
    integer        ValueForPAE;
    integer        ValueForPAF;
    integer        WrPointer;
    integer        RdPointer;
    integer        OldRdPointer;
    integer        RefPointer;
    integer        CntRCLKforResEF;
    integer        MarkedPointer;
    integer        CntWCLKforResFF;
    integer        CntRCLKforSetOR;
    integer        CntRCLKforFirstWord;
    integer        CntWCLKforSetPAF;
    integer        CntWCLKforSetPAF_1;
    integer        CntWCLKforResPAF;
    integer        CntWCLKforResPAF_1;
    integer        CntWCLKforSetIR;
    integer        CntRCLKforSetPAE;
    integer        CntRCLKforSetPAE_1;
    integer        CntRCLKforResPAE;
    integer        CntRCLKforResPAE_1;
    integer        CountForSerial;

    reg [17:0]    TmpMemLocRead_H;
    reg [17:0]    TmpMemLocRead_L;
    reg [35:0]    TmpMemLocRead;
    reg [35:0]    TmpMemLocOE;

    reg [37:0]    TmpOffset;
    reg [18:0]    TmpEmptyOffset;
    reg [18:0]    TmpFullOffset;

    reg [18:0]    TmpOffsetRead;

    reg           FlagWCLKskew2;
    reg           FlagWCLKskew1;
    reg           FlagRCLKskew2;
    reg           FlagRCLKskew1;

    reg           Viol = 1'b0;

    time          time_OE;
    time          time_RCLK;
    time          TimeForFlag;
    time          TimeForFlag_1;
    time          RCLKASY_01;
    time          RCLKSY_01;
    time          OEASY_01;
    time          OESY_01;
    time          tRPE;

    ///////////////////////////////////////////////////////////////////////////
    //Interconnect Path Delay Section
    ///////////////////////////////////////////////////////////////////////////

    buf   (D0_ipd , D0);
    buf   (D1_ipd , D1);
    buf   (D2_ipd , D2);
    buf   (D3_ipd , D3);
    buf   (D4_ipd , D4);
    buf   (D5_ipd , D5);
    buf   (D6_ipd , D6);
    buf   (D7_ipd , D7);
    buf   (D8_ipd , D8);
    buf   (D9_ipd , D9);
    buf   (D10_ipd, D10);
    buf   (D11_ipd, D11);
    buf   (D12_ipd, D12);
    buf   (D13_ipd, D13);
    buf   (D14_ipd, D14);
    buf   (D15_ipd, D15);
    buf   (D16_ipd, D16);
    buf   (D17_ipd, D17);
    buf   (D18_ipd, D18);
    buf   (D19_ipd, D19);
    buf   (D20_ipd, D20);
    buf   (D21_ipd, D21);
    buf   (D22_ipd, D22);
    buf   (D23_ipd, D23);
    buf   (D24_ipd, D24);
    buf   (D25_ipd, D25);
    buf   (D26_ipd, D26);
    buf   (D27_ipd, D27);
    buf   (D28_ipd, D28);
    buf   (D29_ipd, D29);
    buf   (D30_ipd, D30);
    buf   (D31_ipd, D31);
    buf   (D32_ipd, D32);
    buf   (D33_ipd, D33);
    buf   (D34_ipd, D34);
    buf   (D35_ipd, D35);

    buf   (ASYRNeg_ipd , ASYRNeg );
    buf   (ASYWNeg_ipd , ASYWNeg );
    buf   (FSEL0_ipd   , FSEL0   );
    buf   (FSEL1_ipd   , FSEL1   );
    buf   (FWFT_ipd    , FWFT    );
    buf   (LDNeg_ipd   , LDNeg   );
    buf   (MARK_ipd    , MARK    );
    buf   (OENeg_ipd   , OENeg   );
    buf   (MRSNeg_ipd  , MRSNeg  );
    buf   (PFM_ipd     , PFM     );
    buf   (PRSNeg_ipd  , PRSNeg  );
    buf   (RCLK_ipd    , RCLK    );
    buf   (RENNeg_ipd  , RENNeg  );
    buf   (RCSNeg_ipd  , RCSNeg  );
    buf   (RTNeg_ipd   , RTNeg   );
    buf   (SENNeg_ipd  , SENNeg  );
    buf   (SCLK_ipd    , SCLK    );
    buf   (WCLK_ipd    , WCLK    );
    buf   (WENNeg_ipd  , WENNeg  );
    buf   (WCSNeg_ipd  , WCSNeg  );

    ///////////////////////////////////////////////////////////////////////////
    // Propagation  delay Section
    ///////////////////////////////////////////////////////////////////////////

    nmos   (Q35,   QOut_zd[35] , 1);
    nmos   (Q34,   QOut_zd[34] , 1);
    nmos   (Q33,   QOut_zd[33] , 1);
    nmos   (Q32,   QOut_zd[32] , 1);
    nmos   (Q31,   QOut_zd[31] , 1);
    nmos   (Q30,   QOut_zd[30] , 1);
    nmos   (Q29,   QOut_zd[29] , 1);
    nmos   (Q28,   QOut_zd[28] , 1);
    nmos   (Q27,   QOut_zd[27] , 1);
    nmos   (Q26,   QOut_zd[26] , 1);
    nmos   (Q25,   QOut_zd[25] , 1);
    nmos   (Q24,   QOut_zd[24] , 1);
    nmos   (Q23,   QOut_zd[23] , 1);
    nmos   (Q22,   QOut_zd[22] , 1);
    nmos   (Q21,   QOut_zd[21] , 1);
    nmos   (Q20,   QOut_zd[20] , 1);
    nmos   (Q19,   QOut_zd[19] , 1);
    nmos   (Q18,   QOut_zd[18] , 1);
    nmos   (Q17,   QOut_zd[17] , 1);
    nmos   (Q16,   QOut_zd[16] , 1);
    nmos   (Q15,   QOut_zd[15] , 1);
    nmos   (Q14,   QOut_zd[14] , 1);
    nmos   (Q13,   QOut_zd[13] , 1);
    nmos   (Q12,   QOut_zd[12] , 1);
    nmos   (Q11,   QOut_zd[11] , 1);
    nmos   (Q10,   QOut_zd[10] , 1);
    nmos   (Q9 ,   QOut_zd[9]  , 1);
    nmos   (Q8 ,   QOut_zd[8]  , 1);
    nmos   (Q7 ,   QOut_zd[7]  , 1);
    nmos   (Q6 ,   QOut_zd[6]  , 1);
    nmos   (Q5 ,   QOut_zd[5]  , 1);
    nmos   (Q4 ,   QOut_zd[4]  , 1);
    nmos   (Q3 ,   QOut_zd[3]  , 1);
    nmos   (Q2 ,   QOut_zd[2]  , 1);
    nmos   (Q1 ,   QOut_zd[1]  , 1);
    nmos   (Q0 ,   QOut_zd[0]  , 1);

    nmos   (EF1Neg  , EFNeg_zd[1] , 1);
    nmos   (EF2Neg  , EFNeg_zd[2] , 1);
    nmos   (FF1Neg  , FFNeg_zd[1] , 1);
    nmos   (FF2Neg  , FFNeg_zd[2] , 1);
    nmos   (PAE1Neg , PAENeg_zd[1] , 1);
    nmos   (PAE2Neg , PAENeg_zd[2] , 1);
    nmos   (PAF1Neg , PAFNeg_zd[1] , 1);
    nmos   (PAF2Neg , PAFNeg_zd[2] , 1);

// Needed for Checks violation
    assign #0.5 WCLK_d = WCLK;
    assign #0.5 SCLK_d = SCLK;

 // Needed for TimingChecks
 // VHDL CheckEnable Equivalent

    wire OE_Q0_SYN;
    assign OE_Q0_SYN = (FromOE == true || FlagForDelay) && ASYRNeg;
    wire OE_Q0_ASYN;
    assign OE_Q0_ASYN = (FromOE == true || FlagForDelay) && ~ASYRNeg;
    wire RCLK_Q0_SYN;
    assign RCLK_Q0_SYN = FromRCLK == true && ASYRNeg;
    wire RCLK_Q0_ASYN;
    assign RCLK_Q0_ASYN = FromRCLK == true && ~ASYRNeg;
    wire setup_RENNeg;
    assign setup_RENNeg = RENNeg && ~RTNeg;
    wire setup_WENNeg;
    assign setup_WENNeg = WENNeg && ~RTNeg;

    specify
        // tipd delays: interconnect path delays , mapped to input port delays.
        // In Verilog is not necessary to declare any tipd_ delay variables,
        // they can be taken from SDF file
        // With all the other delays real delays would be taken from SDF file

                // tpd delays:
        // tA
        specparam   tpd_RCLK_Q0_SYN_EQ_1      = 1;
        specparam   tpd_RCLK_Q0_ASYN_EQ_1     = 1;
        // tOLZ,tOHZ,tOE
        specparam   tpd_OENeg_Q0_SYN_EQ_1     = 1;
        specparam   tpd_OENeg_Q0_ASYN_EQ_1    = 1;

        // tRSF
        specparam   tpd_MRSNeg_EFNeg     =  1;
        specparam   tpd_MRSNeg_FFNeg     =  1;
        specparam   tpd_MRSNeg_PAENeg    =  1;
        specparam   tpd_MRSNeg_PAFNeg    =  1;
        specparam   tpd_MRSNeg_Q0        =  1;
        specparam   tpd_PRSNeg_EFNeg     =  1;
        specparam   tpd_PRSNeg_FFNeg     =  1;
        specparam   tpd_PRSNeg_PAENeg    =  1;
        specparam   tpd_PRSNeg_PAFNeg    =  1;
        specparam   tpd_PRSNeg_Q0        =  1;

        // tWFF,tREF,tPAFS,tPAES,tPAFA,tPAEA,tHF
        specparam   tpd_WCLK_FFNeg_SYN_EQ_1   =  1;
        specparam   tpd_WCLK_FFNeg_ASYN_EQ_1  =  1;
        specparam   tpd_RCLK_FFNeg            =  1;
        specparam   tpd_RCLK_EFNeg_SYN_EQ_1   =  1;
        specparam   tpd_RCLK_EFNeg_ASYN_EQ_1  =  1;
        specparam   tpd_WCLK_EFNeg            =  1;
        specparam   tpd_RCLK_EFNeg            =  1;
        specparam   tpd_WCLK_PAFNeg_ASYN_EQ_1 =  1;
        specparam   tpd_WCLK_PAFNeg_SYN_EQ_1  =  1;
        specparam   tpd_RCLK_PAFNeg           =  1;
        specparam   tpd_RCLK_PAENeg_ASYN_EQ_1 =  1;
        specparam   tpd_RCLK_PAENeg_SYN_EQ_1  =  1;
        specparam   tpd_WCLK_PAENeg           =  1;

        // tsetup values: setup times
        // tDS
        specparam   tsetup_D0_WCLK      =  1;
        specparam   tsetup_FWFT_SCLK    =  1;

        // tENS,tLDS,tWCSS
        specparam   tsetup_WENNeg_WCLK   =  1;
        specparam   tsetup_LDNeg_WCLK    =  1;
        specparam   tsetup_WCSNeg_WCLK   =  1;
        specparam   tsetup_LDNeg_RCLK    =  1;
        specparam   tsetup_RENNeg_RCLK   =  1;
        specparam   tsetup_WENNeg_RCLK   =  1;
        specparam   tsetup_RTNeg_RCLK    =  1;
        specparam   tsetup_RCSNeg_RCLK   =  1;
        specparam   tsetup_MARK_RCLK     =  1;
        specparam   tsetup_LDNeg_SCLK    =  1;
        specparam   tsetup_SENNeg_SCLK   =  1;

        // tRSS
        specparam   tsetup_RENNeg_MRSNeg  = 1;
        specparam   tsetup_WENNeg_MRSNeg  = 1;
        specparam   tsetup_FWFT_MRSNeg    = 1;
        specparam   tsetup_LDNeg_MRSNeg   = 1;
        specparam   tsetup_FSEL0_MRSNeg   = 1;
        specparam   tsetup_FSEL1_MRSNeg   = 1;
        specparam   tsetup_PFM_MRSNeg     = 1;
        specparam   tsetup_RTNeg_MRSNeg   = 1;
        specparam   tsetup_SENNeg_MRSNeg  = 1;
        specparam   tsetup_RENNeg_PRSNeg  = 1;
        specparam   tsetup_WENNeg_PRSNeg  = 1;
        specparam   tsetup_RTNeg_PRSNeg   = 1;
        specparam   tsetup_SENNeg_PRSNeg  = 1;

        // thold values: hold times
        // tDH
        specparam   thold_D0_WCLK    = 1;
        specparam   thold_FWFT_SCLK  = 1;

        // tENH,tLDH,tWCSH
        specparam   thold_WENNeg_WCLK  = 1;
        specparam   thold_LDNeg_WCLK   = 1;
        specparam   thold_WCSNeg_WCLK  = 1;
        specparam   thold_LDNeg_RCLK   = 1;
        specparam   thold_RENNeg_RCLK  = 1;
        specparam   thold_RTNeg_RCLK   = 1;
        specparam   thold_RCSNeg_RCLK  = 1;
        specparam   thold_MARK_RCLK    = 1;
        specparam   thold_LDNeg_SCLK   = 1;
        specparam   thold_SENNeg_SCLK  = 1;

        // tRSR
        specparam   thold_RENNeg_MRSNeg  = 1;
        specparam   thold_WENNeg_MRSNeg  = 1;
        specparam   thold_FWFT_MRSNeg    = 1;
        specparam   thold_LDNeg_MRSNeg   = 1;
        specparam   thold_RENNeg_PRSNeg  = 1;
        specparam   thold_WENNeg_PRSNeg  = 1;

        // tpw values: pulse widths
        // tCLKL, tCLKH
        specparam   tpw_WCLK_SYN_EQ_1_negedge   = 1;
        specparam   tpw_WCLK_ASYN_EQ_1_negedge  = 1;
        specparam   tpw_WCLK_SYN_EQ_1_posedge   = 1;
        specparam   tpw_WCLK_ASYN_EQ_1_posedge  = 1;
        specparam   tpw_RCLK_SYN_EQ_1_negedge   = 1;
        specparam   tpw_RCLK_ASYN_EQ_1_negedge  = 1;
        specparam   tpw_RCLK_SYN_EQ_1_posedge   = 1;
        specparam   tpw_RCLK_ASYN_EQ_1_posedge  = 1;
        specparam   tpw_SCLK_posedge            = 1;
        specparam   tpw_SCLK_negedge            = 1;

        // tPW
        specparam   tpw_MRSNeg_negedge  = 1;
        specparam   tpw_PRSNeg_negedge  = 1;

        // tperiod values
        // tCLK
        specparam   tperiod_WCLK_SYN_EQ_1_posedge   = 1;
        specparam   tperiod_WCLK_ASYN_EQ_1_posedge  = 1;
        specparam   tperiod_RCLK_SYN_EQ_1_posedge   = 1;
        specparam   tperiod_RCLK_ASYN_EQ_1_posedge  = 1;
        specparam   tperiod_SCLK_posedge            = 1;

        // tSKEW1 (skew time)
        specparam   tdevice_SKEW1  = 5;
        // tSKEW2 (skew time)
        specparam   tdevice_SKEW2  = 6;

///////////////////////////////////////////////////////////////////////////////
// Input Port  Delays  don't require Verilog description
///////////////////////////////////////////////////////////////////////////////
// Path delays                                                               //
///////////////////////////////////////////////////////////////////////////////

        (MRSNeg *> EF1Neg) = tpd_MRSNeg_EFNeg;
        (MRSNeg *> EF2Neg) = tpd_MRSNeg_EFNeg;
        (PRSNeg *> EF1Neg) = tpd_PRSNeg_EFNeg;
        (PRSNeg *> EF2Neg) = tpd_PRSNeg_EFNeg;
        if (~ASYRNeg && CopyEFNeg)  (WCLK *> EF1Neg) = tpd_WCLK_EFNeg;
        if (~ASYRNeg && CopyEFNeg)  (WCLK *> EF2Neg) = tpd_WCLK_EFNeg;
        if (~ASYRNeg && ~CopyEFNeg) (RCLK *> EF1Neg) = tpd_RCLK_EFNeg_ASYN_EQ_1;
        if (~ASYRNeg && ~CopyEFNeg) (RCLK *> EF2Neg) = tpd_RCLK_EFNeg_ASYN_EQ_1;
        if (ASYRNeg)  (RCLK  *> EF1Neg) = tpd_RCLK_EFNeg_SYN_EQ_1;
        if (ASYRNeg)  (RCLK  *> EF2Neg) = tpd_RCLK_EFNeg_SYN_EQ_1;

        (MRSNeg *> FF1Neg) = tpd_MRSNeg_FFNeg;
        (MRSNeg *> FF2Neg) = tpd_MRSNeg_FFNeg;
        (PRSNeg *> FF1Neg) = tpd_PRSNeg_FFNeg;
        (PRSNeg *> FF2Neg) = tpd_PRSNeg_FFNeg;
        if (~ASYWNeg && CopyFFNeg)  (RCLK *> FF1Neg) = tpd_RCLK_FFNeg;
        if (~ASYWNeg && CopyFFNeg)  (RCLK *> FF2Neg) = tpd_RCLK_FFNeg;
        if (~ASYWNeg && ~CopyFFNeg) (WCLK *> FF1Neg) = tpd_WCLK_FFNeg_ASYN_EQ_1;
        if (~ASYWNeg && ~CopyFFNeg) (WCLK *> FF2Neg) = tpd_WCLK_FFNeg_ASYN_EQ_1;
        if (ASYWNeg)  (WCLK  *> FF1Neg) = tpd_WCLK_FFNeg_SYN_EQ_1;
        if (ASYWNeg)  (WCLK  *> FF2Neg) = tpd_WCLK_FFNeg_SYN_EQ_1;

        (MRSNeg *> PAE1Neg) = tpd_MRSNeg_PAENeg;
        (MRSNeg *> PAE2Neg) = tpd_MRSNeg_PAENeg;
        (PRSNeg *> PAE1Neg) = tpd_PRSNeg_PAENeg;
        (PRSNeg *> PAE2Neg) = tpd_PRSNeg_PAENeg;
        if (ProgFlagMode == Asynchronous && ~FlagAbd && ~CopyPAE)
                                  (RCLK *> PAE1Neg) = tpd_RCLK_PAENeg_ASYN_EQ_1;
        if (ProgFlagMode == Asynchronous && ~FlagAbd && ~CopyPAE)
                                  (RCLK *> PAE2Neg) = tpd_RCLK_PAENeg_ASYN_EQ_1;
        if (ProgFlagMode == Synchronous || FlagAbd)
                                   (RCLK *> PAE1Neg) = tpd_RCLK_PAENeg_SYN_EQ_1;
        if (ProgFlagMode == Synchronous || FlagAbd)
                                   (RCLK *> PAE2Neg) = tpd_RCLK_PAENeg_SYN_EQ_1;
        if (ProgFlagMode == Asynchronous && CopyPAE)
                                   (WCLK *> PAE1Neg) = tpd_WCLK_PAENeg;
        if (ProgFlagMode == Asynchronous && CopyPAE)
                                   (WCLK *> PAE2Neg) = tpd_WCLK_PAENeg;

        (MRSNeg *> PAF1Neg) = tpd_MRSNeg_PAFNeg;
        (MRSNeg *> PAF2Neg) = tpd_MRSNeg_PAFNeg;
        (PRSNeg *> PAF1Neg) = tpd_PRSNeg_PAFNeg;
        (PRSNeg *> PAF2Neg) = tpd_PRSNeg_PAFNeg;
        if (ProgFlagMode == Asynchronous && ~FlagAbd && ~CopyPAF)
                                  (WCLK *> PAF1Neg) = tpd_WCLK_PAFNeg_ASYN_EQ_1;
        if (ProgFlagMode == Asynchronous && ~FlagAbd && ~CopyPAF)
                                  (WCLK *> PAF2Neg) = tpd_WCLK_PAFNeg_ASYN_EQ_1;
        if (ProgFlagMode == Synchronous || FlagAbd)
                                   (WCLK *> PAF1Neg) = tpd_WCLK_PAFNeg_SYN_EQ_1;
        if (ProgFlagMode == Synchronous || FlagAbd)
                                   (WCLK *> PAF2Neg) = tpd_WCLK_PAFNeg_SYN_EQ_1;
        if (ProgFlagMode == Asynchronous && CopyPAF)
                                   (RCLK *> PAF1Neg) = tpd_RCLK_PAFNeg;
        if (ProgFlagMode == Asynchronous && CopyPAF)
                                   (RCLK *> PAF2Neg) = tpd_RCLK_PAFNeg;

        if (~MRSNeg) (MRSNeg *> Q0)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q1)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q2)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q3)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q4)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q5)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q6)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q7)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q8)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q9)  = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q10) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q11) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q12) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q13) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q14) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q15) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q16) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q17) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q18) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q19) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q20) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q21) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q22) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q23) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q24) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q25) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q26) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q27) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q28) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q29) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q30) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q31) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q32) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q33) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q34) = tpd_MRSNeg_Q0;
        if (~MRSNeg) (MRSNeg *> Q35) = tpd_MRSNeg_Q0;

        if (~PRSNeg) (PRSNeg *> Q0)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q1)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q2)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q3)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q4)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q5)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q6)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q7)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q8)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q9)  = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q10) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q11) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q12) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q13) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q14) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q15) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q16) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q17) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q18) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q19) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q20) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q21) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q22) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q23) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q24) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q25) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q26) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q27) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q28) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q29) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q30) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q31) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q32) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q33) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q34) = tpd_PRSNeg_Q0;
        if (~PRSNeg) (PRSNeg *> Q35) = tpd_PRSNeg_Q0;

        if (OE_Q0_ASYN) (OENeg *> Q0)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q1)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q2)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q3)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q4)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q5)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q6)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q7)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q8)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q9)  = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q10) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q11) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q12) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q13) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q14) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q15) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q16) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q17) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q18) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q19) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q20) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q21) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q22) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q23) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q24) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q25) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q26) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q27) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q28) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q29) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q30) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q31) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q32) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q33) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q34) = tpd_OENeg_Q0_ASYN_EQ_1;
        if (OE_Q0_ASYN) (OENeg *> Q35) = tpd_OENeg_Q0_ASYN_EQ_1;

        if (OE_Q0_SYN) (OENeg *> Q0)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q1)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q2)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q3)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q4)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q5)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q6)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q7)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q8)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q9)  = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q10) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q11) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q12) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q13) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q14) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q15) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q16) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q17) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q18) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q19) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q20) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q21) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q22) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q23) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q24) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q25) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q26) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q27) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q28) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q29) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q30) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q31) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q32) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q33) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q34) = tpd_OENeg_Q0_SYN_EQ_1;
        if (OE_Q0_SYN) (OENeg *> Q35) = tpd_OENeg_Q0_SYN_EQ_1;

        if (RCLK_Q0_ASYN) (RCLK *> Q0)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q1)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q2)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q3)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q4)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q5)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q6)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q7)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q8)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q9)  = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q10) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q11) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q12) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q13) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q14) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q15) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q16) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q17) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q18) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q19) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q20) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q21) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q22) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q23) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q24) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q25) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q26) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q27) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q28) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q29) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q30) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q31) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q32) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q33) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q34) = tpd_RCLK_Q0_ASYN_EQ_1;
        if (RCLK_Q0_ASYN) (RCLK *> Q35) = tpd_RCLK_Q0_ASYN_EQ_1;

        if (RCLK_Q0_SYN) (RCLK *> Q0)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q1)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q2)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q3)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q4)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q5)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q6)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q7)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q8)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q9)  = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q10) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q11) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q12) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q13) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q14) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q15) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q16) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q17) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q18) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q19) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q20) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q21) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q22) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q23) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q24) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q25) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q26) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q27) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q28) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q29) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q30) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q31) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q32) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q33) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q34) = tpd_RCLK_Q0_SYN_EQ_1;
        if (RCLK_Q0_SYN) (RCLK *> Q35) = tpd_RCLK_Q0_SYN_EQ_1;

////////////////////////////////////////////////////////////////////////////////
// Timing Violation                                                           //
////////////////////////////////////////////////////////////////////////////////
        $setup ( D0 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D1 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D2 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D3 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D4 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D5 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D6 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D7 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D8 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D9 , posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D10, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D11, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D12, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D13, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D14, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D15, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D16, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D17, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D18, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D19, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D20, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D21, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D22, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D23, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D24, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D25, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D26, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D27, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D28, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D29, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D30, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D31, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D32, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D33, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D34, posedge WCLK,  tsetup_D0_WCLK, Viol);
        $setup ( D35, posedge WCLK,  tsetup_D0_WCLK, Viol);

        $setup ( FWFT,  posedge SCLK &&& (SENNeg===0), tsetup_FWFT_SCLK,  Viol);
        $setup ( WENNeg,posedge WCLK &&& (WENNeg===0), tsetup_WENNeg_WCLK,Viol);
        $setup ( RENNeg,posedge RCLK &&& (RENNeg===0), tsetup_RENNeg_RCLK,Viol);
        $setup ( RENNeg,posedge RCLK &&& setup_RENNeg,tsetup_RENNeg_RCLK,Viol);
        $setup ( WENNeg,posedge RCLK &&& setup_WENNeg,tsetup_WENNeg_RCLK,Viol);
        $setup ( MARK,  posedge RCLK &&& (MARK===1), tsetup_MARK_RCLK,  Viol);
        $setup ( SENNeg,posedge SCLK &&& (SENNeg===0), tsetup_SENNeg_SCLK,Viol);
        $setup ( RTNeg, posedge RCLK &&& (RTNeg===0),  tsetup_RTNeg_RCLK, Viol);
        $setup ( LDNeg, posedge RCLK &&& (LDNeg===0),  tsetup_LDNeg_RCLK, Viol);
        $setup ( LDNeg, posedge WCLK &&& (LDNeg===0), tsetup_LDNeg_WCLK, Viol);
        $setup ( LDNeg, posedge SCLK &&& (LDNeg===0), tsetup_LDNeg_SCLK, Viol);
        $setup ( WCSNeg,posedge WCLK &&& (WCSNeg===0),tsetup_WCSNeg_WCLK, Viol);
        $setup ( RCSNeg,posedge RCLK &&& (RCSNeg===0), tsetup_RCSNeg_RCLK,Viol);

        $setup ( RENNeg, negedge MRSNeg &&& (RENNeg===1),
                                          tsetup_RENNeg_MRSNeg, Viol);
        $setup ( WENNeg, negedge MRSNeg &&& (WENNeg===1),
                                          tsetup_WENNeg_MRSNeg, Viol);
        $setup ( FWFT,   negedge MRSNeg,  tsetup_FWFT_MRSNeg  , Viol);
        $setup ( LDNeg,  negedge MRSNeg,  tsetup_LDNeg_MRSNeg , Viol);
        $setup ( FSEL0,  negedge MRSNeg,  tsetup_FSEL0_MRSNeg , Viol);
        $setup ( FSEL1,  negedge MRSNeg,  tsetup_FSEL1_MRSNeg , Viol);
        $setup ( PFM,    negedge MRSNeg,  tsetup_PFM_MRSNeg   , Viol);
        $setup ( RTNeg,  negedge MRSNeg &&& (RTNeg===1),
                                          tsetup_RTNeg_MRSNeg , Viol);
        $setup ( SENNeg, negedge MRSNeg &&& (SENNeg===1),
                                          tsetup_SENNeg_MRSNeg, Viol);
        $setup ( RENNeg, negedge PRSNeg &&& (RENNeg===1),
                                          tsetup_RENNeg_PRSNeg, Viol);
        $setup ( WENNeg, negedge PRSNeg &&& (WENNeg===1),
                                          tsetup_WENNeg_PRSNeg, Viol);
        $setup ( RTNeg,  negedge PRSNeg &&& (RTNeg===1),
                                          tsetup_RTNeg_PRSNeg , Viol);
        $setup ( SENNeg, negedge PRSNeg &&& (SENNeg===1),
                                          tsetup_SENNeg_PRSNeg, Viol);

        $hold ( posedge WCLK, D0 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D1 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D2 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D3 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D4 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D5 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D6 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D7 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D8 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D9 ,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D10,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D11,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D12,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D13,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D14,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D15,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D16,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D17,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D18,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D19,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D20,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D21,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D22,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D23,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D24,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D25,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D26,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D27,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D28,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D29,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D30,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D31,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D32,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D33,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D34,  thold_D0_WCLK, Viol);
        $hold ( posedge WCLK, D35,  thold_D0_WCLK, Viol);

        $hold ( posedge SCLK &&& (SENNeg===0),FWFT,   thold_FWFT_SCLK,  Viol);
        $hold ( posedge WCLK &&& (WENNeg===0),WENNeg, thold_WENNeg_WCLK,Viol);
        $hold ( posedge RCLK &&& (RENNeg===0),RENNeg, thold_RENNeg_RCLK,Viol);
        $hold ( posedge RCLK &&& (MARK===1)  ,MARK,   thold_MARK_RCLK,  Viol);
        $hold ( posedge SCLK &&& (SENNeg===0),SENNeg, thold_SENNeg_SCLK,Viol);
        $hold ( posedge RCLK &&& (RTNeg===0) ,RTNeg,  thold_RTNeg_RCLK, Viol);
        $hold ( posedge RCLK &&& (LDNeg===0) ,LDNeg,  thold_LDNeg_RCLK, Viol);
        $hold ( posedge WCLK &&& (LDNeg===0) ,LDNeg,  thold_LDNeg_WCLK, Viol);
        $hold ( posedge SCLK &&& (LDNeg===0) ,LDNeg,  thold_LDNeg_SCLK, Viol);
        $hold ( posedge WCLK &&& (WCSNeg===0),WCSNeg, thold_WCSNeg_WCLK, Viol);
        $hold ( posedge RCLK &&& (RCSNeg===0),RCSNeg, thold_RCSNeg_RCLK,Viol);

        $hold ( posedge MRSNeg &&& (RENNeg===1),RENNeg,
                                                     thold_RENNeg_MRSNeg, Viol);
        $hold ( posedge MRSNeg &&& (WENNeg===1),WENNeg,
                                                     thold_WENNeg_MRSNeg, Viol);
        $hold ( posedge MRSNeg, FWFT,    thold_FWFT_MRSNeg  , Viol);
        $hold ( posedge MRSNeg, LDNeg,   thold_LDNeg_MRSNeg , Viol);

        $hold ( posedge PRSNeg &&& (RENNeg===1),RENNeg,
                                                     thold_RENNeg_PRSNeg, Viol);
        $hold ( posedge PRSNeg &&& (WENNeg===1),WENNeg,
                                                     thold_WENNeg_PRSNeg, Viol);

        $width (negedge WCLK &&& (ASYWNeg===1), tpw_WCLK_SYN_EQ_1_negedge);
        $width (negedge WCLK &&& (ASYWNeg===0), tpw_WCLK_ASYN_EQ_1_negedge);
        $width (posedge WCLK &&& (ASYWNeg===1), tpw_WCLK_SYN_EQ_1_posedge);
        $width (posedge WCLK &&& (ASYWNeg===0), tpw_WCLK_ASYN_EQ_1_posedge);
        $width (negedge RCLK &&& (ASYRNeg===1), tpw_WCLK_SYN_EQ_1_negedge);
        $width (negedge RCLK &&& (ASYRNeg===0), tpw_WCLK_ASYN_EQ_1_negedge);
        $width (posedge RCLK &&& (ASYRNeg===1), tpw_WCLK_SYN_EQ_1_posedge);
        $width (posedge RCLK &&& (ASYRNeg===0), tpw_WCLK_ASYN_EQ_1_posedge);
        $width (posedge SCLK ,                  tpw_SCLK_negedge);
        $width (negedge SCLK ,                  tpw_SCLK_negedge);
        $width (negedge MRSNeg ,                tpw_MRSNeg_negedge);
        $width (negedge PRSNeg ,                tpw_PRSNeg_negedge);

        $period (posedge RCLK &&& ASYRNeg===1, tperiod_RCLK_SYN_EQ_1_posedge);
        $period (posedge RCLK &&& ASYRNeg===0, tperiod_RCLK_ASYN_EQ_1_posedge);
        $period (posedge WCLK &&& ASYWNeg===1, tperiod_WCLK_SYN_EQ_1_posedge);
        $period (posedge WCLK &&& ASYWNeg===0, tperiod_WCLK_ASYN_EQ_1_posedge);
        $period (posedge SCLK, tperiod_SCLK_posedge);

    endspecify

////////////////////////////////////////////////////////////////////////////////
//      Main Behavior Block
////////////////////////////////////////////////////////////////////////////////

    initial
      begin
          Reset      = no;
          PAFNeg_zd  = 2'b11;
          CopyPAF    = 2'b11;
          PAENeg_zd  = 2'b00;
          CopyPAE    = 2'b00;
          FlagForDelay = 1'b0;
          FlagForOE    = 1'b0;
          FlagRCS      = 1'b0;
          FlagRCSNeg   = 1'b0;
          WrPointer    = 1'b0;
          RdPointer    = 1'b0;
          PaLdEmptyOk  = yes;
          PaLdFullOk   = yes;
          SerLdOk      = yes;
          EnReadOffs   = yes;
          ByteOffset      = LSBEmptyOffset;
          ReadByteOffset  = LSBEmptyOffset;
          TmpMemLocOE     = 36'h0000;
          TmpMemLocRead   = 36'h0000;
          Retransmit      = done;
          CountForSerial  = 1'b0;
          ResetOR         = no;
          ResetEF     = no;
          SetOR       = no;
          ResetFF     = no;
          SetPAF      = no;
          SetPAFabd   = no;
          SetPAF_1    = no;
          ResetPAF    = no;
          ResetPAFabd = no;
          ResetPAF_1  = no;
          SetIR       = no;
          ResetPAE    = no;
          ResetPAEabd = no;
          ResetPAE_1  = no;
          SetPAE_1    = no;
          SetPAE      = no;
          SetPAEabd   = no;
          PaLdEmptyEnd= no;
          SerLdEnd    = no;
          PaLdFullEnd = no;
          FirstWord   = no;
          EnFirstWord = no;
      end

////////////////////////////////////////////////////////////////////////////////
//      MRESET
////////////////////////////////////////////////////////////////////////////////

    always @(MRSNeg)
      begin
          if (~MRSNeg)
            begin
                Reset      = yes;
                Enwrite    = yes;
                PAFNeg_zd  = 2'b11;
                CopyPAF    = 2'b11;
                PAENeg_zd  = 2'b00;
                CopyPAE    = 2'b00;
                FlagForDelay = 1'b0;
                FlagForOE    = 1'b0;
                FlagRCS      = 1'b0;
                FlagRCSNeg   = 1'b0;
                WrPointer    = 1'b0;
                RdPointer    = 1'b0;
                PaLdEmptyOk  = yes;
                PaLdFullOk   = yes;
                SerLdOk      = yes;
                EnReadOffs   = yes;
                ByteOffset      = LSBEmptyOffset;
                ReadByteOffset  = LSBEmptyOffset;
                TmpMemLocOE     = 36'h0000;
                TmpMemLocRead   = 36'h0000;
                Retransmit      = done;
                CountForSerial  = 1'b0;
                ResetOR         = no;
                ResetEF     = no;
                SetOR       = no;
                ResetFF     = no;
                SetPAF      = no;
                SetPAFabd   = no;
                SetPAF_1    = no;
                ResetPAF    = no;
                ResetPAFabd = no;
                ResetPAF_1  = no;
                SetIR       = no;
                ResetPAE    = no;
                ResetPAEabd = no;
                ResetPAE_1  = no;
                SetPAE_1    = no;
                SetPAE      = no;
                SetPAEabd   = no;
                PaLdEmptyEnd= no;
                PaLdFullEnd = no;
                SerLdEnd    = no;
                FirstWord   = no;
                EnFirstWord = no;

                if (LDNeg)
                  begin
                      ProgramMode = Serial;
                      if (~FSEL1  && ~FSEL0)
                        begin
                            FullOffset  = 1023;
                            EmptyOffset = 1023;
                        end
                      else if (FSEL1  && ~FSEL0)
                        begin
                            FullOffset  = 31;
                            EmptyOffset = 31;
                        end
                      else if (~FSEL1  && FSEL0)
                        begin
                            FullOffset  = 15;
                            EmptyOffset = 15;
                        end
                      else if (FSEL1  && FSEL0)
                        begin
                            FullOffset  = 7;
                            EmptyOffset = 7;
                        end
                    end
                else if (~LDNeg)
                  begin
                      ProgramMode = Parallel;
                      if (~FSEL1  && ~FSEL0)
                        begin
                            FullOffset  = 127;
                            EmptyOffset = 127;
                        end
                      else if (FSEL1  && ~FSEL0)
                        begin
                            FullOffset  = 511;
                            EmptyOffset = 511;
                        end
                      else if (~FSEL1  && FSEL0)
                        begin
                            FullOffset  = 255;
                            EmptyOffset = 255;
                        end
                      else if (FSEL1  && FSEL0)
                        begin
                            FullOffset  = 63;
                            EmptyOffset = 63;
                        end
                  end

                ValueForPAE = EmptyOffset;
                ValueForPAF = TotalLoc - FullOffset;

                if (~PFM)
                    ProgFlagMode = Asynchronous;
                else if (PFM)
                  begin
                    ProgFlagMode = Synchronous;
                  end

                if (~FWFT)
                  begin
                      Mode = IDTStandard;
                      EFNeg_zd [1:2] = 2'b00;
                      FFNeg_zd [1:2]  = 2'b11;
                      CopyEFNeg = 2'b00;
                      CopyFFNeg = 2'b11;
                  end
                else if (FWFT)
                  begin
                      Mode = FWFTMode;
                      EFNeg_zd [1:2]  = 2'b11;
                      FFNeg_zd [1:2]  = 2'b00;
                      CopyEFNeg  = 2'b11;
                      CopyFFNeg  = 2'b00;
                  end

                if (~ASYRNeg)
                  begin
                      if (FWFT)
                        begin
                            $display ("Warning - FIFO must operate"&
                                             "in IDT Standard mode");
                            Mode = IDTStandard;
                        end
                      ReadOperation = Asynchronous;
                      TimeForFlag = RCLKASY_01;
                      TimeForFlag_1 = OEASY_01;
                  end
                else if (ASYRNeg)
                  begin
                      ReadOperation = Synchronous;
                      TimeForFlag = RCLKSY_01;
                      TimeForFlag_1 = OESY_01;
                  end

                if (~ASYWNeg)
                    WriteOperation = Asynchronous;
                else if (ASYWNeg)
                  begin
                    WriteOperation = Synchronous;
                  end

                if (~OENeg)
                    QOut_zd [35:0] = 36'h000000000;
                else if (OENeg)
                  begin
                    QOut_zd [35:0] = 36'hzzzzzzzzz;
                  end
            end
          else if (MRSNeg)
              Reset = no;
      end

////////////////////////////////////////////////////////////////////////////////
//      PRESET
////////////////////////////////////////////////////////////////////////////////
    always @(PRSNeg)
      begin
          if (~PRSNeg)
            begin
                Reset = no;
                PAFNeg_zd  = 2'b11;
                CopyPAF    = 2'b11;
                PAENeg_zd  = 2'b00;
                CopyPAE    = 2'b00;
                FlagForDelay = 1'b0;
                FlagForOE    = 1'b0;
                FlagRCS      = 1'b0;
                WrPointer    = 1'b0;
                RdPointer    = 1'b0;
                PaLdEmptyOk  = yes;
                PaLdFullOk   = yes;
                SerLdOk      = yes;
                EnReadOffs   = yes;
                ByteOffset      = LSBEmptyOffset;
                ReadByteOffset  = LSBEmptyOffset;
                TmpMemLocOE     = 36'h0000;
                TmpMemLocRead   = 36'h0000;
                Retransmit      = done;
                CountForSerial  = 1'b0;
                ResetOR         = no;
                ResetEF     = no;
                SetOR       = no;
                ResetFF     = no;
                SetPAF      = no;
                SetPAFabd   = no;
                SetPAF_1    = no;
                ResetPAF    = no;
                ResetPAFabd = no;
                ResetPAF_1  = no;
                SetIR       = no;
                ResetPAE    = no;
                ResetPAEabd = no;
                ResetPAE_1  = no;
                SetPAE_1    = no;
                SetPAE      = no;
                SetPAEabd   = no;
                PaLdEmptyEnd= no;
                PaLdFullEnd = no;
                SerLdEnd    = no;
                FirstWord   = no;
                EnFirstWord = no;
                if (Mode == IDTStandard)
                  begin

                      EFNeg_zd  = 2'b00;
                      FFNeg_zd  = 2'b11;
                      CopyEFNeg = 2'b00;
                      CopyFFNeg = 2'b11;
                  end
                else
                  begin

                      EFNeg_zd   = 2'b11;
                      FFNeg_zd   = 2'b00;
                      CopyEFNeg  = 2'b11;
                      CopyFFNeg  = 2'b00;
                  end
               if (~OENeg)
                   QOut_zd [35:0] = 36'h0000;
               else if (OENeg)
                   QOut_zd [35:0] = 36'hzzzz;
            end
          else if (PRSNeg)
              Reset = no;
      end

////////////////////////////////////////////////////////////////////////////////
//      WRITE
////////////////////////////////////////////////////////////////////////////////

    always @(posedge WCLK)
      begin
          FlagWCLKskew2 = 1'b1;
          FlagWCLKskew2 <= #tdevice_SKEW2 1'b0;
          FlagWCLKskew1 = 1'b1;
          FlagWCLKskew1 <= #tdevice_SKEW1 1'b0;
      end

   always @(posedge WCLK_d)
      begin
          if (Reset == no)
            begin
                if (Mode == IDTStandard)
                  begin
                    if (~WENNeg && CopyFFNeg && Enwrite == yes
                        && LDNeg && ~WCSNeg)
                      begin
                        if (~Viol)
                          begin
                            MemDataLow [WrPointer]  = DIn[17 : 0];
                            MemDataHigh [WrPointer] = DIn[35 : 18];
                          end
                        else
                          begin
                            MemDataLow [WrPointer]  = -1;
                            MemDataHigh [WrPointer] = -1;
                            Viol = 1'b0;
                          end
                        if (WrPointer == TotalLoc)
                            WrPointer = 0;
                        else
                            WrPointer =  WrPointer + 1;
                        if (ReadOperation == Synchronous)
                          begin
                            if (~CopyEFNeg)
                                if (ResetEF == no)
                                  begin
                                    ResetEF = yes;
                                    CntRCLKforResEF = 1;
                                  end
                          end
                        else
                          begin
                            EFNeg_zd [1:2] = 2'b11;
                            CopyEFNeg = 1'b1;
                          end
                        Pointer;
                        if (WrPointer == RefPointer)
                          begin
                            FFNeg_zd [1:2] = 2'b00;
                            CopyFFNeg = 1'b0;
                          end
                        SetFlagsWrite(
                                      ValueForPAE,
                                      ValueForPAF);
                      end
                  end
                else
                  begin
                    if (~WENNeg && ~CopyFFNeg && Enwrite == yes &&
                        LDNeg && ~WCSNeg)
                      begin
                        if (~Viol)
                          begin
                            MemDataLow [WrPointer]  = DIn[17 : 0];
                            MemDataHigh [WrPointer] = DIn[35 : 18];
                          end
                        else
                          begin
                            MemDataLow [WrPointer]  = -1;
                            MemDataHigh [WrPointer] = -1;
                            Viol = 1'b0;
                          end
                        if (WrPointer == TotalLoc)
                            WrPointer = 0;
                        else
                            WrPointer =  WrPointer + 1;
                        Pointer;
                        if (WrPointer == RefPointer)
                          begin
                            FFNeg_zd = 2'b11;
                            CopyFFNeg = 1'b1;
                          end
                        if (CopyEFNeg)
                          if (EnFirstWord == no)
                            begin
                              EnFirstWord = yes;
                              CntRCLKforFirstWord = 2;
                            end
                        SetFlagsWrite(
                                      ValueForPAE,
                                      ValueForPAF);
                      end
                  end

// Counting Write Cycles

                if (SetPAF == yes)
                    CountCLK
                           ( CntWCLKforSetPAF,
                             SetPAF,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             Const0,
                             Const0,
                             no);

                if (SetPAFabd == yes)
                    CountCLK
                           ( CntWCLKforSetPAF,
                             SetPAF,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             Const0,
                             Const0,
                             yes);

                if (SetPAF_1 == yes)
                    CountCLK
                           ( CntWCLKforSetPAF_1,
                             SetPAF_1,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             Const0,
                             Const0,
                             no);

                if (ResetPAF == yes)
                    CountCLK
                           ( CntWCLKforResPAF,
                             ResetPAF,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             FlagRCLKskew2,
                             Const1,
                             no);

                if (ResetPAFabd == yes)
                    CountCLK
                           ( CntWCLKforResPAF,
                             ResetPAFabd,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             Const0,
                             Const1,
                             yes);

                if (ResetPAF_1 == yes)
                    CountCLK
                           ( CntWCLKforResPAF_1,
                             ResetPAF_1,
                             CopyPAF,
                             PAFNeg_zd[1:2],
                             FlagRCLKskew2,
                             Const1,
                             no);

                if (ResetFF == yes)
                    CountCLK
                           ( CntWCLKforResFF,
                             ResetFF,
                             CopyFFNeg,
                             FFNeg_zd[1:2],
                             FlagRCLKskew1,
                             Const1,
                             no);

                if (SetIR == yes)
                    CountCLK
                           ( CntWCLKforSetIR,
                             SetIR,
                             CopyFFNeg,
                             FFNeg_zd[1:2],
                             FlagRCLKskew1,
                             Const0,
                             no);

// Parallel Loading Offset Registers

                if (ProgramMode == Parallel && Enwrite == yes)
                  begin
                    if (~WENNeg && RENNeg && SENNeg && ~LDNeg)
                      begin
                        ParallelLoad;
                        if (PaLdEmptyEnd == yes)
                          begin
                            PaLdEmptyEnd = no;
                            if (PaLdEmptyOk == yes)
                              begin
                                EmptyOffset = TmpEmptyOffset;
                                ValueForPAE =  EmptyOffset;
                                SetFlags(
                                          ValueForPAE,
                                          ValueForPAF);
                              end
                            PaLdEmptyOk = yes;
                          end
                        if (PaLdFullEnd == yes)
                          begin
                            PaLdFullEnd = no;
                            if (PaLdFullOk == yes)
                              begin
                                FullOffset = TmpFullOffset;
                                ValueForPAF = TotalLoc - FullOffset;
                                SetFlags(
                                         ValueForPAE,
                                         ValueForPAF);
                              end
                            PaLdFullOk = yes;
                          end
                      end
                  end

            end
      end

////////////////////////////////////////////////////////////////////////////////
//      READ
////////////////////////////////////////////////////////////////////////////////

    always @(posedge RCLK)
      begin
          if (Reset == no)
            begin
              FlagRCLKskew2 = 1'b1;
              FlagRCLKskew2 <= #tdevice_SKEW2 1'b0;
              FlagRCLKskew1 = 1'b1;
              FlagRCLKskew1 <= #tdevice_SKEW1 1'b0;
              FlagRCS = 1'b0;
              FlagRCSNeg = 1'b0;
              if (ReadOperation == Synchronous ||
                 (ReadOperation == Asynchronous &&  ~FlagRPE))
                begin
                  if (Mode == IDTStandard)
                    begin
                      if (MARK)
                        begin
                          if ((Retransmit == done) &&
                             (((WrPointer - RdPointer) >= 0 &&
                             (WrPointer - RdPointer) >= 128) ||
                             ((WrPointer - RdPointer) <= 0 &&
                             (RdPointer - WrPointer) <= TotalLoc-127)) &&
                              ~OENeg && ~RCSNeg)
                            begin
                              MarkedPointer = OldRdPointer;
                              Retransmit = marked;
                            end
                          else if ((Retransmit == marked ||
                                    Retransmit == hold) && RENNeg &&
                                    WENNeg && ~RTNeg)
                            begin
                              Retransmit = initiated;
                              EFNeg_zd [1:2] = 2'b00;
                              CopyEFNeg = 1'b0;
                              RdPointer = MarkedPointer;
                            end
                          else if (Retransmit == initiated)
                            begin
                              FirstWord  = yes;
                              Retransmit = hold;
                              EFNeg_zd [1:2] = 2'b11;
                              CopyEFNeg = 1'b1;
                              SetFlagsRt ( ValueForPAE,
                                           ValueForPAF);
                            end
                        end
                      if (~RENNeg && CopyEFNeg && LDNeg && ~RCSNeg)
                        begin
                          TmpMemLocOE = TmpMemLocRead;
                          SetFlagForOE;
                          if (MemDataLow [RdPointer] == -1)
                            TmpMemLocRead [35:0]= 36'bx;
                          else
                            begin
                              TmpMemLocRead_L = MemDataLow [RdPointer];
                              TmpMemLocRead_H = MemDataHigh[RdPointer];
                              TmpMemLocRead = {TmpMemLocRead_H,TmpMemLocRead_L};
                            end
                          OldRdPointer = RdPointer;
                          if (RdPointer == TotalLoc)
                              RdPointer = 0;
                          else
                              RdPointer =  RdPointer + 1;
                          if (~CopyFFNeg)
                            if (ReadOperation == Synchronous)
                              begin
                                if (ResetFF == no)
                                  begin
                                    ResetFF = yes;
                                    CntWCLKforResFF = 1;
                                  end
                              end
                            else
                              begin
                                  FFNeg_zd [1:2] = 2'b11;
                                  CopyFFNeg = 1'b1;
                              end
                          if (WrPointer == RdPointer)
                            begin
                              EFNeg_zd [1:2] = 2'b00;
                              CopyEFNeg = 1'b0;
                            end
                          SetFlagsRead(
                                        ValueForPAE,
                                        ValueForPAF);
                        end
                    end
                else
                  begin
                    if (MARK)
                      begin
                        if (Retransmit == done &&
                           (((WrPointer - RdPointer) >= 0 &&
                           (WrPointer - RdPointer) >= 128) ||
                             ((WrPointer - RdPointer) <= 0 &&
                             (RdPointer - WrPointer) <= TotalLoc-127)) &&
                            ~OENeg && ~RCSNeg)
                          begin
                            MarkedPointer = OldRdPointer;
                            Retransmit = marked;
                          end
                        else if ((Retransmit == marked ||
                               Retransmit == hold) && RENNeg &&
                               WENNeg && ~RTNeg)
                          begin
                            Retransmit = initiated;
                            EFNeg_zd [1:2] = 2'b11;
                            CopyEFNeg = 1'b1;
                            RdPointer = MarkedPointer;
                          end
                        else if (Retransmit == initiated)
                          begin
                            Retransmit = hold;
                            FirstWord = yes;
                            EFNeg_zd [1:2] = 2'b00;
                            CopyEFNeg = 1'b0;
                          end
                      end
                    if (~RENNeg && ResetOR == yes && LDNeg && RTNeg)
                      begin
                        ResetOR = no;
                        EFNeg_zd [1:2] = 2'b11;
                        CopyEFNeg = 1'b1;
                      end
                    else
                      begin
                        if (((~RENNeg && ~CopyEFNeg) || FirstWord == yes) &&
                               LDNeg && ~RCSNeg)
                          begin
                            TmpMemLocOE = TmpMemLocRead;
                            SetFlagForOE;
                            if (MemDataLow [RdPointer] == -1)
                                TmpMemLocRead = 36'bx;
                            else
                              begin
                                TmpMemLocRead_L = MemDataLow [RdPointer];
                                TmpMemLocRead_H = MemDataHigh[RdPointer];
                                TmpMemLocRead={TmpMemLocRead_H,TmpMemLocRead_L};
                              end
                            OldRdPointer = RdPointer;
                            if (RdPointer == TotalLoc)
                                RdPointer = 0;
                            else
                                RdPointer =  RdPointer + 1;
                            if (CopyFFNeg)
                              begin
                                if (ReadOperation == Synchronous)
                                  begin
                                    if (SetIR == no)
                                      begin
                                        SetIR = yes;
                                        CntWCLKforSetIR = 1;
                                      end
                                  end
                                else
                                  begin
                                    FFNeg_zd [1:2] = 2'b00;
                                    CopyFFNeg = 1'b0;
                                  end
                              end
                            if (WrPointer == RdPointer)
                                ResetOR = yes;
                            if (FirstWord == no)
                            SetFlagsRead(
                                         ValueForPAE,
                                         ValueForPAF);
                            FirstWord = no;
                          end
                      end
                  end
                end

// Reading Offset Registers

              if (WENNeg && ~RENNeg && SENNeg && ~LDNeg)
                    ParallelRead;

// Enable Reading Offset Registers

              if (RENNeg)
                    EnReadOffs = yes;

// Counting Read Cycles

              if (ResetEF == yes)
                    CountCLK
                           ( CntRCLKforResEF,
                             ResetEF,
                             CopyEFNeg,
                             EFNeg_zd[1:2],
                             FlagWCLKskew1,
                             Const1,
                             no);

              if (EnFirstWord == yes)
                begin
                    if (CntRCLKforFirstWord == 0)
                      begin
                        EnFirstWord = no;
                        TmpMemLocOE = TmpMemLocRead;
                        SetFlagForOE;
                        if (MemDataLow [RdPointer] == -1)
                            TmpMemLocRead = 36'bx;
                        else
                          begin
                            TmpMemLocRead_L = MemDataLow [RdPointer];
                            TmpMemLocRead_H = MemDataHigh[RdPointer];
                            TmpMemLocRead = {TmpMemLocRead_H,TmpMemLocRead_L};
                          end
                        OldRdPointer = RdPointer;
                        if (RdPointer == TotalLoc)
                            RdPointer = 0;
                        else
                            RdPointer =  RdPointer + 1;
                        EFNeg_zd [1:2] = 2'b00;
                        CopyEFNeg = 1'b0;
                      end
                    else
                      begin
                        if (~FlagWCLKskew1)
                          CntRCLKforFirstWord = CntRCLKforFirstWord-1;
                      end
                end

              if (ResetPAE == yes)
                    CountCLK
                           ( CntRCLKforResPAE,
                             ResetPAE,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             FlagWCLKskew2,
                             Const1,
                             no);

              if (ResetPAEabd == yes)
                    CountCLK
                           ( CntRCLKforResPAE,
                             ResetPAEabd,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             Const0,
                             Const1,
                             yes);

              if (ResetPAE_1 == yes)
                    CountCLK
                           ( CntRCLKforResPAE_1,
                             ResetPAE_1,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             FlagWCLKskew2,
                             Const1,
                             no);

              if (SetPAE == yes)
                    CountCLK
                           ( CntRCLKforSetPAE,
                             SetPAE,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             Const0,
                             Const0,
                             no);

              if (SetPAEabd == yes)
                    CountCLK
                           ( CntRCLKforSetPAE,
                             SetPAE,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             Const0,
                             Const0,
                             yes);

              if (SetPAE_1 == yes)
                    CountCLK
                           ( CntRCLKforSetPAE_1,
                             SetPAE_1,
                             CopyPAE,
                             PAENeg_zd[1:2],
                             Const0,
                             Const0,
                             no);

              time_RCLK = $time + TimeForFlag;
              if (~OENeg && (~RCSNeg || ~LDNeg))
                begin
                    QOut_zd [35:0] = TmpMemLocRead;
                    FromOE = false;
                    FromRCLK = true;
                end
              else if (RCSNeg && LDNeg)
                begin
                    QOut_zd [35:0] = 36'bz;
                    FromOE = false;
                    FromRCLK = true;
                end
            end
      end

////////////////////////////////////////////////////////////////////////////////
//     Serial Loading Offset Registers
////////////////////////////////////////////////////////////////////////////////

    always @(posedge SCLK_d)
      begin
          if (Reset == no && Enwrite == yes && ProgramMode == Serial)
            begin
              if (WENNeg && RENNeg && ~SENNeg && ~LDNeg)
                begin
                  if (SerLdEnd == no)
                     SerialLoad;
                  if (SerLdEnd == yes)
                    begin
                      SerLdEnd = no;
                      if (SerLdOk == yes)
                        begin
                          TmpEmptyOffset = TmpOffset [18:0];
                          EmptyOffset = TmpEmptyOffset;
                          TmpFullOffset = TmpOffset [37:19];
                          FullOffset = TmpFullOffset;
                          ValueForPAE = EmptyOffset;
                          ValueForPAF = TotalLoc - FullOffset;
                          SetFlags(
                                    ValueForPAE,
                                    ValueForPAF);
                        end
                    end
                end
            end
      end

////////////////////////////////////////////////////////////////////////////////
//  Deasert Retransmit Mode
////////////////////////////////////////////////////////////////////////////////

    always @(negedge RCLK)
      begin
          if (Reset == no && ~MARK && (Retransmit == marked ||
              Retransmit == hold || Retransmit == initiated))
            begin
              Retransmit = done;
              SetFlagsRt ( ValueForPAE,
                           ValueForPAF);
            end
      end

     always @(posedge CopyEFNeg)
      begin
        FlagRPE = 1'b1;
        FlagRPE <= #tRPE 1'b0;
      end

     always @(negedge RCSNeg)
      begin
        FlagRCS = 1'b1;
      end

     always @(posedge RCSNeg)
      begin
        FlagRCSNeg = 1'b1;
      end

    always @(OENeg)
      begin
          if (Reset == no)
            begin
                if (OENeg)
                  begin
                    TmpMemLocOE = TmpMemLocRead;
                    QOut_zd [35:0] = 36'bz;
                    FromRCLK = false;
                    FromOE = true;
                  end
                else if ((~OENeg) && (~RCSNeg &&
                          (~FlagRCS || FlagRCSNeg)))
                  begin
                    time_OE = $time + TimeForFlag_1;
                    if (~RCSNeg && (~FlagRCS || FlagRCSNeg))
                      begin
                        if (FlagForOE)
                          begin
                            QOut_zd [35:0] = TmpMemLocOE;
                            QOut_zd [35:0] <=  #0.5 TmpMemLocRead;
                            if (time_OE >= time_RCLK)
                              begin
                                FromOE = true;
                                FromRCLK = false;
                              end
                            else
                              begin
                                FlagForDelay = 1'b1;
                                FlagForDelay <= #1 1'b0;
                                FromOE = false;
                                FromRCLK = true;
                              end
                          end
                        else
                          begin
                            QOut_zd [35:0] = TmpMemLocRead;
                            FromOE = true;
                            FromRCLK = false;
                          end
                      end
                  end
            end
      end

task SetFlagForOE;

begin
    if (OENeg)
      begin
        FlagForOE = 1'b1;
        FlagForOE <= #TimeForFlag 1'b0;
      end
end
endtask

task Pointer;

begin
    if (Retransmit == done)
        RefPointer = RdPointer;
    else
        RefPointer = MarkedPointer;
end
endtask

task SetFlags;
input SetFlagsPae;
input SetFlagsPaf;

integer SetFlagsPae;
integer SetFlagsPaf;

begin
    if ((WrPointer > RdPointer &&
        WrPointer - RdPointer >= SetFlagsPae+1) ||
       (WrPointer < RdPointer &&
       TotalLoc - RdPointer + WrPointer >= SetFlagsPae) ||
       (WrPointer == RdPointer && Mode == FWFTMode && CopyFFNeg == 1'b1) ||
       (WrPointer == RdPointer && Mode == IDTStandard && CopyFFNeg == 1'b0))
      begin
        ResetPAEabd = yes;
        CntRCLKforResPAE = 2;
      end
    else
      begin
        SetPAEabd = yes;
        CntRCLKforSetPAE = 2;
      end
    Pointer;
    if ((WrPointer > RefPointer &&
       WrPointer - RefPointer >= SetFlagsPaf+1) ||
       (WrPointer < RefPointer &&
        TotalLoc - RefPointer + WrPointer >= SetFlagsPaf) ||
       (WrPointer == RefPointer && Mode == FWFTMode && CopyFFNeg == 1'b1) ||
       (WrPointer == RefPointer && Mode == IDTStandard && CopyFFNeg == 1'b0))
      begin
        SetPAFabd = yes;
        CntWCLKforSetPAF = 2;
      end
    else
      begin
        ResetPAFabd = yes;
        CntWCLKforResPAF = 2;
      end
end
endtask

task SetFlagsRt;
input SetFlagsRtPae;
input SetFlagsRtPaf;

integer SetFlagsRtPae;
integer SetFlagsRtPaf;

begin
    if ((WrPointer > RdPointer &&
        WrPointer - RdPointer >= SetFlagsRtPae+1) ||
       (WrPointer < RdPointer &&
       TotalLoc - RdPointer + WrPointer >= SetFlagsRtPae) ||
       (WrPointer == RdPointer && Mode == FWFTMode && CopyFFNeg == 1'b1) ||
       (WrPointer == RdPointer && Mode == IDTStandard && CopyFFNeg == 1'b0))
      begin
        ResetPAE = yes;
        CntRCLKforResPAE = 1;
      end
    else
      begin
        SetPAE = yes;
        CntRCLKforSetPAE = 1;
      end
    Pointer;
    if ((WrPointer > RefPointer &&
       WrPointer - RefPointer >= SetFlagsRtPaf+1) ||
       (WrPointer < RefPointer &&
        TotalLoc - RefPointer + WrPointer >= SetFlagsRtPaf) ||
       (WrPointer == RefPointer && Mode == FWFTMode && CopyFFNeg == 1'b1) ||
       (WrPointer == RefPointer && Mode == IDTStandard && CopyFFNeg == 1'b0))
      begin
        SetPAF = yes;
        CntWCLKforSetPAF = 1;
      end
    else
      begin
        ResetPAF = yes;
        CntWCLKforResPAF = 1;
      end
end
endtask

task SetFlagsWrite;
input ValueForPAE_Wr;
input ValueForPAF_Wr;

integer ValueForPAE_Wr;
integer ValueForPAF_Wr;
begin

    if(WrPointer >= RdPointer)
      begin
        if ((WrPointer > RdPointer &&
            WrPointer - RdPointer == ValueForPAE_Wr+1) ||
           (WrPointer == RdPointer &&
            TotalLoc == ValueForPAE_Wr))
            if (ProgFlagMode == Asynchronous)
              begin
                PAENeg_zd [1:2] = 2'b11;
                CopyPAE = 1'b1;
              end
            else
              begin
                ResetPAE = yes;
                CntRCLKforResPAE = 1;
              end
      end
    else
      begin
        if (TotalLoc - RdPointer + WrPointer == ValueForPAE_Wr)
            if (ProgFlagMode == Asynchronous)
              begin
                PAENeg_zd [1:2] = 2'b11;
                CopyPAE = 1'b1;
              end
            else
              begin
                ResetPAE_1 = yes;
                CntRCLKforResPAE_1 = 1;
              end
      end
    Pointer;
    if (WrPointer >= RefPointer)
      begin
        if ((WrPointer > RefPointer &&
            WrPointer - RefPointer == ValueForPAF_Wr+1) ||
           (WrPointer == RefPointer &&
            WrPointer - RefPointer == ValueForPAF_Wr))
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAFNeg_zd [1:2] = 2'b00;
                CopyPAF = 1'b0;
              end
            else
              begin
                SetPAF = yes;
                CntWCLKforSetPAF = 2;
              end
          end
      end
    else
      begin
        if (TotalLoc - RefPointer + WrPointer == ValueForPAF_Wr)
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAFNeg_zd [1:2] = 2'b00;
                CopyPAF = 1'b0;
              end
            else
              begin
                SetPAF_1 = yes;
                CntWCLKforSetPAF_1 = 2;
              end
          end
      end
end
endtask

task SetFlagsRead;

input ValueForPAE_Rd;
input ValueForPAF_Rd;

integer ValueForPAE_Rd;
integer ValueForPAF_Rd;

begin
    if (WrPointer >= RdPointer)
      begin
        if (WrPointer - RdPointer == ValueForPAE_Rd)
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAENeg_zd [1:2] = 2'b00;
                CopyPAE = 1'b0;
              end
            else
              begin
                SetPAE = yes;
                CntRCLKforSetPAE = 2;
              end
          end
      end
    else
      begin
        if (TotalLoc - RdPointer + WrPointer == ValueForPAE_Rd-1)
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAENeg_zd [1:2] = 2'b00;
                CopyPAE = 1'b0;
              end
            else
              begin
                SetPAE_1 = yes;
                CntRCLKforSetPAE_1 = 2;
              end
          end
      end
    Pointer;
    if (WrPointer >= RefPointer)
      begin
        if ((WrPointer > RefPointer &&
             WrPointer - RefPointer == ValueForPAF_Rd)||
            (WrPointer == RefPointer &&
             TotalLoc == ValueForPAF_Rd))
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAFNeg_zd [1:2] = 2'b11;
                CopyPAF = 1'b1;
              end
            else
              begin
                ResetPAF = yes;
                CntWCLKforResPAF = 1;
              end
          end
      end
    else
      begin
        if (TotalLoc - RefPointer + WrPointer == ValueForPAF_Rd-1)
          begin
            if (ProgFlagMode == Asynchronous)
              begin
                PAFNeg_zd [1:2] = 2'b11;
                CopyPAF = 1'b1;
              end
            else
              begin
                ResetPAF_1 = yes;
                CntWCLKforResPAF_1 = 1;
              end
          end
      end
end
endtask

task CountCLK;

inout Counter;
inout Condition;
inout CopyFlag;
inout [1:2] Flag;
input SkewFlag;
input Value;
input abd;

integer Counter;
reg  Condition;
reg  CopyFlag;
reg  [1:2] Flag;
reg  SkewFlag;
reg  Value;
reg  abd;

begin

    if (Counter == 0)
      begin
        Flag [1]= Value;
        Flag [2]= Value;
        CopyFlag = Value;
        Condition = no;
        if (abd == yes)
          begin
            FlagAbd = 1'b1;
            FlagAbd <= #1 1'b0;
          end
      end
    else
      begin
        if (~SkewFlag)
            Counter = Counter-1;
      end

end
endtask

task ParallelLoad;

begin
    if (ByteOffset == LSBEmptyOffset)
      begin
        if (~Viol)
            TmpEmptyOffset = {3'b111,DIn[15:0]};
        else
          begin
            PaLdEmptyOk = no;
            Viol = 1'b0;
          end
        ByteOffset = MSBEmptyOffset;
      end
    else if (ByteOffset == MSBEmptyOffset)
      begin
        if (~Viol)
            TmpEmptyOffset = TmpEmptyOffset & {DIn [2:0],16'hFFFF};
        else
          begin
            PaLdEmptyOk = no;
            Viol = 1'b0;
          end
        PaLdEmptyEnd = yes;
        ByteOffset = LSBFullOffset;
      end
    else if (ByteOffset == LSBFullOffset)
      begin
        if (~Viol)
            TmpFullOffset = {3'b111,DIn[15:0]};
        else
          begin
            PaLdFullOk = no;
            Viol = 1'b0;
          end
        ByteOffset = MSBFullOffset;
      end
    else
      begin
        if (~Viol)
            TmpFullOffset = TmpFullOffset & {DIn [2:0],16'hFFFF};
        else
          begin
            PaLdFullOk = no;
            Viol = 1'b0;
          end
        ByteOffset = LSBEmptyOffset;
        PaLdFullEnd = yes;
      end
end
endtask

task SerialLoad;

begin
    if (~Viol)
        TmpOffset [CountForSerial] = FWFT ;
    else
      begin
        SerLdOk = no;
        Viol = 1'b0;
      end
    CountForSerial = CountForSerial + 1;
    if (CountForSerial == 38)
      begin
        SerLdEnd = yes;
        CountForSerial = 0;
      end
end
endtask

task ParallelRead;

begin

    TmpMemLocOE = TmpMemLocRead;
    SetFlagForOE;
    if (ReadByteOffset == LSBEmptyOffset && EnReadOffs == yes)
      begin
        TmpOffsetRead = EmptyOffset;
        TmpMemLocRead [15:0] = TmpOffsetRead [15:0];
        ReadByteOffset = MSBEmptyOffset;
        EnReadOffs = no;
      end
    else if (ReadByteOffset == MSBEmptyOffset && EnReadOffs == yes)
      begin
        TmpOffsetRead = EmptyOffset;
        TmpMemLocRead [2:0] = TmpOffsetRead [18:16];
        ReadByteOffset = LSBFullOffset;
        EnReadOffs = no;
      end
    else if (ReadByteOffset == LSBFullOffset && EnReadOffs == yes)
      begin
        TmpOffsetRead = FullOffset;
        TmpMemLocRead [15:0] = TmpOffsetRead [15:0];
        ReadByteOffset = MSBFullOffset;
        EnReadOffs = no;
      end
    else if (ReadByteOffset == MSBFullOffset && EnReadOffs == yes)
      begin
        TmpOffsetRead = FullOffset;
        TmpMemLocRead [2:0] = TmpOffsetRead [18:16];
        ReadByteOffset = LSBEmptyOffset;
        EnReadOffs = no;
      end
end
endtask

  reg  BuffInRCLKASY, BuffInRCLKSY, BuffInOEASY, BuffInOESY, BuffInRPE ;
  wire  BuffOutRCLKASY, BuffOutRCLKSY, BuffOutOEASY, BuffOutOESY, BuffOutRPE;

    BUFFER    BUFRCLKASY   (BuffOutRCLKASY, BuffInRCLKASY);
    BUFFER    BUFRCLKSY    (BuffOutRCLKSY, BuffInRCLKSY);
    BUFFER    BUFOEASY     (BuffOutOEASY, BuffInOEASY);
    BUFFER    BUFOESY      (BuffOutOESY, BuffInOESY);
    BUFFER    BUFRPE       (BuffOutRPE, BuffInRPE);

    initial
      begin
         BuffInRCLKASY  = 1'b1;
         BuffInRCLKSY   = 1'b1;
         BuffInOEASY    = 1'b1;
         BuffInOESY     = 1'b1;
         BuffInRPE      = 1'b1;
      end

    always @(posedge BuffOutRCLKASY)
      begin
          RCLKASY_01 = $time;
      end
    always @(posedge BuffOutRCLKSY)
      begin
          RCLKSY_01 = $time;
      end
    always @(posedge BuffOutOEASY)
      begin
          OEASY_01 = $time;
      end
    always @(posedge BuffOutOESY)
      begin
          OESY_01 = $time;
      end
    always @(posedge BuffOutRPE)
      begin
          tRPE = $time;
      end

endmodule

module BUFFER (OUT,IN);
  input IN;
  output OUT;
    buf   ( OUT, IN);
endmodule