//////////////////////////////////////////////////////////////////////////////// // File name : idt723651.v //////////////////////////////////////////////////////////////////////////////// // Copyright (C) 1999 Integrated Device Technology; http://www.idt.com/ // Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT // and supported by Free Model Foundry; http://www.FreeModelFoundry.com // // This program is free software; you can redistribute it and/or modify // it under the terms of the GNU General Public License version 2 as // published by the Free Software Foundation. // // This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no // warranty with respect to the information contained herein. IDT DISCLAIMS // AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE // ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN // NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN // CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, // CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR // APPLICATION OF THE VHDL model. Further, IDT reserves the right to make // changes without notice to any product herein to improve reliability, // function, or design. IDT does not convey any license under patent rights // or any other intellectual property rights, including those of third parties. // IDT is not obligated to provide maintenance or support for the licensed VHDL // model. /////////////////////////////////////////////////////////////////////////////// // // MODIFICATION HISTORY : // // version | author | mod date | changes made // V1.0 Arkadi Poliakov 99 06 21 initial release // Y.A.T // V1.1 R. Munden 02 JUN 16 licensing changed to GPL // //////////////////////////////////////////////////////////////////////////////// // // PART DESCRIPTION : // // Library: FIFO // Technology: CMOS // Part: IDT723651 // // Description: SyncFIFO 2048x36 Memory // //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module IDT723651 ( A0 , // 36 pin Port-A data bus A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 , A9 , A10 , A11, A12 , A13 , A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30 , A31 , A32 , A33, A34, A35, AENeg, // Almost-Empty Flag AFNeg, // Almost-Full Flag B0 , // 36 pin Port-B data bus B1, B2 , B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35, CLKA, // Port-A clock CLKB, // Port-B clock CSANeg, // Port-A Chip Select CSBNeg, // Port-B Chip Select ENA, // Port-A Enable ENB , // Port-B Enable FS0SD, // Flag Offset Select // and Serial Data FS1SEN, // Flag Offset Select // and Serial Enable IR, // Input Ready Flag MBA, // Port-A Mailbox Select MBB, // Port-B Mailbox Select MBF1Neg , // Mail1 Register Flag MBF2Neg , // Mail2 Register Flag ORB, // Output ready flag // Name OR not avalable in VHDL RTM, RFM, // Read From Mark RSTNeg, // Reset WRA, // Port-A Write/Read Select // Active high Write , // Active low Read WRB // Port-B Write/Read Select // Active high Read , // Active low Write ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations inout A0; // Bidirectional 36 bit Data Port A. inout A1; inout A2; inout A3; inout A4; inout A5; inout A6; inout A7; inout A8; inout A9; inout A10; inout A11; inout A12; inout A13; inout A14; inout A15; inout A16; inout A17; inout A18; inout A19; inout A20; inout A21; inout A22; inout A23; inout A24; inout A25; inout A26; inout A27; inout A28; inout A29; inout A30; inout A31; inout A32; inout A33; inout A34; inout A35; output AENeg; // Almost-Empty Flag output AFNeg; // Almost-Full Flag inout B0; // Bidirectional 36 bit Data Port B inout B1; inout B2; inout B3; inout B4; inout B5; inout B6; inout B7; inout B8; inout B9; inout B10; inout B11; inout B12; inout B13; inout B14; inout B15; inout B16; inout B17; inout B18; inout B19; inout B20; inout B21; inout B22; inout B23; inout B24; inout B25; inout B26; inout B27; inout B28; inout B29; inout B30; inout B31; inout B32; inout B33; inout B34; inout B35; input CLKA; // Port-A clock input CLKB; // Port-B clock input CSANeg; // Port-A Chip Select input CSBNeg; // Port-B Chip Select input ENA; // Port-A Enable input ENB; // Port-B Enable input FS0SD; // Flag Offset 0 / Serial Data input FS1SEN; // Flag Offset Select output IR; // Input ready Flag input MBA; // Port-A Mailbox Select input MBB; // Port-B Mailbox Select output MBF1Neg; // Mail1 Register Flag output MBF2Neg; // Mail2 Register Flag output ORB; // Output Ready Flag input RFM; // Read From Mark input RSTNeg; // Reset input RTM; // Retransmit Mode input WRA; // Port-A Write/Read Select input WRB; // Port-B Write/Read Select wire IR; wire ORB; reg MBF1Negint, MBF2Negint; wire AENeg, AFNeg,AENegint, AFNegint, MBF1Neg,MBF2Neg ; reg [35: 0] Aout; wire A0out,A1out,A2out,A3out,A4out,A5out,A6out,A7out,A8out, A9out,A10out,A11out,A12out,A13out, A14out,A15out,A16out,A17out,A18out,A19out,A20out,A21out, A22out,A23out,A24out,A25out, A26out,A27out,A28out,A29out,A30out,A31out,A32out,A33out, A34out,A35out ; wire A0in,A1in,A2in,A3in,A4in,A5in,A6in,A7in,A8in,A9in,A10in, A11in,A12in,A13in,A14in,A15in, A16in,A17in,A18in,A19in,A20in,A21in,A22in,A23in,A24in, A25in,A26in,A27in,A28in,A29in,A30in,A31in, A32in,A33in,A34in,A35in; wire [35: 0] Ain; assign Ain = {A35in,A34in,A33in,A32in,A31in,A30in,A29in,A28in,A27in, A26in,A25in,A24in,A23in,A22in,A21in,A20in, A19in,A18in,A17in,A16in,A15in,A14in,A13in,A12in,A11in, A10in,A9in,A8in,A7in,A6in,A5in,A4in, A3in,A2in,A1in,A0in }; reg [35: 0] Bout; wire B0out,B1out,B2out,B3out,B4out,B5out,B6out,B7out,B8out, B9out,B10out,B11out,B12out,B13out, B14out,B15out,B16out,B17out,B18out,B19out,B20out,B21out, B22out,B23out,B24out,B25out, B26out,B27out,B28out,B29out,B30out,B31out,B32out,B33out, B34out,B35out ; wire B0in,B1in,B2in,B3in,B4in,B5in,B6in,B7in,B8in,B9in,B10in, B11in,B12in,B13in,B14in,B15in, B16in,B17in,B18in,B19in,B20in,B21in,B22in,B23in,B24in, B25in,B26in,B27in,B28in,B29in,B30in,B31in, B32in,B33in,B34in,B35in; wire [35: 0] Bin; assign Bin = {B35in,B34in,B33in,B32in,B31in,B30in,B29in,B28in,B27in, B26in,B25in,B24in,B23in,B22in,B21in,B20in, B19in,B18in,B17in,B16in,B15in,B14in,B13in,B12in,B11in, B10in,B9in,B8in,B7in,B6in,B5in,B4in, B3in,B2in,B1in,B0in }; assign {A35out,A34out,A33out,A32out,A31out,A30out,A29out,A28out, A27out,A26out,A25out,A24out,A23out,A22out,A21out,A20out, A19out,A18out,A17out,A16out,A15out,A14out,A13out,A12out, A11out,A10out,A9out,A8out,A7out,A6out,A5out,A4out, A3out,A2out,A1out,A0out } = Aout ; assign {B35out,B34out,B33out,B32out,B31out,B30out,B29out,B28out, B27out,B26out,B25out,B24out,B23out,B22out,B21out,B20out, B19out,B18out,B17out,B16out,B15out,B14out,B13out,B12out, B11out,B10out,B9out,B8out,B7out,B6out,B5out,B4out, B3out,B2out,B1out,B0out } = Bout ; parameter timingmodel = "defaulttimingmodel"; parameter SRAMSize = 2048; parameter SRAMWordLength = 36; // number of bits in SRAM word parameter NumBitProg = 22; // Bit number for serial programming of X1,Y1, parameter OffsetLength = 11; parameter SizeReg = 11; reg [SRAMWordLength -1 :0] SRAM1 [0:SRAMSize -1]; reg [SRAMWordLength -1 :0] SRAM2 [0:SRAMSize -1]; wire CLKA_ipd; wire CLKB_ipd; wire CSANeg_ipd; wire CSBNeg_ipd; wire ENA_ipd,ENB_ipd; wire MBA_ipd,MBB_ipd; wire RTM_ipd, RFM_ipd; reg ORBint,IRint;/////////////////////////?? wire RSTNeg_ipd,MRS2Neg_ipd,PRS2Neg_ipd,PRS1Neg_ipd,SIZE_ipd,SPMNeg_ipd, FS0SD_ipd,FS1SEN_ipd; wire RST1Neg_ipd ; wire WRA_ipd; wire WRB_ipd; wire A0_ipd, Check1,Check2; wire [35: 0] B_ipd; //? // buffers for qualifying all inputs for MIPD buf (RSTNeg_ipd,RSTNeg); buf (A0in, A0); buf (A1in, A1); buf (A2in, A2); buf (A3in, A3); buf (A4in, A4); buf (A5in, A5); buf (A6in, A6); buf (A7in, A7); buf (A8in, A8); buf (A9in, A9); buf (A10in, A10); buf (A11in, A11); buf (A12in, A12); buf (A13in, A13); buf (A14in, A14); buf (A15in, A15); buf (A16in, A16); buf (A17in, A17); buf (A18in, A18); buf (A19in, A19); buf (A20in, A20); buf (A21in, A21); buf (A22in, A22); buf (A23in, A23); buf (A24in, A24); buf (A25in, A25); buf (A26in, A26); buf (A27in, A27); buf (A28in, A28); buf (A29in, A29); buf (A30in, A30); buf (A31in, A31); buf (A32in, A32); buf (A33in, A33); buf (A34in, A34); buf (A35in, A35); buf (B0in, B0); buf (B1in, B1); buf (B2in, B2); buf (B3in, B3); buf (B4in, B4); buf (B5in, B5); buf (B6in, B6); buf (B7in, B7); buf (B8in, B8); buf (B9in, B9); buf (B10in, B10); buf (B11in, B11); buf (B12in, B12); buf (B13in, B13); buf (B14in, B14); buf (B15in, B15); buf (B16in, B16); buf (B17in, B17); buf (B18in, B18); buf (B19in, B19); buf (B20in, B20); buf (B21in, B21); buf (B22in, B22); buf (B23in, B23); buf (B24in, B24); buf (B25in, B25); buf (B26in, B26); buf (B27in, B27); buf (B28in, B28); buf (B29in, B29); buf (B30in, B30); buf (B31in, B31); buf (B32in, B32); buf (B33in, B33); buf (B34in, B34); buf (B35in, B35); buf (CLKB_ipd, CLKB); buf (CLKA_ipd, CLKA); buf (CSANeg_ipd, CSANeg ); buf (CSBNeg_ipd, CSBNeg ); buf (ENA_ipd, ENA); buf (ENB_ipd, ENB); buf (MBA_ipd, MBA); buf (MBB_ipd, MBB); buf (WRA_ipd, WRA); buf (WRB_ipd, WRB); buf (FS0SD_ipd,FS0SD); buf (FS1SEN_ipd,FS1SEN); buf (RTM_ipd,RTM ); buf (RFM_ipd,RFM ); // buffers for qualifying all outputs as accelerated nets buf (AENeg, AENegint); buf (AFNeg, AFNegint); buf (MBF1Neg, MBF1Negint); buf (MBF2Neg, MBF2Negint); buf (ORB,ORBint); buf (IR,IRint); nmos (A0, A0out, 1); nmos (A1, A1out, 1); nmos (A2, A2out, 1); nmos (A3, A3out, 1); nmos (A4, A4out, 1); nmos (A5, A5out, 1); nmos (A6, A6out, 1); nmos (A7, A7out, 1); nmos (A8, A8out, 1); nmos (A9, A9out, 1); nmos (A10, A10out, 1); nmos (A11, A11out, 1); nmos (A12, A12out, 1); nmos (A13, A13out, 1); nmos (A14, A14out, 1); nmos (A15, A15out, 1); nmos (A16, A16out, 1); nmos (A17, A17out, 1); nmos (A18, A18out, 1); nmos (A19, A19out, 1); nmos (A20, A20out, 1); nmos (A21, A21out, 1); nmos (A22, A22out, 1); nmos (A23, A23out, 1); nmos (A24, A24out, 1); nmos (A25, A25out, 1); nmos (A26, A26out, 1); nmos (A27, A27out, 1); nmos (A28, A28out, 1); nmos (A29, A29out, 1); nmos (A30, A30out, 1); nmos (A31, A31out, 1); nmos (A32, A32out, 1); nmos (A33, A33out, 1); nmos (A34, A34out, 1); nmos (A35, A35out, 1); nmos (B0, B0out, 1); nmos (B1, B1out, 1); nmos (B2, B2out, 1); nmos (B3, B3out, 1); nmos (B4, B4out, 1); nmos (B5, B5out, 1); nmos (B6, B6out, 1); nmos (B7, B7out, 1); nmos (B8, B8out, 1); nmos (B9, B9out, 1); nmos (B10, B10out, 1); nmos (B11, B11out, 1); nmos (B12, B12out, 1); nmos (B13, B13out, 1); nmos (B14, B14out, 1); nmos (B15, B15out, 1); nmos (B16, B16out, 1); nmos (B17, B17out, 1); nmos (B18, B18out, 1); nmos (B19, B19out, 1); nmos (B20, B20out, 1); nmos (B21, B21out, 1); nmos (B22, B22out, 1); nmos (B23, B23out, 1); nmos (B24, B24out, 1); nmos (B25, B25out, 1); nmos (B26, B26out, 1); nmos (B27, B27out, 1); nmos (B28, B28out, 1); nmos (B29, B29out, 1); nmos (B30, B30out, 1); nmos (B31, B31out, 1); nmos (B32, B32out, 1); nmos (B33, B33out, 1); nmos (B34, B34out, 1); nmos (B35, B35out, 1); specify // tipd delays: interconnect path delays, mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays: propagation delays specparam tpd_CLKA_A0 =1; specparam tpd_CLKA_FFNeg =1; // tWFF //???? specparam tpd_CLKB_EFNeg =1; // tREF specparam tpd_CLKB_PEFBNeg =1; // tPPE specparam tpd_CLKB_AENeg =1; // tPAE specparam tpd_CLKA_AFNeg =1; // tPAF specparam tpd_CLKA_MBF1Neg =1; // tPMF specparam tpd_CLKA_MBF2Neg =1; // tPMF specparam tpd_CLKB_MBF1Neg =1; // tPMF specparam tpd_CLKB_MBF2Neg =1; // tPMF specparam tpd_CLKA_B0 =1; // tPMR specparam tpd_CLKA_IR =1; // tPIR specparam tpd_CLKB_ORB =1; // tPOR specparam tpd_CLKB_A0 =1; // tPMR specparam tpd_CLKB_B0 =1; // tA //??? specparam tpd_A0_PEFANeg =1; // tPDPE specparam tpd_B0_PEFBNeg =1; // tPDPE specparam tpd_ODDEVEN_PEFANeg =1; // tPOPE specparam tpd_ODDEVEN_PEFBNeg =1; // tPOPE specparam tpd_ODDEVEN_ParityBits =1; // tPOPB specparam tpd_CSANeg_PEFANeg =1; // tPEPE specparam tpd_ENA_PEFANeg =1; // tPEPE specparam tpd_WRA_PEFANeg =1; // tPEPE specparam tpd_MBA_PEFANeg =1; // tPEPE specparam tpd_PGA_PEFANeg =1; // tPEPE specparam tpd_CSBNeg_PEFBNeg =1; // tPEPE specparam tpd_ENB_PEFBNeg =1; // tPEPE specparam tpd_WRB_PEFBNeg =1; // tPEPE specparam tpd_PGB_PEFBNeg =1; // tPEPE specparam tpd_RSTNeg_AENeg =1; // tRSF specparam tpd_RSTNeg_AFNeg =1; // tRSF specparam tpd_RSTNeg_MBF1Neg =1; // tRSF specparam tpd_RSTNeg_MBF2Neg =1; // tRSF specparam tpd_CSBNeg_A0 =1; // tEN/tDIS specparam tpd_WRB_A0 =1; // tEN/tDIS specparam tpd_CSBNeg_B0 =1; // tEN/tDIS specparam tpd_WRB_B0 =1; // tEN/tDIS specparam tpd_ODDEVEN_A8 =1; // tPOPB specparam tpd_WRA_A8 =1; // tPEPB specparam tpd_WRB_A8 =1; // tPEPB specparam tpd_ENB_A8 =1; // tPEPB specparam tpd_ENA_A8 =1; // tPEPB specparam tpd_CSBNeg_A8 =1; // tPEPB specparam tpd_CSANeg_A8 =1; // tPEPB specparam tpd_PGA_A8 =1; // tPEPB specparam tpd_PGB_A8 =1; // tPEPB specparam tpd_MBA_A8 =1; // tPEPB specparam tpd_MBB_B0 =1; // tMDV // tpw values: pulse widths specparam tpw_CLKA = 1; // tCLKA specparam tpw_CLKB = 1; // tCLKB specparam tpw_CLKA_posedge = 1; // tCLKH specparam tpw_CLKB_posedge = 1; // tCLKH specparam tpw_CLKA_negedge = 1; // tCLKL specparam tpw_CLKB_negedge = 1; // tCLKL // tsetup values: setup times specparam tsetup_A0_CLKA_posedge = 1; // tDS specparam tsetup_B0_CLKB_posedge = 1; // tDS specparam tsetup_CSANeg_CLKA_posedge = 1; // tENS1 specparam tsetup_WRA_CLKA_posedge = 1; // tENS1 specparam tsetup_CSBNeg_CLKB_posedge= 1; // tENS1 specparam tsetup_WRB_CLKB_posedge = 1; // tENS1 specparam tsetup_ENA_CLKA_posedge = 1; // tENS2 specparam tsetup_ENB_CLKB_posedge = 1; // tENS2 specparam tsetup_MBA_CLKA_posedge = 1; // tENS3 specparam tsetup_MBB_CLKB_posedge = 1; //tMDV specparam tsetup_RSTNeg_CLKA_posedge = 1; // tRSTS specparam tsetup_RSTNeg_CLKB_posedge = 1; // tRSTS specparam tsetup_FS0SD_CLKA_posedge = 1; // tSDS specparam tsetup_FS1SEN_CLKA_posedge = 1; // tSDS specparam tsetup_SW0_CLKB_posedge = 1; // tFSS specparam tsetup_SW1_CLKB_posedge = 1; specparam tsetup_BENeg_CLKB_posedge = 1; specparam tsetup_SIZ1_CLKB_posedge = 1; specparam tsetup_SIZ0_CLKB_posedge = 1; specparam tsetup_FS1SEN_RSTNeg_posedge = 1; specparam tsetup_MRS1_CLKA_posedge = 1; specparam tsetup_MRS1_CLKB_posedge = 1; specparam tsetup_MRS2_CLKB_posedge = 1; specparam tsetup_PRS1_CLKA_posedge= 1; specparam tsetup_PRS1_CLKB_posedge= 1; specparam tsetup_MRS2_CLKA_posedge= 1; specparam tsetup_PRS2_CLKA_posedge= 1; specparam tsetup_PRS2_CLKB_posedge= 1; specparam tsetup_FS0sd_MRS1_posedge= 1; specparam tsetup_FS1SEN_MRS1_posedge= 1; specparam tsetup_MRS2_SPM_posedge= 1; specparam tsetup_MRS1_SPM_posedge= 1; specparam tsetup_MRS2_BEF_posedge= 1; specparam tsetup_MRS1_BEF_posedge= 1; specparam tsetup_FS0SD_RSTNeg_posedge= 1; specparam tsetup_RTM_CLKB_posedge= 1; specparam tsetup_RFM_CLKB_posedge= 1; //tRMS // thold values: hold times //tRMS specparam thold_RSTNeg_CLKB_posedge = 1; // tRSTS specparam thold_RSTNeg_CLKA_posedge = 1; // tRSTS specparam thold_BEF_CLKA_posedge = 1; specparam thold_FS1SEN_MRS2_posedge = 1; specparam thold_FS1SEN_MRS1_posedge= 1; specparam thold_MRS1_BEF_posedge = 1; specparam thold_MRS2_BEF_posedge = 1; specparam thold_MRS1_CLKA_posedge = 1; specparam thold_MRS2_CLKB_posedge = 1; specparam thold_MRS2_CLKA_posedge= 1; specparam thold_MRS1_CLKB_posedge= 1; specparam thold_PRS1_CLKA_posedge= 1; specparam thold_PRS2_CLKB_posedge= 1; specparam thold_PRS1_CLKB_posedge= 1; specparam thold_PRS2_CLKA_posedge= 1; specparam thold_FS0sd_MRS1_posedge= 1; specparam thold_FS0sd_MRS2_posedge= 1; specparam thold_MRS1_SPM_posedge= 1; specparam thold_MRS2_SPM_posedge= 1; specparam thold_SW0_CLKB_posedge = 1; specparam thold_SW1_CLKB_posedge = 1; specparam thold_BENeg_CLKB_posedge = 1; specparam thold_SIZ1_CLKB_posedge = 1; specparam thold_SIZ0_CLKB_posedge = 1; specparam thold_A0_CLKA_posedge = 1; // tDH specparam thold_B0_CLKB_posedge = 1; // tDH specparam thold_CSANeg_CLKA_posedge = 1; // tENH1 specparam thold_WRA_CLKA_posedge = 1; // tENH1 specparam thold_CSBNeg_CLKB_posedge = 1; // tENH1 specparam thold_WRB_CLKB_posedge = 1; // tENH1 specparam thold_ENA_CLKA_posedge = 1; // tENH2 specparam thold_ENB_CLKB_posedge = 1; // tENH2 specparam thold_MBA_CLKA_posedge = 1; // tENH3 specparam thold_MBB_CLKB_posedge = 1; //tMDV specparam thold_ODDEVEN_CLKB_posedge = 1; // tPGH specparam thold_PGB_CLKB_posedge= 1; // tPGH specparam thold_RST_CLKA_posedge= 1; // tRSTH specparam thold_RST_CLKB_posedge= 1; // tRSTH specparam thold_FS0SD_RSTNeg_posedge = 1; // tFSH specparam thold_FS1SEN_RSTNeg_posedge = 1; // tFSH specparam thold_RTM_CLKB_posedge= 1; //tRMH specparam thold_RFM_CLKB_posedge= 1; //tRMH specparam thold_FS0SD_CLKA_posedge = 1; // tSDH specparam thold_FS1SEN_CLKA_posedge = 1; // tSDH specparam tpd_SIZ0_B8= 1; specparam tpd_SIZ1_B8= 1; specparam tpd_RSTNeg_EFNeg= 1; specparam tpd_SIZ0_PEFBNeg = 1; specparam tpd_SIZ1_PEFBNeg = 1; specparam tpd_ODDEVEN_B8 = 1; specparam tpd_SIZ0_B0 = 1; specparam tpd_SIZ1_B0 = 1; /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description //////////////////////////////////////////////////////////////////////////////// // Path delays // //////////////////////////////////////////////////////////////////////////////// (RSTNeg*> AFNeg) = tpd_RSTNeg_AFNeg; (RSTNeg*> AENeg) = tpd_RSTNeg_AENeg; (CLKA *> IR ) = tpd_CLKA_IR; (CLKB *> ORB ) = tpd_CLKB_ORB; (CLKB *> AENeg ) = tpd_CLKB_AENeg; (CLKA *> AFNeg ) = tpd_CLKA_AFNeg; (CLKA *> MBF1Neg ) = tpd_CLKA_MBF1Neg; (CLKA *> MBF2Neg ) = tpd_CLKA_MBF2Neg; (CLKB *> MBF1Neg ) = tpd_CLKB_MBF1Neg; (CLKB *> MBF2Neg ) = tpd_CLKB_MBF2Neg;//?? (CLKB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18, B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 ) = tpd_CLKB_B0; (CLKB *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,A19, A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 ) = tpd_CLKB_A0; (CLKA *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19, B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 ) = tpd_CLKA_B0; (CSANeg *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18, A19,A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 ) = tpd_CSBNeg_A0; (CSBNeg *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18, B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 ) = tpd_CSBNeg_B0; (MBB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19, B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 ) = tpd_MBB_B0; (WRA *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,A19, A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 ) = tpd_CSBNeg_A0; // net (WRB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19, B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 ) = tpd_MBB_B0; //////////////////////////////////////////////////////////////////////////////// // Timing Violation // //////////////////////////////////////////////////////////////////////////////// // CLK period checking $period (posedge CLKA, tpw_CLKA); $period (posedge CLKB, tpw_CLKB); // CLKA pulse width check(high & low) $width ( posedge CLKA, tpw_CLKA_posedge); $width ( negedge CLKA, tpw_CLKA_negedge); // VitalPeriodPulseCheck ( TestSignal => CLKA,... // CLKB pulse width check(high & low) $width ( posedge CLKB, tpw_CLKB_posedge); $width ( negedge CLKB, tpw_CLKB_negedge); // VitalPeriodPulseCheck ( TestSignal => CLKB,... // A/CLKA setup/hold time check $setuphold ( posedge CLKA &&& Check2, A0, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A1, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A2, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A3, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A4, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A5, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A6, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A7, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A8, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A9, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A10, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A11, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A12, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A13, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A14, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A15, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A16, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A17, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A18, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A19, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A20, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A21, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A22, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A23, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A24, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A25, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A26, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A27, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A28, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A29, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A30, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A31, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A32, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A33, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A34, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); $setuphold ( posedge CLKA &&& Check2, A35, tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge); // B/CLKB setup/hold time check $setuphold ( posedge CLKB &&& Check1, B0, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B1, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B2, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B3, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B4, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B5, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B6, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B7, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B8, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B9, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B10, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B11, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B12, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B13, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B14, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B15, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B16, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B17, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B18, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B19, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B20, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B21, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B22, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B23, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B24, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B25, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B26, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B27, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B28, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B29, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B30, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B31, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B32, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B33, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B34, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); $setuphold ( posedge CLKB &&& Check1, B35, tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge); // ENA/CLKA setup/hold time check $setuphold ( posedge CLKA, ENA, tsetup_ENA_CLKA_posedge,thold_ENA_CLKA_posedge); $setuphold ( posedge CLKB, ENB, tsetup_ENB_CLKB_posedge,thold_ENB_CLKB_posedge); // CSBNeg/CLKB setup/hold time check $setuphold ( posedge CLKB, CSBNeg, tsetup_CSBNeg_CLKB_posedge, thold_CSBNeg_CLKB_posedge); $setuphold ( posedge CLKA, CSANeg, tsetup_CSANeg_CLKA_posedge, thold_CSANeg_CLKA_posedge); // WRA/CLKA setup/hold time check $setuphold ( posedge CLKA, WRA, tsetup_WRA_CLKA_posedge,thold_WRA_CLKA_posedge); $setuphold ( posedge CLKB, WRB, tsetup_WRB_CLKB_posedge,thold_WRB_CLKB_posedge); // MBA/CLKA setup/hold time check $setuphold ( posedge CLKA, MBA, tsetup_MBA_CLKA_posedge,thold_MBA_CLKA_posedge); $setuphold ( posedge CLKB, MBB, tsetup_MBB_CLKB_posedge,thold_MBB_CLKB_posedge); // RFM,RTM setup/hold time check i podpravit RESET i td!!!!!!!!!!!!!!! $setuphold ( posedge CLKB, RFM, tsetup_RFM_CLKB_posedge,thold_RFM_CLKB_posedge); $setuphold ( posedge CLKB, RTM, tsetup_RTM_CLKB_posedge,thold_RTM_CLKB_posedge); //RSTNeg/CLKA $setuphold ( posedge CLKA, RSTNeg, tsetup_RSTNeg_CLKA_posedge,thold_RSTNeg_CLKA_posedge); $setuphold ( posedge CLKB, RSTNeg, tsetup_RSTNeg_CLKB_posedge,thold_RSTNeg_CLKB_posedge); //RSTNeg/FS0SD $setuphold ( posedge RSTNeg, FS0SD, tsetup_FS0SD_RSTNeg_posedge,thold_FS0SD_RSTNeg_posedge); $setuphold ( posedge RSTNeg, FS1SEN, tsetup_FS1SEN_RSTNeg_posedge,thold_FS1SEN_RSTNeg_posedge); // FS0SD, FS1SEN/ CLKA setup/hold time check $setuphold ( posedge CLKA, FS0SD, tsetup_FS0SD_CLKA_posedge, thold_FS0SD_CLKA_posedge); $setuphold ( posedge CLKA, FS1SEN, tsetup_FS1SEN_CLKA_posedge, thold_FS1SEN_CLKA_posedge); // Signal endspecify //////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // //////////////////////////////////////////////////////////////////////////////// // instead of A0, B0, ..... for behavior you should use: // - A0in, B0in ( in any expressions), // - A0out, B0out - in left-hand parts of assignment statements reg [OffsetLength -1:0] X1, Y1; // AlFull-AlEmpty Offset regs reg [35 : 0] Mail1, Mail2, Mailout1, Mailout2, OutReg,ChadowOutReg,OutReg1, Aux1,FWTTreg; time tSKEW1, tSKEW2; // min tSKEW vals to be reg [OffsetLength:0] WritePoint, ReadPoint,ChadowReadPoint,FW; reg [OffsetLength:0] CountWords ,ChadowCountWords,CountWords_P; reg ef2l_a, ef1l_a,ef2l_b ,ef1l_b, read_b_enable, pp_inp,ORB2L; reg [SizeReg:0] rdp_2,rdp_1,r1_shadow; reg [SizeReg:0] af_a, ae_a, af_b, ae_b; reg read_a_enable; reg [35:0] r1,r2; // YAT pipeline for first word -3 clka delay reg [SizeReg:0] w1_ptr,ChadowReadPoint_ptr,r1_ptr; reg Viol1,Viol2, In1, In2, In3,Rd, Wr, Rd1, Wr1,SRAM2_In1,SRAM2_In3, FWT1,FWT2, // for fthowfall first word FWT1S,FWT2S, ORBPint,ORAPint, // for delayed OR fall RETRMODE ,R3int, // For RETRANSM MODE SW1L,SW0L, SIZ1L, SIZ0L; reg RdFull, RdAlFull,WrFirstCell, WrAlEmCell, RdFull1, RdAlFull1,WrFirstCell1, WrAlEmCell1, Net1,Net2; integer ReadNo, LimitC,CountR3int, LimitB; reg [2:0] state; assign Check1 = !CSBNeg_ipd && !WRB_ipd && ENB_ipd && MBB_ipd; // signal for setup checking between CLKB and B bus assign Check2 = !CSANeg_ipd && WRA_ipd && ENA_ipd; // signal for setup checking between CLKA and A bus `define IDLE 'b000 `define MasterReset 'b001 `define ParProg 'b010 `define prX1 'b011 `define prY2 'b100 `define prX2 'b101 `define SerProg 'b110 wire MRS1PAR,MRS2PAR; reg FirstTime; reg En, ren1,ren2; always // Reset of FIFO1 begin @( negedge RSTNeg_ipd); Mailout1 = 0; Mail1=0; Mailout2 = 0; Mail2=0;Mailout1 = 0; MBF1Negint <= 1; FirstTime=1;En=0; ren1 =0; ren2 =0; r1 =0; r2 =0; OutReg <= 0; MBF2Negint <= 1; pp_inp = 0; RETRMODE <=0;R3int<=0;CountR3int<=0; ChadowCountWords <=0; ChadowOutReg <= 0; //for RETRANSMIT MODE In1 =0; In3 =0;Wr =0; Rd =0; Viol1 =0; ReadNo = 1; X1 =0; Y1 =0; fork begin repeat (4) @( posedge CLKA_ipd) if (RSTNeg_ipd) Viol1 =1 ; // 4 CLKA clocks checking end begin repeat (4) @( posedge CLKB_ipd) if (RSTNeg_ipd) Viol1 =1 ; // 4 CLKB clocks checking end begin repeat (3) @( posedge CLKB_ipd); ORBint <= 0; FWT1 <= 0; FWT1S<= 0;ORBPint = 0; //!!!!!!!!!!!!!!ORBint,FWT1 <= 0 end join if ( ! Viol1) begin WritePoint <= 0; ReadPoint <= 0; ChadowReadPoint <= 0; CountWords <= 0; CountWords_P <= 0; @( posedge RSTNeg_ipd); repeat (2) @( posedge CLKA_ipd); // if (state != `SerProg)IRint <= 1; end else $display ("Time = %0d. FIFO1 Reset time is less 4 periods .\n ", $time); end always @( posedge RSTNeg_ipd) // Loading FIFO1 AlFull-AlEmpty Offset regs X1,Y1 case ( {FS1SEN_ipd,FS0SD_ipd}) 2'b10:begin X1 = 64 ;Y1 = 64 ;end 2'b01:begin X1 = 8; Y1 = 8; end endcase reg BigEndian, M_R; reg [8:0] Ser; initial state =0; always // state mashine - implementation of Reset begin @( posedge CLKA_ipd); case (state) `IDLE : begin if ( !RSTNeg_ipd ) state <= `MasterReset; M_R =0; end `MasterReset: if (RSTNeg_ipd ) begin if ( !FS1SEN_ipd && !FS0SD_ipd ) state <= `ParProg; // Parallel programing else if ( FS1SEN_ipd&& FS0SD_ipd) begin state <= `SerProg;Ser =1; Y1=0;X1=0; end// Serial programing else state <= `IDLE; // Preset values of Offset end //else if (RSTNeg_ipd ) state <= `IDLE; `ParProg: if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint) begin Y1 = Ain[OffsetLength-1:0]; state <= `prX1; pp_inp = 1;end `prX1: if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint) begin X1 = Ain[OffsetLength-1:0]; state <= `IDLE; SRAM2_In1 <=1; Rd1 <=1; // start FFCIRCint <= 1; with SKEW1 end `SerProg: // Serial programing if(!FS1SEN_ipd) begin if( Ser <= NumBitProg/2) Y1 = {Y1,FS0SD_ipd}; else X1 = {X1,FS0SD_ipd}; if( Ser == NumBitProg) begin In1 <=1; Rd <=1; // start IRint <= 1 with SKEW1 @( posedge CLKB_ipd); SRAM2_In1 <=1; Rd1 <=1; // start FFCIRCint <= 1; with SKEW1 state <= `IDLE; end else Ser <= Ser +1; end endcase end reg FIFO1_STD_Mode,FIFO2_STD_Mode; ////////////////// port A operations ///////////////////////////////// always @( Mail2 ) Mailout2 = Mail2; always @( CSANeg_ipd or WRA_ipd or Mailout2 or MBA_ipd) if ( CSANeg_ipd | WRA_ipd ) Aout = 36 'h ZZZZZZZZZ; // no chip-select and no read from FIFO else if (!CSANeg_ipd && !WRA_ipd ) //?? && MBA_ipd) Aout = Mailout2; //MAIL2 to bus A always @ (posedge En) // change by YAT for go En to 0 after 1 posedge CLKB begin @(posedge CLKB_ipd ); En <= @(negedge CLKB_ipd ) 0; end always @( posedge CLKA_ipd ) begin case ( { CSANeg_ipd, WRA_ipd, ENA_ipd, MBA_ipd}) 4 'b0110: if (IRint &&( state == `IDLE) && RSTNeg_ipd) // write to FIFO begin if (!RETRMODE ) begin ORBPint <= 0; // new change YAT 06_11 if (( CountWords == 0) && FirstTime && ~ORBint && ~ren1) begin FWTTreg = Ain; FW =1; //First writen word in FWTT mode FirstTime <=0; // Assign to OutReg En =1; if ( pp_inp == 1) pp_inp = 0; // include for pp_inp to 0 when we have first word // En <=@(negedge CLKB_ipd ) 0; // YAT 06/11/99 = end changing end else begin // end new change //////// FIFO1 write ///////// SRAM1 [WritePoint] <= Ain; FWT1S = 0; pp_inp =0; if (WritePoint != (SRAMSize-1) ) WritePoint<= WritePoint +1; else WritePoint <= 0; CountWords_P = CountWords_P +1; CountWords <=CountWords_P; end end else begin ORBPint <= 0; //////// FIFO1 write in RETRANSMIT MODE write ///////// SRAM1 [WritePoint] <= Ain; FWT1S = 0; if (WritePoint != (SRAMSize-1) ) WritePoint<= WritePoint +1; else WritePoint <= 0; ChadowCountWords <= ChadowCountWords +1; CountWords_P = CountWords_P +1; CountWords <=CountWords_P; end end 4 'b0111: begin if (MBF1Negint) begin Mail1 = Ain ; MBF1Negint = 0; end end // Mail 1 Write 4 'b0011: begin MBF2Negint = 1; Aout = Mailout2 ; end // Mail 2 Read / set MBF2 endcase end ////////////////////// port B operations ///////////////////////////////// always @( Mail1) Mailout1 = Mail1; always @( CSBNeg_ipd or WRB_ipd or MBB_ipd or Mailout1 or OutReg or ENB_ipd) begin if ( CSBNeg_ipd || !WRB_ipd ) Bout = 36 'h ZZZZZZZZZ; // no chip-select and no read from FIFO else if ( !CSBNeg_ipd && WRB_ipd && ! MBB_ipd ) Bout = OutReg ; else if ( !CSBNeg_ipd && WRB_ipd && MBB_ipd ) Bout = Mailout1; end always @(posedge CLKB_ipd) begin r1 <=FWTTreg; ren1 <=En; r2 <=r1; ren2 <= ren1; if (ren2 ) begin OutReg <= r2 ; end end // YAT end pipeline /////// set retransmit mode flipflop RETRMODE to 1 and Chadow registers always @( posedge CLKB_ipd ) if (ORBint) if (RTM_ipd && !RETRMODE) begin RETRMODE <= 1; ChadowReadPoint <=ReadPoint ;//!!??-1 ot useif n Ch.out reg ChadowCountWords<=CountWords; //??+ 1;ot useif n Ch.out reg ChadowOutReg<=OutReg; ChadowReadPoint_ptr = r1_ptr-1; end always begin @(ChadowCountWords) if (RSTNeg_ipd &&(ChadowCountWords < CountWords)) ChadowCountWords<=CountWords; end // DELAY for 3 reading in the RETRMODE ,for check MIN 3 WORDS // (R3int <= 1 after 2 words reading) always @( posedge CLKB_ipd ) begin if( RETRMODE &&!CSBNeg_ipd && !MBB_ipd && WRB_ipd && ENB_ipd && ORBint ) begin if( CountR3int <= 4) CountR3int<= CountR3int+1; if( CountR3int == 2 ) R3int <= 1; end end // RETRMODE- start Retransmit from select position, always @( posedge CLKB_ipd ) if ( RFM_ipd && RTM_ipd && RETRMODE ) if( R3int) begin ReadPoint = ChadowReadPoint; CountWords <= ChadowCountWords; CountWords_P <= ChadowCountWords; OutReg = ChadowOutReg; // not delay ta !! CountR3int <=0; R3int<=0; // if ( ChadowCountWords !=0) ORBint <= 1; end else $display ("Time = %0d. FIFO retransmit loop less 3 words .\n ", $time); ////// RESET retransmit mode flipflop RETRMODE always @( posedge CLKB_ipd ) if (!RTM_ipd ) begin RETRMODE <=0;CountR3int <=0; R3int<=0;end /////// EMPTY / ALMOST EMPTY FLAGs behavior /////////////////////// always ///// for FIFO1 begin @( CountWords); if ((CountWords == 0) && RSTNeg_ipd) begin ORBPint <= 1; // ORBint = 0; FWT1 <= 0; //AENegint = 0; FirstTime <= 1; end end // ORB fall delay for tact //////////////////////////////////////// always @( posedge CLKB_ipd ) begin case ( { CSBNeg_ipd, WRB_ipd, ENB_ipd, MBB_ipd ,RSTNeg_ipd}) 5'b01101: if (ORBPint) begin //////// FIFO1 attempt Read ////////// // ORBint <= 0; ORBPint <= 0; end endcase end // ORB rise /////////////////////////////// always begin @( negedge WrFirstCell) ; repeat (2) @( posedge CLKB_ipd ) ; // 3 to 2 !!!!!!!!!!!!! FWT1 <= 1;FWT1S <= 0; // tREF after CLKB end always begin // FWT1 for Froufall First World in FIFO1 @( posedge FWT1 ) ; @( posedge CLKB_ipd ) ; //!!!!!!!!!!! // ORBint <= 1; FWT1S <= 0; FWT1 <= 0; end always begin @( negedge WrAlEmCell) ; if (RSTNeg)begin repeat (2) @( posedge CLKB_ipd ) ; // AENegint = 1; end // tREF after CLKB end //---------------------- // AE in the beginning of the RETRANSMIT LOOP //?? always // begin @( posedge CLKB_ipd ) if ( RFM_ipd && RTM_ipd && RETRMODE ) if (ChadowCountWords > (X1+1)) begin repeat (2) @( posedge CLKB_ipd ) ; // AENegint = 1; end // end //----------------------- // new behavior of AFLA from IDT 18 august reg afla, afla_old, af1l_a, bcmpen_af_a,rcven_af_a, af2la_a; reg aflgen_a,no_inc_w1; reg ira,orb, ORB1int; reg [SizeReg:0] wtp_1,wtp_2, afp_a, r1_ptr_retr; wire mrstl1,prstl1,csal,ena,wrla,mba; wire [SizeReg - 1:0] y1; assign mrstl1 = RSTNeg_ipd; assign prstl1 =1'b1; assign csal = CSANeg_ipd; assign ena = ENA_ipd; assign wrla = WRA_ipd; assign mba = MBA_ipd; assign y1 = Y1; assign AFNegint = afla; reg ira_in,irb_in,ira_old,ff1l_a,fflgen_a; reg irhdl1_lchd_a; reg ff1l_b,fflgen_b; reg irhdl1_lchd_b; reg fs0_reg,fs1_reg,spml,pp_end,sp_end,palcntl,sercntl,irhdl2,irhdl1; reg aflgen_b,en_irb,en2_irb, counter1_irb ,counter2_irb,eql_orb; wire fs0sd,fs1senl,befwftl; //assign spml = SPMNeg_ipd; assign fs0sd = FS0SD_ipd; assign fs1senl=FS1SEN_ipd; // assign befwftl = BEFWFT_ipd; assign befwftl = 1'b0; reg rcven_ae_a_old, bcmpen_ae_a, rcven_ae_a; reg ora_old,ef2l_a_old; wire unienl; reg aelgen_a,eflgen_a; reg [SizeReg:0] aep_a; assign unienl =1'b1; reg bcmpen_af_b,rcven_af_b; reg [SizeReg:0] afp_b; wire csbl,enb,wlrb,mbb,bm,size; assign csbl = CSBNeg_ipd; assign enb = ENB_ipd; assign wlrb = WRB_ipd; assign mbb = MBB_ipd; assign bm = 1'b0; // BM_ipd; reg aelb, aelb_old, ae1l_b, rcven_ae_b_old, bcmpen_ae_b, rcven_ae_b, ae2la_b, orb_b2; reg orb_old,ef2l_b_old,aften_ae_b_old,aften_ae_b,bmaft_orb; reg aelgen_b,eflgen_b; reg bmaft_reg1, bmaft_reg2, bmaft_reg3,reseting1; reg [SizeReg:0] aep_b, rdpone_orb; wire [SizeReg-1:0] x1; reg counter1_orb,counter2_orb; reg en_orb, en2_orb; reg eq_orb, eql_orb_old; assign x1 = X1; assign AENegint = aelb; integer sd_counter,counter_bm_r1,bm_r1; always @(fs0_reg or fs1_reg or mrstl1 or pp_end or sp_end) begin spml = ~(~fs0_reg && ~fs1_reg ); spml = 1'b1; //? palcntl = ~(~fs0_reg && ~fs1_reg && spml && mrstl1 && pp_end); sercntl = ~(~fs0_reg && fs1_reg && ~spml && mrstl1 && sp_end); irhdl2 = ~(~fs0_reg && ~fs1_reg && palcntl) && ~(~fs0_reg && fs1_reg && ~spml && sercntl); irhdl1 = ~(~fs0_reg && fs1_reg && ~spml && sercntl); end always @(mrstl1 or fs0sd or fs1senl) begin if (mrstl1 == 1'b0) fs0_reg = fs0sd; if (mrstl1 == 1'b0) fs1_reg = fs1senl; end always @(negedge mrstl1) // begin reset begin // befwftl = 1'b0; //? counter_bm_r1 = 0; reseting1 = 1'b1; pp_end = 1'b0; sp_end = 1'b0; fflgen_a = 1'b0; eflgen_b = 1'b0; afla = 1'b1; af1l_a = 1'b1; aelb = 1'b0; ae1l_b = 1'b0; rcven_ae_b = 1'b0; w1_ptr=0;r1_ptr=0; @(posedge CLKA_ipd);@(posedge CLKA_ipd);@(posedge CLKA_ipd);@(posedge CLKA_ipd); @(posedge mrstl1) #5 reseting1 = 1'b0; end always @(posedge mrstl1) // reset fs1 and fs0 =0 : 4 clocks and two clocks begin // befwftl = 1'b1; //? if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0)) begin no_inc_w1 = 1'b1; @(posedge CLKA_ipd);@(posedge CLKA_ipd);//@(posedge CLKA_ipd);@(posedge CLKA_ipd); if (unienl == 1'b1) begin @(posedge CLKA_ipd); @(posedge CLKA_ipd); end no_inc_w1 = 1'b0; end end always @(posedge mrstl1 ) begin // tSKEW1 = 0; // tSKEW2 =0; if (reseting1 == 1'b1) begin if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0)) fs1_reg = fs1_reg;// clka4 ==1 else if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0) && (spml == 1'b1)) begin /* parallel programming mode */ if ((mrstl1 == 1'b0)) @(posedge mrstl1); no_inc_w1 = 1'b1; @(posedge CLKA_ipd); @(posedge CLKA_ipd); @(posedge CLKA_ipd);// y1 = f1_in; @(posedge CLKA_ipd);// x1 = f1_in; if (unienl == 1'b1) begin @(posedge CLKA_ipd);// y2 = f1_in; @(posedge CLKA_ipd);// x2 = f1_in; end no_inc_w1 = 1'b0; pp_end = 1'b1; end else if (spml == 1'b1) begin /* preset values */ no_inc_w1 = 1'b0; end else if ((fs1_reg == 1'b1) && (fs0_reg == 1'b0) && (spml == 1'b0)) begin if ((mrstl1 == 1'b0)) @(posedge mrstl1); no_inc_w1 = 1'b1; for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1) begin @(posedge CLKA_ipd) if (fs1senl == 1'b0) ;//y1[sd_counter] = fs0sd; else sd_counter=sd_counter+1; end for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1) begin @(posedge CLKA_ipd) if (fs1senl == 1'b0) ;//x1[sd_counter] = fs0sd; else sd_counter=sd_counter+1; end if (unienl == 1'b1) begin for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1) begin @(posedge CLKA_ipd) if (fs1senl == 1'b0) ;//y2[sd_counter] = fs0sd; else sd_counter=sd_counter+1; end for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1) begin @(posedge CLKA_ipd) if (fs1senl == 1'b0) ;//x2[sd_counter] = fs0sd; else sd_counter=sd_counter+1; /* set counter back for next try */ end end no_inc_w1 = 1'b0; sp_end = 1'b1; end end end /* AFLA */ always @( posedge CLKA_ipd) begin if (CSANeg_ipd==0 && WRA_ipd==1 && ENA_ipd == 1 && MBA_ipd==0) // if (IRint &&( state == `IDLE) && RSTNeg_ipd) // write to FIFO // YAT 06/11/99 added if (!RETRMODE &&!(( CountWords == 0) && FirstTime)) // for IRA set 0 pp_inp =0; if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint && (state == `ParProg )) begin pp_inp = 1;end if ((ira == 1'b1) && (csal == 1'b0) && (wrla == 1'b1) && (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) )) begin if ((no_inc_w1 == 1'b0) && (pp_inp == 1'b0)) begin w1_ptr = w1_ptr + 1; end end ira_old = ira; if (((csal == 1'b0) && (wrla == 1'b1) && (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) ) && (ira == 1'b1) && (irhdl1 == 1'b1)) || (ira == 1'b0) || ((mrstl1 == 1'b0))) begin ira = ira_in;IRint <= ira; end if (((csal == 1'b0) && (wrla == 1'b1) && (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) ) && (ira_old == 1'b1) && (irhdl1 == 1'b1)) || ((ira_old == 1'b0) || (ff1l_a == 1'b0)) || ((mrstl1 == 1'b0) )) begin ff1l_a = fflgen_a; end /* AFLA */ afla_old = afla; if ((mrstl1 == 1'b0) ) afla = 1'b1; else if ((mrstl1 == 1'b0) || ((afla == 1'b0) || (rcven_af_a == 1'b1)) || ((~csal && ena && wrla && ~mba && ira) && (irhdl2 == 1'b1))) afla = af1l_a; if ((bcmpen_af_a == 1'b1) && (afla_old !== af1l_a) && ((mrstl1 == 1'b1) )) rcven_af_a = 1'b1; else rcven_af_a = 1'b0; af2la_a = ~(~afla || rcven_af_a); af_a = y1 + w1_ptr; if ((mrstl1 == 1'b0) ) af1l_a = 1'b1; else if (((mrstl1 == 1'b0) || ((afla_old == 1'b0) || (af1l_a == 1'b0)) || ((~csal && ena && wrla && ~mba && ira) && (irhdl2 == 1'b1))) && (irhdl2 == 1'b1)) af1l_a = aflgen_a; end always @(y1 or w1_ptr or af1l_a or af2la_a) afp_a = y1 + w1_ptr + af1l_a + af2la_a; always @(af_a or r1_ptr) begin if ((r1_ptr[0] == af_a[0]) && (r1_ptr[1] == af_a[1])) bcmpen_af_a = 1'b1; else bcmpen_af_a = 1'b0; end always @(r1_ptr or afp_a or irhdl2 or r1_ptr_retr) begin if (irhdl2 == 1'b0) aflgen_a = 1'b1; else if (((w1_ptr[SizeReg] !== afp_a[SizeReg]) || (r1_ptr_retr[SizeReg] !== afp_a[SizeReg])) && ((r1_ptr_retr[SizeReg - 1:0] <= afp_a[SizeReg-1:0]) || ((w1_ptr[SizeReg] !== afp_a[SizeReg]) && (r1_ptr_retr[SizeReg] == afp_a[SizeReg])))) aflgen_a = 1'b0; else aflgen_a =#tSKEW2 1'b1; // aflgen_a = 1'b1; end // new for IDT723644 // for ira always @(posedge CLKA_ipd or negedge mrstl1 or negedge prstl1) begin if ((mrstl1 == 1'b0) ) #1 irhdl1_lchd_a = irhdl1; else if (((csal == 1'b0) && (wrla == 1'b1) && (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) ) && (ira == 1'b1) && (irhdl1 == 1'b1)) || (ira == 1'b0) || ((mrstl1 == 1'b0) )) begin irhdl1_lchd_a = irhdl1; end end always @(irhdl1_lchd_a or fflgen_a or ff1l_a) begin if (irhdl1_lchd_a == 1'b0) ira_in = fflgen_a; else if (irhdl1_lchd_a == 1'b1) ira_in = ff1l_a; end always @(w1_ptr or ira or ff1l_a) wtp_1 = w1_ptr + ira + ff1l_a; always @(wtp_1 or r1_ptr or irhdl1 or mrstl1) begin if ( RETRMODE) r1_ptr_retr = ChadowReadPoint_ptr; else r1_ptr_retr = r1_ptr; if ((irhdl1 == 1'b0) || (mrstl1 == 1'b0) ) fflgen_a = 1'b0; else if ((wtp_1[SizeReg-1:0] == r1_ptr_retr[SizeReg-1:0]) && (wtp_1[SizeReg] !== r1_ptr_retr[SizeReg])) fflgen_a = 1'b0; else fflgen_a = 1'b1; end //always @(w1_ptr or ira or ff1l_a) // wtp_1 = w1_ptr + ira + ff1l_a; // end for AELA from IDT ( 25 august) // begin for AFB flag from IDT ( 31 august) always @(posedge CLKB_ipd) begin if (bm == 1'b0) bm_r1 = 0; end //////////////////////////////////////////////////////////////////////////////// // begin work for AEB flag ( 31 august) always @(posedge CLKB_ipd) begin aften_ae_b_old = aften_ae_b; orb_old = orb; if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0) || (bmaft_orb == 1'b0)) || ((csbl == 1'b0) && (wlrb == 1'b1) && (mbb == 1'b0) && (enb == 1'b1) && (befwftl == 1'b0) && (orb == 1'b1) && (ef2l_b == 1'b0) && (eq_orb == 1'b1)) || (orb == 1'b0) || ((mrstl1 == 1'b0) )) begin if (befwftl == 1'b0) orb = ef2l_b; else orb = ef1l_b; end ef2l_b_old = ef2l_b; if (eql_orb == 1'b0) ef2l_b = 1'b0; else if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0) || (bmaft_orb == 1'b0)) || ((orb_old == 1'b0) || (ef2l_b == 1'b0)) || ((mrstl1 == 1'b0) )) begin ef2l_b = ef1l_b; end if (eql_orb_old == 1'b0) ef1l_b = 1'b0; else if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0) || (bmaft_orb == 1'b0)) || ((orb_old == 1'b0) || (ef1l_b == 1'b0) || (ef2l_b_old == 1'b0)) || ((mrstl1 == 1'b0) )) begin ef1l_b = eflgen_b; end ORBint <= orb; // ORB1int = ef2l_b && read_b_enable; // 9 june "=" ORB2L <= ef2l_b; ORB1int = orb; if (ORBint && RTM_ipd && !RETRMODE) ChadowReadPoint_ptr = r1_ptr; if ((mrstl1 == 1'b0) ) ; else if (read_b_enable == 1'b1) if (bm == 1'b0) begin r1_ptr = r1_ptr + 1; // ReadPoint = r1_ptr; end if (bm == 1'b0) aften_ae_b = ~befwftl && orb_b2 && orb; else if (bm == 1'b1) aften_ae_b = bmaft_orb; ef2l_b_old = ef2l_b; rcven_ae_b_old = rcven_ae_b; if ((bcmpen_ae_b == 1'b1) && (aelb !== ae1l_b) && ((mrstl1 == 1'b1) )) rcven_ae_b = 1'b1; else rcven_ae_b = 1'b0; aelb_old = aelb; if ((mrstl1 == 1'b0) ) aelb = 1'b0; else if (((en_orb == 1'b1) && (en2_orb == 1'b1)) || (rcven_ae_b_old == 1'b1) || (aelb == 1'b0)) aelb = ae1l_b; if ((mrstl1 == 1'b0) ) ae1l_b = 1'b0; else if (((en_orb == 1'b1) && (en2_orb == 1'b1)) || (aften_ae_b_old || ~ae1l_b || ~aelb_old)) ae1l_b = aelgen_b; orb_b2 = ~orb; ae2la_b = ~(~aelb || rcven_ae_b); // 9 June 1999 this process was included into this place to debug ORBint beh. case ( { CSBNeg_ipd, WRB_ipd, ENB_ipd, MBB_ipd }) 5'b0110: // read FIFO port B begin if (CountWords ==0) FirstTime <=1; //9 june FirstTime <=1 when FIFO is empty if ( (ORBint||(ORB1int&&~ren2))&& ORB2L && RSTNeg_ipd && !(( RFM_ipd && RTM_ipd && RETRMODE )===1)) //////// FIFO1 Read ////////// begin // if (CountWords !=0) OutReg = SRAM1 [ReadPoint]; //YAT $ if (ReadPoint != (SRAMSize-1) ) ReadPoint <= ReadPoint +1;else ReadPoint <= 0; if (CountWords !=0) begin CountWords_P = CountWords_P - 1; CountWords <= CountWords_P ; end // CountWords <= CountWords - 1; Bout = OutReg; if ( CountWords == SRAMSize) begin In1 <=1; Rd <=1; end // it means RdFull <= 1; RdFull <= # tSKEW1 0; if ( CountWords == SRAMSize - Y1 ) begin In3 <=1; Rd <=1; end // it means RdAlFull <= 1; RdAlFull <= # tSKEW2 0; end end // begin change by YAT 06/21 5'b0100: // case ENB = 0 with CountWord!=0 and ORB = 0 begin if ( (~ORBint&&(ORB1int&&~ren2)) && RSTNeg_ipd && !(( RFM_ipd && RTM_ipd && RETRMODE )===1)) //////// FIFO1 Read ////////// begin if (CountWords !=0) OutReg = SRAM1 [ReadPoint]; //YAT $ if (ReadPoint != (SRAMSize-1) ) ReadPoint <= ReadPoint +1;else ReadPoint <= 0; if (CountWords !=0) begin CountWords_P = CountWords_P - 1; CountWords <= CountWords_P ; end // CountWords <= CountWords - 1; Bout = OutReg; //?????????????????????????????????? end end // end cnange by YAT 06/21 5 'b0011: begin if (MBF2Negint) begin Mail2 = Bin; MBF2Negint = 0;end end // Mail 2 Write 5 'b0111: begin MBF1Negint = 1;Bout = Mailout1; end // Mail 1 Read / set MBF1 endcase end always @(posedge CLKB_ipd or negedge mrstl1) begin if (bm == 1'b0) begin counter1_orb = 1'b1; counter2_orb = 1'b1; end end always @(posedge CLKB_ipd or negedge mrstl1) begin if ((mrstl1 == 1'b0) ) begin bmaft_reg1 = 1'b0; bmaft_reg2 = 1'b0; bmaft_reg3 = 1'b0; end else begin bmaft_reg2 = bmaft_reg1; bmaft_reg1 = ~(en_orb && en2_orb); if (bmaft_reg2 == 1'b0) bmaft_reg3 = 1'b0; else begin if (bmaft_reg3 == 1'b1) bmaft_reg3 = 1'b1; else bmaft_reg3 = orb_b2; end end end always @(bmaft_reg3 or orb or befwftl) begin bmaft_orb = ~befwftl && orb && bmaft_reg3; end always @(posedge eql_orb) begin if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0) || (bmaft_orb == 1'b0)) || ((orb_old == 1'b0) || (ef2l_b_old == 1'b0))) begin ef2l_b = ef1l_b; end if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0) || (bmaft_orb == 1'b0)) || ((orb_old == 1'b0) || (ef1l_b == 1'b0) || (ef2l_b_old == 1'b0))) begin ef1l_b = eflgen_b; end end always @(w1_ptr or aep_b or irhdl2) begin if (irhdl2 == 1'b0) aelgen_b = 1'b0; else if (((r1_ptr[SizeReg] !== aep_b[SizeReg]) || (w1_ptr[SizeReg] == aep_b[SizeReg])) && ((w1_ptr[SizeReg-1:0] <= aep_b[SizeReg-1:0]) || ((w1_ptr[SizeReg] !== aep_b[SizeReg]) && (r1_ptr[SizeReg] !== aep_b[SizeReg])))) aelgen_b = 1'b0; else aelgen_b = #tSKEW2 1'b1; // aelgen_b = 1'b1; end always @(rdp_1 or w1_ptr or mrstl1 or prstl1) begin if ((rdp_1 == w1_ptr) || (mrstl1 == 1'b0) ) eflgen_b = 1'b0; else if ( tSKEW1 == 0) eflgen_b = 1'b1 ; else eflgen_b =#tSKEW1 1'b1; end always @(x1 or r1_ptr or ae1l_b or ae2la_b) aep_b = x1 + r1_ptr + ae1l_b + ae2la_b; always @(w1_ptr or r1_ptr) begin ae_b = x1 + r1_ptr; if ((w1_ptr[0] == ae_b[0]) && (w1_ptr[1] == ae_b[1])) bcmpen_ae_b = 1'b1; else bcmpen_ae_b = 1'b0; end always @(r1_ptr or ef1l_b or ef2l_b) if (befwftl == 1'b0) rdp_1 = r1_ptr + ef1l_b + ef2l_b; else rdp_1 = r1_ptr + ef1l_b + orb; always @(posedge CLKB_ipd or negedge mrstl1 or negedge prstl1) begin eql_orb_old = eql_orb; if ((bm == 1'b0) || (befwftl == 1'b1)) eql_orb = 1'b1; else if (((mrstl1 == 1'b0) || (prstl1 == 1'b0)) && (bm == 1'b1) && (befwftl == 1'b0)) begin eql_orb = 1'b0; ef1l_b = 1'b0; ef2l_b = 1'b0; end else if (((en_orb == 1'b1) && (en2_orb == 1'b1)) || (eql_orb == 1'b0) || ((mrstl1 == 1'b0) )) begin if (rdpone_orb == w1_ptr) begin eql_orb = 1'b0; ef1l_b = 1'b0; ef2l_b = 1'b0; end else eql_orb = 1'b1; end if ( RFM) begin ef2l_b = 1'b1; ef1l_b = 1'b1; orb = 1'b1; // r1_ptr = ChadowReadPoint; r1_ptr = ChadowReadPoint_ptr; end end always @(csbl or enb or wlrb or mbb or ef2l_b or orb or irhdl2 or CLKB_ipd or befwftl or bm or eql_orb) begin /* RCLK */ if (CLKB_ipd == 1'b0) if (((~csbl && enb && wlrb && ~mbb && ~(~ef2l_b && ~(eql_orb && orb && bm && ~befwftl))) || (~orb && ef2l_b && ~befwftl)) && (irhdl2 == 1'b1)) read_b_enable = 1'b1; else read_b_enable = 1'b0; end always @(csal or ena or ~wrla or mba or ef2l_a or irhdl2 or CLKA_ipd) begin /* RCLK */ if (CLKA_ipd == 1'b0) if (((~csal && ena && ~wrla && ~mba && ef2l_a) || ( ef2l_a)) && (irhdl2 == 1'b1)) read_a_enable = 1'b1; else read_a_enable = 1'b0; end always @(eql_orb or orb or bm or befwftl) begin eq_orb = ~(eql_orb && orb && bm && ~befwftl); end always @(r1_ptr or eql_orb) begin rdpone_orb = r1_ptr + eql_orb; end always @(CLKB_ipd or mrstl1 or irhdl2 or befwftl or orb or ef2l_b or mbb or enb or wlrb or csbl or bm or eql_orb) begin if ((mrstl1 == 1'b0) ) en_orb = 1'b0; else if (CLKB_ipd == 1'b0) en_orb = irhdl2 && ((~befwftl && ~orb && ef2l_b) || (~mbb && enb && wlrb && ~csbl && ~(~ef2l_b && ~(~befwftl && bm && eql_orb && orb)))); end always @(CLKB_ipd or en_orb) begin if ((en_orb == 1'b0) || ( CLKB_ipd== 1'b0)) en2_orb = ~(bm && ~(counter1_orb && counter2_orb)); end // end for AEB flag ( 31 august) //************************************************************************** ///////////////////////////////////////////////////////////////////////// // Importing tSKEW vals from an SDF file // // (DEVICE construct should be applied for this purpose) // // Calculating actual tSKEW vals // ///////////////////////////////////////////////////////////////////////// reg BuffIn1, BuffIn2; wire BuffOut1, BuffOut2; time tBuffIn1, tBuffIn2; VITALbuf SKEW1 (BuffOut1, BuffIn1); VITALbuf SKEW2 (BuffOut2, BuffIn2); initial // extracting minimal tSKEW1 value begin #1 // non-zero value should be specified tBuffIn1 = $time; BuffIn1 <= 1'b0; @(BuffOut1); tSKEW1 = $time - tBuffIn1; end initial // extracting minimal tSKEW2 value begin #1 // non-zero value should be specified tBuffIn2 = $time; BuffIn2 <= 1'b0; @(BuffOut2); tSKEW2 = $time - tBuffIn2; end //************************************************************************** endmodule module VITALbuf ( OUT,IN); input IN; output OUT; not ( OUT, IN); endmodule