/*------------------------------------------------------------------------------ -------------------------------------------------------------------------------- -- File Name: idt723611.v -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- 2.0 O.Jankovic 05 Dec 12 initial version -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: FLASH MEMORY -- Technology: CMOS -- Part: IDT723611 -- -- Description: 64 x 36 High-speed FIFO -- -------------------------------------------------------------------------------- ------------------------------------------------------------------------------*/ ////////////////////////////////////////////////////////////////////////////// // MODULE DECLARATION // ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ns module idt723611 ( CLKA , CLKB , CSANeg , CSBNeg , ENA , ENB , FS0 , FS1 , MBA , MBB , OddEVENNeg , PGA , PGB , RSTNeg , WRANeg , WRBNeg , A0 , A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 , A9 , A10 , A11 , A12 , A13 , A14 , A15 , A16 , A17 , A18 , A19 , A20 , A21 , A22 , A23 , A24 , A25 , A26 , A27 , A28 , A29 , A30 , A31 , A32 , A33 , A34 , A35 , B0 , B1 , B2 , B3 , B4 , B5 , B6 , B7 , B8 , B9 , B10 , B11 , B12 , B13 , B14 , B15 , B16 , B17 , B18 , B19 , B20 , B21 , B22 , B23 , B24 , B25 , B26 , B27 , B28 , B29 , B30 , B31 , B32 , B33 , B34 , B35 , AENeg , AFNeg , EFNeg , FFNeg , MBF1Neg , MBF2Neg , PEFANeg , PEFBNeg ); //////////////////////////////////////////////////////////////////////// // Port / Part Pin Declarations //////////////////////////////////////////////////////////////////////// input CLKA ; input CLKB ; input CSANeg ; input CSBNeg ; input ENA ; input ENB ; input FS0 ; input FS1 ; input MBA ; input MBB ; input OddEVENNeg ; input PGA ; input PGB ; input RSTNeg ; input WRANeg ; input WRBNeg ; inout A0 ; inout A1 ; inout A2 ; inout A3 ; inout A4 ; inout A5 ; inout A6 ; inout A7 ; inout A8 ; inout A9 ; inout A10 ; inout A11 ; inout A12 ; inout A13 ; inout A14 ; inout A15 ; inout A16 ; inout A17 ; inout A18 ; inout A19 ; inout A20 ; inout A21 ; inout A22 ; inout A23 ; inout A24 ; inout A25 ; inout A26 ; inout A27 ; inout A28 ; inout A29 ; inout A30 ; inout A31 ; inout A32 ; inout A33 ; inout A34 ; inout A35 ; inout B0 ; inout B1 ; inout B2 ; inout B3 ; inout B4 ; inout B5 ; inout B6 ; inout B7 ; inout B8 ; inout B9 ; inout B10 ; inout B11 ; inout B12 ; inout B13 ; inout B14 ; inout B15 ; inout B16 ; inout B17 ; inout B18 ; inout B19 ; inout B20 ; inout B21 ; inout B22 ; inout B23 ; inout B24 ; inout B25 ; inout B26 ; inout B27 ; inout B28 ; inout B29 ; inout B30 ; inout B31 ; inout B32 ; inout B33 ; inout B34 ; inout B35 ; output AENeg ; output AFNeg ; output EFNeg ; output FFNeg ; output MBF1Neg ; output MBF2Neg ; output PEFANeg ; output PEFBNeg ; // interconnect path delay signals wire CLKA_ipd ; wire CLKB_ipd ; wire CSANeg_ipd ; wire CSBNeg_ipd ; wire ENA_ipd ; wire ENB_ipd ; wire FS0_ipd ; wire FS1_ipd ; wire MBA_ipd ; wire MBB_ipd ; wire OddEVENNeg_ipd ; wire PGA_ipd ; wire PGB_ipd ; wire RSTNeg_ipd ; wire WRANeg_ipd ; wire WRBNeg_ipd ; wire A0_ipd ; wire A1_ipd ; wire A2_ipd ; wire A3_ipd ; wire A4_ipd ; wire A5_ipd ; wire A6_ipd ; wire A7_ipd ; wire A8_ipd ; wire A9_ipd ; wire A10_ipd ; wire A11_ipd ; wire A12_ipd ; wire A13_ipd ; wire A14_ipd ; wire A15_ipd ; wire A16_ipd ; wire A17_ipd ; wire A18_ipd ; wire A19_ipd ; wire A20_ipd ; wire A21_ipd ; wire A22_ipd ; wire A23_ipd ; wire A24_ipd ; wire A25_ipd ; wire A26_ipd ; wire A27_ipd ; wire A28_ipd ; wire A29_ipd ; wire A30_ipd ; wire A31_ipd ; wire A32_ipd ; wire A33_ipd ; wire A34_ipd ; wire A35_ipd ; wire [35 : 0 ] AIn; assign AIn = { A35_ipd , A34_ipd , A33_ipd , A32_ipd , A31_ipd , A30_ipd , A29_ipd , A28_ipd , A27_ipd , A26_ipd , A25_ipd , A24_ipd , A23_ipd , A22_ipd , A21_ipd , A20_ipd , A19_ipd , A18_ipd , A17_ipd , A16_ipd , A15_ipd , A14_ipd , A13_ipd , A12_ipd , A11_ipd , A10_ipd , A9_ipd , A8_ipd , A7_ipd , A6_ipd , A5_ipd , A4_ipd , A3_ipd , A2_ipd , A1_ipd, A0_ipd}; reg [35 : 0 ] AOut_zd; wire B0_ipd ; wire B1_ipd ; wire B2_ipd ; wire B3_ipd ; wire B4_ipd ; wire B5_ipd ; wire B6_ipd ; wire B7_ipd ; wire B8_ipd ; wire B9_ipd ; wire B10_ipd ; wire B11_ipd ; wire B12_ipd ; wire B13_ipd ; wire B14_ipd ; wire B15_ipd ; wire B16_ipd ; wire B17_ipd ; wire B18_ipd ; wire B19_ipd ; wire B20_ipd ; wire B21_ipd ; wire B22_ipd ; wire B23_ipd ; wire B24_ipd ; wire B25_ipd ; wire B26_ipd ; wire B27_ipd ; wire B28_ipd ; wire B29_ipd ; wire B30_ipd ; wire B31_ipd ; wire B32_ipd ; wire B33_ipd ; wire B34_ipd ; wire B35_ipd ; wire [35 : 0 ] BIn; assign BIn = { B35_ipd , B34_ipd , B33_ipd , B32_ipd , B31_ipd , B30_ipd , B29_ipd , B28_ipd , B27_ipd , B26_ipd , B25_ipd , B24_ipd , B23_ipd , B22_ipd , B21_ipd , B20_ipd , B19_ipd , B18_ipd , B17_ipd , B16_ipd , B15_ipd , B14_ipd , B13_ipd , B12_ipd , B11_ipd , B10_ipd , B9_ipd , B8_ipd , B7_ipd , B6_ipd , B5_ipd , B4_ipd , B3_ipd , B2_ipd , B1_ipd, B0_ipd}; reg [35 : 0 ] BOut_zd; // internal delays wire A0_zd ; wire A1_zd ; wire A2_zd ; wire A3_zd ; wire A4_zd ; wire A5_zd ; wire A6_zd ; wire A7_zd ; wire A8_zd ; wire A9_zd ; wire A10_zd ; wire A11_zd ; wire A12_zd ; wire A13_zd ; wire A14_zd ; wire A15_zd ; wire A16_zd ; wire A17_zd ; wire A18_zd ; wire A19_zd ; wire A20_zd ; wire A21_zd ; wire A22_zd ; wire A23_zd ; wire A24_zd ; wire A25_zd ; wire A26_zd ; wire A27_zd ; wire A28_zd ; wire A29_zd ; wire A30_zd ; wire A31_zd ; wire A32_zd ; wire A33_zd ; wire A34_zd ; wire A35_zd ; wire A0_Pass ; wire A1_Pass ; wire A2_Pass ; wire A3_Pass ; wire A4_Pass ; wire A5_Pass ; wire A6_Pass ; wire A7_Pass ; wire A8_Pass ; wire A9_Pass ; wire A10_Pass ; wire A11_Pass ; wire A12_Pass ; wire A13_Pass ; wire A14_Pass ; wire A15_Pass ; wire A16_Pass ; wire A17_Pass ; wire A18_Pass ; wire A19_Pass ; wire A20_Pass ; wire A21_Pass ; wire A22_Pass ; wire A23_Pass ; wire A24_Pass ; wire A25_Pass ; wire A26_Pass ; wire A27_Pass ; wire A28_Pass ; wire A29_Pass ; wire A30_Pass ; wire A31_Pass ; wire A32_Pass ; wire A33_Pass ; wire A34_Pass ; wire A35_Pass ; reg [35 : 0] AOut_Pass= 36'bz; assign { A35_Pass , A34_Pass , A33_Pass , A32_Pass , A31_Pass , A30_Pass , A29_Pass , A28_Pass , A27_Pass , A26_Pass , A25_Pass, A24_Pass, A23_Pass, A22_Pass, A21_Pass, A20_Pass, A19_Pass, A18_Pass, A17_Pass, A16_Pass, A15_Pass, A14_Pass, A13_Pass, A12_Pass, A11_Pass, A10_Pass, A9_Pass, A8_Pass, A7_Pass, A6_Pass, A5_Pass, A4_Pass, A3_Pass, A2_Pass, A1_Pass, A0_Pass } = AOut_Pass; wire B0_zd ; wire B1_zd ; wire B2_zd ; wire B3_zd ; wire B4_zd ; wire B5_zd ; wire B6_zd ; wire B7_zd ; wire B8_zd ; wire B9_zd ; wire B10_zd ; wire B11_zd ; wire B12_zd ; wire B13_zd ; wire B14_zd ; wire B15_zd ; wire B16_zd ; wire B17_zd ; wire B18_zd ; wire B19_zd ; wire B20_zd ; wire B21_zd ; wire B22_zd ; wire B23_zd ; wire B24_zd ; wire B25_zd ; wire B26_zd ; wire B27_zd ; wire B28_zd ; wire B29_zd ; wire B30_zd ; wire B31_zd ; wire B32_zd ; wire B33_zd ; wire B34_zd ; wire B35_zd ; wire B0_Pass ; wire B1_Pass ; wire B2_Pass ; wire B3_Pass ; wire B4_Pass ; wire B5_Pass ; wire B6_Pass ; wire B7_Pass ; wire B8_Pass ; wire B9_Pass ; wire B10_Pass ; wire B11_Pass ; wire B12_Pass ; wire B13_Pass ; wire B14_Pass ; wire B15_Pass ; wire B16_Pass ; wire B17_Pass ; wire B18_Pass ; wire B19_Pass ; wire B20_Pass ; wire B21_Pass ; wire B22_Pass ; wire B23_Pass ; wire B24_Pass ; wire B25_Pass ; wire B26_Pass ; wire B27_Pass ; wire B28_Pass ; wire B29_Pass ; wire B30_Pass ; wire B31_Pass ; wire B32_Pass ; wire B33_Pass ; wire B34_Pass ; wire B35_Pass ; reg [35 : 0] BOut_Pass = 36'bz; assign { B35_Pass , B34_Pass , B33_Pass , B32_Pass , B31_Pass , B30_Pass , B29_Pass , B28_Pass , B27_Pass , B26_Pass , B25_Pass, B24_Pass, B23_Pass, B22_Pass, B21_Pass, B20_Pass, B19_Pass, B18_Pass, B17_Pass, B16_Pass, B15_Pass, B14_Pass, B13_Pass, B12_Pass, B11_Pass, B10_Pass, B9_Pass, B8_Pass, B7_Pass, B6_Pass, B5_Pass, B4_Pass, B3_Pass, B2_Pass, B1_Pass, B0_Pass } = BOut_Pass; reg AENeg_zd ; reg AFNeg_zd ; reg EFNeg_zd ; reg FFNeg_zd ; reg MBF1Neg_zd ; reg MBF2Neg_zd ; reg PEFANeg_zd ; reg PEFBNeg_zd ; reg Viol = 1'b0; parameter FIFOMemorySize =64; integer MemDataL[0:FIFOMemorySize-1]; integer MemDataH[0:FIFOMemorySize-1]; parameter TimingModel = "DefaultTimingModel"; reg [35:0] MAIL1 ; reg [35:0] MAIL2 ; parameter partID = "idt723611L15PFG"; reg flagCLKAskew2 = 1'b0; reg flagCLKAskew1 = 1'b0; reg flagCLKBskew2 = 1'b0; reg flagCLKBskew1 = 1'b0; integer INTER_AE = 5; integer INTER_AF = 5; integer INTER_FF = 5; integer INTER_EF = 5; integer OffsetRegister = 0; integer FL_MBF1 = 0; integer FL_MBF2 = 0; reg READMAIL1 =1'b0; reg READMAIL2 =1'b0; integer RDPoint = 0; integer WRPoint = 0; integer Count = 0; integer CLKA_late; integer CLKB_late; reg IN_FFNeg = 1'b0; reg IN_EFNeg = 1'b0; reg IN_AFNeg = 1'b0; reg IN_AENeg = 1'b0; reg RST_FLEG = 1'b0; reg FF_FLEG = 1'b0; reg IN_MBF1Neg = 1'b0; reg IN_MBF2Neg = 1'b0; reg [35:0] Parity_Data ; reg reseted ; integer COUNTB = 0; integer COUNTA = 0; integer COUNT = 0; time tdevice_SKEW1 = 8; time tdevice_SKEW2 = 16; reg [35:0] Outtput_Reg_A = 36'b0; reg [35:0] Outtput_Reg_B = 36'b0; reg [35:0] POM_Z = 36'bz; reg [35:0] AIn_late = 36'bz; reg [35:0] BIn_late = 36'bz; time tCLKAposedge = 0; time tCLKBposedge = 0; time tCSBNegnegedge = 0; time tCSANegnegedge = 0; time tMBBnegedge = 0; time tMBAnegedge = 0; time tWRANegnegedge = 0; time tWRBNegnegedge = 0; reg FROMCLKA =1'b1; reg FROMCLKB =1'b1; reg FROMMBB =1'b0; reg FROMMBA =1'b0; reg FROMOddEVENNeg = 1'b0; reg FROMENA = 1'b0; reg FROMENB = 1'b0; reg FROMWRANeg =1'b0; reg FROMWRBNeg = 1'b0; reg FROMPGA = 1'b0; reg FROMPGB = 1'b0; reg FROMCSA = 1'b0; reg FROMCSB = 1'b0; /////////////////////////////////////////////////////////////////////////////// //Interconnect Path Delay Section /////////////////////////////////////////////////////////////////////////////// buf (A35_ipd, A35); buf (A34_ipd, A34); buf (A33_ipd, A33); buf (A32_ipd, A32); buf (A31_ipd, A31); buf (A30_ipd, A30); buf (A29_ipd, A29); buf (A28_ipd, A28); buf (A27_ipd, A27); buf (A26_ipd, A26); buf (A25_ipd ,A25 ); buf (A24_ipd ,A24 ); buf (A23_ipd ,A23 ); buf (A22_ipd ,A22 ); buf (A21_ipd ,A21 ); buf (A20_ipd ,A20 ); buf (A19_ipd, A19); buf (A18_ipd, A18); buf (A17_ipd, A17); buf (A16_ipd, A16); buf (A15_ipd, A15); buf (A14_ipd, A14); buf (A13_ipd, A13); buf (A12_ipd, A12); buf (A11_ipd, A11); buf (A10_ipd, A10); buf (A9_ipd , A9 ); buf (A8_ipd , A8 ); buf (A7_ipd , A7 ); buf (A6_ipd , A6 ); buf (A5_ipd , A5 ); buf (A4_ipd , A4 ); buf (A3_ipd , A3 ); buf (A2_ipd , A2 ); buf (A1_ipd , A1 ); buf (A0_ipd , A0 ); buf (B35_ipd, B35); buf (B34_ipd, B34); buf (B33_ipd, B33); buf (B32_ipd, B32); buf (B31_ipd, B31); buf (B30_ipd, B30); buf (B29_ipd, B29); buf (B28_ipd, B28); buf (B27_ipd, B27); buf (B26_ipd, B26); buf (B25_ipd ,B25 ); buf (B24_ipd ,B24 ); buf (B23_ipd ,B23 ); buf (B22_ipd ,B22 ); buf (B21_ipd ,B21 ); buf (B20_ipd ,B20 ); buf (B19_ipd, B19); buf (B18_ipd, B18); buf (B17_ipd, B17); buf (B16_ipd, B16); buf (B15_ipd, B15); buf (B14_ipd, B14); buf (B13_ipd, B13); buf (B12_ipd, B12); buf (B11_ipd, B11); buf (B10_ipd, B10); buf (B9_ipd , B9 ); buf (B8_ipd , B8 ); buf (B7_ipd , B7 ); buf (B6_ipd , B6 ); buf (B5_ipd , B5 ); buf (B4_ipd , B4 ); buf (B3_ipd , B3 ); buf (B2_ipd , B2 ); buf (B1_ipd , B1 ); buf (B0_ipd , B0 ); buf (CLKA_ipd , CLKA ); buf (CLKB_ipd , CLKB ); buf (CSANeg_ipd , CSANeg ); buf (CSBNeg_ipd , CSBNeg ); buf (ENA_ipd , ENA ); buf (ENB_ipd , ENB ); buf (FS0_ipd , FS0 ); buf (FS1_ipd , FS1 ); buf (MBA_ipd , MBA ); buf (MBB_ipd , MBB ); buf (OddEVENNeg_ipd , OddEVENNeg ); buf (PGA_ipd , PGA ); buf (PGB_ipd , PGB ); buf (RSTNeg_ipd , RSTNeg ); buf (WRANeg_ipd , WRANeg ); buf (WRBNeg_ipd , WRBNeg ); /////////////////////////////////////////////////////////////////////////////// // Propagation delay Section /////////////////////////////////////////////////////////////////////////////// nmos (A0 , A0_Pass , 1); nmos (A1 , A1_Pass , 1); nmos (A2 , A2_Pass , 1); nmos (A3 , A3_Pass , 1); nmos (A4 , A4_Pass , 1); nmos (A5 , A5_Pass , 1); nmos (A6 , A6_Pass , 1); nmos (A7 , A7_Pass , 1); nmos (A8 , A8_Pass , 1); nmos (A9 , A9_Pass , 1); nmos (A10, A10_Pass , 1); nmos (A11, A11_Pass , 1); nmos (A12, A12_Pass , 1); nmos (A13, A13_Pass , 1); nmos (A14, A14_Pass , 1); nmos (A15, A15_Pass , 1); nmos (A16, A16_Pass , 1); nmos (A17, A17_Pass , 1); nmos (A18, A18_Pass , 1); nmos (A19, A19_Pass , 1); nmos (A20, A20_Pass , 1); nmos (A21, A21_Pass , 1); nmos (A22, A22_Pass , 1); nmos (A23, A23_Pass , 1); nmos (A24, A24_Pass , 1); nmos (A25, A25_Pass , 1); nmos (A26, A26_Pass , 1); nmos (A27, A27_Pass , 1); nmos (A28, A28_Pass , 1); nmos (A29, A29_Pass , 1); nmos (A30, A30_Pass , 1); nmos (A31, A31_Pass , 1); nmos (A32, A32_Pass , 1); nmos (A33, A33_Pass , 1); nmos (A34, A34_Pass , 1); nmos (A35, A35_Pass , 1); nmos (B0 , B0_Pass , 1); nmos (B1 , B1_Pass , 1); nmos (B2 , B2_Pass , 1); nmos (B3 , B3_Pass , 1); nmos (B4 , B4_Pass , 1); nmos (B5 , B5_Pass , 1); nmos (B6 , B6_Pass , 1); nmos (B7 , B7_Pass , 1); nmos (B8 , B8_Pass , 1); nmos (B9 , B9_Pass , 1); nmos (B10, B10_Pass , 1); nmos (B11, B11_Pass , 1); nmos (B12, B12_Pass , 1); nmos (B13, B13_Pass , 1); nmos (B14, B14_Pass , 1); nmos (B15, B15_Pass , 1); nmos (B16, B16_Pass , 1); nmos (B17, B17_Pass , 1); nmos (B18, B18_Pass , 1); nmos (B19, B19_Pass , 1); nmos (B20, B20_Pass , 1); nmos (B21, B21_Pass , 1); nmos (B22, B22_Pass , 1); nmos (B23, B23_Pass , 1); nmos (B24, B24_Pass , 1); nmos (B25, B25_Pass , 1); nmos (B26, B26_Pass , 1); nmos (B27, B27_Pass , 1); nmos (B28, B28_Pass , 1); nmos (B29, B29_Pass , 1); nmos (B30, B30_Pass , 1); nmos (B31, B31_Pass , 1); nmos (B32, B32_Pass , 1); nmos (B33, B33_Pass , 1); nmos (B34, B34_Pass , 1); nmos (B35, B35_Pass , 1); nmos (AENeg , 1'b0 , ~AENeg_zd ); nmos (AFNeg , 1'b0 , ~AFNeg_zd ); nmos (EFNeg , 1'b0 , ~EFNeg_zd ); nmos (FFNeg , 1'b0 , ~FFNeg_zd ); nmos (AENeg , 1'b1 , AENeg_zd ); nmos (AFNeg , 1'b1 , AFNeg_zd ); nmos (EFNeg , 1'b1 , EFNeg_zd ); nmos (FFNeg , 1'b1 , FFNeg_zd ); nmos (MBF1Neg , 1'b0 , ~MBF1Neg_zd); nmos (MBF2Neg , 1'b0 , ~MBF2Neg_zd); nmos (PEFANeg , 1'b0 , ~PEFANeg_zd); nmos (PEFBNeg , 1'b0 , ~PEFBNeg_zd); nmos (MBF1Neg , 1'b1 , MBF1Neg_zd); nmos (MBF2Neg , 1'b1 , MBF2Neg_zd); nmos (PEFANeg , 1'b1 , PEFANeg_zd); nmos (PEFBNeg , 1'b1 , PEFBNeg_zd); wire deg; specify // tipd delays: interconnect path delays , mapped to input port delays. // In Verilog is not necessary to declare any tipd_ delay variables, // they can be taken from SDF file // With all the other delays real delays would be taken from SDF file // tpd delays specparam tpd_CLKB_B0 =1; specparam tpd_CLKB_B1 =1; specparam tpd_CLKB_B2 =1; specparam tpd_CLKB_B3 =1; specparam tpd_CLKB_B4 =1; specparam tpd_CLKB_B5 =1; specparam tpd_CLKB_B6 =1; specparam tpd_CLKB_B7 =1; specparam tpd_CLKB_B8 =1; specparam tpd_CLKB_B9 =1; specparam tpd_CLKB_B10 =1; specparam tpd_CLKB_B11 =1; specparam tpd_CLKB_B12 =1; specparam tpd_CLKB_B13 =1; specparam tpd_CLKB_B14 =1; specparam tpd_CLKB_B15 =1; specparam tpd_CLKB_B16 =1; specparam tpd_CLKB_B17 =1; specparam tpd_CLKB_B18 =1; specparam tpd_CLKB_B19 =1; specparam tpd_CLKB_B20 =1; specparam tpd_CLKB_B21 =1; specparam tpd_CLKB_B22 =1; specparam tpd_CLKB_B23 =1; specparam tpd_CLKB_B24 =1; specparam tpd_CLKB_B25 =1; specparam tpd_CLKB_B26 =1; specparam tpd_CLKB_B27 =1; specparam tpd_CLKB_B28 =1; specparam tpd_CLKB_B29 =1; specparam tpd_CLKB_B30 =1; specparam tpd_CLKB_B31 =1; specparam tpd_CLKB_B32 =1; specparam tpd_CLKB_B33 =1; specparam tpd_CLKB_B34 =1; specparam tpd_CLKB_B35 =1; specparam tpd_MBB_B0 =1; specparam tpd_MBB_B1 =1; specparam tpd_MBB_B2 =1; specparam tpd_MBB_B3 =1; specparam tpd_MBB_B4 =1; specparam tpd_MBB_B5 =1; specparam tpd_MBB_B6 =1; specparam tpd_MBB_B7 =1; specparam tpd_MBB_B8 =1; specparam tpd_MBB_B9 =1; specparam tpd_MBB_B10 =1; specparam tpd_MBB_B11 =1; specparam tpd_MBB_B12 =1; specparam tpd_MBB_B13 =1; specparam tpd_MBB_B14 =1; specparam tpd_MBB_B15 =1; specparam tpd_MBB_B16 =1; specparam tpd_MBB_B17 =1; specparam tpd_MBB_B18 =1; specparam tpd_MBB_B19 =1; specparam tpd_MBB_B20 =1; specparam tpd_MBB_B21 =1; specparam tpd_MBB_B22 =1; specparam tpd_MBB_B23 =1; specparam tpd_MBB_B24 =1; specparam tpd_MBB_B25 =1; specparam tpd_MBB_B26 =1; specparam tpd_MBB_B27 =1; specparam tpd_MBB_B28 =1; specparam tpd_MBB_B29 =1; specparam tpd_MBB_B30 =1; specparam tpd_MBB_B31 =1; specparam tpd_MBB_B32 =1; specparam tpd_MBB_B33 =1; specparam tpd_MBB_B34 =1; specparam tpd_MBB_B35 =1; specparam tpd_CSANeg_A0 =1; specparam tpd_CSANeg_A1 =1; specparam tpd_CSANeg_A2 =1; specparam tpd_CSANeg_A3 =1; specparam tpd_CSANeg_A4 =1; specparam tpd_CSANeg_A5 =1; specparam tpd_CSANeg_A6 =1; specparam tpd_CSANeg_A7 =1; specparam tpd_CSANeg_A8 =1; specparam tpd_CSANeg_A9 =1; specparam tpd_CSANeg_A10 =1; specparam tpd_CSANeg_A11 =1; specparam tpd_CSANeg_A12 =1; specparam tpd_CSANeg_A13 =1; specparam tpd_CSANeg_A14 =1; specparam tpd_CSANeg_A15 =1; specparam tpd_CSANeg_A16 =1; specparam tpd_CSANeg_A17 =1; specparam tpd_CSANeg_A18 =1; specparam tpd_CSANeg_A19 =1; specparam tpd_CSANeg_A20 =1; specparam tpd_CSANeg_A21 =1; specparam tpd_CSANeg_A22 =1; specparam tpd_CSANeg_A23 =1; specparam tpd_CSANeg_A24 =1; specparam tpd_CSANeg_A25 =1; specparam tpd_CSANeg_A26 =1; specparam tpd_CSANeg_A27 =1; specparam tpd_CSANeg_A28 =1; specparam tpd_CSANeg_A29 =1; specparam tpd_CSANeg_A30 =1; specparam tpd_CSANeg_A31 =1; specparam tpd_CSANeg_A32 =1; specparam tpd_CSANeg_A33 =1; specparam tpd_CSANeg_A34 =1; specparam tpd_CSANeg_A35 =1; specparam tpd_WRANeg_A0 =1; specparam tpd_WRANeg_A1 =1; specparam tpd_WRANeg_A2 =1; specparam tpd_WRANeg_A3 =1; specparam tpd_WRANeg_A4 =1; specparam tpd_WRANeg_A5 =1; specparam tpd_WRANeg_A6 =1; specparam tpd_WRANeg_A7 =1; specparam tpd_WRANeg_A8 =1; specparam tpd_WRANeg_A9 =1; specparam tpd_WRANeg_A10 =1; specparam tpd_WRANeg_A11 =1; specparam tpd_WRANeg_A12 =1; specparam tpd_WRANeg_A13 =1; specparam tpd_WRANeg_A14 =1; specparam tpd_WRANeg_A15 =1; specparam tpd_WRANeg_A16 =1; specparam tpd_WRANeg_A17 =1; specparam tpd_WRANeg_A18 =1; specparam tpd_WRANeg_A19 =1; specparam tpd_WRANeg_A20 =1; specparam tpd_WRANeg_A21 =1; specparam tpd_WRANeg_A22 =1; specparam tpd_WRANeg_A23 =1; specparam tpd_WRANeg_A24 =1; specparam tpd_WRANeg_A25 =1; specparam tpd_WRANeg_A26 =1; specparam tpd_WRANeg_A27 =1; specparam tpd_WRANeg_A28 =1; specparam tpd_WRANeg_A29 =1; specparam tpd_WRANeg_A30 =1; specparam tpd_WRANeg_A31 =1; specparam tpd_WRANeg_A32 =1; specparam tpd_WRANeg_A33 =1; specparam tpd_WRANeg_A34 =1; specparam tpd_WRANeg_A35 =1; specparam tpd_CSBNeg_B0 =1; specparam tpd_CSBNeg_B1 =1; specparam tpd_CSBNeg_B2 =1; specparam tpd_CSBNeg_B3 =1; specparam tpd_CSBNeg_B4 =1; specparam tpd_CSBNeg_B5 =1; specparam tpd_CSBNeg_B6 =1; specparam tpd_CSBNeg_B7 =1; specparam tpd_CSBNeg_B8 =1; specparam tpd_CSBNeg_B9 =1; specparam tpd_CSBNeg_B10 =1; specparam tpd_CSBNeg_B11 =1; specparam tpd_CSBNeg_B12 =1; specparam tpd_CSBNeg_B13 =1; specparam tpd_CSBNeg_B14 =1; specparam tpd_CSBNeg_B15 =1; specparam tpd_CSBNeg_B16 =1; specparam tpd_CSBNeg_B17 =1; specparam tpd_CSBNeg_B18 =1; specparam tpd_CSBNeg_B19 =1; specparam tpd_CSBNeg_B20 =1; specparam tpd_CSBNeg_B21 =1; specparam tpd_CSBNeg_B22 =1; specparam tpd_CSBNeg_B23 =1; specparam tpd_CSBNeg_B24 =1; specparam tpd_CSBNeg_B25 =1; specparam tpd_CSBNeg_B26 =1; specparam tpd_CSBNeg_B27 =1; specparam tpd_CSBNeg_B28 =1; specparam tpd_CSBNeg_B29 =1; specparam tpd_CSBNeg_B30 =1; specparam tpd_CSBNeg_B31 =1; specparam tpd_CSBNeg_B32 =1; specparam tpd_CSBNeg_B33 =1; specparam tpd_CSBNeg_B34 =1; specparam tpd_CSBNeg_B35 =1; specparam tpd_WRBNeg_B0 =1; specparam tpd_WRBNeg_B1 =1; specparam tpd_WRBNeg_B2 =1; specparam tpd_WRBNeg_B3 =1; specparam tpd_WRBNeg_B4 =1; specparam tpd_WRBNeg_B5 =1; specparam tpd_WRBNeg_B6 =1; specparam tpd_WRBNeg_B7 =1; specparam tpd_WRBNeg_B8 =1; specparam tpd_WRBNeg_B9 =1; specparam tpd_WRBNeg_B10 =1; specparam tpd_WRBNeg_B11 =1; specparam tpd_WRBNeg_B12 =1; specparam tpd_WRBNeg_B13 =1; specparam tpd_WRBNeg_B14 =1; specparam tpd_WRBNeg_B15 =1; specparam tpd_WRBNeg_B16 =1; specparam tpd_WRBNeg_B17 =1; specparam tpd_WRBNeg_B18 =1; specparam tpd_WRBNeg_B19 =1; specparam tpd_WRBNeg_B20 =1; specparam tpd_WRBNeg_B21 =1; specparam tpd_WRBNeg_B22 =1; specparam tpd_WRBNeg_B23 =1; specparam tpd_WRBNeg_B24 =1; specparam tpd_WRBNeg_B25 =1; specparam tpd_WRBNeg_B26 =1; specparam tpd_WRBNeg_B27 =1; specparam tpd_WRBNeg_B28 =1; specparam tpd_WRBNeg_B29 =1; specparam tpd_WRBNeg_B30 =1; specparam tpd_WRBNeg_B31 =1; specparam tpd_WRBNeg_B32 =1; specparam tpd_WRBNeg_B33 =1; specparam tpd_WRBNeg_B34 =1; specparam tpd_WRBNeg_B35 =1; specparam tpd_CLKA_A0 =1; specparam tpd_CLKA_A1 =1; specparam tpd_CLKA_A2 =1; specparam tpd_CLKA_A3 =1; specparam tpd_CLKA_A4 =1; specparam tpd_CLKA_A5 =1; specparam tpd_CLKA_A6 =1; specparam tpd_CLKA_A7 =1; specparam tpd_CLKA_A8 =1; specparam tpd_CLKA_A9 =1; specparam tpd_CLKA_A10 =1; specparam tpd_CLKA_A11 =1; specparam tpd_CLKA_A12 =1; specparam tpd_CLKA_A13 =1; specparam tpd_CLKA_A14 =1; specparam tpd_CLKA_A15 =1; specparam tpd_CLKA_A16 =1; specparam tpd_CLKA_A17 =1; specparam tpd_CLKA_A18 =1; specparam tpd_CLKA_A19 =1; specparam tpd_CLKA_A20 =1; specparam tpd_CLKA_A21 =1; specparam tpd_CLKA_A22 =1; specparam tpd_CLKA_A23 =1; specparam tpd_CLKA_A24 =1; specparam tpd_CLKA_A25 =1; specparam tpd_CLKA_A26 =1; specparam tpd_CLKA_A27 =1; specparam tpd_CLKA_A28 =1; specparam tpd_CLKA_A29 =1; specparam tpd_CLKA_A30 =1; specparam tpd_CLKA_A31 =1; specparam tpd_CLKA_A32 =1; specparam tpd_CLKA_A33 =1; specparam tpd_CLKA_A34 =1; specparam tpd_CLKA_A35 =1; specparam tpd_CLKA_B0 =1; specparam tpd_CLKA_B1 =1; specparam tpd_CLKA_B2 =1; specparam tpd_CLKA_B3 =1; specparam tpd_CLKA_B4 =1; specparam tpd_CLKA_B5 =1; specparam tpd_CLKA_B6 =1; specparam tpd_CLKA_B7 =1; specparam tpd_CLKA_B8 =1; specparam tpd_CLKA_B9 =1; specparam tpd_CLKA_B10 =1; specparam tpd_CLKA_B11 =1; specparam tpd_CLKA_B12 =1; specparam tpd_CLKA_B13 =1; specparam tpd_CLKA_B14 =1; specparam tpd_CLKA_B15 =1; specparam tpd_CLKA_B16 =1; specparam tpd_CLKA_B17 =1; specparam tpd_CLKA_B18 =1; specparam tpd_CLKA_B19 =1; specparam tpd_CLKA_B20 =1; specparam tpd_CLKA_B21 =1; specparam tpd_CLKA_B22 =1; specparam tpd_CLKA_B23 =1; specparam tpd_CLKA_B24 =1; specparam tpd_CLKA_B25 =1; specparam tpd_CLKA_B26 =1; specparam tpd_CLKA_B27 =1; specparam tpd_CLKA_B28 =1; specparam tpd_CLKA_B29 =1; specparam tpd_CLKA_B30 =1; specparam tpd_CLKA_B31 =1; specparam tpd_CLKA_B32 =1; specparam tpd_CLKA_B33 =1; specparam tpd_CLKA_B34 =1; specparam tpd_CLKA_B35 =1; specparam tpd_CLKB_A0 =1; specparam tpd_CLKB_A1 =1; specparam tpd_CLKB_A2 =1; specparam tpd_CLKB_A3 =1; specparam tpd_CLKB_A4 =1; specparam tpd_CLKB_A5 =1; specparam tpd_CLKB_A6 =1; specparam tpd_CLKB_A7 =1; specparam tpd_CLKB_A8 =1; specparam tpd_CLKB_A9 =1; specparam tpd_CLKB_A10 =1; specparam tpd_CLKB_A11 =1; specparam tpd_CLKB_A12 =1; specparam tpd_CLKB_A13 =1; specparam tpd_CLKB_A14 =1; specparam tpd_CLKB_A15 =1; specparam tpd_CLKB_A16 =1; specparam tpd_CLKB_A17 =1; specparam tpd_CLKB_A18 =1; specparam tpd_CLKB_A19 =1; specparam tpd_CLKB_A20 =1; specparam tpd_CLKB_A21 =1; specparam tpd_CLKB_A22 =1; specparam tpd_CLKB_A23 =1; specparam tpd_CLKB_A24 =1; specparam tpd_CLKB_A25 =1; specparam tpd_CLKB_A26 =1; specparam tpd_CLKB_A27 =1; specparam tpd_CLKB_A28 =1; specparam tpd_CLKB_A29 =1; specparam tpd_CLKB_A30 =1; specparam tpd_CLKB_A31 =1; specparam tpd_CLKB_A32 =1; specparam tpd_CLKB_A33 =1; specparam tpd_CLKB_A34 =1; specparam tpd_CLKB_A35 =1; specparam tpd_OddEVENNeg_A8 =1; specparam tpd_OddEVENNeg_A17 =1; specparam tpd_OddEVENNeg_A26 =1; specparam tpd_OddEVENNeg_A35 =1; specparam tpd_OddEVENNeg_B8 =1; specparam tpd_OddEVENNeg_B17 =1; specparam tpd_OddEVENNeg_B26 =1; specparam tpd_OddEVENNeg_B35 =1; specparam tpd_ENA_A0 =1; specparam tpd_ENA_A1 =1; specparam tpd_ENA_A2 =1; specparam tpd_ENA_A3 =1; specparam tpd_ENA_A4 =1; specparam tpd_ENA_A5 =1; specparam tpd_ENA_A6 =1; specparam tpd_ENA_A7 =1; specparam tpd_ENA_A8 =1; specparam tpd_ENA_A9 =1; specparam tpd_ENA_A10 =1; specparam tpd_ENA_A11 =1; specparam tpd_ENA_A12 =1; specparam tpd_ENA_A13 =1; specparam tpd_ENA_A14 =1; specparam tpd_ENA_A15 =1; specparam tpd_ENA_A16 =1; specparam tpd_ENA_A17 =1; specparam tpd_ENA_A18 =1; specparam tpd_ENA_A19 =1; specparam tpd_ENA_A20 =1; specparam tpd_ENA_A21 =1; specparam tpd_ENA_A22 =1; specparam tpd_ENA_A23 =1; specparam tpd_ENA_A24 =1; specparam tpd_ENA_A25 =1; specparam tpd_ENA_A26 =1; specparam tpd_ENA_A27 =1; specparam tpd_ENA_A28 =1; specparam tpd_ENA_A29 =1; specparam tpd_ENA_A30 =1; specparam tpd_ENA_A31 =1; specparam tpd_ENA_A32 =1; specparam tpd_ENA_A33 =1; specparam tpd_ENA_A34 =1; specparam tpd_ENA_A35 =1; specparam tpd_ENB_B0 =1; specparam tpd_ENB_B1 =1; specparam tpd_ENB_B2 =1; specparam tpd_ENB_B3 =1; specparam tpd_ENB_B4 =1; specparam tpd_ENB_B5 =1; specparam tpd_ENB_B6 =1; specparam tpd_ENB_B7 =1; specparam tpd_ENB_B8 =1; specparam tpd_ENB_B9 =1; specparam tpd_ENB_B10 =1; specparam tpd_ENB_B11 =1; specparam tpd_ENB_B12 =1; specparam tpd_ENB_B13 =1; specparam tpd_ENB_B14 =1; specparam tpd_ENB_B15 =1; specparam tpd_ENB_B16 =1; specparam tpd_ENB_B17 =1; specparam tpd_ENB_B18 =1; specparam tpd_ENB_B19 =1; specparam tpd_ENB_B20 =1; specparam tpd_ENB_B21 =1; specparam tpd_ENB_B22 =1; specparam tpd_ENB_B23 =1; specparam tpd_ENB_B24 =1; specparam tpd_ENB_B25 =1; specparam tpd_ENB_B26 =1; specparam tpd_ENB_B27 =1; specparam tpd_ENB_B28 =1; specparam tpd_ENB_B29 =1; specparam tpd_ENB_B30 =1; specparam tpd_ENB_B31 =1; specparam tpd_ENB_B32 =1; specparam tpd_ENB_B33 =1; specparam tpd_ENB_B34 =1; specparam tpd_ENB_B35 =1; specparam tpd_MBA_A0 =1; specparam tpd_MBA_A1 =1; specparam tpd_MBA_A2 =1; specparam tpd_MBA_A3 =1; specparam tpd_MBA_A4 =1; specparam tpd_MBA_A5 =1; specparam tpd_MBA_A6 =1; specparam tpd_MBA_A7 =1; specparam tpd_MBA_A8 =1; specparam tpd_MBA_A9 =1; specparam tpd_MBA_A10 =1; specparam tpd_MBA_A11 =1; specparam tpd_MBA_A12 =1; specparam tpd_MBA_A13 =1; specparam tpd_MBA_A14 =1; specparam tpd_MBA_A15 =1; specparam tpd_MBA_A16 =1; specparam tpd_MBA_A17 =1; specparam tpd_MBA_A18 =1; specparam tpd_MBA_A19 =1; specparam tpd_MBA_A20 =1; specparam tpd_MBA_A21 =1; specparam tpd_MBA_A22 =1; specparam tpd_MBA_A23 =1; specparam tpd_MBA_A24 =1; specparam tpd_MBA_A25 =1; specparam tpd_MBA_A26 =1; specparam tpd_MBA_A27 =1; specparam tpd_MBA_A28 =1; specparam tpd_MBA_A29 =1; specparam tpd_MBA_A30 =1; specparam tpd_MBA_A31 =1; specparam tpd_MBA_A32 =1; specparam tpd_MBA_A33 =1; specparam tpd_MBA_A34 =1; specparam tpd_MBA_A35 =1; specparam tpd_PGA_A0 =1; specparam tpd_PGA_A1 =1; specparam tpd_PGA_A2 =1; specparam tpd_PGA_A3 =1; specparam tpd_PGA_A4 =1; specparam tpd_PGA_A5 =1; specparam tpd_PGA_A6 =1; specparam tpd_PGA_A7 =1; specparam tpd_PGA_A8 =1; specparam tpd_PGA_A9 =1; specparam tpd_PGA_A10 =1; specparam tpd_PGA_A11 =1; specparam tpd_PGA_A12 =1; specparam tpd_PGA_A13 =1; specparam tpd_PGA_A14 =1; specparam tpd_PGA_A15 =1; specparam tpd_PGA_A16 =1; specparam tpd_PGA_A17 =1; specparam tpd_PGA_A18 =1; specparam tpd_PGA_A19 =1; specparam tpd_PGA_A20 =1; specparam tpd_PGA_A21 =1; specparam tpd_PGA_A22 =1; specparam tpd_PGA_A23 =1; specparam tpd_PGA_A24 =1; specparam tpd_PGA_A25 =1; specparam tpd_PGA_A26 =1; specparam tpd_PGA_A27 =1; specparam tpd_PGA_A28 =1; specparam tpd_PGA_A29 =1; specparam tpd_PGA_A30 =1; specparam tpd_PGA_A31 =1; specparam tpd_PGA_A32 =1; specparam tpd_PGA_A33 =1; specparam tpd_PGA_A34 =1; specparam tpd_PGA_A35 =1; specparam tpd_PGB_B0 =1; specparam tpd_PGB_B1 =1; specparam tpd_PGB_B2 =1; specparam tpd_PGB_B3 =1; specparam tpd_PGB_B4 =1; specparam tpd_PGB_B5 =1; specparam tpd_PGB_B6 =1; specparam tpd_PGB_B7 =1; specparam tpd_PGB_B8 =1; specparam tpd_PGB_B9 =1; specparam tpd_PGB_B10 =1; specparam tpd_PGB_B11 =1; specparam tpd_PGB_B12 =1; specparam tpd_PGB_B13 =1; specparam tpd_PGB_B14 =1; specparam tpd_PGB_B15 =1; specparam tpd_PGB_B16 =1; specparam tpd_PGB_B17 =1; specparam tpd_PGB_B18 =1; specparam tpd_PGB_B19 =1; specparam tpd_PGB_B20 =1; specparam tpd_PGB_B21 =1; specparam tpd_PGB_B22 =1; specparam tpd_PGB_B23 =1; specparam tpd_PGB_B24 =1; specparam tpd_PGB_B25 =1; specparam tpd_PGB_B26 =1; specparam tpd_PGB_B27 =1; specparam tpd_PGB_B28 =1; specparam tpd_PGB_B29 =1; specparam tpd_PGB_B30 =1; specparam tpd_PGB_B31 =1; specparam tpd_PGB_B32 =1; specparam tpd_PGB_B33 =1; specparam tpd_PGB_B34 =1; specparam tpd_PGB_B35 =1; specparam tpd_A0_PEFANeg =1; specparam tpd_A1_PEFANeg =1; specparam tpd_A2_PEFANeg =1; specparam tpd_A3_PEFANeg =1; specparam tpd_A4_PEFANeg =1; specparam tpd_A5_PEFANeg =1; specparam tpd_A6_PEFANeg =1; specparam tpd_A7_PEFANeg =1; specparam tpd_A8_PEFANeg =1; specparam tpd_A9_PEFANeg =1; specparam tpd_A10_PEFANeg =1; specparam tpd_A11_PEFANeg =1; specparam tpd_A12_PEFANeg =1; specparam tpd_A13_PEFANeg =1; specparam tpd_A14_PEFANeg =1; specparam tpd_A15_PEFANeg =1; specparam tpd_A16_PEFANeg =1; specparam tpd_A17_PEFANeg =1; specparam tpd_A18_PEFANeg =1; specparam tpd_A19_PEFANeg =1; specparam tpd_A20_PEFANeg =1; specparam tpd_A21_PEFANeg =1; specparam tpd_A22_PEFANeg =1; specparam tpd_A23_PEFANeg =1; specparam tpd_A24_PEFANeg =1; specparam tpd_A25_PEFANeg =1; specparam tpd_A26_PEFANeg =1; specparam tpd_A27_PEFANeg =1; specparam tpd_A28_PEFANeg =1; specparam tpd_A29_PEFANeg =1; specparam tpd_A30_PEFANeg =1; specparam tpd_A31_PEFANeg =1; specparam tpd_A32_PEFANeg =1; specparam tpd_A33_PEFANeg =1; specparam tpd_A34_PEFANeg =1; specparam tpd_A35_PEFANeg =1; specparam tpd_B0_PEFBNeg =1; specparam tpd_B1_PEFBNeg =1; specparam tpd_B2_PEFBNeg =1; specparam tpd_B3_PEFBNeg =1; specparam tpd_B4_PEFBNeg =1; specparam tpd_B5_PEFBNeg =1; specparam tpd_B6_PEFBNeg =1; specparam tpd_B7_PEFBNeg =1; specparam tpd_B8_PEFBNeg =1; specparam tpd_B9_PEFBNeg =1; specparam tpd_B10_PEFBNeg =1; specparam tpd_B11_PEFBNeg =1; specparam tpd_B12_PEFBNeg =1; specparam tpd_B13_PEFBNeg =1; specparam tpd_B14_PEFBNeg =1; specparam tpd_B15_PEFBNeg =1; specparam tpd_B16_PEFBNeg =1; specparam tpd_B17_PEFBNeg =1; specparam tpd_B18_PEFBNeg =1; specparam tpd_B19_PEFBNeg =1; specparam tpd_B20_PEFBNeg =1; specparam tpd_B21_PEFBNeg =1; specparam tpd_B22_PEFBNeg =1; specparam tpd_B23_PEFBNeg =1; specparam tpd_B24_PEFBNeg =1; specparam tpd_B25_PEFBNeg =1; specparam tpd_B26_PEFBNeg =1; specparam tpd_B27_PEFBNeg =1; specparam tpd_B28_PEFBNeg =1; specparam tpd_B29_PEFBNeg =1; specparam tpd_B30_PEFBNeg =1; specparam tpd_B31_PEFBNeg =1; specparam tpd_B32_PEFBNeg =1; specparam tpd_B33_PEFBNeg =1; specparam tpd_B34_PEFBNeg =1; specparam tpd_B35_PEFBNeg =1; specparam tpd_CLKA_FFNeg =1; specparam tpd_CLKB_EFNeg =1; specparam tpd_CLKB_AENeg =1; specparam tpd_CLKA_AFNeg =1; specparam tpd_CLKA_MBF1Neg =1; specparam tpd_CLKA_MBF2Neg =1; specparam tpd_CLKB_MBF1Neg =1; specparam tpd_CLKB_MBF2Neg =1; specparam tpd_OddEVENNeg_PEFANeg =1; specparam tpd_OddEVENNeg_PEFBNeg =1; specparam tpd_CSANeg_PEFANeg =1; specparam tpd_ENA_PEFANeg =1; specparam tpd_WRANeg_PEFANeg =1; specparam tpd_MBA_PEFANeg =1; specparam tpd_PGA_PEFANeg =1; specparam tpd_CSBNeg_PEFBNeg =1; specparam tpd_ENB_PEFBNeg =1; specparam tpd_WRBNeg_PEFBNeg =1; specparam tpd_MBB_PEFBNeg =1; specparam tpd_PGB_PEFBNeg =1; specparam tpd_RSTNeg_AENeg =1; specparam tpd_RSTNeg_AFNeg =1; specparam tpd_RSTNeg_MBF1Neg =1; specparam tpd_RSTNeg_MBF2Neg =1; //tsetup values specparam tsetup_A0_CLKA =1; specparam tsetup_A1_CLKA =1; specparam tsetup_A2_CLKA =1; specparam tsetup_A3_CLKA =1; specparam tsetup_A4_CLKA =1; specparam tsetup_A5_CLKA =1; specparam tsetup_A6_CLKA =1; specparam tsetup_A7_CLKA =1; specparam tsetup_A8_CLKA =1; specparam tsetup_A9_CLKA =1; specparam tsetup_A10_CLKA =1; specparam tsetup_A11_CLKA =1; specparam tsetup_A12_CLKA =1; specparam tsetup_A13_CLKA =1; specparam tsetup_A14_CLKA =1; specparam tsetup_A15_CLKA =1; specparam tsetup_A16_CLKA =1; specparam tsetup_A17_CLKA =1; specparam tsetup_A18_CLKA =1; specparam tsetup_A19_CLKA =1; specparam tsetup_A20_CLKA =1; specparam tsetup_A21_CLKA =1; specparam tsetup_A22_CLKA =1; specparam tsetup_A23_CLKA =1; specparam tsetup_A24_CLKA =1; specparam tsetup_A25_CLKA =1; specparam tsetup_A26_CLKA =1; specparam tsetup_A27_CLKA =1; specparam tsetup_A28_CLKA =1; specparam tsetup_A29_CLKA =1; specparam tsetup_A30_CLKA =1; specparam tsetup_A31_CLKA =1; specparam tsetup_A32_CLKA =1; specparam tsetup_A33_CLKA =1; specparam tsetup_A34_CLKA =1; specparam tsetup_A35_CLKA =1; specparam tsetup_B0_CLKB =1; specparam tsetup_B1_CLKB =1; specparam tsetup_B2_CLKB =1; specparam tsetup_B3_CLKB =1; specparam tsetup_B4_CLKB =1; specparam tsetup_B5_CLKB =1; specparam tsetup_B6_CLKB =1; specparam tsetup_B7_CLKB =1; specparam tsetup_B8_CLKB =1; specparam tsetup_B9_CLKB =1; specparam tsetup_B10_CLKB =1; specparam tsetup_B11_CLKB =1; specparam tsetup_B12_CLKB =1; specparam tsetup_B13_CLKB =1; specparam tsetup_B14_CLKB =1; specparam tsetup_B15_CLKB =1; specparam tsetup_B16_CLKB =1; specparam tsetup_B17_CLKB =1; specparam tsetup_B18_CLKB =1; specparam tsetup_B19_CLKB =1; specparam tsetup_B20_CLKB =1; specparam tsetup_B21_CLKB =1; specparam tsetup_B22_CLKB =1; specparam tsetup_B23_CLKB =1; specparam tsetup_B24_CLKB =1; specparam tsetup_B25_CLKB =1; specparam tsetup_B26_CLKB =1; specparam tsetup_B27_CLKB =1; specparam tsetup_B28_CLKB =1; specparam tsetup_B29_CLKB =1; specparam tsetup_B30_CLKB =1; specparam tsetup_B31_CLKB =1; specparam tsetup_B32_CLKB =1; specparam tsetup_B33_CLKB =1; specparam tsetup_B34_CLKB =1; specparam tsetup_B35_CLKB =1; specparam tsetup_CSANeg_CLKA =1; specparam tsetup_WRANeg_CLKA =1; specparam tsetup_WRBNeg_CLKB =1; specparam tsetup_CSBNeg_CLKB =1; specparam tsetup_WRBNeg_CLKA =1; specparam tsetup_ENA_CLKA =1; specparam tsetup_ENB_CLKB =1; specparam tsetup_MBA_CLKA =1; specparam tsetup_MBB_CLKB =1; specparam tsetup_OddEVENNeg_CLKB =1; specparam tsetup_PGB_CLKB =1; specparam tsetup_RSTNeg_CLKA =1; specparam tsetup_RSTNeg_CLKB =1; specparam tsetup_FS0_RSTNeg =1; specparam tsetup_FS1_RSTNeg =1; //thold values specparam thold_A0_CLKA =1; specparam thold_A1_CLKA =1; specparam thold_A2_CLKA =1; specparam thold_A3_CLKA =1; specparam thold_A4_CLKA =1; specparam thold_A5_CLKA =1; specparam thold_A6_CLKA =1; specparam thold_A7_CLKA =1; specparam thold_A8_CLKA =1; specparam thold_A9_CLKA =1; specparam thold_A10_CLKA =1; specparam thold_A11_CLKA =1; specparam thold_A12_CLKA =1; specparam thold_A13_CLKA =1; specparam thold_A14_CLKA =1; specparam thold_A15_CLKA =1; specparam thold_A16_CLKA =1; specparam thold_A17_CLKA =1; specparam thold_A18_CLKA =1; specparam thold_A19_CLKA =1; specparam thold_A20_CLKA =1; specparam thold_A21_CLKA =1; specparam thold_A22_CLKA =1; specparam thold_A23_CLKA =1; specparam thold_A24_CLKA =1; specparam thold_A25_CLKA =1; specparam thold_A26_CLKA =1; specparam thold_A27_CLKA =1; specparam thold_A28_CLKA =1; specparam thold_A29_CLKA =1; specparam thold_A30_CLKA =1; specparam thold_A31_CLKA =1; specparam thold_A32_CLKA =1; specparam thold_A33_CLKA =1; specparam thold_A34_CLKA =1; specparam thold_A35_CLKA =1; specparam thold_B0_CLKB =1; specparam thold_B1_CLKB =1; specparam thold_B2_CLKB =1; specparam thold_B3_CLKB =1; specparam thold_B4_CLKB =1; specparam thold_B5_CLKB =1; specparam thold_B6_CLKB =1; specparam thold_B7_CLKB =1; specparam thold_B8_CLKB =1; specparam thold_B9_CLKB =1; specparam thold_B10_CLKB =1; specparam thold_B11_CLKB =1; specparam thold_B12_CLKB =1; specparam thold_B13_CLKB =1; specparam thold_B14_CLKB =1; specparam thold_B15_CLKB =1; specparam thold_B16_CLKB =1; specparam thold_B17_CLKB =1; specparam thold_B18_CLKB =1; specparam thold_B19_CLKB =1; specparam thold_B20_CLKB =1; specparam thold_B21_CLKB =1; specparam thold_B22_CLKB =1; specparam thold_B23_CLKB =1; specparam thold_B24_CLKB =1; specparam thold_B25_CLKB =1; specparam thold_B26_CLKB =1; specparam thold_B27_CLKB =1; specparam thold_B28_CLKB =1; specparam thold_B29_CLKB =1; specparam thold_B30_CLKB =1; specparam thold_B31_CLKB =1; specparam thold_B32_CLKB =1; specparam thold_B33_CLKB =1; specparam thold_B34_CLKB =1; specparam thold_B35_CLKB =1; specparam thold_CSANeg_CLKA =1; specparam thold_WRANeg_CLKA =1; specparam thold_CSBNeg_CLKB =1; specparam thold_WRBNeg_CLKB =1; specparam thold_ENA_CLKA =1; specparam thold_MBA_CLKA =1; specparam thold_ENB_CLKB =1; specparam thold_MBB_CLKB =1; specparam thold_OddEVENNeg_CLKB =1; specparam thold_RSTNeg_CLKA =1; specparam thold_RSTNeg_CLKB =1; specparam thold_FS0_RSTNeg =1; specparam thold_FS1_RSTNeg =1; //tpw values specparam tpw_CLKA_negedge = 1; specparam tpw_CLKA_posedge = 1; specparam tperiod_CLKA = 1; specparam tpw_CLKB_negedge = 1; specparam tpw_CLKB_posedge = 1; specparam tperiod_CLKB = 1; //tdevice values: values for internal delays /////////////////////////////////////////////////////////////////////////////// // Input Port Delays don't require Verilog description /////////////////////////////////////////////////////////////////////////////// // Path delays // /////////////////////////////////////////////////////////////////////////////// // Data ouptut paths if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B0 ) = tpd_CLKB_B0; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B1 ) = tpd_CLKB_B1; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B2 ) = tpd_CLKB_B2; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B3 ) = tpd_CLKB_B3; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B4 ) = tpd_CLKB_B4; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B5 ) = tpd_CLKB_B5; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B6 ) = tpd_CLKB_B6; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B7 ) = tpd_CLKB_B7; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B8 ) = tpd_CLKB_B8; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B9 ) = tpd_CLKB_B9; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B10 ) = tpd_CLKB_B10; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B11 ) = tpd_CLKB_B11; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B12 ) = tpd_CLKB_B12; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B13 ) = tpd_CLKB_B13; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B14 ) = tpd_CLKB_B14; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B15 ) = tpd_CLKB_B15; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B16 ) = tpd_CLKB_B16; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B17 ) = tpd_CLKB_B17; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B18 ) = tpd_CLKB_B18; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B19 ) = tpd_CLKB_B19; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B20 ) = tpd_CLKB_B20; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B21 ) = tpd_CLKB_B21; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B22 ) = tpd_CLKB_B22; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B23 ) = tpd_CLKB_B23; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B24 ) = tpd_CLKB_B24; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B25 ) = tpd_CLKB_B25; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B26 ) = tpd_CLKB_B26; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B27 ) = tpd_CLKB_B27; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B28 ) = tpd_CLKB_B28; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B29 ) = tpd_CLKB_B29; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B30 ) = tpd_CLKB_B30; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B31 ) = tpd_CLKB_B31; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B32 ) = tpd_CLKB_B32; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B33 ) = tpd_CLKB_B33; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B34 ) = tpd_CLKB_B34; if (FROMCLKB && (READMAIL1 ==1'b0)) ( CLKB => B35 ) = tpd_CLKB_B35; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B0 ) = tpd_MBB_B0; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B1 ) = tpd_MBB_B1; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B2 ) = tpd_MBB_B2; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B3 ) = tpd_MBB_B3; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B4 ) = tpd_MBB_B4; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B5 ) = tpd_MBB_B5; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B6 ) = tpd_MBB_B6; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B7 ) = tpd_MBB_B7; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B8 ) = tpd_MBB_B8; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B9 ) = tpd_MBB_B9; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B10 ) = tpd_MBB_B10; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B11 ) = tpd_MBB_B11; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B12 ) = tpd_MBB_B12; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B13 ) = tpd_MBB_B13; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B14 ) = tpd_MBB_B14; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B15 ) = tpd_MBB_B15; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B16 ) = tpd_MBB_B16; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B17 ) = tpd_MBB_B17; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B18 ) = tpd_MBB_B18; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B19 ) = tpd_MBB_B19; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B20 ) = tpd_MBB_B20; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B21 ) = tpd_MBB_B21; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B22 ) = tpd_MBB_B22; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B23 ) = tpd_MBB_B23; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B24 ) = tpd_MBB_B24; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B25 ) = tpd_MBB_B25; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B26 ) = tpd_MBB_B26; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B27 ) = tpd_MBB_B27; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B28 ) = tpd_MBB_B28; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B29 ) = tpd_MBB_B29; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B30 ) = tpd_MBB_B30; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B31 ) = tpd_MBB_B31; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B32 ) = tpd_MBB_B32; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B33 ) = tpd_MBB_B33; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B34 ) = tpd_MBB_B34; if (FROMMBB && (READMAIL1 ==1'b0)) ( MBB => B35 ) = tpd_MBB_B35; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A0 ) = tpd_CLKB_A0; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A1 ) = tpd_CLKB_A1; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A2 ) = tpd_CLKB_A2; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A3 ) = tpd_CLKB_A3; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A4 ) = tpd_CLKB_A4; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A5 ) = tpd_CLKB_A5; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A6 ) = tpd_CLKB_A6; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A7 ) = tpd_CLKB_A7; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A8 ) = tpd_CLKB_A8; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A9 ) = tpd_CLKB_A9; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A10 ) = tpd_CLKB_A10; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A11 ) = tpd_CLKB_A11; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A12 ) = tpd_CLKB_A12; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A13 ) = tpd_CLKB_A13; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A14 ) = tpd_CLKB_A14; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A15 ) = tpd_CLKB_A15; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A16 ) = tpd_CLKB_A16; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A17 ) = tpd_CLKB_A17; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A18 ) = tpd_CLKB_A18; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A19 ) = tpd_CLKB_A19; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A20 ) = tpd_CLKB_A20; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A21 ) = tpd_CLKB_A21; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A22 ) = tpd_CLKB_A22; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A23 ) = tpd_CLKB_A23; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A24 ) = tpd_CLKB_A24; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A25 ) = tpd_CLKB_A25; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A26 ) = tpd_CLKB_A26; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A27 ) = tpd_CLKB_A27; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A28 ) = tpd_CLKB_A28; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A29 ) = tpd_CLKB_A29; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A30 ) = tpd_CLKB_A30; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A31 ) = tpd_CLKB_A31; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A32 ) = tpd_CLKB_A32; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A33 ) = tpd_CLKB_A33; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A34 ) = tpd_CLKB_A34; if (FROMCLKB && (READMAIL2 ==1'b1))( CLKB => A35 ) = tpd_CLKB_A35; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B0 ) = tpd_CLKA_B0; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B1 ) = tpd_CLKA_B1; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B2 ) = tpd_CLKA_B2; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B3 ) = tpd_CLKA_B3; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B4 ) = tpd_CLKA_B4; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B5 ) = tpd_CLKA_B5; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B6 ) = tpd_CLKA_B6; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B7 ) = tpd_CLKA_B7; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B8 ) = tpd_CLKA_B8; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B9 ) = tpd_CLKA_B9; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B10 ) = tpd_CLKA_B10; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B11 ) = tpd_CLKA_B11; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B12 ) = tpd_CLKA_B12; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B13 ) = tpd_CLKA_B13; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B14 ) = tpd_CLKA_B14; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B15 ) = tpd_CLKA_B15; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B16 ) = tpd_CLKA_B16; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B17 ) = tpd_CLKA_B17; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B18 ) = tpd_CLKA_B18; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B19 ) = tpd_CLKA_B19; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B20 ) = tpd_CLKA_B20; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B21 ) = tpd_CLKA_B21; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B22 ) = tpd_CLKA_B22; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B23 ) = tpd_CLKA_B23; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B24 ) = tpd_CLKA_B24; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B25 ) = tpd_CLKA_B25; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B26 ) = tpd_CLKA_B26; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B27 ) = tpd_CLKA_B27; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B28 ) = tpd_CLKA_B28; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B29 ) = tpd_CLKA_B29; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B30 ) = tpd_CLKA_B30; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B31 ) = tpd_CLKA_B31; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B32 ) = tpd_CLKA_B32; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B33 ) = tpd_CLKA_B33; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B34 ) = tpd_CLKA_B34; if (FROMCLKA && (READMAIL1 ==1'b1))( CLKA => B35 ) = tpd_CLKA_B35; if (FROMCSA && (READMAIL2 ==1'b1)) ( CSANeg => A8 ) = tpd_CSANeg_A8; if (FROMCSA && (READMAIL2 ==1'b1)) ( CSANeg => A17 ) = tpd_CSANeg_A17; if (FROMCSA && (READMAIL2 ==1'b1)) ( CSANeg => A26 ) = tpd_CSANeg_A26; if (FROMCSA && (READMAIL2 ==1'b1)) ( CSANeg => A35 ) = tpd_CSANeg_A35; if (FROMCSB && (READMAIL1 ==1'b1)) ( CSBNeg => B8 ) = tpd_CSBNeg_B8; if (FROMCSB && (READMAIL1 ==1'b1)) ( CSBNeg => B17 ) = tpd_CSBNeg_B17; if (FROMCSB && (READMAIL1 ==1'b1)) ( CSBNeg => B26 ) = tpd_CSBNeg_B26; if (FROMCSB && (READMAIL1 ==1'b1)) ( CSBNeg => B35 ) = tpd_CSBNeg_B35; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A0 ) = tpd_CSANeg_A0; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A1 ) = tpd_CSANeg_A1; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A2 ) = tpd_CSANeg_A2; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A3 ) = tpd_CSANeg_A3; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A4 ) = tpd_CSANeg_A4; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A5 ) = tpd_CSANeg_A5; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A6 ) = tpd_CSANeg_A6; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A7 ) = tpd_CSANeg_A7; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A8 ) = tpd_CSANeg_A8; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A9 ) = tpd_CSANeg_A9; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A10 ) = tpd_CSANeg_A10; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A11 ) = tpd_CSANeg_A11; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A12 ) = tpd_CSANeg_A12; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A13 ) = tpd_CSANeg_A13; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A14 ) = tpd_CSANeg_A14; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A15 ) = tpd_CSANeg_A15; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A16 ) = tpd_CSANeg_A16; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A17 ) = tpd_CSANeg_A17; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A18 ) = tpd_CSANeg_A18; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A19 ) = tpd_CSANeg_A19; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A20 ) = tpd_CSANeg_A20; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A21 ) = tpd_CSANeg_A21; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A22 ) = tpd_CSANeg_A22; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A23 ) = tpd_CSANeg_A23; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A24 ) = tpd_CSANeg_A24; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A25 ) = tpd_CSANeg_A25; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A26 ) = tpd_CSANeg_A26; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A27 ) = tpd_CSANeg_A27; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A28 ) = tpd_CSANeg_A28; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A29 ) = tpd_CSANeg_A29; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A30 ) = tpd_CSANeg_A30; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A31 ) = tpd_CSANeg_A31; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A32 ) = tpd_CSANeg_A32; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A33 ) = tpd_CSANeg_A33; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A34 ) = tpd_CSANeg_A34; if (FROMCSA && (READMAIL2 ==1'b0)) ( CSANeg => A35 ) = tpd_CSANeg_A35; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B0 ) = tpd_CSBNeg_B0; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B1 ) = tpd_CSBNeg_B1; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B2 ) = tpd_CSBNeg_B2; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B3 ) = tpd_CSBNeg_B3; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B4 ) = tpd_CSBNeg_B4; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B5 ) = tpd_CSBNeg_B5; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B6 ) = tpd_CSBNeg_B6; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B7 ) = tpd_CSBNeg_B7; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B8 ) = tpd_CSBNeg_B8; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B9 ) = tpd_CSBNeg_B9; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B10 ) = tpd_CSBNeg_B10; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B11 ) = tpd_CSBNeg_B11; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B12 ) = tpd_CSBNeg_B12; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B13 ) = tpd_CSBNeg_B13; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B14 ) = tpd_CSBNeg_B14; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B15 ) = tpd_CSBNeg_B15; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B16 ) = tpd_CSBNeg_B16; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B17 ) = tpd_CSBNeg_B17; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B18 ) = tpd_CSBNeg_B18; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B19 ) = tpd_CSBNeg_B19; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B20 ) = tpd_CSBNeg_B20; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B21 ) = tpd_CSBNeg_B21; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B22 ) = tpd_CSBNeg_B22; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B23 ) = tpd_CSBNeg_B23; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B24 ) = tpd_CSBNeg_B24; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B25 ) = tpd_CSBNeg_B25; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B26 ) = tpd_CSBNeg_B26; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B27 ) = tpd_CSBNeg_B27; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B28 ) = tpd_CSBNeg_B28; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B29 ) = tpd_CSBNeg_B29; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B30 ) = tpd_CSBNeg_B30; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B31 ) = tpd_CSBNeg_B31; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B32 ) = tpd_CSBNeg_B32; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B33 ) = tpd_CSBNeg_B33; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B34 ) = tpd_CSBNeg_B34; if (FROMCSB && (READMAIL1 ==1'b0)) ( CSBNeg => B35 ) = tpd_CSBNeg_B35; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A0 ) = tpd_WRANeg_A0; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A1 ) = tpd_WRANeg_A1; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A2 ) = tpd_WRANeg_A2; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A3 ) = tpd_WRANeg_A3; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A4 ) = tpd_WRANeg_A4; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A5 ) = tpd_WRANeg_A5; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A6 ) = tpd_WRANeg_A6; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A7 ) = tpd_WRANeg_A7; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A8 ) = tpd_WRANeg_A8; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A9 ) = tpd_WRANeg_A9; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A10 )= tpd_WRANeg_A10; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A11 )= tpd_WRANeg_A11; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A12 )= tpd_WRANeg_A12; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A13 )= tpd_WRANeg_A13; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A14 )= tpd_WRANeg_A14; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A15 )= tpd_WRANeg_A15; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A16 )= tpd_WRANeg_A16; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A17 )= tpd_WRANeg_A17; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A18 )= tpd_WRANeg_A18; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A19 )= tpd_WRANeg_A19; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A20 )= tpd_WRANeg_A20; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A21 )= tpd_WRANeg_A21; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A22 )= tpd_WRANeg_A22; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A23 )= tpd_WRANeg_A23; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A24 )= tpd_WRANeg_A24; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A25 )= tpd_WRANeg_A25; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A26 )= tpd_WRANeg_A26; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A27 )= tpd_WRANeg_A27; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A28 )= tpd_WRANeg_A28; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A29 )= tpd_WRANeg_A29; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A30 )= tpd_WRANeg_A30; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A31 )= tpd_WRANeg_A31; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A32 )= tpd_WRANeg_A32; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A33 )= tpd_WRANeg_A33; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A34 )= tpd_WRANeg_A34; if (FROMWRANeg && (READMAIL2 ==1'b0))( WRANeg => A35 )= tpd_WRANeg_A35; if (FROMWRBNeg && (READMAIL2 ==1'b0))( WRBNeg => B0 ) = tpd_WRBNeg_B0; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B1 ) = tpd_WRBNeg_B1; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B2 ) = tpd_WRBNeg_B2; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B3 ) = tpd_WRBNeg_B3; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B4 ) = tpd_WRBNeg_B4; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B5 ) = tpd_WRBNeg_B5; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B6 ) = tpd_WRBNeg_B6; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B7 ) = tpd_WRBNeg_B7; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B8 ) = tpd_WRBNeg_B8; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B9 ) = tpd_WRBNeg_B9; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B10 ) = tpd_WRBNeg_B10; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B11 ) = tpd_WRBNeg_B11; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B12 ) = tpd_WRBNeg_B12; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B13 ) = tpd_WRBNeg_B13; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B14 ) = tpd_WRBNeg_B14; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B15 ) = tpd_WRBNeg_B15; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B16 ) = tpd_WRBNeg_B16; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B17 ) = tpd_WRBNeg_B17; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B18 ) = tpd_WRBNeg_B18; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B19 ) = tpd_WRBNeg_B19; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B20 ) = tpd_WRBNeg_B20; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B21 ) = tpd_WRBNeg_B21; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B22 ) = tpd_WRBNeg_B22; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B23 ) = tpd_WRBNeg_B23; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B24 ) = tpd_WRBNeg_B24; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B25 ) = tpd_WRBNeg_B25; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B26 ) = tpd_WRBNeg_B26; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B27 ) = tpd_WRBNeg_B27; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B28 ) = tpd_WRBNeg_B28; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B29 ) = tpd_WRBNeg_B29; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B30 ) = tpd_WRBNeg_B30; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B31 ) = tpd_WRBNeg_B31; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B32 ) = tpd_WRBNeg_B32; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B33 ) = tpd_WRBNeg_B33; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B34 ) = tpd_WRBNeg_B34; if (FROMWRBNeg && (READMAIL2 ==1'b0))(WRBNeg => B35 ) = tpd_WRBNeg_B35; if (FROMOddEVENNeg && (READMAIL2 ==1'b1)) ( OddEVENNeg => A8 ) = tpd_OddEVENNeg_A8; if (FROMOddEVENNeg && (READMAIL2 ==1'b1)) ( OddEVENNeg => A17 ) = tpd_OddEVENNeg_A17; if (FROMOddEVENNeg && (READMAIL2 ==1'b1)) ( OddEVENNeg => A26 ) = tpd_OddEVENNeg_A26; if (FROMOddEVENNeg && (READMAIL2 ==1'b1)) ( OddEVENNeg => A35 ) = tpd_OddEVENNeg_A35; if (FROMOddEVENNeg && (READMAIL1 ==1'b1)) ( OddEVENNeg => B8 ) = tpd_OddEVENNeg_B8; if (FROMOddEVENNeg && (READMAIL1 ==1'b1)) ( OddEVENNeg => B17 ) = tpd_OddEVENNeg_B17; if (FROMOddEVENNeg && (READMAIL1 ==1'b1)) ( OddEVENNeg => B26 ) = tpd_OddEVENNeg_B26; if (FROMOddEVENNeg && (READMAIL1 ==1'b1)) ( OddEVENNeg => B35 ) = tpd_OddEVENNeg_B35; if (FROMENA && (READMAIL2 ==1'b1)) ( ENA => A8 ) = tpd_ENA_A8; if (FROMENA && (READMAIL2 ==1'b1)) ( ENA => A17 ) = tpd_ENA_A17; if (FROMENA && (READMAIL2 ==1'b1)) ( ENA => A26 ) = tpd_ENA_A26; if (FROMENA && (READMAIL2 ==1'b1)) ( ENA => A35 ) = tpd_ENA_A35; if (FROMENB && (READMAIL1 ==1'b1)) ( ENB => B8 ) = tpd_ENB_B8; if (FROMENB && (READMAIL1 ==1'b1)) ( ENB => B17 ) = tpd_ENB_B17; if (FROMENB && (READMAIL1 ==1'b1)) ( ENB => B26 ) = tpd_ENB_B26; if (FROMENB && (READMAIL1 ==1'b1)) ( ENB => B35 ) = tpd_ENB_B35; if (FROMWRANeg && (READMAIL2 ==1'b1)) ( WRANeg => A8 ) = tpd_WRANeg_A8; if (FROMWRANeg && (READMAIL2 ==1'b1)) ( WRANeg => A17 ) = tpd_WRANeg_A17; if (FROMWRANeg && (READMAIL2 ==1'b1)) ( WRANeg => A26 ) = tpd_WRANeg_A26; if (FROMWRANeg && (READMAIL2 ==1'b1)) ( WRANeg => A35 ) = tpd_WRANeg_A35; if (FROMWRBNeg && (READMAIL1 ==1'b1)) ( WRBNeg => B8 ) = tpd_WRBNeg_B8; if (FROMWRBNeg && (READMAIL1 ==1'b1)) ( WRBNeg => B17 ) = tpd_WRBNeg_B17; if (FROMWRBNeg && (READMAIL1 ==1'b1)) ( WRBNeg => B26 ) = tpd_WRBNeg_B26; if (FROMWRBNeg && (READMAIL1 ==1'b1)) ( WRBNeg => B35 ) = tpd_WRBNeg_B35; if (FROMMBA && (READMAIL2 ==1'b1)) ( MBA => A8 ) = tpd_MBA_A8; if (FROMMBA && (READMAIL2 ==1'b1)) ( MBA => A17 ) = tpd_MBA_A17; if (FROMMBA && (READMAIL2 ==1'b1)) ( MBA => A26 ) = tpd_MBA_A26; if (FROMMBA && (READMAIL2 ==1'b1)) ( MBA => A35 ) = tpd_MBA_A35; if (FROMMBB && (READMAIL1 ==1'b1)) ( MBB => B8 ) = tpd_MBB_B8; if (FROMMBB && (READMAIL1 ==1'b1)) ( MBB => B17 ) = tpd_MBB_B17; if (FROMMBB && (READMAIL1 ==1'b1)) ( MBB => B26 ) = tpd_MBB_B26; if (FROMMBB && (READMAIL1 ==1'b1)) ( MBB => B35 ) = tpd_MBB_B35; if (FROMPGA && (READMAIL2 ==1'b1)) ( PGA => A8 ) = tpd_PGA_A8; if (FROMPGA && (READMAIL2 ==1'b1)) ( PGA => A17 ) = tpd_PGA_A17; if (FROMPGA && (READMAIL2 ==1'b1)) ( PGA => A26 ) = tpd_PGA_A26; if (FROMPGA && (READMAIL2 ==1'b1)) ( PGA => A35 ) = tpd_PGA_A35; if (FROMPGB && (READMAIL1 ==1'b1)) ( PGB => B8 ) = tpd_PGB_B8; if (FROMPGB && (READMAIL1 ==1'b1)) ( PGB => B17 ) = tpd_PGB_B17; if (FROMPGB && (READMAIL1 ==1'b1)) ( PGB => B26 ) = tpd_PGB_B26; if (FROMPGB && (READMAIL1 ==1'b1)) ( PGB => B35 ) = tpd_PGB_B35; ( A0 => PEFANeg ) = tpd_A0_PEFANeg; ( A1 => PEFANeg ) = tpd_A1_PEFANeg; ( A2 => PEFANeg ) = tpd_A2_PEFANeg; ( A3 => PEFANeg ) = tpd_A3_PEFANeg; ( A4 => PEFANeg ) = tpd_A4_PEFANeg; ( A5 => PEFANeg ) = tpd_A5_PEFANeg; ( A6 => PEFANeg ) = tpd_A6_PEFANeg; ( A7 => PEFANeg ) = tpd_A7_PEFANeg; ( A8 => PEFANeg ) = tpd_A8_PEFANeg; ( A9 => PEFANeg ) = tpd_A9_PEFANeg; ( A10 => PEFANeg ) = tpd_A10_PEFANeg; ( A11 => PEFANeg ) = tpd_A11_PEFANeg; ( A12 => PEFANeg ) = tpd_A12_PEFANeg; ( A13 => PEFANeg ) = tpd_A13_PEFANeg; ( A14 => PEFANeg ) = tpd_A14_PEFANeg; ( A15 => PEFANeg ) = tpd_A15_PEFANeg; ( A16 => PEFANeg ) = tpd_A16_PEFANeg; ( A17 => PEFANeg ) = tpd_A17_PEFANeg; ( A18 => PEFANeg ) = tpd_A18_PEFANeg; ( A19 => PEFANeg ) = tpd_A19_PEFANeg; ( A20 => PEFANeg ) = tpd_A20_PEFANeg; ( A21 => PEFANeg ) = tpd_A21_PEFANeg; ( A22 => PEFANeg ) = tpd_A22_PEFANeg; ( A23 => PEFANeg ) = tpd_A23_PEFANeg; ( A24 => PEFANeg ) = tpd_A24_PEFANeg; ( A25 => PEFANeg ) = tpd_A25_PEFANeg; ( A26 => PEFANeg ) = tpd_A26_PEFANeg; ( A27 => PEFANeg ) = tpd_A27_PEFANeg; ( A28 => PEFANeg ) = tpd_A28_PEFANeg; ( A29 => PEFANeg ) = tpd_A29_PEFANeg; ( A30 => PEFANeg ) = tpd_A30_PEFANeg; ( A31 => PEFANeg ) = tpd_A31_PEFANeg; ( A32 => PEFANeg ) = tpd_A32_PEFANeg; ( A33 => PEFANeg ) = tpd_A33_PEFANeg; ( A34 => PEFANeg ) = tpd_A34_PEFANeg; ( A35 => PEFANeg ) = tpd_A35_PEFANeg; ( B0 => PEFBNeg ) = tpd_B0_PEFBNeg; ( B1 => PEFBNeg ) = tpd_B1_PEFBNeg; ( B2 => PEFBNeg ) = tpd_B2_PEFBNeg; ( B3 => PEFBNeg ) = tpd_B3_PEFBNeg; ( B4 => PEFBNeg ) = tpd_B4_PEFBNeg; ( B5 => PEFBNeg ) = tpd_B5_PEFBNeg; ( B6 => PEFBNeg ) = tpd_B6_PEFBNeg; ( B7 => PEFBNeg ) = tpd_B7_PEFBNeg; ( B8 => PEFBNeg ) = tpd_B8_PEFBNeg; ( B9 => PEFBNeg ) = tpd_B9_PEFBNeg; ( B10 => PEFBNeg ) = tpd_B10_PEFBNeg; ( B11 => PEFBNeg ) = tpd_B11_PEFBNeg; ( B12 => PEFBNeg ) = tpd_B12_PEFBNeg; ( B13 => PEFBNeg ) = tpd_B13_PEFBNeg; ( B14 => PEFBNeg ) = tpd_B14_PEFBNeg; ( B15 => PEFBNeg ) = tpd_B15_PEFBNeg; ( B16 => PEFBNeg ) = tpd_B16_PEFBNeg; ( B17 => PEFBNeg ) = tpd_B17_PEFBNeg; ( B18 => PEFBNeg ) = tpd_B18_PEFBNeg; ( B19 => PEFBNeg ) = tpd_B19_PEFBNeg; ( B20 => PEFBNeg ) = tpd_B20_PEFBNeg; ( B21 => PEFBNeg ) = tpd_B21_PEFBNeg; ( B22 => PEFBNeg ) = tpd_B22_PEFBNeg; ( B23 => PEFBNeg ) = tpd_B23_PEFBNeg; ( B24 => PEFBNeg ) = tpd_B24_PEFBNeg; ( B25 => PEFBNeg ) = tpd_B25_PEFBNeg; ( B26 => PEFBNeg ) = tpd_B26_PEFBNeg; ( B27 => PEFBNeg ) = tpd_B27_PEFBNeg; ( B28 => PEFBNeg ) = tpd_B28_PEFBNeg; ( B29 => PEFBNeg ) = tpd_B29_PEFBNeg; ( B30 => PEFBNeg ) = tpd_B30_PEFBNeg; ( B31 => PEFBNeg ) = tpd_B31_PEFBNeg; ( B32 => PEFBNeg ) = tpd_B32_PEFBNeg; ( B33 => PEFBNeg ) = tpd_B33_PEFBNeg; ( B34 => PEFBNeg ) = tpd_B34_PEFBNeg; ( B35 => PEFBNeg ) = tpd_B35_PEFBNeg; if (CLKA ) ( CLKA => FFNeg ) = tpd_CLKA_FFNeg; if (CLKB ) ( CLKB => EFNeg ) = tpd_CLKB_EFNeg; if (CLKB ) ( CLKB => AENeg ) = tpd_CLKB_AENeg; if (CLKA ) ( CLKA => AFNeg ) = tpd_CLKA_AFNeg; if (CLKA ) ( CLKA => MBF1Neg ) = tpd_CLKA_MBF1Neg; if (CLKA ) ( CLKA => MBF2Neg ) = tpd_CLKA_MBF2Neg; if (CLKB ) ( CLKB => MBF1Neg ) = tpd_CLKB_MBF1Neg; if (CLKB ) ( CLKB => MBF2Neg ) = tpd_CLKB_MBF2Neg; if (OddEVENNeg)(OddEVENNeg => PEFANeg ) = tpd_OddEVENNeg_PEFANeg; if (~OddEVENNeg)(OddEVENNeg => PEFANeg ) = tpd_OddEVENNeg_PEFANeg; if (OddEVENNeg)(OddEVENNeg => PEFBNeg ) = tpd_OddEVENNeg_PEFBNeg; if (~OddEVENNeg)(OddEVENNeg => PEFBNeg ) = tpd_OddEVENNeg_PEFBNeg; if (CSANeg) (CSANeg => PEFBNeg ) = tpd_CSANeg_PEFANeg; if (~CSANeg)(CSANeg => PEFANeg ) = tpd_CSANeg_PEFANeg; if (CSBNeg) (CSBNeg => PEFBNeg ) = tpd_CSBNeg_PEFBNeg; if (~CSBNeg)(CSBNeg => PEFBNeg ) = tpd_CSBNeg_PEFBNeg; if (ENA) (ENA => PEFBNeg ) = tpd_ENA_PEFANeg; if (~ENA)(ENA => PEFANeg ) = tpd_ENA_PEFANeg; if (ENB) (ENB => PEFBNeg ) = tpd_ENB_PEFBNeg; if (~ENB)(ENB => PEFBNeg ) = tpd_ENB_PEFBNeg; if (WRANeg) (WRANeg => PEFBNeg ) = tpd_WRANeg_PEFANeg; if (~WRANeg)(WRANeg => PEFANeg ) = tpd_WRANeg_PEFANeg; if (WRBNeg) (WRBNeg => PEFBNeg ) = tpd_WRBNeg_PEFBNeg; if (~WRBNeg)(WRBNeg => PEFBNeg ) = tpd_WRBNeg_PEFBNeg; if (MBA) (MBA => PEFBNeg ) = tpd_MBA_PEFANeg; if (~MBA)(MBA => PEFANeg ) = tpd_MBA_PEFANeg; if (MBB) (MBB => PEFBNeg ) = tpd_MBB_PEFBNeg; if (~MBB)(MBB => PEFBNeg ) = tpd_MBB_PEFBNeg; if (PGA) (PGA => PEFBNeg ) = tpd_PGA_PEFANeg; if (~PGA)(PGA => PEFANeg ) = tpd_PGA_PEFANeg; if (PGB) (PGB => PEFBNeg ) = tpd_PGB_PEFBNeg; if (~PGB)(PGB => PEFBNeg ) = tpd_PGB_PEFBNeg; if (~RSTNeg)(RSTNeg => MBF1Neg ) = tpd_RSTNeg_MBF1Neg; if (~RSTNeg)(RSTNeg => MBF2Neg ) = tpd_RSTNeg_MBF2Neg; if (~RSTNeg)(RSTNeg => AENeg ) = tpd_RSTNeg_AENeg; if (~RSTNeg)(RSTNeg => AFNeg ) = tpd_RSTNeg_AFNeg; ////////////////////////////////////////////////////////////////////////////// // Timing Violation // ////////////////////////////////////////////////////////////////////////////// $setup (A0 , posedge CLKA , tsetup_A0_CLKA ,Viol); $setup (A1 , posedge CLKA , tsetup_A1_CLKA ,Viol); $setup (A2 , posedge CLKA , tsetup_A2_CLKA ,Viol); $setup (A3 , posedge CLKA , tsetup_A3_CLKA ,Viol); $setup (A4 , posedge CLKA , tsetup_A4_CLKA ,Viol); $setup (A5 , posedge CLKA , tsetup_A5_CLKA ,Viol); $setup (A6 , posedge CLKA , tsetup_A6_CLKA ,Viol); $setup (A7 , posedge CLKA , tsetup_A7_CLKA ,Viol); $setup (A8 , posedge CLKA , tsetup_A8_CLKA ,Viol); $setup (A9 , posedge CLKA , tsetup_A9_CLKA ,Viol); $setup (A10 , posedge CLKA , tsetup_A10_CLKA ,Viol); $setup (A11 , posedge CLKA , tsetup_A11_CLKA ,Viol); $setup (A12 , posedge CLKA , tsetup_A12_CLKA ,Viol); $setup (A13 , posedge CLKA , tsetup_A13_CLKA ,Viol); $setup (A14 , posedge CLKA , tsetup_A14_CLKA ,Viol); $setup (A15 , posedge CLKA , tsetup_A15_CLKA ,Viol); $setup (A16 , posedge CLKA , tsetup_A16_CLKA ,Viol); $setup (A17 , posedge CLKA , tsetup_A17_CLKA ,Viol); $setup (A18 , posedge CLKA , tsetup_A18_CLKA ,Viol); $setup (A19 , posedge CLKA , tsetup_A19_CLKA ,Viol); $setup (A20 , posedge CLKA , tsetup_A20_CLKA ,Viol); $setup (A21 , posedge CLKA , tsetup_A21_CLKA ,Viol); $setup (A22 , posedge CLKA , tsetup_A22_CLKA ,Viol); $setup (A23 , posedge CLKA , tsetup_A23_CLKA ,Viol); $setup (A24 , posedge CLKA , tsetup_A24_CLKA ,Viol); $setup (A25 , posedge CLKA , tsetup_A25_CLKA ,Viol); $setup (A26 , posedge CLKA , tsetup_A26_CLKA ,Viol); $setup (A27 , posedge CLKA , tsetup_A27_CLKA ,Viol); $setup (A28 , posedge CLKA , tsetup_A28_CLKA ,Viol); $setup (A29 , posedge CLKA , tsetup_A29_CLKA ,Viol); $setup (A30 , posedge CLKA , tsetup_A30_CLKA ,Viol); $setup (A31 , posedge CLKA , tsetup_A31_CLKA ,Viol); $setup (A32 , posedge CLKA , tsetup_A32_CLKA ,Viol); $setup (A33 , posedge CLKA , tsetup_A33_CLKA ,Viol); $setup (A34 , posedge CLKA , tsetup_A34_CLKA ,Viol); $setup (A35 , posedge CLKA , tsetup_A35_CLKA ,Viol); $setup (B0 , posedge CLKB , tsetup_B0_CLKB ,Viol); $setup (B1 , posedge CLKB , tsetup_B1_CLKB ,Viol); $setup (B2 , posedge CLKB , tsetup_B2_CLKB ,Viol); $setup (B3 , posedge CLKB , tsetup_B3_CLKB ,Viol); $setup (B4 , posedge CLKB , tsetup_B4_CLKB ,Viol); $setup (B5 , posedge CLKB , tsetup_B5_CLKB ,Viol); $setup (B6 , posedge CLKB , tsetup_B6_CLKB ,Viol); $setup (B7 , posedge CLKB , tsetup_B7_CLKB ,Viol); $setup (B8 , posedge CLKB , tsetup_B8_CLKB ,Viol); $setup (B9 , posedge CLKB , tsetup_B9_CLKB ,Viol); $setup (B10 , posedge CLKB , tsetup_B10_CLKB ,Viol); $setup (B11 , posedge CLKB , tsetup_B11_CLKB ,Viol); $setup (B12 , posedge CLKB , tsetup_B12_CLKB ,Viol); $setup (B13 , posedge CLKB , tsetup_B13_CLKB ,Viol); $setup (B14 , posedge CLKB , tsetup_B14_CLKB ,Viol); $setup (B15 , posedge CLKB , tsetup_B15_CLKB ,Viol); $setup (B16 , posedge CLKB , tsetup_B16_CLKB ,Viol); $setup (B17 , posedge CLKB , tsetup_B17_CLKB ,Viol); $setup (B18 , posedge CLKB , tsetup_B18_CLKB ,Viol); $setup (B19 , posedge CLKB , tsetup_B19_CLKB ,Viol); $setup (B20 , posedge CLKB , tsetup_B20_CLKB ,Viol); $setup (B21 , posedge CLKB , tsetup_B21_CLKB ,Viol); $setup (B22 , posedge CLKB , tsetup_B22_CLKB ,Viol); $setup (B23 , posedge CLKB , tsetup_B23_CLKB ,Viol); $setup (B24 , posedge CLKB , tsetup_B24_CLKB ,Viol); $setup (B25 , posedge CLKB , tsetup_B25_CLKB ,Viol); $setup (B26 , posedge CLKB , tsetup_B26_CLKB ,Viol); $setup (B27 , posedge CLKB , tsetup_B27_CLKB ,Viol); $setup (B28 , posedge CLKB , tsetup_B28_CLKB ,Viol); $setup (B29 , posedge CLKB , tsetup_B29_CLKB ,Viol); $setup (B30 , posedge CLKB , tsetup_B30_CLKB ,Viol); $setup (B31 , posedge CLKB , tsetup_B31_CLKB ,Viol); $setup (B32 , posedge CLKB , tsetup_B32_CLKB ,Viol); $setup (B33 , posedge CLKB , tsetup_B33_CLKB ,Viol); $setup (B34 , posedge CLKB , tsetup_B34_CLKB ,Viol); $setup (B35 , posedge CLKB , tsetup_B35_CLKB ,Viol); $setup (CSANeg, posedge CLKA, tsetup_CSANeg_CLKA ,Viol); $setup (CSBNeg, posedge CLKB, tsetup_CSBNeg_CLKB ,Viol); $setup (WRANeg, posedge CLKA, tsetup_WRANeg_CLKA ,Viol); $setup (WRBNeg, posedge CLKB, tsetup_WRBNeg_CLKB ,Viol); $setup (ENA , posedge CLKA, tsetup_ENA_CLKA ,Viol); $setup (ENB , posedge CLKB, tsetup_ENB_CLKB ,Viol); $setup (MBA , posedge CLKA, tsetup_MBA_CLKA ,Viol); $setup (MBB , posedge CLKB, tsetup_MBB_CLKB ,Viol); $setup (OddEVENNeg , posedge CLKB, tsetup_OddEVENNeg_CLKB ,Viol); $setup (PGB , posedge CLKB, tsetup_PGB_CLKB ,Viol); $setup (RSTNeg, posedge CLKA, tsetup_RSTNeg_CLKA ,Viol); $setup (RSTNeg, posedge CLKB, tsetup_RSTNeg_CLKB ,Viol); $setup (FS0 , negedge RSTNeg, tsetup_FS0_RSTNeg ,Viol); $setup (FS1 , negedge RSTNeg, tsetup_FS1_RSTNeg ,Viol); $hold ( posedge CLKA ,A0 , thold_A0_CLKA ,Viol); $hold ( posedge CLKA ,A1 , thold_A1_CLKA ,Viol); $hold ( posedge CLKA ,A2 , thold_A2_CLKA ,Viol); $hold ( posedge CLKA ,A3 , thold_A3_CLKA ,Viol); $hold ( posedge CLKA ,A4 , thold_A4_CLKA ,Viol); $hold ( posedge CLKA ,A5 , thold_A5_CLKA ,Viol); $hold ( posedge CLKA ,A6 , thold_A6_CLKA ,Viol); $hold ( posedge CLKA ,A7 , thold_A7_CLKA ,Viol); $hold ( posedge CLKA ,A8 , thold_A8_CLKA ,Viol); $hold ( posedge CLKA ,A9 , thold_A9_CLKA ,Viol); $hold ( posedge CLKA ,A10 , thold_A10_CLKA ,Viol); $hold ( posedge CLKA ,A11 , thold_A11_CLKA ,Viol); $hold ( posedge CLKA ,A12 , thold_A12_CLKA ,Viol); $hold ( posedge CLKA ,A13 , thold_A13_CLKA ,Viol); $hold ( posedge CLKA ,A14 , thold_A14_CLKA ,Viol); $hold ( posedge CLKA ,A15 , thold_A15_CLKA ,Viol); $hold ( posedge CLKA ,A16 , thold_A16_CLKA ,Viol); $hold ( posedge CLKA ,A17 , thold_A17_CLKA ,Viol); $hold ( posedge CLKA ,A18 , thold_A18_CLKA ,Viol); $hold ( posedge CLKA ,A19 , thold_A19_CLKA ,Viol); $hold ( posedge CLKA ,A20 , thold_A20_CLKA ,Viol); $hold ( posedge CLKA ,A21 , thold_A21_CLKA ,Viol); $hold ( posedge CLKA ,A22 , thold_A22_CLKA ,Viol); $hold ( posedge CLKA ,A23 , thold_A23_CLKA ,Viol); $hold ( posedge CLKA ,A24 , thold_A24_CLKA ,Viol); $hold ( posedge CLKA ,A25 , thold_A25_CLKA ,Viol); $hold ( posedge CLKA ,A26 , thold_A26_CLKA ,Viol); $hold ( posedge CLKA ,A27 , thold_A27_CLKA ,Viol); $hold ( posedge CLKA ,A28 , thold_A28_CLKA ,Viol); $hold ( posedge CLKA ,A29 , thold_A29_CLKA ,Viol); $hold ( posedge CLKA ,A30 , thold_A30_CLKA ,Viol); $hold ( posedge CLKA ,A31 , thold_A31_CLKA ,Viol); $hold ( posedge CLKA ,A32 , thold_A32_CLKA ,Viol); $hold ( posedge CLKA ,A33 , thold_A33_CLKA ,Viol); $hold ( posedge CLKA ,A34 , thold_A34_CLKA ,Viol); $hold ( posedge CLKA ,A35 , thold_A35_CLKA ,Viol); $hold ( posedge CLKB ,B0 , thold_B0_CLKB ,Viol); $hold ( posedge CLKB ,B1 , thold_B1_CLKB ,Viol); $hold ( posedge CLKB ,B2 , thold_B2_CLKB ,Viol); $hold ( posedge CLKB ,B3 , thold_B3_CLKB ,Viol); $hold ( posedge CLKB ,B4 , thold_B4_CLKB ,Viol); $hold ( posedge CLKB ,B5 , thold_B5_CLKB ,Viol); $hold ( posedge CLKB ,B6 , thold_B6_CLKB ,Viol); $hold ( posedge CLKB ,B7 , thold_B7_CLKB ,Viol); $hold ( posedge CLKB ,B8 , thold_B8_CLKB ,Viol); $hold ( posedge CLKB ,B9 , thold_B9_CLKB ,Viol); $hold ( posedge CLKB ,B10 , thold_B10_CLKB ,Viol); $hold ( posedge CLKB ,B11 , thold_B11_CLKB ,Viol); $hold ( posedge CLKB ,B12 , thold_B12_CLKB ,Viol); $hold ( posedge CLKB ,B13 , thold_B13_CLKB ,Viol); $hold ( posedge CLKB ,B14 , thold_B14_CLKB ,Viol); $hold ( posedge CLKB ,B15 , thold_B15_CLKB ,Viol); $hold ( posedge CLKB ,B16 , thold_B16_CLKB ,Viol); $hold ( posedge CLKB ,B17 , thold_B17_CLKB ,Viol); $hold ( posedge CLKB ,B18 , thold_B18_CLKB ,Viol); $hold ( posedge CLKB ,B19 , thold_B19_CLKB ,Viol); $hold ( posedge CLKB ,B20 , thold_B20_CLKB ,Viol); $hold ( posedge CLKB ,B21 , thold_B21_CLKB ,Viol); $hold ( posedge CLKB ,B22 , thold_B22_CLKB ,Viol); $hold ( posedge CLKB ,B23 , thold_B23_CLKB ,Viol); $hold ( posedge CLKB ,B24 , thold_B24_CLKB ,Viol); $hold ( posedge CLKB ,B25 , thold_B25_CLKB ,Viol); $hold ( posedge CLKB ,B26 , thold_B26_CLKB ,Viol); $hold ( posedge CLKB ,B27 , thold_B27_CLKB ,Viol); $hold ( posedge CLKB ,B28 , thold_B28_CLKB ,Viol); $hold ( posedge CLKB ,B29 , thold_B29_CLKB ,Viol); $hold ( posedge CLKB ,B30 , thold_B30_CLKB ,Viol); $hold ( posedge CLKB ,B31 , thold_B31_CLKB ,Viol); $hold ( posedge CLKB ,B32 , thold_B32_CLKB ,Viol); $hold ( posedge CLKB ,B33 , thold_B33_CLKB ,Viol); $hold ( posedge CLKB ,B34 , thold_B34_CLKB ,Viol); $hold ( posedge CLKB ,B35 , thold_B35_CLKB ,Viol); $hold ( posedge CLKA ,CSANeg, thold_CSANeg_CLKA ,Viol); $hold ( posedge CLKB ,CSBNeg, thold_CSBNeg_CLKB ,Viol); $hold ( posedge CLKA ,ENA , thold_ENA_CLKA ,Viol); $hold ( posedge CLKB ,ENB , thold_ENB_CLKB ,Viol); $hold ( posedge CLKA ,WRANeg, thold_WRANeg_CLKA ,Viol); $hold ( posedge CLKB ,WRBNeg, thold_WRBNeg_CLKB ,Viol); $hold ( posedge CLKA ,MBA , thold_MBA_CLKA ,Viol); $hold ( posedge CLKB ,MBB , thold_MBB_CLKB ,Viol); $hold ( posedge CLKB ,OddEVENNeg,thold_OddEVENNeg_CLKB ,Viol); $hold ( negedge CLKB ,OddEVENNeg,thold_OddEVENNeg_CLKB ,Viol); $hold ( posedge CLKB ,PGB ,thold_OddEVENNeg_CLKB ,Viol); $hold ( negedge CLKB ,PGB ,thold_OddEVENNeg_CLKB ,Viol); $hold ( posedge CLKA ,RSTNeg, thold_RSTNeg_CLKA ,Viol); $hold ( posedge CLKB ,RSTNeg, thold_RSTNeg_CLKB ,Viol); $hold ( posedge RSTNeg,FS0, thold_FS0_RSTNeg ,Viol); $hold ( negedge RSTNeg,FS0, thold_FS0_RSTNeg ,Viol); $hold ( posedge RSTNeg,FS1, thold_FS1_RSTNeg ,Viol); $hold ( negedge RSTNeg,FS1, thold_FS1_RSTNeg ,Viol); $width ( negedge CLKA, tpw_CLKA_negedge ); $width ( posedge CLKA, tpw_CLKA_negedge ); $width ( negedge CLKB, tpw_CLKB_negedge ); $width ( posedge CLKB, tpw_CLKB_negedge ); $period( posedge CLKA , tperiod_CLKA); $period( negedge CLKA , tperiod_CLKA); $period( posedge CLKB , tperiod_CLKB); $period( negedge CLKB , tperiod_CLKB); endspecify ////////////////////////////////////////////////////////////////////////////// // Main Behavior Block // ////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////// // reset ////////////////////////////////////////////////////////// always @(negedge RSTNeg) begin RST_FLEG = 1'b1; reseted =1'b0; MBF1Neg_zd = 1'b1; IN_MBF1Neg = 1'b1; MBF2Neg_zd = 1'b1; IN_MBF2Neg = 1'b1; end always @(posedge RSTNeg) begin RDPoint = 0; WRPoint = 0; Count = 0; COUNT =0; RST_FLEG =1'b0; if (reseted == 1'b1) begin FF_FLEG =1'b1; COUNTA =0; end if (FS1 == 1'b1 && FS0 == 1'b1) OffsetRegister = 16; else if (FS1== 1'b1 && FS0 == 1'b0) OffsetRegister = 12; else if (FS1 == 1'b0 && FS0 == 1'b1) OffsetRegister = 8; else if (FS1 == 1'b0 && FS0 == 1'b0) OffsetRegister = 4; end ////////////////////////////////////////////////////////// //AOut (BOut) is in the high_impedance when //CSANeg(CSBNeg) or W/RA (W/RB) is high ////////////////////////////////////////////////////////// always @(posedge CSANeg or posedge WRANeg) begin READMAIL1 =1'b0; READMAIL2 =1'b0; AOut_zd [35:0] = 36'bz; end always @(posedge CSBNeg or posedge WRBNeg) begin READMAIL1 =1'b0; READMAIL2 =1'b0; BOut_zd [35:0] = 36'bz; end always @( CLKA) begin CLKA_late = #1 CLKA; end always @( CLKB) begin CLKB_late = #1 CLKB; end always @(posedge CLKA_late) begin if ( RST_FLEG ==1'b1) begin if (COUNTA< 5) COUNTA =COUNTA+1; if (COUNTA ==4 && COUNTB ==4) reseted = 1'b1; if (COUNTA == 2) begin FFNeg_zd = 1'b0; IN_EFNeg = 1'b0; AFNeg_zd = 1'b1; IN_AFNeg = 1'b1; end end ////////////////////////////////////////////////////////// //FFNeg is HIGH after 2 CLKA after RESET ////////////////////////////////////////////////////////// if ( FF_FLEG ==1'b1) begin COUNTA =COUNTA+1; if ( COUNTA ==2) begin FFNeg_zd = 1'b1; IN_FFNeg = 1'b1; COUNTA = 0; COUNTB = 0; FF_FLEG = 1'b0; reseted = 1'b0; end end ////////////////////////////////////////////////////////// // MBF2Neg is High on CLKA edge ////////////////////////////////////////////////////////// if ( CSANeg==1'b0 && WRANeg ==1'b0 && ENA ==1'b1 && MBA ==1'b1) begin FL_MBF2 =0; IN_MBF2Neg = 1'b1; MBF2Neg_zd = 1'b1; end ////////////////////////////////////////////////////////// // FIFO write ////////////////////////////////////////////////////////// if ( CSANeg ==1'b0 && WRANeg ==1'b1 && ENA ==1'b1 && MBA ==1'b0 && IN_FFNeg == 1'b1) begin READMAIL1 = 1'b0; if (Viol==1'b0) begin MemDataH[WRPoint] = AIn[35:18]; MemDataL[WRPoint] = AIn[17:0]; end else begin MemDataH[WRPoint] = -1; MemDataL[WRPoint] = -1; Viol=1'b0; end Count = Count + 1; if ((Count == FIFOMemorySize ) && ( flagCLKAskew1 == 1'b0)) begin IN_FFNeg =1'b0; FFNeg_zd = 1'b0; end if (( WRPoint == FIFOMemorySize -1) && (Count <= FIFOMemorySize )) WRPoint = 0; else WRPoint = WRPoint +1; if ( ( Count == 64 - OffsetRegister) && (flagCLKAskew2 ==1'b0)) begin IN_AFNeg = 1'b0; AFNeg_zd = 1'b0; end if ( ( Count == OffsetRegister+1 ) && IN_AENeg == 1'b0) INTER_AE = 0; if (IN_EFNeg == 1'b0) INTER_EF = 0; end ////////////////////////////////////////////////////////// // END fifo write ////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////// // set FF on 1 fleg 2 clkA ////////////////////////////////////////////////////////// if (INTER_FF < 3) INTER_FF = INTER_FF+1; if ((INTER_FF == 2) && flagCLKAskew1 ==1'b0) begin INTER_FF =3; FFNeg_zd =1'b1; IN_FFNeg = 1'b1; end ////////////////////////////////////////////////////////// // Set AF on 0fleg 2 clkA ////////////////////////////////////////////////////////// if ( INTER_AF < 3) INTER_AF = INTER_AF+1; if (( INTER_AF == 2 ) && flagCLKAskew2 ==1'b0) begin INTER_AF =3; AFNeg_zd = 1'b1; IN_AFNeg = 1'b1; end ////////////////////////////////////////////////////////// // WRITE to MAIL1 Register ////////////////////////////////////////////////////////// if ( CSANeg==1'b0 && WRANeg ==1'b1 && ENA ==1'b1 && MBA ==1'b1 && IN_MBF1Neg ==1'b1) begin MAIL1[35:0] = AIn[35:0]; READMAIL1 =1'b1; IN_MBF1Neg = 1'b0; MBF1Neg_zd =1'b0; end ////////////////////////////////////////////////////////// // READ from MAIL1 Register ////////////////////////////////////////////////////////// if ( CSBNeg== 1'b0 && WRBNeg == 1'b0 && ENB == 1'b1 && MBB == 1'b1) begin READMAIL1= 1'b1; FL_MBF1 = 1'b1; if (PGB == 1'b1) begin PEFBNeg_zd = 1'b1; end else BOut_zd[35:0]=MAIL1[35:0]; end end always @(AIn[35:0]) begin AIn_late[35:0] = #1 AIn[35:0]; end always @(BIn[35:0]) begin BIn_late[35:0] = #1 BIn[35:0]; end always @(AIn_late[35:0] or OddEVENNeg or WRANeg or PGA) begin if ( (WRANeg ==1'b1) && (AIn_late[1] !== 1'bz) && (AIn_late[1] !== 1'bx)) PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,0,0,AIn[35:0]); else if ( (WRANeg ==1'b0) && (AIn_late[1] !== 1'bz) && (AIn_late[1] !== 1'bx)) begin if (PGA ==1'b1) PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,0,1,AIn[35:0]); else PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,0,0,AIn[35:0]); end if ( ( CSANeg == 1'b0) && ( WRANeg == 1'b0) && ( ENA ==1'b1) && (MBA ==1'b1) && (PGA ==1'b1)) begin PEFANeg_zd =1'b1; PARITY_GENERATION( 0,OddEVENNeg,MAIL2[35:0], AOut_zd[35:0], BOut_zd[35:0]); READMAIL2=1'b1; end end always @(BIn_late[35:0] or OddEVENNeg or WRBNeg or PGB) begin POM_Z[35:0]=36'bz; if ( ( WRBNeg ==1'b1) && (BIn_late[1] !== 1'bz) && (BIn_late[1] !== 1'bx)) PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,1,0,BIn[35:0]); else if ( ( WRBNeg ==1'b0) && (BIn_late[1] !== 1'bz) && (BIn_late[1] !== 1'bx)) begin if (PGB ==1'b1) PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,1,1,BIn[35:0]); else PARITY_CHECKING(PEFANeg_zd,PEFBNeg_zd,1,0,BIn[35:0]); end if ( CSBNeg==1'b0 && WRBNeg ==1'b0 && ENB ==1'b1 && MBB ==1'b1 && PGB ==1'b1) begin PEFBNeg_zd =1'b1; PARITY_GENERATION( 1,OddEVENNeg,MAIL1[35:0], AOut_zd[35:0], BOut_zd[35:0]); READMAIL1=1'b1; end end always @(posedge CLKB_late) begin if ( RST_FLEG ==1'b1) begin if ( COUNTB< 5 ) COUNTB=COUNTB+1; if ( COUNTA == 4 && COUNTB == 4) reseted =1'b1; if ( COUNTB == 2) begin EFNeg_zd =1'b0; IN_EFNeg =1'b0; AENeg_zd =1'b0; IN_AENeg =1'b0; end end ////////////////////////////////////////////////////////// // Set EF on 0fleg 3 clkB ////////////////////////////////////////////////////////// if ( INTER_EF < 2) INTER_EF = INTER_EF+1; if ( INTER_EF == 2 && flagCLKAskew1 ==1'b0) begin INTER_EF =3; EFNeg_zd =1'b1; IN_EFNeg =1'b1; end ////////////////////////////////////////////////////////// // Set AE on 0fleg 2 clkA ////////////////////////////////////////////////////////// if ( INTER_AE < 3) INTER_AE =INTER_AE+1; if ( INTER_AE == 2 && flagCLKAskew2 ==1'b0) begin INTER_AE =3; AENeg_zd =1'b1; IN_AENeg =1'b1; end ////////////////////////////////////////////////////////// // MBF1Neg is High on CLKB edge ////////////////////////////////////////////////////////// if ( CSBNeg== 1'b0 && WRBNeg == 1'b0 && ENB == 1'b1 && MBB == 1'b1) begin FL_MBF1 = 0; IN_MBF1Neg =1'b1; MBF1Neg_zd =1'b1; end ////////////////////////////////////////////////////////// // FIFO read ////////////////////////////////////////////////////////// if ( CSBNeg ==1'b0 && WRBNeg ==1'b0 && ENB ==1'b1 && MBB ==1'b0 && IN_EFNeg ==1'b1 ) begin READMAIL2 = 1'b0; if ( (MemDataH[RDPoint] >= 0) && (MemDataL[RDPoint] >= 0)) begin if ( PGB ==1'b0) begin BOut_zd[35:18] = MemDataH[RDPoint] ; BOut_zd[17:0] = MemDataL[RDPoint] ; Outtput_Reg_B[35:18] = MemDataH[RDPoint] ; Outtput_Reg_B[17:0] = MemDataL[RDPoint] ; end else begin Parity_Data[ 35:18] = MemDataH[RDPoint] ; Parity_Data[17:0] = MemDataL[RDPoint]; PARITY_GENERATION( 1,OddEVENNeg,Parity_Data[ 35:0], AOut_zd[35:0], BOut_zd[35:0]); end end else begin BOut_zd[35:0] = 36'bx; end Count = Count - 1; if ( RDPoint < FIFOMemorySize - 1) RDPoint = RDPoint+1; else RDPoint = 0; if ( Count == 0 && flagCLKAskew1 == 1'b0) begin IN_EFNeg = 1'b0; EFNeg_zd = 1'b0; end if ( IN_FFNeg == 1'b0) INTER_FF = 0; if ( Count == OffsetRegister && flagCLKAskew1 == 1'b0) begin IN_AENeg = 1'b0; AENeg_zd = 1'b0; end if ( Count == 64 - OffsetRegister-1 && IN_AFNeg == 1'b0) INTER_AF = 0; end ////////////////////////////////////////////////////////// // write to MAIL2 Register ////////////////////////////////////////////////////////// if ( CSBNeg== 1'b0 && WRBNeg == 1'b1 && ENB == 1'b1 && MBB == 1'b1 && IN_MBF2Neg == 1'b1) begin READMAIL2 = 1'b1; MAIL2[35:0] = BIn[35:0]; IN_MBF2Neg = 1'b0; MBF2Neg_zd = 1'b0; end ////////////////////////////////////////////////////////// // READ from MAIL2 Register ////////////////////////////////////////////////////////// if ( CSANeg==1'b0 && WRANeg ==1'b0 && ENA ==1'b1 && MBA ==1'b1) begin READMAIL2=1'b1; FL_MBF2 = 1; if (PGA ==1'b0) begin AOut_zd[35:0]=MAIL2[35:0]; end end end ////////////////////////////////////////////////////////// // SETUP CLKL_flag ////////////////////////////////////////////////////////// always @(posedge CLKA_late) begin flagCLKAskew2 = 1'b1; flagCLKAskew2 <= #tdevice_SKEW2 1'b0; flagCLKAskew1 = 1'b1; flagCLKAskew1 <= #tdevice_SKEW1 1'b0; end ////////////////////////////////////////////////////////// // PROCESS: SETUP CLKR_flag ////////////////////////////////////////////////////////// always @(posedge CLKB) begin flagCLKBskew2 = 1'b1; flagCLKBskew2 <= #tdevice_SKEW2 1'b0; flagCLKBskew1 = 1'b1; flagCLKBskew1 <= #tdevice_SKEW1 1'b0; end always @(negedge CSBNeg) begin if ( ( CSBNeg == 1'b0 ) && ( WRBNeg ==1'b0) && ( MBB ==1'b0)) BOut_zd[35:0]=Outtput_Reg_B[35:0]; end always @(negedge WRBNeg) begin if ( ( CSBNeg == 1'b0 ) && ( WRBNeg ==1'b0) && ( MBB ==1'b0)) BOut_zd[35:0]=Outtput_Reg_B[35:0]; end always @(negedge CSANeg) begin if ( ( CSANeg == 1'b0 ) && ( WRANeg ==1'b0) ) AOut_zd[35:0]=Outtput_Reg_A[35:0]; end always @(negedge WRANeg) begin if ( ( CSANeg == 1'b0 ) && ( WRANeg ==1'b0) && ( MBA ==1'b0)) AOut_zd[35:0]=Outtput_Reg_A[35:0]; end ////////////////////////////////////////////////////////// // Output Data Gen ////////////////////////////////////////////////////////// always @(AOut_zd) begin : OutputGenA if (AOut_zd[0] !== 1'bz) begin FROMCSA = 1'b0; FROMCLKA = 1'b0; FROMWRANeg= 1'b0; FROMMBA = 1'b0; if (( tCLKAposedge > tCSANegnegedge ) && ( tCLKAposedge > tWRANegnegedge )) FROMCLKA = 1'b1; else if (((tCSANegnegedge + tpd_CSANeg_A0) > (tMBAnegedge + tpd_MBA_A0)) && ((tCSANegnegedge + tpd_CSANeg_A0) > (tWRANegnegedge + tpd_WRANeg_A0))) FROMCSA = 1'b1; else FROMWRANeg = 1'b1; AOut_Pass[35:0] = AOut_zd[35:0]; end else begin FROMCSA = 1'b0; FROMCLKA = 1'b0; FROMWRANeg= 1'b0; FROMMBA = 1'b0; if ((tCSANegnegedge + tpd_CSANeg_A0) > (tWRANegnegedge + tpd_WRANeg_A0)) FROMCSA = 1'b1; else FROMWRANeg = 1'b1; AOut_Pass[35:0] = 36'bz; end end always @(BOut_zd) begin : OutputGenB if (BOut_zd[0] !== 1'bz) begin FROMCSB = 1'b0; FROMCLKB = 1'b0; FROMWRBNeg= 1'b0; FROMMBB = 1'b0; if (( tCLKBposedge >tCSBNegnegedge ) && ( tCLKBposedge >tpd_WRBNeg_B0 )) FROMCLKB = 1'b1; else if (((tCSBNegnegedge + tpd_CSBNeg_B0) > (tMBBnegedge + tpd_MBB_B0)) && ((tCSBNegnegedge + tpd_CSBNeg_B0) > (tWRBNegnegedge + tpd_WRBNeg_B0))) FROMCSB = 1'b1; else FROMWRBNeg = 1'b1; BOut_Pass[35:0] = BOut_zd[35:0]; end else begin FROMCSB = 1'b0; FROMCLKB = 1'b0; FROMWRBNeg= 1'b0; FROMMBB = 1'b0; if ((tCSBNegnegedge + tpd_CSBNeg_B0) >(tWRBNegnegedge + tpd_WRBNeg_B0)) FROMCSB = 1'b1; else FROMWRBNeg = 1'b1; BOut_Pass[35:0] = 36'bz; end end //////////////////////////////////////////////////////////////////////////// //// obtain 'LAST_EVENT information //////////////////////////////////////////////////////////////////////////// always @(negedge WRBNeg) begin tWRBNegnegedge = $time; end always @(negedge MBB) begin tMBBnegedge = $time; end always @(posedge CLKB) begin tCLKBposedge = $time; end always @(negedge CSBNeg) begin tCSBNegnegedge = $time; end always @(negedge WRANeg) begin tWRANegnegedge = $time; end always @(negedge MBA) begin tMBAnegedge = $time; end always @(posedge CLKA) begin tCLKAposedge = $time; end always @(negedge CSANeg) begin tCSANegnegedge = $time; end //////////////////////////////////////////////////////////////////////////// //// PROCEDURE FOR PARITY CHECKING //////////////////////////////////////////////////////////////////////////// task PARITY_CHECKING ; output PEFANeg_zd,PEFBNeg_zd; input Port_Side; input FLEG; input [35:0] DataIn; integer INTER ; reg ParityLow ; reg [8:0] Check; integer i; integer j; integer FLEG; reg [35:0] POM; begin if (FLEG == 0) begin INTER =0; ParityLow = 1'b0; Check [8:0] = 9'b0; POM = DataIn [35:0]; for (i=1;i<=4;i=i+1) begin if (INTER == 0) begin if ( i == 1 ) Check [8:0] = POM [8:0]; if ( i == 2 ) Check [8:0] = POM [17:9]; if ( i == 3 ) Check [8:0] = POM [26:18]; if ( i == 4 ) Check [8:0] = POM [35:27]; ParityLow = 1'b0; for (j=0;j<=8;j=j+1) begin if ( Check [j] == 1'b1 ) begin if (ParityLow == 1'b0 ) ParityLow = 1'b1; else ParityLow = 1'b0; end end if (((ParityLow == 1'b0 ) && (OddEVENNeg ==1'b0)) || ((ParityLow == 1'b1) && (OddEVENNeg == 1'b1))) begin if ( Port_Side==0 ) PEFANeg_zd = 1'b1; else PEFBNeg_zd = 1'b1; end else begin if ( Port_Side==0 ) begin PEFANeg_zd = 1'b0; INTER = 1; end else begin PEFBNeg_zd = 1'b0; INTER = 1; end end end end end else begin if ( Port_Side==0 ) PEFANeg_zd = 1'b1; else PEFBNeg_zd = 1'b1; end end endtask //////////////////////////////////////////////////////////////////////////// //// PROCEDURE FOR PARITY GENERATING //////////////////////////////////////////////////////////////////////////// task PARITY_GENERATION; input Port_side; input ODD_OR_EVEN; input [35:0] DataIn; output[35:0] AOut_zd, BOut_zd; integer Poz ; reg ParityLow ; reg [8:0] Check; reg [35:0] DataOut; reg [35:0] Pom; integer i; integer j; begin ParityLow =1'b0; DataOut [35:0] = DataIn [35:0]; Pom = DataIn [35:0]; for (i = 0;i<=3;i=i+1) begin if (i==0 ) Check [8:0] = Pom [8:0]; if (i==1 ) Check [8:0] = Pom [17:9]; if (i==2 ) Check [8:0] = Pom [26:18]; if (i==3 ) Check [8:0] = Pom [35:27]; ParityLow = 1'b0; for (j=0;j<=7;j=j+1) begin if ( Check [j] == 1'b1 ) if (ParityLow == 1'b0 ) ParityLow = 1'b1; else ParityLow = 1'b0; end if (((ParityLow == 1'b0) && (OddEVENNeg == 1'b1)) || ((ParityLow == 1'b1) && (OddEVENNeg == 1'b0 ))) begin Poz = 8 + i*9; DataOut [Poz] = 1'b1; end else begin Poz = 8 + i*9; DataOut [Poz] = 1'b0; end end if (Port_side == 0) begin AOut_zd[35:0] = DataOut [ 35:0]; Outtput_Reg_A[35:0] = DataOut [ 35:0]; BOut_zd[35:0] = 36'bz; end else begin BOut_zd[35:0] = DataOut [ 35:0]; Outtput_Reg_B[35:0] = DataOut [ 35:0]; AOut_zd[35:0] = 36'bz; end end endtask endmodule