-------------------------------------------------------------------------------- -- File Name: stds3383.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 AUG 13 Initial release -- V1.1 R. Munden 02 JUN 24 change CE, CX to std_ulogic -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: STNDS -- Technology: N/A -- Part: STDS3383 -- -- Desciption: FET Bus-Exchange Switch -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.switch_pkg.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY stds3383 IS GENERIC ( -- tipd delays: interconnect path delays tipd_BENeg : VitalDelayType01 := VitalZeroDelay01; tipd_BX : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_C : VitalDelayType01 := VitalZeroDelay01; tipd_B : VitalDelayType01 := VitalZeroDelay01; tipd_A : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A_B : VitalDelayType01 := UnitDelay01; tpd_BENeg_A : VitalDelayType01 := UnitDelay01; tpd_BX_A : VitalDelayType01 := UnitDelay01; -- generic control parameters MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; InstancePath : STRING := DefaultInstancePath; -- For FMF SDF techonology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( BENeg : IN std_logic := 'U'; BX : IN std_logic := 'U'; A : INOUT std_logic := 'Z'; B : INOUT std_logic := 'Z'; C : INOUT std_logic := 'Z'; D : INOUT std_logic := 'Z' ); ATTRIBUTE VITAL_LEVEL0 of stds3383 : ENTITY IS TRUE; END stds3383; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF stds3383 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL BENeg_ipd : std_ulogic := 'X'; SIGNAL BX_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL C_ipd : std_ulogic := 'X'; SIGNAL B_ipd : std_ulogic := 'X'; SIGNAL A_ipd : std_ulogic := 'X'; signal CE : std_ulogic := 'X'; signal CX : std_ulogic := 'X'; signal SUBSTRATE1 : std_logic := 'Z'; signal SUBSTRATE2 : std_logic := 'Z'; signal SUBSTRATE3 : std_logic := 'Z'; signal SUBSTRATE4 : std_logic := 'Z'; signal SUB_DRIVE_1D : std_logic := 'Z'; signal SUB_DRIVE_1S : std_logic := 'Z'; signal SUB_DRIVE_2D : std_logic := 'Z'; signal SUB_DRIVE_2S : std_logic := 'Z'; signal SUB_DRIVE_3D : std_logic := 'Z'; signal SUB_DRIVE_3S : std_logic := 'Z'; signal SUB_DRIVE_4D : std_logic := 'Z'; signal SUB_DRIVE_4S : std_logic := 'Z'; signal AUX_EN : X01 := '1'; signal SUSPEND : boolean; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (D_ipd, D, tipd_D); w_2 : VitalWireDelay (C_ipd, C, tipd_C); w_3 : VitalWireDelay (B_ipd, B, tipd_B); w_4 : VitalWireDelay (A_ipd, A, tipd_A); w_5 : VitalWireDelay (BENeg_ipd, BENeg, tipd_BENeg); w_6 : VitalWireDelay (BX_ipd, BX, tipd_BX); END BLOCK; SW1: BILATERAL port map ( GATE => CE, DRAIN => A, SOURCE => C, SUBSTRATE => SUBSTRATE1, SUB_DRIVE_D => SUB_DRIVE_1D, SUB_DRIVE_S => SUB_DRIVE_1S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW2: BILATERAL port map ( GATE => CE, DRAIN => B, SOURCE => D, SUBSTRATE => SUBSTRATE2, SUB_DRIVE_D => SUB_DRIVE_2D, SUB_DRIVE_S => SUB_DRIVE_2S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW3: BILATERAL port map ( GATE => CX, DRAIN => A, SOURCE => D, SUBSTRATE => SUBSTRATE3, SUB_DRIVE_D => SUB_DRIVE_3D, SUB_DRIVE_S => SUB_DRIVE_3S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW4: BILATERAL port map ( GATE => CX, DRAIN => B, SOURCE => C, SUBSTRATE => SUBSTRATE4, SUB_DRIVE_D => SUB_DRIVE_4D, SUB_DRIVE_S => SUB_DRIVE_4S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); ---------------------------------------------------------------------------- -- Control Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (BENeg_ipd, BX_ipd) -- Functionality Results Variables VARIABLE E_zd : std_ulogic; VARIABLE X_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE E_GlitchData : VitalGlitchDataType; VARIABLE X_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ X_zd := VitalAND2(a => BX_ipd, b => not(BENeg_ipd)); E_zd := VitalAND2(a => not(BX_ipd), b => not(BENeg_ipd)); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => CE, OutSignalName => "CE", OutTemp => E_zd, GlitchData => E_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BENeg_ipd'LAST_EVENT, PathDelay => tpd_BENeg_A, PathCondition => TRUE), 1 => (InputChangeTime => BX_ipd'LAST_EVENT, PathDelay => tpd_BX_A, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => CX, OutSignalName => "CX", OutTemp => X_zd, GlitchData => X_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => BENeg_ipd'LAST_EVENT, PathDelay => tpd_BENeg_A, PathCondition => TRUE), 1 => (InputChangeTime => BX_ipd'LAST_EVENT, PathDelay => tpd_BX_A, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;