-------------------------------------------------------------------------------- -- File Name: stds3251.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 AUG 16 Initial release -- V1.1 R. Munden 00 NOV 04 Change GATE type to X01 -- V1.2 R. Munden 02 OCT 27 Change GATE type to std_logic_vector -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: STNDS -- Technology: FET Switch -- Part: STDS3251 -- -- Description: 8 to 1 Mux/Demux FET Switch -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.switch_pkg.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY stds3251 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; tipd_B5 : VitalDelayType01 := VitalZeroDelay01; tipd_B6 : VitalDelayType01 := VitalZeroDelay01; tipd_B7 : VitalDelayType01 := VitalZeroDelay01; tipd_B8 : VitalDelayType01 := VitalZeroDelay01; tipd_S0 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; tipd_S2 : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A_B1 : VitalDelayType01 := UnitDelay01; tpd_OENeg_A : VitalDelayType01 := UnitDelay01; tpd_S0_B1 : VitalDelayType01 := UnitDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A : INOUT std_logic := 'Z'; B1 : INOUT std_logic := 'Z'; B2 : INOUT std_logic := 'Z'; B3 : INOUT std_logic := 'Z'; B4 : INOUT std_logic := 'Z'; B5 : INOUT std_logic := 'Z'; B6 : INOUT std_logic := 'Z'; B7 : INOUT std_logic := 'Z'; B8 : INOUT std_logic := 'Z'; S0 : IN std_logic := 'U'; S1 : IN std_logic := 'U'; S2 : IN std_logic := 'U'; OENeg : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of stds3251 : ENTITY IS TRUE; END stds3251; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of stds3251 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL A_ipd : std_ulogic := 'Z'; SIGNAL B1_ipd : std_ulogic := 'Z'; SIGNAL B2_ipd : std_ulogic := 'Z'; SIGNAL B3_ipd : std_ulogic := 'Z'; SIGNAL B4_ipd : std_ulogic := 'Z'; SIGNAL B5_ipd : std_ulogic := 'Z'; SIGNAL B6_ipd : std_ulogic := 'Z'; SIGNAL B7_ipd : std_ulogic := 'Z'; SIGNAL B8_ipd : std_ulogic := 'Z'; SIGNAL S0_ipd : std_ulogic := 'X'; SIGNAL S1_ipd : std_ulogic := 'X'; SIGNAL S2_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; signal GATE : std_logic_vector(8 downto 1) := (others => 'X'); signal Gate_zd : std_logic_vector(8 downto 1); signal SUBSTRATE1 : std_logic := 'Z'; signal SUBSTRATE2 : std_logic := 'Z'; signal SUBSTRATE3 : std_logic := 'Z'; signal SUBSTRATE4 : std_logic := 'Z'; signal SUBSTRATE5 : std_logic := 'Z'; signal SUBSTRATE6 : std_logic := 'Z'; signal SUBSTRATE7 : std_logic := 'Z'; signal SUBSTRATE8 : std_logic := 'Z'; signal SUB_DRIVE1_D : std_logic := 'Z'; signal SUB_DRIVE2_D : std_logic := 'Z'; signal SUB_DRIVE3_D : std_logic := 'Z'; signal SUB_DRIVE4_D : std_logic := 'Z'; signal SUB_DRIVE5_D : std_logic := 'Z'; signal SUB_DRIVE6_D : std_logic := 'Z'; signal SUB_DRIVE7_D : std_logic := 'Z'; signal SUB_DRIVE8_D : std_logic := 'Z'; signal SUB_DRIVE1_S : std_logic := 'Z'; signal SUB_DRIVE2_S : std_logic := 'Z'; signal SUB_DRIVE3_S : std_logic := 'Z'; signal SUB_DRIVE4_S : std_logic := 'Z'; signal SUB_DRIVE5_S : std_logic := 'Z'; signal SUB_DRIVE6_S : std_logic := 'Z'; signal SUB_DRIVE7_S : std_logic := 'Z'; signal SUB_DRIVE8_S : std_logic := 'Z'; signal AUX_EN : X01 := '1'; signal SUSPEND : boolean; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A_ipd, A, tipd_A); w_2 : VitalWireDelay (B1_ipd, B1, tipd_B1); w_3 : VitalWireDelay (B2_ipd, B2, tipd_B2); w_4 : VitalWireDelay (B3_ipd, B3, tipd_B3); w_5 : VitalWireDelay (B4_ipd, B4, tipd_B4); w_6 : VitalWireDelay (B5_ipd, B5, tipd_B5); w_7 : VitalWireDelay (B6_ipd, B6, tipd_B6); w_8 : VitalWireDelay (B7_ipd, B7, tipd_B7); w_9 : VitalWireDelay (B8_ipd, B8, tipd_B8); w_10 : VitalWireDelay (S0_ipd, S0, tipd_S0); w_11 : VitalWireDelay (S1_ipd, S1, tipd_S1); w_12 : VitalWireDelay (S2_ipd, S2, tipd_S2); w_13 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); END BLOCK; sw1: bilateral PORT MAP ( GATE => GATE(1), DRAIN => A, SOURCE => B1, SUBSTRATE => SUBSTRATE1, SUB_DRIVE_D => SUB_DRIVE1_D, SUB_DRIVE_S => SUB_DRIVE1_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw2: bilateral PORT MAP ( GATE => GATE(2), DRAIN => A, SOURCE => B2, SUBSTRATE => SUBSTRATE2, SUB_DRIVE_D => SUB_DRIVE2_D, SUB_DRIVE_S => SUB_DRIVE2_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw3: bilateral PORT MAP ( GATE => GATE(3), DRAIN => A, SOURCE => B3, SUBSTRATE => SUBSTRATE3, SUB_DRIVE_D => SUB_DRIVE3_D, SUB_DRIVE_S => SUB_DRIVE3_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw4: bilateral PORT MAP ( GATE => GATE(4), DRAIN => A, SOURCE => B4, SUBSTRATE => SUBSTRATE4, SUB_DRIVE_D => SUB_DRIVE4_D, SUB_DRIVE_S => SUB_DRIVE4_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw5: bilateral PORT MAP ( GATE => GATE(5), DRAIN => A, SOURCE => B5, SUBSTRATE => SUBSTRATE5, SUB_DRIVE_D => SUB_DRIVE5_D, SUB_DRIVE_S => SUB_DRIVE5_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw6: bilateral PORT MAP ( GATE => GATE(6), DRAIN => A, SOURCE => B6, SUBSTRATE => SUBSTRATE6, SUB_DRIVE_D => SUB_DRIVE6_D, SUB_DRIVE_S => SUB_DRIVE6_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw7: bilateral PORT MAP ( GATE => GATE(7), DRAIN => A, SOURCE => B7, SUBSTRATE => SUBSTRATE7, SUB_DRIVE_D => SUB_DRIVE7_D, SUB_DRIVE_S => SUB_DRIVE7_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw8: bilateral PORT MAP ( GATE => GATE(8), DRAIN => A, SOURCE => B8, SUBSTRATE => SUBSTRATE8, SUB_DRIVE_D => SUB_DRIVE8_D, SUB_DRIVE_S => SUB_DRIVE8_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); ---------------------------------------------------------------------------- -- Select Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (OENeg_ipd, S0_ipd, S1_ipd, S2_ipd) -- Functionality Results Variables VARIABLE Gate_drive : std_logic_vector(8 downto 1); BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Gate_drive := VitalDECODER8(data => (S2_ipd & S1_ipd & S0_ipd), enable => not OENeg_ipd); Gate_zd <= Gate_drive; END PROCESS; ---------------------------------------------------------------------------- -- Path Delay Processes generated as a function of data width ---------------------------------------------------------------------------- DataOut_Width : FOR i IN 8 DOWNTO 1 GENERATE DataOut_Delay : PROCESS (Gate_zd(i)) VARIABLE Gate_GlitchData:VitalGlitchDataArrayType(8 Downto 1); BEGIN VitalPathDelay01 ( OutSignal => GATE(i), OutSignalName => "Gate", OutTemp => Gate_zd(i), Mode => OnEvent, GlitchData => Gate_GlitchData(i), Paths => ( 0 => (InputChangeTime => OENeg_ipd'LAST_EVENT, PathDelay => tpd_OENeg_A, PathCondition => TRUE), 1 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_B1, PathCondition => TRUE), 2 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_B1, PathCondition => TRUE), 3 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_B1, PathCondition => TRUE) ) ); END PROCESS; END GENERATE; END vhdl_behavioral;