--------------------------------------------------------------------------------
--  File name : stds16292.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000, 2002 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY :
--
--  version: | author: | mod date: | changes made
--     V1.0   R. Munden  00 JUL 24   Initial release based on work done by
--                                   James Holl
--     V1.1   R. Munden  02 JUN 24   change GATEx to std_ulogic
--  This is a zero delay model.  It will not use interconnect delays or path 
--  delays annotated to the A or B ports. Delays on control pins will work.
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     STNDS
--  Technology:  FET Bus Switch
--  Part:        STDS16292
--
--  Description:  2-TO-1 FET Mux/Demux w/ Pulldowns
--------------------------------------------------------------------------------

LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;
                 USE IEEE.VITAL_timing.ALL;
                 USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;     USE FMF.gen_utils.ALL;
                 USE FMF.switch_pkg.all;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY stds16292 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A              : VitalDelayType01 := VitalZeroDelay01;
        tipd_B1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_B2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_S              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_B1            : VitalDelayType01Z := UnitDelay01Z;
        tpd_S_A             : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        MsgOn               : BOOLEAN  := DefaultMsgOn;
        XOn                 : BOOLEAN  := DefaultXOn;
        InstancePath        : STRING   := DefaultInstancePath;
        -- For FMF SDF techonology file usage
        TimingModel         : STRING   := DefaultTimingModel
    );
    PORT (
        S           : IN    std_logic := 'X';
        A           : INOUT std_logic := 'Z';
        B1          : INOUT std_logic := 'Z';
        B2          : INOUT std_logic := 'Z'
    );
    ATTRIBUTE VITAL_LEVEL0 of stds16292 : ENTITY IS TRUE;
END stds16292;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of stds16292 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE;

    SIGNAL S_ipd        : std_ulogic := 'U';
    SIGNAL A_ipd        : std_ulogic := 'Z';
    SIGNAL B1_ipd       : std_ulogic := 'Z';
    SIGNAL B2_ipd       : std_ulogic := 'Z';

    SIGNAL LOW1         : std_logic := '0';
    SIGNAL LOW2         : std_logic := '0';

    SIGNAL GATE1        : std_ulogic := 'X';
    SIGNAL GATE2        : std_ulogic := 'X';

    SIGNAL SUBSTRATE1: std_logic := 'Z';
    SIGNAL SUBSTRATE2: std_logic := 'Z';

    SIGNAL SUB_DRIVE1_D: std_logic := 'Z';
    SIGNAL SUB_DRIVE1_S: std_logic := 'Z';
    SIGNAL SUB_DRIVE2_D: std_logic := 'Z';
    SIGNAL SUB_DRIVE2_S: std_logic := 'Z';

    SIGNAL AUX_EN: X01 := '1';
    SIGNAL SUSPEND: boolean;

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (S_ipd, S, tipd_S);
        w_3: VitalWireDelay (A_ipd, A, tipd_A);
        w_4: VitalWireDelay (B1_ipd, B1, tipd_B1);
        w_5: VitalWireDelay (B2_ipd, B2, tipd_B2);

    END BLOCK;

	sw1: bilateral PORT MAP	(
			GATE => GATE1,
			DRAIN => A,
			SOURCE => B1,
			SUBSTRATE => SUBSTRATE1,
			SUB_DRIVE_D => SUB_DRIVE1_D,
			SUB_DRIVE_S => SUB_DRIVE1_S,
			AUX_EN => AUX_EN,
			SUSPEND => SUSPEND);

	sw2: bilateral PORT MAP (
			GATE => GATE2,
			DRAIN => A,
			SOURCE => B2,
			SUBSTRATE => SUBSTRATE2,
			SUB_DRIVE_D => SUB_DRIVE2_D,
			SUB_DRIVE_S => SUB_DRIVE2_S,
			AUX_EN => AUX_EN,
			SUSPEND => SUSPEND);

	sw3: bilateral PORT MAP (
			GATE => GATE1,
			DRAIN => LOW1,
			SOURCE => B2,
			SUBSTRATE => SUBSTRATE2,
			SUB_DRIVE_D => SUB_DRIVE2_D,
			SUB_DRIVE_S => SUB_DRIVE2_S,
			AUX_EN => AUX_EN,
			SUSPEND => SUSPEND);

	sw4: bilateral PORT MAP (
			GATE => GATE2,
			DRAIN => LOW2,
			SOURCE => B1,
			SUBSTRATE => SUBSTRATE1,
			SUB_DRIVE_D => SUB_DRIVE1_D,
			SUB_DRIVE_S => SUB_DRIVE1_S,
			AUX_EN => AUX_EN,
			SUSPEND => SUSPEND);

        LOW1 <= 'L';
        LOW2 <= 'L';

    ----------------------------------------------------------------------------
    -- Control Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (S_ipd)

        -- Functionality Results Variables
        VARIABLE Q1_zd           : std_ulogic;
        VARIABLE Q2_zd           : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Q1_GlitchData   : VitalGlitchDataType;
        VARIABLE Q2_GlitchData   : VitalGlitchDataType;

    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Q1_zd := VitalINV(data => S_ipd);
        Q2_zd := VitalBUF(data => S_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => GATE1,
            OutSignalName   => "GATE1",
            OutTemp         => Q1_zd,
            GlitchData      => Q1_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => S_ipd'LAST_EVENT,
                      PathDelay         => tpd_S_A,
                      PathCondition     => TRUE)
            )
        );

        VitalPathDelay01 (
            OutSignal       => GATE2,
            OutSignalName   => "GATE2",
            OutTemp         => Q2_zd,
            GlitchData      => Q2_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => S_ipd'LAST_EVENT,
                      PathDelay         => tpd_S_A,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS;

END vhdl_behavioral;