-------------------------------------------------------------------------------- -- File name : stds16233.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made -- V1.0 R. Munden 99 AUG 12 Initial release based on work done by -- James Holl -- V1.1 R. Munden 02 JUN 22 change GATEx to std_ulogic -- This is a zero delay model. It will not use interconnect delays or path -- delays annotated to the A or B ports. -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: STNDS -- Technology: FET Bus Switch -- Part: STDS16233 -- -- Description: 2-TO-1 FET Mux/Demux -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.switch_pkg.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY stds16233 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_SEL : VitalDelayType01 := VitalZeroDelay01; tipd_TEST : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A_B1 : VitalDelayType01Z := UnitDelay01Z; tpd_SEL_A : VitalDelayType01 := UnitDelay01; -- generic control parameters MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; InstancePath : STRING := DefaultInstancePath; -- For FMF SDF techonology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( SEL : IN std_logic := 'X'; TEST : IN std_logic := 'X'; A : INOUT std_logic := 'Z'; B1 : INOUT std_logic := 'Z'; B2 : INOUT std_logic := 'Z' ); ATTRIBUTE VITAL_LEVEL0 of stds16233 : ENTITY IS TRUE; END stds16233; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of stds16233 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL SEL_ipd : std_ulogic := 'U'; SIGNAL TEST_ipd : std_ulogic := 'U'; SIGNAL A_ipd : std_ulogic := 'Z'; SIGNAL B1_ipd : std_ulogic := 'Z'; SIGNAL B2_ipd : std_ulogic := 'Z'; SIGNAL GATE1 : std_ulogic := 'X'; SIGNAL GATE2 : std_ulogic := 'X'; SIGNAL SUBSTRATE1: std_logic := 'Z'; SIGNAL SUBSTRATE2: std_logic := 'Z'; SIGNAL SUB_DRIVE1_D: std_logic := 'Z'; SIGNAL SUB_DRIVE1_S: std_logic := 'Z'; SIGNAL SUB_DRIVE2_D: std_logic := 'Z'; SIGNAL SUB_DRIVE2_S: std_logic := 'Z'; SIGNAL AUX_EN: X01 := '1'; SIGNAL SUSPEND: boolean; SIGNAL K1, K2, K3, K4, K5, K6, K7, K8, K9, K10: boolean; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (SEL_ipd, SEL, tipd_SEL); w_2: VitalWireDelay (TEST_ipd, TEST, tipd_TEST); w_3: VitalWireDelay (A_ipd, A, tipd_A); w_4: VitalWireDelay (B1_ipd, B1, tipd_B1); w_5: VitalWireDelay (B2_ipd, B2, tipd_B2); END BLOCK; sw1: bilateral PORT MAP ( GATE => GATE1, DRAIN => A, SOURCE => B1, SUBSTRATE => SUBSTRATE1, SUB_DRIVE_D => SUB_DRIVE1_D, SUB_DRIVE_S => SUB_DRIVE1_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw2: bilateral PORT MAP ( GATE => GATE2, DRAIN => A, SOURCE => B2, SUBSTRATE => SUBSTRATE2, SUB_DRIVE_D => SUB_DRIVE2_D, SUB_DRIVE_S => SUB_DRIVE2_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sub_drive1_d <= tri_out_buf(gate2, B2); sub_drive2_d <= tri_out_buf(gate1, B1); RECONCILE: process (TEST, A'TRANSACTION, K5, K10) variable PENDING: boolean; variable G12ON: boolean; begin G12ON := EQUAL(To_X01(TEST), '1'); if (A'ACTIVE and G12ON and not PENDING) then AUX_EN <= '0'; PENDING := TRUE; SUSPEND <= TRUE; K1 <= not K1; end if; if (K10'EVENT and PENDING) then PENDING := FALSE; SUSPEND <= FALSE; if (not EQUAL(A, B1) or not EQUAL(A, B2)) then AUX_EN <= '0'; PENDING := TRUE; SUSPEND <= TRUE; K1 <= not K1; end if; elsif (K5'EVENT and PENDING and SAME_VALS(resolved(SUBSTRATE1 & A) & resolved(SUBSTRATE1 & B1) & resolved(SUBSTRATE1 & B2)) and SAME_VALS(resolved(SUBSTRATE2 & A) & resolved(SUBSTRATE2 & B1) & resolved(SUBSTRATE2 & B2))) then AUX_EN <= '1'; end if; end process RECONCILE; K2 <= K1; K3 <= K2; K4 <= K3; K5 <= K4; K6 <= K5; K7 <= K6; K8 <= K7; K9 <= K8; K10 <= K9; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (SEL_ipd, TEST_ipd) -- Functionality Results Variables VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Q1_GlitchData : VitalGlitchDataType; VARIABLE Q2_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Q1_zd := VitalOR2(a => not SEL_ipd, b => TEST_ipd); Q2_zd := VitalOR2(a => SEL_ipd, b => TEST_ipd); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => GATE1, OutSignalName => "GATE1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SEL_ipd'LAST_EVENT, PathDelay => tpd_SEL_A, PathCondition => TRUE), 1 => (InputChangeTime => TEST_ipd'LAST_EVENT, PathDelay => tpd_SEL_A, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => GATE2, OutSignalName => "GATE2", OutTemp => Q2_zd, GlitchData => Q2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => SEL_ipd'LAST_EVENT, PathDelay => tpd_SEL_A, PathCondition => TRUE), 1 => (InputChangeTime => TEST_ipd'LAST_EVENT, PathDelay => tpd_SEL_A, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;