-------------------------------------------------------------------------------- -- File name : stds16232.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made -- V1.0 R. Munden 99 AUG 12 Initial release based on work done by -- James Holl -- V1.1 R. Munden 02 JUN 22 change GATEx and Qx to std_ulogic -- This is a zero delay model. It will not use interconnect delays or path -- delays annotated to the A or B ports. -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: STNDS -- Technology: FET Bus Switch -- Part: STDS16232 -- -- Description: Synchronous 2-TO-1 FET Mux/Demux -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.switch_pkg.all; USE FMF.ff_package.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY stds16232 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_S0 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A_B1 : VitalDelayType01Z := UnitDelay01Z; tpd_CLK_A : VitalDelayType01 := UnitDelay01; -- tsetup values: setup times tsetup_S0_CLK : VitalDelayType := UnitDelay; tsetup_CLKENNeg_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_S0_CLK : VitalDelayType := UnitDelay; thold_CLKENNeg_CLK : VitalDelayType := UnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- generic control parameters TimingChecksOn : Boolean := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; InstancePath : STRING := DefaultInstancePath; -- For FMF SDF techonology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( S0 : IN std_logic := 'U'; S1 : IN std_logic := 'U'; CLK : IN std_logic := 'U'; CLKENNeg : IN std_logic := 'U'; A : INOUT std_logic := 'Z'; B1 : INOUT std_logic := 'Z'; B2 : INOUT std_logic := 'Z' ); ATTRIBUTE VITAL_LEVEL0 of stds16232 : ENTITY IS TRUE; END stds16232; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of stds16232 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL S0_ipd : std_ulogic := 'U'; SIGNAL S1_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL CLKENNeg_ipd : std_ulogic := 'U'; SIGNAL A_ipd : std_ulogic := 'Z'; SIGNAL B1_ipd : std_ulogic := 'Z'; SIGNAL B2_ipd : std_ulogic := 'Z'; SIGNAL GATE1 : std_ulogic := 'X'; SIGNAL GATE0 : std_ulogic := 'X'; SIGNAL Q0 : std_ulogic := 'X'; SIGNAL Q1 : std_ulogic := 'X'; SIGNAL SUBSTRATE1: std_logic := 'Z'; SIGNAL SUBSTRATE2: std_logic := 'Z'; SIGNAL SUB_DRIVE1_D: std_logic := 'Z'; SIGNAL SUB_DRIVE1_S: std_logic := 'Z'; SIGNAL SUB_DRIVE2_D: std_logic := 'Z'; SIGNAL SUB_DRIVE2_S: std_logic := 'Z'; SIGNAL AUX_EN: X01 := '1'; SIGNAL SUSPEND: boolean; SIGNAL K1, K2, K3, K4, K5, K6, K7, K8, K9, K10: boolean; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (S0_ipd, S0, tipd_S0); w_2: VitalWireDelay (S1_ipd, S1, tipd_S1); w_3: VitalWireDelay (A_ipd, A, tipd_A); w_4: VitalWireDelay (B1_ipd, B1, tipd_B1); w_5: VitalWireDelay (B2_ipd, B2, tipd_B2); w_6: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_7: VitalWireDelay (CLKENNeg_ipd, CLKENNeg, tipd_CLKENNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- sw1: bilateral PORT MAP ( GATE => GATE0, DRAIN => A, SOURCE => B2, SUBSTRATE => SUBSTRATE1, SUB_DRIVE_D => SUB_DRIVE1_D, SUB_DRIVE_S => SUB_DRIVE1_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sw2: bilateral PORT MAP ( GATE => GATE1, DRAIN => A, SOURCE => B1, SUBSTRATE => SUBSTRATE2, SUB_DRIVE_D => SUB_DRIVE2_D, SUB_DRIVE_S => SUB_DRIVE2_S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); sub_drive1_d <= tri_out_buf(gate1, B1); sub_drive2_d <= tri_out_buf(gate0, B2); VitalXOR2(a=> Q0, b=> Q1, q=> Gate1); Gate0 <= Q0; RECONCILE: process (Gate0, Gate1, A'TRANSACTION, K5, K10) variable PENDING: boolean; variable G01ON: boolean; begin G01ON := EQUAL(To_X01(Gate0 AND Gate1), '1'); if (A'ACTIVE and G01ON and not PENDING) then AUX_EN <= '0'; PENDING := TRUE; SUSPEND <= TRUE; K1 <= not K1; end if; if (K10'EVENT and PENDING) then PENDING := FALSE; SUSPEND <= FALSE; if (not EQUAL(A, B1) or not EQUAL(A, B2)) then AUX_EN <= '0'; PENDING := TRUE; SUSPEND <= TRUE; K1 <= not K1; end if; elsif (K5'EVENT and PENDING and SAME_VALS(resolved(SUBSTRATE1 & A) & resolved(SUBSTRATE1 & B1) & resolved(SUBSTRATE1 & B2)) and SAME_VALS(resolved(SUBSTRATE2 & A) & resolved(SUBSTRATE2 & B1) & resolved(SUBSTRATE2 & B2))) then AUX_EN <= '1'; end if; end process RECONCILE; K2 <= K1; K3 <= K2; K4 <= K3; K5 <= K4; K6 <= K5; K7 <= K6; K8 <= K7; K9 <= K8; K10 <= K9; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLK_ipd, S0_ipd, S1_ipd, CLKENNeg_ipd) -- Timing Check Variables VARIABLE Tviol_S0_CLK : X01 := '0'; VARIABLE TD_S0_CLK : VitalTimingDataType; VARIABLE Tviol_S1_CLK : X01 := '0'; VARIABLE TD_S1_CLK : VitalTimingDataType; VARIABLE Tviol_CLKENNeg_CLK : X01 := '0'; VARIABLE TD_CLKENNeg_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation0 : X01 := '0'; VARIABLE Violation1 : X01 := '0'; -- Functionality Results Variables VARIABLE Q0_zd : std_ulogic; VARIABLE PrevData0 : std_logic_vector(0 to 3); VARIABLE Q1_zd : std_ulogic; VARIABLE PrevData1 : std_logic_vector(0 to 3); -- Output Glitch Detection Variables VARIABLE Q0_GlitchData : VitalGlitchDataType; VARIABLE Q1_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => S0_ipd, TestSignalName => "S0", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_S0_CLK, SetupLow => tsetup_S0_CLK, HoldHigh => thold_S0_CLK, HoldLow => thold_S0_CLK, CheckEnabled => (to_X01(CLKENNeg_ipd) = '0'), RefTransition => '/', HeaderMsg => InstancePath & "/stds16232", TimingData => TD_S0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_S0_CLK ); VitalSetupHoldCheck ( TestSignal => S1_ipd, TestSignalName => "S1", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_S0_CLK, SetupLow => tsetup_S0_CLK, HoldHigh => thold_S0_CLK, HoldLow => thold_S0_CLK, CheckEnabled => (to_X01(CLKENNeg_ipd) = '0'), RefTransition => '/', HeaderMsg => InstancePath & "/stds16232", TimingData => TD_S1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_S1_CLK ); VitalSetupHoldCheck ( TestSignal => CLKENNeg_ipd, TestSignalName => "CLKENNeg", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CLKENNeg_CLK, SetupLow => tsetup_CLKENNeg_CLK, HoldHigh => thold_CLKENNeg_CLK, HoldLow => thold_CLKENNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/stds16232", TimingData => TD_CLKENNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CLKENNeg_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/stds16232", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation0 := Tviol_S0_CLK OR Pviol_CLK OR Tviol_CLKENNeg_CLK; Violation1 := Tviol_S1_CLK OR Pviol_CLK OR Tviol_CLKENNeg_CLK; VitalStateTable ( StateTable => DFFCEN_tab, DataIn => (Violation0, CLKENNeg_ipd, CLK_ipd, S0_ipd), Result => Q0_zd, PreviousDataIn => PrevData0 ); VitalStateTable ( StateTable => DFFCEN_tab, DataIn => (Violation1, CLKENNeg_ipd, CLK_ipd, S1_ipd), Result => Q1_zd, PreviousDataIn => PrevData1 ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_A, PathCondition => (to_X01(CLKENNeg) = '0')) ) ); VitalPathDelay01 ( OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => tpd_CLK_A, PathCondition => (to_X01(CLKENNeg) = '0')) ) ); END PROCESS; END vhdl_behavioral;