-------------------------------------------------------------------------------- -- File name : stds16212.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made -- V1.0 R. Munden 99 JUL 26 Initial release based on work done by -- James Holl -- V1.1 R. Munden 02 MAY 16 change types of GATE signals -- This model is zero delay on the data ports. Control ports can make use -- of annotated delays. -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: STNDS -- Technology: FET Bus Exchange Switch -- Part: STDS16212 -- -- Description: 24 Bit Bus Exchange Switch -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.switch_pkg.all; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY stds16212 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_S0 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; tipd_S2 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_A1_B1 : VitalDelayType01 := UnitDelay01; tpd_S0_A1 : VitalDelayType01 := UnitDelay01; -- generic control parameters MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; InstancePath : STRING := DefaultInstancePath; -- For FMF SDF techonology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( S0 : IN std_logic := 'X'; S1 : IN std_logic := 'X'; S2 : IN std_logic := 'X'; A1 : INOUT std_logic := 'Z'; A2 : INOUT std_logic := 'Z'; B1 : INOUT std_logic := 'Z'; B2 : INOUT std_logic := 'Z' ); END stds16212; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF stds16212 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; SIGNAL A1_ipd : std_ulogic := 'Z'; SIGNAL A2_ipd : std_ulogic := 'Z'; SIGNAL B1_ipd : std_ulogic := 'Z'; SIGNAL B2_ipd : std_ulogic := 'Z'; SIGNAL S0_ipd : std_ulogic := 'Z'; SIGNAL S1_ipd : std_ulogic := 'Z'; SIGNAL S2_ipd : std_ulogic := 'Z'; signal GATE1 : std_ulogic := 'X'; signal GATE2 : std_ulogic := 'X'; signal GATE3 : std_ulogic := 'X'; signal GATE4 : std_ulogic := 'X'; signal SUBSTRATE1: std_logic := 'Z'; signal SUBSTRATE2: std_logic := 'Z'; signal SUBSTRATE3: std_logic := 'Z'; signal SUBSTRATE4: std_logic := 'Z'; signal SUB_DRIVE_1D: std_logic := 'Z'; signal SUB_DRIVE_2D: std_logic := 'Z'; signal SUB_DRIVE_3D: std_logic := 'Z'; signal SUB_DRIVE_4D: std_logic := 'Z'; signal SUB_DRIVE_1S: std_logic := 'Z'; signal SUB_DRIVE_2S: std_logic := 'Z'; signal SUB_DRIVE_3S: std_logic := 'Z'; signal SUB_DRIVE_4S: std_logic := 'Z'; signal AUX_EN: X01 := '1'; signal SUSPEND: boolean; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (S0_ipd, S0, tipd_S0); w_2: VitalWireDelay (S1_ipd, S1, tipd_S1); w_3: VitalWireDelay (S2_ipd, S2, tipd_S2); w_4: VitalWireDelay (B1_ipd, B1, tipd_B1); w_5: VitalWireDelay (B2_ipd, B2, tipd_B2); w_6: VitalWireDelay (A1_ipd, A1, tipd_A1); w_7: VitalWireDelay (A2_ipd, A2, tipd_A2); END BLOCK; SW1: BILATERAL port map ( GATE => GATE1, DRAIN => A1, SOURCE => B1, SUBSTRATE => SUBSTRATE1, SUB_DRIVE_D => SUB_DRIVE_1D, SUB_DRIVE_S => SUB_DRIVE_1S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW2: BILATERAL port map ( GATE => GATE2, DRAIN => A1, SOURCE => B2, SUBSTRATE => SUBSTRATE2, SUB_DRIVE_D => SUB_DRIVE_2D, SUB_DRIVE_S => SUB_DRIVE_2S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW3: BILATERAL port map ( GATE => GATE3, DRAIN => A2, SOURCE => B1, SUBSTRATE => SUBSTRATE3, SUB_DRIVE_D => SUB_DRIVE_3D, SUB_DRIVE_S => SUB_DRIVE_3S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); SW4: BILATERAL port map ( GATE => GATE4, DRAIN => A2, SOURCE => B2, SUBSTRATE => SUBSTRATE4, SUB_DRIVE_D => SUB_DRIVE_4D, SUB_DRIVE_S => SUB_DRIVE_4S, AUX_EN => AUX_EN, SUSPEND => SUSPEND); ---------------------------------------------------------------------------- -- Control Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (S2_ipd, S1_ipd, S0_ipd) -- Functionality Results Variables VARIABLE Gate1_zd : std_ulogic; VARIABLE Gate2_zd : std_ulogic; VARIABLE Gate3_zd : std_ulogic; VARIABLE Gate4_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Gate1_GlitchData : VitalGlitchDataType; VARIABLE Gate2_GlitchData : VitalGlitchDataType; VARIABLE Gate3_GlitchData : VitalGlitchDataType; VARIABLE Gate4_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Gate1_zd := VitalOR2(a => VitalAND3(a => S2_ipd, b => S1_ipd, c => not S0_ipd), b => VitalAND3(a => not S2_ipd, b => not S1_ipd, c => S0_ipd)); Gate2_zd := VitalOR2(a => VitalAND3(a => S2_ipd, b => S1_ipd, c => S0_ipd), b => VitalAND3(a => not S2_ipd, b => S1_ipd, c => not S0_ipd)); Gate3_zd := VitalOR2(a => VitalAND3(a => S2_ipd, b => S1_ipd, c => S0_ipd), b => VitalAND3(a => not S2_ipd, b => S1_ipd, c => S0_ipd)); Gate4_zd := VitalOR2(a => VitalAND3(a => S2_ipd, b => S1_ipd, c => not S0_ipd), b => VitalAND3(a => S2_ipd, b => not S1_ipd, c => not S0_ipd)); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => GATE1, OutSignalName => "GATE1", OutTemp => Gate1_zd, GlitchData => Gate1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 1 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 2 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => GATE2, OutSignalName => "GATE2", OutTemp => Gate2_zd, GlitchData => Gate2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 1 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 2 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => GATE3, OutSignalName => "GATE3", OutTemp => Gate3_zd, GlitchData => Gate3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 1 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 2 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => GATE4, OutSignalName => "GATE4", OutTemp => Gate4_zd, GlitchData => Gate4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => S2_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 1 => (InputChangeTime => S1_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE), 2 => (InputChangeTime => S0_ipd'LAST_EVENT, PathDelay => tpd_S0_A1, PathCondition => TRUE) ) ); END PROCESS; end vhdl_behavioral;