FMF Timing for STDH16836 Parts version: | author: | mod date: | changes made: V1.0 S.Randjic,D.Djokovic 01 OCT 06 Initial release 1ns STDH16836 SN74ALVCH162836DL_2V5Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGG_2V5Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGV_2V5Texas Instruments SCES129B-Revised February 1999 Values are for VCC = 2.48V to 2.52V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (1.0:2.7:4.4) (1.0:2.7:4.4)) (IOPATH LENeg Y (1.1:3.4:5.8) (1.1:3.4:5.8)) (IOPATH CLK Y (1.0:3.1:5.2) (1.0:3.1:5.2)) (IOPATH OENeg Y () () (1.0:2.8:4.7) (1.1:3.7:6.4) (1.0:2.8:4.7) (1.1:3.7:6.4)) )) (TIMINGCHECK (SETUP A CLK (1.4)) (SETUP (COND CLK == 1 A) LENeg (1.2:1.8:2.4)) (SETUP (COND CLK == 0 A) LENeg (1.4:2.1:2.8)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) SN74ALVCH162836DL_2V7Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGG_2V7Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGV_2V7Texas Instruments SCES129B-Revised February 1999 Values are for VCC = 2.7V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (2.2:3.4:4.6) (2.2:3.4:4.6)) (IOPATH LENeg Y (3.0:4.6:6.1) (3.0:4.6:6.1)) (IOPATH CLK Y (2.7:4.1:5.5) (2.7:4.1:5.5)) (IOPATH OENeg Y () () (2.6:3.9:5.2) (3.2:4.9:6.5) (2.6:3.9:5.2) (3.2:4.9:6.5)) )) (TIMINGCHECK (SETUP A CLK (1.7)) (SETUP (COND CLK == 1 A) LENeg (1.6)) (SETUP (COND CLK == 0 A) LENeg (1.5)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) SN74ALVCH162836DL_3V3Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGG_3V3Texas Instruments SCES129B-Revised February 1999 SN74ALVCH162836DGV_3V3Texas Instruments SCES129B-Revised February 1999 Values are for VCC = 3.0V to 3.6V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (1.2:2.6:4.0) (1.2:2.6:4.0)) (IOPATH LENeg Y (1.4:3.2:5.1) (1.4:3.2:5.1)) (IOPATH CLK Y (1.1:3.0:5.0) (1.1:3.0:5.0)) (IOPATH OENeg Y () () (1.7:3.4:5.1) (1.2:3.3:5.5) (1.7:3.4:5.1) (1.2:3.3:5.5)) )) (TIMINGCHECK (SETUP A CLK (1.5)) (SETUP (COND CLK == 1 A) LENeg (1.3)) (SETUP (COND CLK == 0 A) LENeg (1.2)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) IDT74ALVCH162836PA_2V5Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PV_2V5Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PF_2V5Integrated Device Tecnology DSC-4900/1 Revised March 1999 Values are for VCC = 2.48V to 2.52V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (1.0:2.7:4.4) (1.0:2.7:4.4)) (IOPATH LENeg Y (1.1:3.4:5.8) (1.1:3.4:5.8)) (IOPATH CLK Y (1.0:3.1:5.2) (1.0:3.1:5.2)) (IOPATH OENeg Y () () (1.0:2.8:4.7) (1.1:3.7:6.4) (1.0:2.8:4.7) (1.1:3.7:6.4)) )) (TIMINGCHECK (SETUP A CLK (1.4)) (SETUP (COND CLK == 1 A) LENeg (1.2)) (SETUP (COND CLK == 0 A) LENeg (1.4)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) IDT74ALVCH162836PA_2V7Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PV_2V7Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PF_2V7Integrated Device Tecnology DSC-4900/1 Revised March 1999 Values are for VCC = 2.7V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (2.2:3.4:4.6) (2.2:3.4:4.6)) (IOPATH LENeg Y (3.0:4.6:6.1) (3.0:4.6:6.1)) (IOPATH CLK Y (2.7:4.1:5.5) (2.7:4.1:5.5)) (IOPATH OENeg Y () () (2.6:3.9:5.2) (3.2:4.9:6.5) (2.6:3.9:5.2) (3.2:4.9:6.5)) )) (TIMINGCHECK (SETUP A CLK (1.7)) (SETUP (COND CLK == 1 A) LENeg (1.6)) (SETUP (COND CLK == 0 A) LENeg (1.5)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) IDT74ALVCH162836PA_3V3Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PV_3V3Integrated Device Tecnology DSC-4900/1 Revised March 1999 IDT74ALVCH162836PF_3V3Integrated Device Tecnology DSC-4900/1 Revised March 1999 Values are for VCC = 3.0V to 3.6V, TA =-40C to +80C (DELAY (ABSOLUTE (IOPATH A Y (1.2:2.6:4.0) (1.2:2.6:4.0)) (IOPATH LENeg Y (1.4:3.2:5.1) (1.4:3.2:5.1)) (IOPATH CLK Y (1.1:3.0:5.0) (1.1:3.0:5.0)) (IOPATH OENeg Y () () (1.7:3.4:5.1) (1.2:3.3:5.5) (1.7:3.4:5.1) (1.2:3.3:5.5)) )) (TIMINGCHECK (SETUP A CLK (1.5)) (SETUP (COND CLK == 1 A) LENeg (1.3)) (SETUP (COND CLK == 0 A) LENeg (1.2)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.6)) ) IDT74ALVCH16836PA_2V5Integrated Device Tecnology DSC-4998/1 Revised March 1999 IDT74ALVCH16836PV_2V5Integrated Device Tecnology DSC-4998/1 Revised March 1999 IDT74ALVCH16836PF_2V5Integrated Device Tecnology DSC-4998/1 Revised March 1999 Values are for VCC = 2.48V to 2.52V, TA =-40C to +80C Typ values are derived (DELAY (ABSOLUTE (IOPATH A Y (1.0:2.7:4.2) (1.0:2.7:4.2)) (IOPATH LENeg Y (1.3:3.4:5) (1.3:3.4:5)) (IOPATH CLK Y (1.4:3.8:5.5) (1.4:3.8:5.5)) (IOPATH OENeg Y () () (1.0:2.8:4.5) (1.4:3.8:5.5) (1.0:2.8:4.5) (1.4:3.8:5.5)) )) (TIMINGCHECK (SETUP A CLK (1.4)) (SETUP (COND CLK == 1 A) LENeg (1.2)) (SETUP (COND CLK == 0 A) LENeg (1.4)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.67)) ) IDT74ALVCH16836PA_3V3Integrated Device Tecnology DSC-4998/1 Revised March 1999 IDT74ALVCH16836PV_3V3Integrated Device Tecnology DSC-4998/1 Revised March 1999 IDT74ALVCH16836PF_3V3Integrated Device Tecnology DSC-4998/1 Revised March 1999 Values are for VCC = 3.0V to 3.6V, TA =-40C to +80C Typ values are derived (DELAY (ABSOLUTE (IOPATH A Y (1:2.4:3.6) (1:2.4:3.6)) (IOPATH LENeg Y (1.3:2.6:4.2) (1.3:2.6:4.2)) (IOPATH CLK Y (1.4:3.0:4.5) (1.4:3.0:4.5)) (IOPATH OENeg Y () () (1.3:2.6:3.9) (1.1:3.1:4.6) (1.3:2.6:3.9) (1.1:3.1:4.6)) )) (TIMINGCHECK (SETUP A CLK (1.5)) (SETUP (COND CLK == 1 A) LENeg (1.3)) (SETUP (COND CLK == 0 A) LENeg (1.2)) (HOLD A CLK (0.9)) (HOLD A LENeg (1.1)) (WIDTH (posedge CLK) (3.3)) (WIDTH (negedge LENeg) (3.3)) (PERIOD (posedge CLK) (6.67)) )