version: | author: | mod date: | changes made: V1.0 R. Munden 99 Nov 26 Initial release 1ns std174 74ACT174MTCFairchild Semiconductor DS009935 November 1999 74ACT174PCFairchild Semiconductor DS009935 November 1999 74ACT174SCFairchild Semiconductor DS009935 November 1999 74ACT174SJFairchild Semiconductor DS009935 November 1999 Values are for VCC=4.5V to 5.5V, CL=50pF, Ta=25C (DELAY (ABSOLUTE (IOPATH CLK Q (1.5:7.0:10.5) (1.5:7.0:10.5)) (IOPATH CLRNeg Q (1.5:6.5:9.5) (1.5:6.5:9.5)) )) (TIMINGCHECK (SETUP D CLK (1.5:1.5:1.5)) (HOLD D CLK (2.0:2.0:2.0)) (RECOVERY CLRNeg CLK (0.5:0.5:0.5)) (WIDTH (posedge CLK) (3.0:3.0:3.0)) (WIDTH (negedge CLK) (3.0:3.0:3.0)) (WIDTH (negedge CLRNeg) (3.0:3.0:3.0)) (PERIOD (posedge CLK) (6.0:6.0:6.0)) ) CD74ACT174DTexas Instruments SCHS241 September 1998 CD74ACT174NTexas Instruments SCHS241 September 1998 Values are for VCC=4.5V to 5.5V, CL=50pF, Ta=-40C to 85C (DELAY (ABSOLUTE (IOPATH CLK Q (3.6:7.2:12.6) (3.6:7.2:12.6)) (IOPATH CLRNeg Q (4.0:8.0:14.1) (4.0:8.0:14.1)) )) (TIMINGCHECK (SETUP D CLK (2:2:2)) (HOLD D CLK (2.2:2.2:2.2)) (RECOVERY CLRNeg CLK (1.5:1.5:1.5)) (WIDTH (posedge CLK) (5.4:5.4:5.4)) (WIDTH (negedge CLK) (5.4:5.4:5.4)) (WIDTH (negedge CLRNeg) (3.5:3.5:3.5)) (PERIOD (posedge CLK) (11:11:11)) ) DM74ALS174MFairchild Semiconductor DS006112 February 1998 DM74ALS174NFairchild Semiconductor DS006112 February 1998 DM74ALS174SJFairchild Semiconductor DS006112 February 1998 Values are for VCC=4.5V to 5.5V, CL=50pF, Ta=0C to 70C (DELAY (ABSOLUTE (IOPATH CLK Q (3:8:15) (5:9:17)) (IOPATH CLRNeg Q (8:16:23) (8:16:23)) )) (TIMINGCHECK (SETUP D CLK (10:10:10)) (HOLD D CLK (0:0:0)) (RECOVERY CLRNeg CLK (6:6:6)) (WIDTH (posedge CLK) (10:10:10)) (WIDTH (negedge CLK) (10:10:10)) (WIDTH (negedge CLRNeg) (10:10:10)) (PERIOD (posedge CLK) (20:20:20)) ) SN74ALS174DTexas Instruments SDAS207D-revised May 1996 SN74ALS174NTexas Instruments SDAS207D-revised May 1996 SN74ALS174NSTexas Instruments SDAS207D-revised May 1996 Values are for VCC=4.5V to 5.5V, CL=50pF, Ta=0C to 70C (DELAY (ABSOLUTE (IOPATH CLK Q (3:10:20) (5:12:24)) (IOPATH CLRNeg Q (3:10:20) (5:15:30)) )) (TIMINGCHECK (SETUP D CLK (10:10:10)) (HOLD D CLK (0:0:0)) (RECOVERY CLRNeg CLK (6:6:6)) (WIDTH (posedge CLK) (10:10:10)) (WIDTH (negedge CLK) (10:10:10)) (WIDTH (negedge CLRNeg) (15:15:15)) (PERIOD (posedge CLK) (20:20:20)) ) 74F174PCFairchild Semiconductor DS009489 July 1999 74F174SCFairchild Semiconductor DS009489 July 1999 74F174SJFairchild Semiconductor DS009489 July 1999 Values are for VCC=4.5V to 5.5V, CL=50pF, Ta=25C (DELAY (ABSOLUTE (IOPATH CLK Q (3.5:5.5:8.0) (4.0:7.0:10.0)) (IOPATH CLRNeg Q (5.0:10.0:14.0) (5.0:10.0:14.0)) )) (TIMINGCHECK (SETUP D CLK (4.8:4.8:4.8)) (HOLD D CLK (0:0:0)) (RECOVERY CLRNeg CLK (5.0:5.0:5.0)) (WIDTH (posedge CLK) (4.0:4.0:4.0)) (WIDTH (negedge CLK) (6.0:6.0:6.0)) (WIDTH (negedge CLRNeg) (5.0:5.0:5.0)) (PERIOD (posedge CLK) (12.5:12.5:12.5)) ) N74F174DPhilips Semiconductors IC15 Data Handbook 1988 Oct 07 N74F174NPhilips Semiconductors IC15 Data Handbook 1988 Oct 07 Values are for VCC=5.0V, CL=50pF, Ta=25C (DELAY (ABSOLUTE (IOPATH CLK Q (3.5:5.5:8.0) (4.5:6.0:10.0)) (IOPATH CLRNeg Q (5.0:8.5:14.0) (5.0:8.5:14.0)) )) (TIMINGCHECK (SETUP D CLK (4:4:4)) (HOLD D CLK (0:0:0)) (RECOVERY CLRNeg CLK (5:5:5)) (WIDTH (posedge CLK) (4:4:4)) (WIDTH (negedge CLK) (5:5:5)) (WIDTH (negedge CLRNeg) (5:5:5)) (PERIOD (posedge CLK) (12.5:12.5:12.5)) )