version: | author: | mod date: | changes made: V1.0 R. Munden 01 Aug 07 Initial release 1ns std166 SN74ALS166DTexas Instruments SDAS156D-Revised August 2000 SN74ALS166DBTexas Instruments SDAS156D-Revised August 2000 SN74ALS166NTexas Instruments SDAS156D-Revised August 2000 The Values listed are for VCC=4.5V-5.5V, CL=50pF, Ta=0 to +70 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (2:7:12) (2:9:13)) (IOPATH CLRNeg Q (4:9:14) (4:9:14)) )) (TIMINGCHECK (SETUP CLRNeg CLK (11:11:11)) (SETUP SH CLK (16:16:16)) (SETUP DA CLK (7:7:7)) (SETUP SER CLK (0:0:0)) (SETUP CLKINH CLK (0:0:0)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (3:3:3)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (10:10:10)) (WIDTH (negedge CLRNeg) (9:9:9)) (PERIOD (posedge CLK) (23:23:23)) ) N74F166DPhilips Semiconductors Data Sheet Feb. 14, 1991 N74F166NPhilips Semiconductors Data Sheet Feb. 14, 1991 The Values listed are for VCC=5V, CL=50pF, Ta=0 to +70 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (5:7.5:12) (3.5:6:9)) (IOPATH CLRNeg Q (4:6.5:9.5) (4:6.5:9.5)) )) (TIMINGCHECK (SETUP CLRNeg CLK (4.5:4.5:4.5)) (SETUP SH CLK (4:4:4)) (SETUP DA CLK (4:4:4)) (SETUP SER CLK (4:4:4)) (SETUP CLKINH CLK (4:4:4)) (HOLD SER CLK (1:1:1)) (HOLD DA CLK (1:1:1)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (5:5:5)) (WIDTH (negedge CLRNeg) (4:4:4)) (PERIOD (posedge CLK) (10:10:10)) ) 74HC166DPhilips Semiconductors Data Sheet 1990 74HC166DBPhilips Semiconductors Data Sheet 1990 74HC166NPhilips Semiconductors Data Sheet 1990 74HC166PWPhilips Semiconductors Data Sheet 1990 The Values listed are for VCC=4.5V, CL=50pF, Ta=-40 to +85 Celsius Typical values are at Ta=25C (DELAY (ABSOLUTE (IOPATH CLK Q (9:18:38) (9:18:38)) (IOPATH CLRNeg Q (8:17:40) (8:17:40)) )) (TIMINGCHECK (SETUP CLRNeg CLK (0:0:0)) (SETUP SH CLK (25:25:25)) (SETUP DA CLK (20:20:20)) (SETUP SER CLK (0:0:0)) (SETUP CLKINH CLK (20:20:20)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (2:2:2)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (2:2:2)) (WIDTH (posedge CLK) (20:20:20)) (WIDTH (negedge CLRNeg) (25:25:25)) (PERIOD (posedge CLK) (42:42:42)) ) SN74HC166DTexas Instruments SCLS117B-Revised May 1997 SN74HC166NTexas Instruments SCLS117B-Revised May 1997 The Values listed are for VCC=4.5V, CL=50pF, Ta=-40 to +85 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK Q (7:15:38) (7:15:38)) (IOPATH CLRNeg Q (9:18:30) (9:18:30)) )) (TIMINGCHECK (SETUP CLRNeg CLK (10:10:10)) (SETUP SH CLK (36:36:36)) (SETUP DA CLK (20:20:20)) (SETUP SER CLK (20:20:20)) (SETUP CLKINH CLK (25:25:25)) (HOLD SER CLK (5:5:5)) (HOLD DA CLK (5:5:5)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (20:20:20)) (WIDTH (negedge CLRNeg) (25:25:25)) (PERIOD (posedge CLK) (40:40:40)) ) 74HCT166DPhilips Semiconductors Data Sheet 1990 74HCT166DBPhilips Semiconductors Data Sheet 1990 74HCT166NPhilips Semiconductors Data Sheet 1990 The Values listed are for VCC=4.5V, CL=50pF, Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (11:23:50) (11:23:50)) (IOPATH CLRNeg Q (11:22:50) (11:22:50)) )) (TIMINGCHECK (SETUP CLRNeg CLK (0:0:0)) (SETUP SH CLK (38:38:38)) (SETUP DA CLK (20:20:20)) (SETUP SER CLK (0:0:0)) (SETUP CLKINH CLK (20:20:20)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (0:0:0)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (25:25:25)) (WIDTH (negedge CLRNeg) (31:31:31)) (PERIOD (posedge CLK) (50:50:50)) ) DM74LS166MFairchild Semiconductor data sheet March 2000 DM74LS166NFairchild Semiconductor data sheet March 2000 DM74LS166WMFairchild Semiconductor data sheet March 2000 The Values listed are for VCC=5V, CL=15pF, Ta=+25 Celsius Typ values are derived (DELAY (ABSOLUTE (IOPATH CLK Q (8:16:35) (8:16:35)) (IOPATH CLRNeg Q (6:12:30) (6:12:30)) )) (TIMINGCHECK (SETUP CLRNeg CLK (0:0:0)) (SETUP SH CLK (30:30:30)) (SETUP DA CLK (20:20:20)) (SETUP SER CLK (20:20:20)) (SETUP CLKINH CLK (0:0:0)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (0:0:0)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (20:20:20)) (WIDTH (negedge CLRNeg) (20:20:20)) (PERIOD (posedge CLK) (40:40:40)) ) SN74LS166ADTexas Instruments SDLS119-Revised March 1988 SN74LS166ANTexas Instruments SDLS119-Revised March 1988 The Values listed are for VCC=5V, CL=15pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (5:11:20) (7:14:25)) (IOPATH CLRNeg Q (9:19:30) (9:19:30)) )) (TIMINGCHECK (SETUP CLRNeg CLK (0:0:0)) (SETUP SH CLK (30:30:30)) (SETUP DA CLK (20:20:20)) (SETUP SER CLK (30:30:30)) (SETUP CLKINH CLK (0:0:0)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (0:0:0)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (25:25:25)) (WIDTH (negedge CLRNeg) (20:20:20)) (PERIOD (posedge CLK) (40:40:40)) ) SN74LV166AD_3V3Texas Instruments SCLS456-Revised February 2001 SN74LV166ADB_3V3Texas Instruments SCLS456-Revised February 2001 SN74LV166ADGV_3V3Texas Instruments SCLS456-Revised February 2001 SN74LV166APW_3V3Texas Instruments SCLS456-Revised February 2001 The Values listed are for VCC=3.0 to 3.6V, CL=50pF, Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (1:8.3:21.5) (1:8.3:21.5)) (IOPATH CLRNeg Q (1:7.9:18.5) (1:7.9:18.5)) )) (TIMINGCHECK (SETUP CLRNeg CLK (4:4:4)) (SETUP SH CLK (6:6:6)) (SETUP DA CLK (6:6:6)) (SETUP SER CLK (6:6:6)) (SETUP CLKINH CLK (5:5:5)) (HOLD SER CLK (0:0:0)) (HOLD DA CLK (0:0:0)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (7:7:7)) (WIDTH (negedge CLRNeg) (7:7:7)) (PERIOD (posedge CLK) (20:20:20)) ) SN74LV166AD_5VTexas Instruments SCLS456-Revised February 2001 SN74LV166ADB_5VTexas Instruments SCLS456-Revised February 2001 SN74LV166ADGV_5VTexas Instruments SCLS456-Revised February 2001 SN74LV166APW_5VTexas Instruments SCLS456-Revised February 2001 The Values listed are for VCC=4.5V-5.5V, CL=50pF, Ta=-40 to +85 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (1:6.1:13.5) (1:6.1:13.5)) (IOPATH CLRNeg Q (1:5.7:12) (1:5.7:12)) )) (TIMINGCHECK (SETUP CLRNeg CLK (3.5:3.5:3.5)) (SETUP SH CLK (4:4:4)) (SETUP DA CLK (4.5:4.5:4.5)) (SETUP SER CLK (4:4:4)) (SETUP CLKINH CLK (3.5:3.5:3.5)) (HOLD SER CLK (1:1:1)) (HOLD DA CLK (1:1:1)) (HOLD SH CLK (0:0:0)) (HOLD CLKINH CLK (0:0:0)) (WIDTH (posedge CLK) (4:4:4)) (WIDTH (negedge CLRNeg) (5:5:5)) (PERIOD (posedge CLK) (12:12:12)) )