version: | author: | mod date: | changes made: V1.0 R. Munden 99 Nov 21 Initial release V1.1 R. Munden 01 Dec 01 Added 10 new partnumbers 1ns STD163 74F163APCFairchild Semiconductor DS009486 revised July 1999 74F163ASCFairchild Semiconductor DS009486 revised July 1999 74F163ASJFairchild Semiconductor DS009486 revised July 1999 Values are for VCC=5.0V, CL=50pF, Ta=25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q0 (3.5:6.0:8.5) (3.5:7.5:10.0)) (IOPATH CLK RCO (5.0:10.0:14.0) (5.0:10.0:14.0)) (IOPATH ENT RCO (2.5:4.5:7.5) (2.5:4.5:7.5)) )) (TIMINGCHECK (SETUP P0 CLK (5.0:5.0:5.0)) (SETUP ENP CLK (11.0:11.0:11.0)) (SETUP LDNeg CLK (11.0:11.0:11.0)) (SETUP CLRNeg CLK (11.0:11.0:11.0)) (HOLD P0 CLK (2.0:2.0:2.0)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (2.0:2.0:2.0)) (HOLD CLRNeg CLK (2.0:2.0:2.0)) (WIDTH (posedge CLK) (5.0:5.0:5.0)) (WIDTH (negedge CLK) (6.0:6.0:6.0)) (PERIOD (posedge CLK) (10.0:10.0:10.0)) ) SN74F163ADTexas Instruments SDFS088 revised October 1993 SN74F163ANTexas Instruments SDFS088 revised October 1993 Values are for VCC=5.0V, CL=50pF, Ta=25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q0 (2.7:5.6:8.5) (2.7:7.1:10.0)) (IOPATH CLK RCO (4.2:9.6:14) (4.2:9.6:14)) (IOPATH ENT RCO (1.7:4.1:7.5) (1.7:4.1:7.5)) )) (TIMINGCHECK (SETUP P0 CLK (5:5:5)) (SETUP ENP CLK (11:11:11)) (SETUP LDNeg CLK (11:11:11)) (SETUP CLRNeg CLK (11:11:11)) (HOLD P0 CLK (2:2:2)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (0:0:0)) (HOLD CLRNeg CLK (0:0:0)) (WIDTH (posedge CLK) (5:5:5)) (WIDTH (negedge CLK) (6:6:6)) (PERIOD (posedge CLK) (10:10:10)) ) MM74HC163MFairchild Semiconductor DS005008 September 2001 MM74HC163NFairchild Semiconductor DS005008 September 2001 MM74HC163SJFairchild Semiconductor DS005008 September 2001 Values are for VCC=4.5V, CL=50pF, Ta=-40 to 85 Celsius Min values are derived (DELAY (ABSOLUTE (IOPATH CLK Q0 (8:17:43) (15:30:52)) (IOPATH CLK RCO (9:18:44) (16:32:54)) (IOPATH ENT RCO (8:16:40) (14:28:49)) )) (TIMINGCHECK (SETUP P0 CLK (38)) (SETUP ENP CLK (44)) (SETUP LDNeg CLK (34)) (SETUP CLRNeg CLK (38)) (HOLD P0 CLK (13)) (HOLD ENP CLK (0)) (HOLD LDNeg CLK (0)) (HOLD CLRNeg CLK (0:0:0)) (WIDTH (posedge CLK) (20)) (WIDTH (negedge CLK) (20)) (PERIOD (posedge CLK) (40)) ) 74HC163DPhilips Semiconductors Product Specification December 1990 74HC163DBPhilips Semiconductors Product Specification December 1990 74HC163NPhilips Semiconductors Product Specification December 1990 74HC163PWPhilips Semiconductors Product Specification December 1990 Values are for VCC=4.5V, CL=50pF, Ta=-40 to 85 Celsius Min values are derived (DELAY (ABSOLUTE (IOPATH CLK Q0 (10:20:46) (10:20:46)) (IOPATH CLK RCO (12:25:54) (12:25:54)) (IOPATH ENT RCO (5:10:26) (5:10:26)) )) (TIMINGCHECK (SETUP P0 CLK (20)) (SETUP ENP CLK (20)) (SETUP LDNeg CLK (20)) (SETUP CLRNeg CLK (44)) (HOLD P0 CLK (0)) (HOLD ENP CLK (0)) (HOLD LDNeg CLK (0)) (HOLD CLRNeg CLK (0:0:0)) (WIDTH (posedge CLK) (20)) (WIDTH (negedge CLK) (20)) (PERIOD (posedge CLK) (45)) ) SN74HC163DTexas Instruments SCLS298A-revised May 1997 SN74HC163NTexas Instruments SCLS298A-revised May 1997 SN74HC163NSTexas Instruments SCLS298A-revised May 1997 Values are for VCC=4.5V, CL=50pF, Ta=-40 to 85 Celsius Min values are derived (DELAY (ABSOLUTE (IOPATH CLK Q0 (12:25:51) (12:25:51)) (IOPATH CLK RCO (12:24:54) (12:24:54)) (IOPATH ENT RCO (8:17:49) (8:17:49)) )) (TIMINGCHECK (SETUP P0 CLK (38)) (SETUP ENP CLK (43)) (SETUP LDNeg CLK (43)) (SETUP CLRNeg CLK (40)) (HOLD P0 CLK (0)) (HOLD ENP CLK (0)) (HOLD LDNeg CLK (0)) (HOLD CLRNeg CLK (0:0:0)) (WIDTH (posedge CLK) (20)) (WIDTH (negedge CLK) (20)) (PERIOD (posedge CLK) (40)) )