version: | author: | mod date: | changes made: V1.0 R. Munden 99 Nov 13 Initial release V1.1 R. Munden 01 OCT 31 Added 7 new part numbers 1ns STD161 74ACT161MTCFairchild Semiconductor DS00931.prf revised December 1998 74ACT161PCFairchild Semiconductor DS00931.prf revised December 1998 74ACT161SCFairchild Semiconductor DS00931.prf revised December 1998 74ACT161SJFairchild Semiconductor DS00931.prf revised December 1998 The values listed are for VCC=5V, CL=50pF, Ta=25C (DELAY (ABSOLUTE (IOPATH CLRNeg Q0 (1.5:6.0:13.5) (1.5:6.0:13.5)) (IOPATH CLK Q0 (1.5:5.5:9.5) (1.5:6.0:10.5)) (IOPATH CLK RCO (2.0:7.0:11.0) (1.5:8.0:12.5)) (IOPATH ENT RCO (1.5:5.5:8.5) (1.5:6.5:9.5)) )) (TIMINGCHECK (SETUP P0 CLK (9.5:9.5:9.5)) (SETUP ENP CLK (5.5:5.5:5.5)) (SETUP LDNeg CLK (8.5:8.5:8.5)) (HOLD P0 CLK (0:0:0)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (0:0:0)) (RECOVERY CLRNeg CLK (0:0:0)) (WIDTH (negedge CLRNeg) (3:3:3)) (WIDTH (posedge CLK) (3:3:3)) (WIDTH (negedge CLK) (3:3:3)) (PERIOD (posedge CLK) (10:10:10)) ) MC74ACT161DMotorola FACT Data rev 3 MC74ACT161NMotorola FACT Data rev 3 The values listed are for VCC=5V, CL=50pF, Ta=25C (DELAY (ABSOLUTE (IOPATH CLRNeg Q0 (1.5:8.0:10.0) (1.5:8.0:10.0)) (IOPATH CLK Q0 (1.5:8.0:9.5) (1.5:8.0:10.5)) (IOPATH CLK RCO (2.0:11.0:11.0) (1.5:11.0:12.5)) (IOPATH ENT RCO (1.5:7.5:8.5) (1.5:8.0:9.5)) )) (TIMINGCHECK (SETUP P0 CLK (9.5:9.5:9.5)) (SETUP ENP CLK (5.5:5.5:5.5)) (SETUP LDNeg CLK (8.5:8.5:8.5)) (HOLD P0 CLK (0:0:0)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (0:0:0)) (RECOVERY CLRNeg CLK (0:0:0)) (WIDTH (negedge CLRNeg) (3.0:3.0:3.0)) (WIDTH (posedge CLK) (3.0:3.0:3.0)) (WIDTH (negedge CLK) (3.0:3.0:3.0)) (PERIOD (posedge CLK) (10:10:10)) ) IDT74LVC161ADC_3V3Integrated Device Technology DSC-5156/- October 1999 IDT74LVC161APG_3V3Integrated Device Technology DSC-5156/- October 1999 IDT74LVC161APY_3V3Integrated Device Technology DSC-5156/- October 1999 IDT74LVC161AQ_3V3Integrated Device Technology DSC-5156/- October 1999 The Values listed are for VCC=3.0 to 3.6V, CL=50pF, Ta=-40 to +85 Celsius Min and typ values are derived (DELAY (ABSOLUTE (IOPATH CLRNeg Q0 (3:6:9) (3:6:9)) (IOPATH CLK Q0 (3:5:8) (3:5:8)) (IOPATH CLK RCO (3:6:9.5) (3:6:9.5)) (IOPATH ENT RCO (3:5:7.8) (3:5:7.8)) )) (TIMINGCHECK (SETUP P0 CLK (3:3:3)) (SETUP ENP CLK (5:5:5)) (SETUP LDNeg CLK (3:3:3)) (HOLD P0 CLK (0:0:0)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (0:0:0)) (RECOVERY CLRNeg CLK (.5:.5:.5)) (WIDTH (negedge CLRNeg) (3:3:3)) (WIDTH (posedge CLK) (4:4:4)) (WIDTH (negedge CLK) (4:4:4)) (PERIOD (posedge CLK) (8:8:8)) ) 74LVC161D_3V3Philips Semiconductors 853-1864 19421 1998 May 20 74LVC161DB_3V3Philips Semiconductors 853-1864 19421 1998 May 20 74LVC161PW_3V3Philips Semiconductors 853-1864 19421 1998 May 20 The Values listed are for VCC=3.0 to 3.6V, CL=50pF, Ta=-40 to +85 Celsius Min values are derived (DELAY (ABSOLUTE (IOPATH CLRNeg Q0 (2.6:5.2:9) (2.6:5.2:9)) (IOPATH CLK Q0 (2.5:4.9:8) (2.5:4.9:8)) (IOPATH CLK RCO (2.8:5.7:9.5) (2.8:5.7:9.5)) (IOPATH ENT RCO (2.3:4.5:7.8) (2.3:4.5:7.8)) )) (TIMINGCHECK (SETUP P0 CLK (2.5:2.5:2.5)) (SETUP ENP CLK (5:5:5)) (SETUP LDNeg CLK (3:3:3)) (HOLD P0 CLK (0:0:0)) (HOLD ENP CLK (0:0:0)) (HOLD LDNeg CLK (0:0:0)) (RECOVERY CLRNeg CLK (0:0:0)) (WIDTH (negedge CLRNeg) (3:3:3)) (WIDTH (posedge CLK) (4:4:4)) (WIDTH (negedge CLK) (4:4:4)) (PERIOD (posedge CLK) (8:8:8)) )