version: | author: | mod date: | changes made: V1.0 R. Munden 98 SEP 21 Initial release 1ns STD112 74F112PCFairchild Semiconductor March 1998 74F112SCFairchild Semiconductor March 1998 74F112SJFairchild Semiconductor March 1998 MC74F112DMotorola Fast and LS TTL Data, DL121 REV 5 MC74F112NMotorola Fast and LS TTL Data, DL121 REV 5 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (2.0:5.0:6.5) (2.0:5.0:6.5)) (IOPATH PRENeg Q (2.0:4.5:6.5) (2.0:4.5:6.5)) (IOPATH CLRNeg Q (2.0:4.5:6.5) (2.0:4.5:6.5)) )) (TIMINGCHECK (SETUP J CLK (4.0)) (SETUP PRENeg CLK (4)) (HOLD J CLK (0.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.5)) (WIDTH (negedge CLK) (4.5)) (WIDTH (negedge PRENeg) (4.5)) (WIDTH (negedge CLRNeg) (4.5)) (PERIOD (posedge CLK) (11.7)) ) SN74F112DTexas Instruments SDFS048A-Revised October 1993 SN74F112NTexas Instruments SDFS048A-Revised October 1993 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (1.2:4.6:6.5) (1.2:4.6:6.5)) (IOPATH PRENeg Q (1.2:4.1:6.5) (1.2:4.1:6.5)) (IOPATH CLRNeg Q (1.2:4.1:6.5) (1.2:4.1:6.5)) )) (TIMINGCHECK (SETUP J CLK (4.0)) (SETUP PRENeg CLK (4)) (HOLD J CLK (0.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.5)) (WIDTH (negedge CLK) (4.5)) (WIDTH (negedge PRENeg) (4.5)) (WIDTH (negedge CLRNeg) (4.5)) (PERIOD (posedge CLK) (9.1)) )