version: | author: | mod date: | changes made: V1.0 R. Munden 98 SEP 01 Initial release 1ns STD109 74AC109MTCNational Semiconductor February 1993 74AC109PCNational Semiconductor February 1993 74AC109SCNational Semiconductor February 1993 74AC109SJNational Semiconductor February 1993 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (2.5:6.0:10.0) (2.0:6.0:10.0)) (IOPATH PRENeg Q (2.5:6.0:9.0) (2.0:6.5:9.5)) (IOPATH CLRNeg Q (2.5:6.0:9.0) (2.0:6.5:9.5)) )) (TIMINGCHECK (SETUP J CLK (4.5)) (SETUP PRENeg CLK (0)) (HOLD J CLK (0.5)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (3.0)) (WIDTH (negedge CLK) (3.0)) (WIDTH (negedge PRENeg) (4.5)) (WIDTH (negedge CLRNeg) (4.5)) (PERIOD (posedge CLK) (6.7)) ) MC74AC109DMotorola FACT Data DL138 Rev 3 MC74AC109NMotorola FACT Data DL138 Rev 3 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK Q (2.5:6.0:10.0) (2.0:6.0:10.0)) (IOPATH PRENeg Q (2.5:6.0:9.0) (2.0:6.5:9.5)) (IOPATH CLRNeg Q (2.5:6.0:9.0) (2.0:6.5:9.5)) )) (TIMINGCHECK (SETUP J CLK (4.5)) (SETUP PRENeg CLK (0)) (HOLD J CLK (0.5)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (3.5)) (WIDTH (negedge CLK) (3.5)) (WIDTH (negedge PRENeg) (3.5)) (WIDTH (negedge CLRNeg) (3.5)) (PERIOD (posedge CLK) (6.7)) ) MC74ACT109DMotorola FACT Data DL138 Rev 3 MC74ACT109NMotorola FACT Data DL138 Rev 3 74ACT109MTCNational Semiconductor February 1993 74ACT109PCNational Semiconductor February 1993 74ACT109SCNational Semiconductor February 1993 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (4.0:7.0:11.0) (3.0:6.0:11.0)) (IOPATH PRENeg Q (2.5:5.5:9.5) (2.5:6.0:10.0)) (IOPATH CLRNeg Q (2.5:5.5:9.5) (2.5:6.0:10.0)) )) (TIMINGCHECK (SETUP J CLK (2.0)) (SETUP PRENeg CLK (0)) (HOLD J CLK (2.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (5.0)) (WIDTH (negedge CLK) (5.0)) (WIDTH (negedge PRENeg) (5.0)) (WIDTH (negedge CLRNeg) (5.0)) (PERIOD (posedge CLK) (6.9)) ) 74F109PCNational Semiconductor November 1994 74F109SCNational Semiconductor November 1994 74F109SJNational Semiconductor November 1994 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (3.8:5.3:7.0) (4.4:6.2:8.0)) (IOPATH PRENeg Q (3.2:5.2:7.0) (3.5:7.0:9.0)) (IOPATH CLRNeg Q (3.2:5.2:7.0) (3.5:7.0:9.0)) )) (TIMINGCHECK (SETUP J CLK (3.0)) (SETUP PRENeg CLK (2)) (HOLD J CLK (1.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (5.0)) (WIDTH (negedge PRENeg) (4.0)) (WIDTH (negedge CLRNeg) (4.0)) (PERIOD (posedge CLK) (10.0)) ) MC74F109DMotorola Fast and LS TTL Data, DL121 REV 5 MC74F109NMotorola Fast and LS TTL Data, DL121 REV 5 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (3.8:5.3:7.0) (4.4:6.2:8.0)) (IOPATH PRENeg Q (2.5:5.2:7.0) (3.5:7.0:9.0)) (IOPATH CLRNeg Q (2.5:5.2:7.0) (3.5:7.0:9.0)) )) (TIMINGCHECK (SETUP J CLK (3.0)) (SETUP PRENeg CLK (2)) (HOLD J CLK (1.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (5.0)) (WIDTH (negedge PRENeg) (4.0)) (WIDTH (negedge CLRNeg) (4.0)) (PERIOD (posedge CLK) (10.0)) ) N74F109DPhilips Semiconductors Product Spec October 1990 N74F109NPhilips Semiconductors Product Spec October 1990 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (3.8:5.3:7.0) (4.4:6.2:8.0)) (IOPATH PRENeg Q (3.2:5.2:7.0) (3.5:7.0:9.0)) (IOPATH CLRNeg Q (3.2:5.2:7.0) (3.5:7.0:9.0)) )) (TIMINGCHECK (SETUP J CLK (3.0)) (SETUP PRENeg CLK (2)) (HOLD J CLK (1.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (5.0)) (WIDTH (negedge PRENeg) (4.0)) (WIDTH (negedge CLRNeg) (4.0)) (PERIOD (posedge CLK) (11.1)) ) SN74F109DTexas Instruments SDFS047A-Revised October 1993 SN74F109NTexas Instruments SDFS047A-Revised October 1993 The values listed are for VCC=5V, CL=50pF, Ta=+25 Celsius (DELAY (ABSOLUTE (IOPATH CLK Q (3.0:4.9:7.0) (3.6:5.8:8.0)) (IOPATH PRENeg Q (2.4:4.8:7.0) (2.7:6.6:9.0)) (IOPATH CLRNeg Q (2.4:4.8:7.0) (2.7:6.6:9.0)) )) (TIMINGCHECK (SETUP J CLK (3.0)) (SETUP PRENeg CLK (2)) (HOLD J CLK (1.0)) (HOLD PRENeg CLK (0)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (5.0)) (WIDTH (negedge PRENeg) (4.0)) (WIDTH (negedge CLRNeg) (4.0)) (PERIOD (posedge CLK) (6.7)) )