-------------------------------------------------------------------------------- -- File Name: mt55l128l36p.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1998-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 98 DEC 16 Initial release -- V1.1 R. Munden 08 AUG 14 Correct timing generic names -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: LVT -- Part: MT55L128L36P -- -- Description: 128k x 36 Pipelined ZBT SRAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.to_nat; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY mt55l128l36p IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17 : VitalDelayType01 := VitalZeroDelay01; tipd_IO18 : VitalDelayType01 := VitalZeroDelay01; tipd_IO19 : VitalDelayType01 := VitalZeroDelay01; tipd_IO20 : VitalDelayType01 := VitalZeroDelay01; tipd_IO21 : VitalDelayType01 := VitalZeroDelay01; tipd_IO22 : VitalDelayType01 := VitalZeroDelay01; tipd_IO23 : VitalDelayType01 := VitalZeroDelay01; tipd_IO24 : VitalDelayType01 := VitalZeroDelay01; tipd_IO25 : VitalDelayType01 := VitalZeroDelay01; tipd_IO26 : VitalDelayType01 := VitalZeroDelay01; tipd_IO27 : VitalDelayType01 := VitalZeroDelay01; tipd_IO28 : VitalDelayType01 := VitalZeroDelay01; tipd_IO29 : VitalDelayType01 := VitalZeroDelay01; tipd_IO30 : VitalDelayType01 := VitalZeroDelay01; tipd_IO31 : VitalDelayType01 := VitalZeroDelay01; tipd_IO32 : VitalDelayType01 := VitalZeroDelay01; tipd_IO33 : VitalDelayType01 := VitalZeroDelay01; tipd_IO34 : VitalDelayType01 := VitalZeroDelay01; tipd_IO35 : VitalDelayType01 := VitalZeroDelay01; tipd_ZZ : VitalDelayType01 := VitalZeroDelay01; tipd_ADV : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; tipd_CLKENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BW4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BW1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_BONeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK_IO0 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_CLKENNeg_CLK : VitalDelayType := UnitDelay; tsetup_A0_CLK : VitalDelayType := UnitDelay; tsetup_IO0_CLK : VitalDelayType := UnitDelay; tsetup_R_CLK : VitalDelayType := UnitDelay; tsetup_ADV_CLK : VitalDelayType := UnitDelay; tsetup_CE1Neg_CLK : VitalDelayType := UnitDelay; tsetup_BW1Neg_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_CLKENNeg_CLK : VitalDelayType := UnitDelay; thold_A0_CLK : VitalDelayType := UnitDelay; thold_IO0_CLK : VitalDelayType := UnitDelay; thold_R_CLK : VitalDelayType := UnitDelay; thold_ADV_CLK : VitalDelayType := UnitDelay; thold_CE1Neg_CLK : VitalDelayType := UnitDelay; thold_BW1Neg_CLK : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : IN std_logic := 'U'; A1 : IN std_logic := 'U'; A2 : IN std_logic := 'U'; A3 : IN std_logic := 'U'; A4 : IN std_logic := 'U'; A5 : IN std_logic := 'U'; A6 : IN std_logic := 'U'; A7 : IN std_logic := 'U'; A8 : IN std_logic := 'U'; A9 : IN std_logic := 'U'; A10 : IN std_logic := 'U'; A11 : IN std_logic := 'U'; A12 : IN std_logic := 'U'; A13 : IN std_logic := 'U'; A14 : IN std_logic := 'U'; A15 : IN std_logic := 'U'; A16 : IN std_logic := 'U'; ADV : IN std_logic := 'U'; R : IN std_logic := 'U'; CLKENNeg : IN std_logic := 'U'; BW4Neg : IN std_logic := 'U'; BW3Neg : IN std_logic := 'U'; BW2Neg : IN std_logic := 'U'; BW1Neg : IN std_logic := 'U'; CE1Neg : IN std_logic := 'U'; CE2Neg : IN std_logic := 'U'; CE2 : IN std_logic := 'U'; CLK : IN std_logic := 'U'; BONeg : IN std_logic := 'U'; OENeg : IN std_logic := 'U'; IO0 : INOUT std_logic := 'Z'; IO1 : INOUT std_logic := 'Z'; IO2 : INOUT std_logic := 'Z'; IO3 : INOUT std_logic := 'Z'; IO4 : INOUT std_logic := 'Z'; IO5 : INOUT std_logic := 'Z'; IO6 : INOUT std_logic := 'Z'; IO7 : INOUT std_logic := 'Z'; IO8 : INOUT std_logic := 'Z'; IO9 : INOUT std_logic := 'Z'; IO10 : INOUT std_logic := 'Z'; IO11 : INOUT std_logic := 'Z'; IO12 : INOUT std_logic := 'Z'; IO13 : INOUT std_logic := 'Z'; IO14 : INOUT std_logic := 'Z'; IO15 : INOUT std_logic := 'Z'; IO16 : INOUT std_logic := 'Z'; IO17 : INOUT std_logic := 'Z'; IO18 : INOUT std_logic := 'Z'; IO19 : INOUT std_logic := 'Z'; IO20 : INOUT std_logic := 'Z'; IO21 : INOUT std_logic := 'Z'; IO22 : INOUT std_logic := 'Z'; IO23 : INOUT std_logic := 'Z'; IO24 : INOUT std_logic := 'Z'; IO25 : INOUT std_logic := 'Z'; IO26 : INOUT std_logic := 'Z'; IO27 : INOUT std_logic := 'Z'; IO28 : INOUT std_logic := 'Z'; IO29 : INOUT std_logic := 'Z'; IO30 : INOUT std_logic := 'Z'; IO31 : INOUT std_logic := 'Z'; IO32 : INOUT std_logic := 'Z'; IO33 : INOUT std_logic := 'Z'; IO34 : INOUT std_logic := 'Z'; IO35 : INOUT std_logic := 'Z'; ZZ : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of mt55l128l36p : ENTITY IS TRUE; END mt55l128l36p; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of mt55l128l36p IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL A0_ipd : std_ulogic := 'X'; SIGNAL A1_ipd : std_ulogic := 'X'; SIGNAL A2_ipd : std_ulogic := 'X'; SIGNAL A3_ipd : std_ulogic := 'X'; SIGNAL A4_ipd : std_ulogic := 'X'; SIGNAL A5_ipd : std_ulogic := 'X'; SIGNAL A6_ipd : std_ulogic := 'X'; SIGNAL A7_ipd : std_ulogic := 'X'; SIGNAL A8_ipd : std_ulogic := 'X'; SIGNAL A9_ipd : std_ulogic := 'X'; SIGNAL A10_ipd : std_ulogic := 'X'; SIGNAL A11_ipd : std_ulogic := 'X'; SIGNAL A12_ipd : std_ulogic := 'X'; SIGNAL A13_ipd : std_ulogic := 'X'; SIGNAL A14_ipd : std_ulogic := 'X'; SIGNAL A15_ipd : std_ulogic := 'X'; SIGNAL A16_ipd : std_ulogic := 'X'; SIGNAL IO0_ipd : std_ulogic := 'X'; SIGNAL IO1_ipd : std_ulogic := 'X'; SIGNAL IO2_ipd : std_ulogic := 'X'; SIGNAL IO3_ipd : std_ulogic := 'X'; SIGNAL IO4_ipd : std_ulogic := 'X'; SIGNAL IO5_ipd : std_ulogic := 'X'; SIGNAL IO6_ipd : std_ulogic := 'X'; SIGNAL IO7_ipd : std_ulogic := 'X'; SIGNAL IO8_ipd : std_ulogic := 'X'; SIGNAL IO9_ipd : std_ulogic := 'X'; SIGNAL IO10_ipd : std_ulogic := 'X'; SIGNAL IO11_ipd : std_ulogic := 'X'; SIGNAL IO12_ipd : std_ulogic := 'X'; SIGNAL IO13_ipd : std_ulogic := 'X'; SIGNAL IO14_ipd : std_ulogic := 'X'; SIGNAL IO15_ipd : std_ulogic := 'X'; SIGNAL IO16_ipd : std_ulogic := 'X'; SIGNAL IO17_ipd : std_ulogic := 'X'; SIGNAL IO18_ipd : std_ulogic := 'X'; SIGNAL IO19_ipd : std_ulogic := 'X'; SIGNAL IO20_ipd : std_ulogic := 'X'; SIGNAL IO21_ipd : std_ulogic := 'X'; SIGNAL IO22_ipd : std_ulogic := 'X'; SIGNAL IO23_ipd : std_ulogic := 'X'; SIGNAL IO24_ipd : std_ulogic := 'X'; SIGNAL IO25_ipd : std_ulogic := 'X'; SIGNAL IO26_ipd : std_ulogic := 'X'; SIGNAL IO27_ipd : std_ulogic := 'X'; SIGNAL IO28_ipd : std_ulogic := 'X'; SIGNAL IO29_ipd : std_ulogic := 'X'; SIGNAL IO30_ipd : std_ulogic := 'X'; SIGNAL IO31_ipd : std_ulogic := 'X'; SIGNAL IO32_ipd : std_ulogic := 'X'; SIGNAL IO33_ipd : std_ulogic := 'X'; SIGNAL IO34_ipd : std_ulogic := 'X'; SIGNAL IO35_ipd : std_ulogic := 'X'; SIGNAL ADV_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL CLKENNeg_ipd : std_ulogic := 'X'; SIGNAL BW4Neg_ipd : std_ulogic := 'X'; SIGNAL BW3Neg_ipd : std_ulogic := 'X'; SIGNAL BW2Neg_ipd : std_ulogic := 'X'; SIGNAL BW1Neg_ipd : std_ulogic := 'X'; SIGNAL CE1Neg_ipd : std_ulogic := 'X'; SIGNAL CE2Neg_ipd : std_ulogic := 'X'; SIGNAL CE2_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL BONeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL ZZ_ipd : std_ulogic := 'X'; SIGNAL ADV_nwv : std_ulogic := 'X'; SIGNAL BONeg_nwv : std_ulogic := 'X'; SIGNAL addr_in, addr_out : STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => '0'); SIGNAL ce, doe : std_ulogic := 'X'; SIGNAL bwa_in, bwb_in, bwc_in, bwd_in, ce_in, rw_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := "XX"; SIGNAL bcount : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'X'); SIGNAL addr_nat : NATURAL := 0; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_2 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_3 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_4 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_5 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_6 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_7 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_8 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_9 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_11 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_13 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_14 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_15 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_16 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_17 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_20 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0); w_21 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1); w_22 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2); w_23 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3); w_24 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4); w_25 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5); w_26 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6); w_27 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7); w_28 : VitalWireDelay (IO8_ipd, IO8, tipd_IO8); w_29 : VitalWireDelay (IO9_ipd, IO9, tipd_IO9); w_30 : VitalWireDelay (IO10_ipd, IO10, tipd_IO10); w_31 : VitalWireDelay (IO11_ipd, IO11, tipd_IO11); w_32 : VitalWireDelay (IO12_ipd, IO12, tipd_IO12); w_33 : VitalWireDelay (IO13_ipd, IO13, tipd_IO13); w_34 : VitalWireDelay (IO14_ipd, IO14, tipd_IO14); w_35 : VitalWireDelay (IO15_ipd, IO15, tipd_IO15); w_36 : VitalWireDelay (IO16_ipd, IO16, tipd_IO16); w_37 : VitalWireDelay (IO17_ipd, IO17, tipd_IO17); w_38 : VitalWireDelay (IO18_ipd, IO18, tipd_IO18); w_39 : VitalWireDelay (IO19_ipd, IO19, tipd_IO19); w_40 : VitalWireDelay (IO20_ipd, IO20, tipd_IO20); w_41 : VitalWireDelay (IO21_ipd, IO21, tipd_IO21); w_42 : VitalWireDelay (IO22_ipd, IO22, tipd_IO22); w_43 : VitalWireDelay (IO23_ipd, IO23, tipd_IO23); w_44 : VitalWireDelay (IO24_ipd, IO24, tipd_IO24); w_45 : VitalWireDelay (IO25_ipd, IO25, tipd_IO25); w_46 : VitalWireDelay (IO26_ipd, IO26, tipd_IO26); w_47 : VitalWireDelay (IO27_ipd, IO27, tipd_IO27); w_48 : VitalWireDelay (IO28_ipd, IO28, tipd_IO28); w_49 : VitalWireDelay (IO29_ipd, IO29, tipd_IO29); w_50 : VitalWireDelay (IO30_ipd, IO30, tipd_IO30); w_51 : VitalWireDelay (IO31_ipd, IO31, tipd_IO31); w_52 : VitalWireDelay (IO32_ipd, IO32, tipd_IO32); w_53 : VitalWireDelay (IO33_ipd, IO33, tipd_IO33); w_54 : VitalWireDelay (IO34_ipd, IO34, tipd_IO34); w_55 : VitalWireDelay (IO35_ipd, IO35, tipd_IO35); w_56 : VitalWireDelay (ADV_ipd, ADV, tipd_ADV); w_57 : VitalWireDelay (R_ipd, R, tipd_R); w_58 : VitalWireDelay (CLKENNeg_ipd, CLKENNeg, tipd_CLKENNeg); w_59 : VitalWireDelay (BW4Neg_ipd, BW4Neg, tipd_BW4Neg); w_60 : VitalWireDelay (BW3Neg_ipd, BW3Neg, tipd_BW3Neg); w_70 : VitalWireDelay (BW2Neg_ipd, BW2Neg, tipd_BW2Neg); w_71 : VitalWireDelay (BW1Neg_ipd, BW1Neg, tipd_BW1Neg); w_72 : VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg); w_73 : VitalWireDelay (CE2Neg_ipd, CE2Neg, tipd_CE2Neg); w_74 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2); w_75 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_76 : VitalWireDelay (BONeg_ipd, BONeg, tipd_BONeg); w_77 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_78 : VitalWireDelay (ZZ_ipd, ZZ, tipd_ZZ); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- ce <= NOT(CE1Neg_ipd) AND NOT(CE2Neg_ipd) AND CE2_ipd; doe <= ce_in(0) AND NOT(rw_in(0)) AND NOT(OENeg_ipd); addr_nat <= To_nat(addr_out); ADV_nwv <= To_X01(ADV_ipd); BONeg_nwv <= To_X01(BONeg_ipd); ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLK_ipd, R_ipd, ADV_ipd, CLKENNeg_ipd, CE1Neg_ipd, CE2Neg_ipd, CE2_ipd, BW1Neg_ipd, BW2Neg_ipd, BW3Neg_ipd, BW4Neg_ipd, A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd, OENeg_ipd, IO35_ipd, IO34_ipd, IO33_ipd, IO32_ipd, IO31_ipd, IO30_ipd, IO29_ipd, IO28_ipd, IO27_ipd, IO26_ipd, IO25_ipd, IO24_ipd, IO23_ipd, IO22_ipd, IO21_ipd, IO20_ipd, IO19_ipd, IO18_ipd, IO17_ipd, IO16_ipd, IO15_ipd, IO14_ipd, IO13_ipd, IO12_ipd, IO11_ipd, IO10_ipd, IO9_ipd, IO8_ipd, IO7_ipd, IO6_ipd, IO5_ipd, IO4_ipd, IO3_ipd, IO2_ipd, IO1_ipd, IO0_ipd) TYPE mem_array IS ARRAY ((2 ** 19) - 1 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0); VARIABLE ram0 : mem_array; VARIABLE ram1 : mem_array; VARIABLE ram2 : mem_array; VARIABLE ram3 : mem_array; CONSTANT HiZ : STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE btemp : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => 'X'); VARIABLE addr : STD_LOGIC_VECTOR (16 DOWNTO 0) := (OTHERS => 'X'); VARIABLE Dq : STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => 'X'); -- Timing Check Variables VARIABLE Tviol_IO0_CLK : X01 := '0'; VARIABLE TD_IO0_CLK : VitalTimingDataType; VARIABLE Tviol_IO1_CLK : X01 := '0'; VARIABLE TD_IO1_CLK : VitalTimingDataType; VARIABLE Tviol_IO2_CLK : X01 := '0'; VARIABLE TD_IO2_CLK : VitalTimingDataType; VARIABLE Tviol_IO3_CLK : X01 := '0'; VARIABLE TD_IO3_CLK : VitalTimingDataType; VARIABLE Tviol_IO4_CLK : X01 := '0'; VARIABLE TD_IO4_CLK : VitalTimingDataType; VARIABLE Tviol_IO5_CLK : X01 := '0'; VARIABLE TD_IO5_CLK : VitalTimingDataType; VARIABLE Tviol_IO6_CLK : X01 := '0'; VARIABLE TD_IO6_CLK : VitalTimingDataType; VARIABLE Tviol_IO7_CLK : X01 := '0'; VARIABLE TD_IO7_CLK : VitalTimingDataType; VARIABLE Tviol_IO8_CLK : X01 := '0'; VARIABLE TD_IO8_CLK : VitalTimingDataType; VARIABLE Tviol_IO9_CLK : X01 := '0'; VARIABLE TD_IO9_CLK : VitalTimingDataType; VARIABLE Tviol_IO10_CLK : X01 := '0'; VARIABLE TD_IO10_CLK : VitalTimingDataType; VARIABLE Tviol_IO11_CLK : X01 := '0'; VARIABLE TD_IO11_CLK : VitalTimingDataType; VARIABLE Tviol_IO12_CLK : X01 := '0'; VARIABLE TD_IO12_CLK : VitalTimingDataType; VARIABLE Tviol_IO13_CLK : X01 := '0'; VARIABLE TD_IO13_CLK : VitalTimingDataType; VARIABLE Tviol_IO14_CLK : X01 := '0'; VARIABLE TD_IO14_CLK : VitalTimingDataType; VARIABLE Tviol_IO15_CLK : X01 := '0'; VARIABLE TD_IO15_CLK : VitalTimingDataType; VARIABLE Tviol_IO16_CLK : X01 := '0'; VARIABLE TD_IO16_CLK : VitalTimingDataType; VARIABLE Tviol_IO17_CLK : X01 := '0'; VARIABLE TD_IO17_CLK : VitalTimingDataType; VARIABLE Tviol_IO18_CLK : X01 := '0'; VARIABLE TD_IO18_CLK : VitalTimingDataType; VARIABLE Tviol_IO19_CLK : X01 := '0'; VARIABLE TD_IO19_CLK : VitalTimingDataType; VARIABLE Tviol_IO20_CLK : X01 := '0'; VARIABLE TD_IO20_CLK : VitalTimingDataType; VARIABLE Tviol_IO21_CLK : X01 := '0'; VARIABLE TD_IO21_CLK : VitalTimingDataType; VARIABLE Tviol_IO22_CLK : X01 := '0'; VARIABLE TD_IO22_CLK : VitalTimingDataType; VARIABLE Tviol_IO23_CLK : X01 := '0'; VARIABLE TD_IO23_CLK : VitalTimingDataType; VARIABLE Tviol_IO24_CLK : X01 := '0'; VARIABLE TD_IO24_CLK : VitalTimingDataType; VARIABLE Tviol_IO25_CLK : X01 := '0'; VARIABLE TD_IO25_CLK : VitalTimingDataType; VARIABLE Tviol_IO26_CLK : X01 := '0'; VARIABLE TD_IO26_CLK : VitalTimingDataType; VARIABLE Tviol_IO27_CLK : X01 := '0'; VARIABLE TD_IO27_CLK : VitalTimingDataType; VARIABLE Tviol_IO28_CLK : X01 := '0'; VARIABLE TD_IO28_CLK : VitalTimingDataType; VARIABLE Tviol_IO29_CLK : X01 := '0'; VARIABLE TD_IO29_CLK : VitalTimingDataType; VARIABLE Tviol_IO30_CLK : X01 := '0'; VARIABLE TD_IO30_CLK : VitalTimingDataType; VARIABLE Tviol_IO31_CLK : X01 := '0'; VARIABLE TD_IO31_CLK : VitalTimingDataType; VARIABLE Tviol_IO32_CLK : X01 := '0'; VARIABLE TD_IO32_CLK : VitalTimingDataType; VARIABLE Tviol_IO33_CLK : X01 := '0'; VARIABLE TD_IO33_CLK : VitalTimingDataType; VARIABLE Tviol_IO34_CLK : X01 := '0'; VARIABLE TD_IO34_CLK : VitalTimingDataType; VARIABLE Tviol_IO35_CLK : X01 := '0'; VARIABLE TD_IO35_CLK : VitalTimingDataType; VARIABLE Tviol_A0_CLK : X01 := '0'; VARIABLE TD_A0_CLK : VitalTimingDataType; VARIABLE Tviol_A1_CLK : X01 := '0'; VARIABLE TD_A1_CLK : VitalTimingDataType; VARIABLE Tviol_A2_CLK : X01 := '0'; VARIABLE TD_A2_CLK : VitalTimingDataType; VARIABLE Tviol_A3_CLK : X01 := '0'; VARIABLE TD_A3_CLK : VitalTimingDataType; VARIABLE Tviol_A4_CLK : X01 := '0'; VARIABLE TD_A4_CLK : VitalTimingDataType; VARIABLE Tviol_A5_CLK : X01 := '0'; VARIABLE TD_A5_CLK : VitalTimingDataType; VARIABLE Tviol_A6_CLK : X01 := '0'; VARIABLE TD_A6_CLK : VitalTimingDataType; VARIABLE Tviol_A7_CLK : X01 := '0'; VARIABLE TD_A7_CLK : VitalTimingDataType; VARIABLE Tviol_A8_CLK : X01 := '0'; VARIABLE TD_A8_CLK : VitalTimingDataType; VARIABLE Tviol_A9_CLK : X01 := '0'; VARIABLE TD_A9_CLK : VitalTimingDataType; VARIABLE Tviol_A10_CLK : X01 := '0'; VARIABLE TD_A10_CLK : VitalTimingDataType; VARIABLE Tviol_A11_CLK : X01 := '0'; VARIABLE TD_A11_CLK : VitalTimingDataType; VARIABLE Tviol_A12_CLK : X01 := '0'; VARIABLE TD_A12_CLK : VitalTimingDataType; VARIABLE Tviol_A13_CLK : X01 := '0'; VARIABLE TD_A13_CLK : VitalTimingDataType; VARIABLE Tviol_A14_CLK : X01 := '0'; VARIABLE TD_A14_CLK : VitalTimingDataType; VARIABLE Tviol_A15_CLK : X01 := '0'; VARIABLE TD_A15_CLK : VitalTimingDataType; VARIABLE Tviol_A16_CLK : X01 := '0'; VARIABLE TD_A16_CLK : VitalTimingDataType; VARIABLE Tviol_CLKEN_CLK : X01 := '0'; VARIABLE TD_CLKEN_CLK : VitalTimingDataType; VARIABLE Tviol_R_CLK : X01 := '0'; VARIABLE TD_R_CLK : VitalTimingDataType; VARIABLE Tviol_ADV_CLK : X01 := '0'; VARIABLE TD_ADV_CLK : VitalTimingDataType; VARIABLE Tviol_CE1_CLK : X01 := '0'; VARIABLE TD_CE1_CLK : VitalTimingDataType; VARIABLE Tviol_CE2_CLK : X01 := '0'; VARIABLE TD_CE2_CLK : VitalTimingDataType; VARIABLE Tviol_CE2Neg_CLK : X01 := '0'; VARIABLE TD_CE2Neg_CLK : VitalTimingDataType; VARIABLE Tviol_BW1_CLK : X01 := '0'; VARIABLE TD_BW1_CLK : VitalTimingDataType; VARIABLE Tviol_BW2_CLK : X01 := '0'; VARIABLE TD_BW2_CLK : VitalTimingDataType; VARIABLE Tviol_BW3_CLK : X01 := '0'; VARIABLE TD_BW3_CLK : VitalTimingDataType; VARIABLE Tviol_BW4_CLK : X01 := '0'; VARIABLE TD_BW4_CLK : VitalTimingDataType; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLK : X01 := '0'; -- Functionality Results Variables VARIABLE IO_zd : std_logic_vector(35 downto 0) := (others => 'X'); VARIABLE Violation : X01 := '0'; -- Output Glitch Detection Variables VARIABLE IO_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => CLKENNeg_ipd, TestSignalName => "CLKENNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CLKENNeg_CLK, SetupLow => tsetup_CLKENNeg_CLK, HoldHigh => thold_CLKENNeg_CLK, HoldLow => thold_CLKENNeg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_CLKEN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CLKEN_CLK); VitalSetupHoldCheck ( TestSignal => A0_ipd, TestSignalName => "A0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A0_CLK); VitalSetupHoldCheck ( TestSignal => A1_ipd, TestSignalName => "A1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A1_CLK); VitalSetupHoldCheck ( TestSignal => A2_ipd, TestSignalName => "A2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A2_CLK); VitalSetupHoldCheck ( TestSignal => A3_ipd, TestSignalName => "A3_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A3_CLK); VitalSetupHoldCheck ( TestSignal => A4_ipd, TestSignalName => "A4_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A4_CLK); VitalSetupHoldCheck ( TestSignal => A5_ipd, TestSignalName => "A5_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A5_CLK); VitalSetupHoldCheck ( TestSignal => A6_ipd, TestSignalName => "A6_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A6_CLK); VitalSetupHoldCheck ( TestSignal => A7_ipd, TestSignalName => "A7_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A7_CLK); VitalSetupHoldCheck ( TestSignal => A8_ipd, TestSignalName => "A8_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A8_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A8_CLK); VitalSetupHoldCheck ( TestSignal => A9_ipd, TestSignalName => "A9_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A9_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A9_CLK); VitalSetupHoldCheck ( TestSignal => A10_ipd, TestSignalName => "A10_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A10_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A10_CLK); VitalSetupHoldCheck ( TestSignal => A11_ipd, TestSignalName => "A11_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A11_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A11_CLK); VitalSetupHoldCheck ( TestSignal => A12_ipd, TestSignalName => "A12_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A12_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A12_CLK); VitalSetupHoldCheck ( TestSignal => A13_ipd, TestSignalName => "A13_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A13_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A13_CLK); VitalSetupHoldCheck ( TestSignal => A14_ipd, TestSignalName => "A14_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A14_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A14_CLK); VitalSetupHoldCheck ( TestSignal => A15_ipd, TestSignalName => "A15_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A15_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A15_CLK); VitalSetupHoldCheck ( TestSignal => A16_ipd, TestSignalName => "A16_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_A16_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A16_CLK); VitalSetupHoldCheck ( TestSignal => IO0_ipd, TestSignalName => "IO0_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO0_CLK); VitalSetupHoldCheck ( TestSignal => IO1_ipd, TestSignalName => "IO1_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO1_CLK); VitalSetupHoldCheck ( TestSignal => IO2_ipd, TestSignalName => "IO2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO2_CLK); VitalSetupHoldCheck ( TestSignal => IO3_ipd, TestSignalName => "IO3_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO3_CLK); VitalSetupHoldCheck ( TestSignal => IO4_ipd, TestSignalName => "IO4_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO4_CLK); VitalSetupHoldCheck ( TestSignal => IO5_ipd, TestSignalName => "IO5_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO5_CLK); VitalSetupHoldCheck ( TestSignal => IO6_ipd, TestSignalName => "IO6_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO6_CLK); VitalSetupHoldCheck ( TestSignal => IO7_ipd, TestSignalName => "IO7_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO7_CLK); VitalSetupHoldCheck ( TestSignal => IO8_ipd, TestSignalName => "IO8_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO8_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO8_CLK); VitalSetupHoldCheck ( TestSignal => IO9_ipd, TestSignalName => "IO9_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO9_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO9_CLK); VitalSetupHoldCheck ( TestSignal => IO10_ipd, TestSignalName => "IO10_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO10_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO10_CLK); VitalSetupHoldCheck ( TestSignal => IO11_ipd, TestSignalName => "IO11_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO11_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO11_CLK); VitalSetupHoldCheck ( TestSignal => IO12_ipd, TestSignalName => "IO12_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO12_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO12_CLK); VitalSetupHoldCheck ( TestSignal => IO13_ipd, TestSignalName => "IO13_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO13_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO13_CLK); VitalSetupHoldCheck ( TestSignal => IO14_ipd, TestSignalName => "IO14_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO14_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO14_CLK); VitalSetupHoldCheck ( TestSignal => IO15_ipd, TestSignalName => "IO15_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO15_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO15_CLK); VitalSetupHoldCheck ( TestSignal => IO16_ipd, TestSignalName => "IO16_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO16_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO16_CLK); VitalSetupHoldCheck ( TestSignal => IO17_ipd, TestSignalName => "IO17_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO17_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO17_CLK); VitalSetupHoldCheck ( TestSignal => IO18_ipd, TestSignalName => "IO18_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO18_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO18_CLK); VitalSetupHoldCheck ( TestSignal => IO19_ipd, TestSignalName => "IO19_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO19_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO19_CLK); VitalSetupHoldCheck ( TestSignal => IO20_ipd, TestSignalName => "IO20_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO20_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO20_CLK); VitalSetupHoldCheck ( TestSignal => IO21_ipd, TestSignalName => "IO21_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO21_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO21_CLK); VitalSetupHoldCheck ( TestSignal => IO22_ipd, TestSignalName => "IO22_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO22_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO22_CLK); VitalSetupHoldCheck ( TestSignal => IO23_ipd, TestSignalName => "IO23_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO23_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO23_CLK); VitalSetupHoldCheck ( TestSignal => IO24_ipd, TestSignalName => "IO24_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO24_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO24_CLK); VitalSetupHoldCheck ( TestSignal => IO25_ipd, TestSignalName => "IO25_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO25_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO25_CLK); VitalSetupHoldCheck ( TestSignal => IO26_ipd, TestSignalName => "IO26_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO26_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO26_CLK); VitalSetupHoldCheck ( TestSignal => IO27_ipd, TestSignalName => "IO27_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO27_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO27_CLK); VitalSetupHoldCheck ( TestSignal => IO28_ipd, TestSignalName => "IO28_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO28_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO28_CLK); VitalSetupHoldCheck ( TestSignal => IO29_ipd, TestSignalName => "IO29_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO29_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO29_CLK); VitalSetupHoldCheck ( TestSignal => IO30_ipd, TestSignalName => "IO30_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO30_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO30_CLK); VitalSetupHoldCheck ( TestSignal => IO31_ipd, TestSignalName => "IO31_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO31_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO31_CLK); VitalSetupHoldCheck ( TestSignal => IO32_ipd, TestSignalName => "IO32_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO32_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO32_CLK); VitalSetupHoldCheck ( TestSignal => IO33_ipd, TestSignalName => "IO33_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO33_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO33_CLK); VitalSetupHoldCheck ( TestSignal => IO34_ipd, TestSignalName => "IO34_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO34_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO34_CLK); VitalSetupHoldCheck ( TestSignal => IO35_ipd, TestSignalName => "IO35_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_IO0_CLK, SetupLow => tsetup_IO0_CLK, HoldHigh => thold_IO0_CLK, HoldLow => thold_IO0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_IO35_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IO35_CLK); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/mt55l128l36p", CheckEnabled => TRUE ); VitalSetupHoldCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_R_CLK, SetupLow => tsetup_R_CLK, HoldHigh => thold_R_CLK, HoldLow => thold_R_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_R_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_R_CLK); VitalSetupHoldCheck ( TestSignal => ADV_ipd, TestSignalName => "ADV_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_ADV_CLK, SetupLow => tsetup_ADV_CLK, HoldHigh => thold_ADV_CLK, HoldLow => thold_ADV_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_ADV_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADV_CLK); VitalSetupHoldCheck ( TestSignal => CE1Neg_ipd, TestSignalName => "CE1Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CE1Neg_CLK, SetupLow => tsetup_CE1Neg_CLK, HoldHigh => thold_CE1Neg_CLK, HoldLow => thold_CE1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_CE1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1_CLK); VitalSetupHoldCheck ( TestSignal => CE2Neg_ipd, TestSignalName => "CE2Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CE1Neg_CLK, SetupLow => tsetup_CE1Neg_CLK, HoldHigh => thold_CE1Neg_CLK, HoldLow => thold_CE1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_CE2Neg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE2Neg_CLK); VitalSetupHoldCheck ( TestSignal => CE2_ipd, TestSignalName => "CE2_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_CE1Neg_CLK, SetupLow => tsetup_CE1Neg_CLK, HoldHigh => thold_CE1Neg_CLK, HoldLow => thold_CE1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_CE2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE2_CLK); VitalSetupHoldCheck ( TestSignal => BW1Neg_ipd, TestSignalName => "BW1Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_BW1Neg_CLK, SetupLow => tsetup_BW1Neg_CLK, HoldHigh => thold_BW1Neg_CLK, HoldLow => thold_BW1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_BW1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BW1_CLK); VitalSetupHoldCheck ( TestSignal => BW2Neg_ipd, TestSignalName => "BW2Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_BW1Neg_CLK, SetupLow => tsetup_BW1Neg_CLK, HoldHigh => thold_BW1Neg_CLK, HoldLow => thold_BW1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_BW2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BW2_CLK); VitalSetupHoldCheck ( TestSignal => BW3Neg_ipd, TestSignalName => "BW3Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_BW1Neg_CLK, SetupLow => tsetup_BW1Neg_CLK, HoldHigh => thold_BW1Neg_CLK, HoldLow => thold_BW1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_BW3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BW3_CLK); VitalSetupHoldCheck ( TestSignal => BW4Neg_ipd, TestSignalName => "BW4Neg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_BW1Neg_CLK, SetupLow => tsetup_BW1Neg_CLK, HoldHigh => thold_BW1Neg_CLK, HoldLow => thold_BW1Neg_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/mt55l128l36p", TimingData => TD_BW4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BW4_CLK); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/mt55l128l36p", CheckEnabled => TRUE ); Violation := Pviol_CLK OR Tviol_BW4_CLK OR Tviol_BW3_CLK OR Tviol_BW2_CLK OR Tviol_BW1_CLK OR Tviol_IO0_CLK OR Tviol_IO1_CLK OR Tviol_IO2_CLK OR Tviol_IO3_CLK OR Tviol_IO4_CLK OR Tviol_IO5_CLK OR Tviol_IO6_CLK OR Tviol_IO7_CLK OR Tviol_IO8_CLK OR Tviol_IO9_CLK OR Tviol_IO10_CLK OR Tviol_IO11_CLK OR Tviol_IO12_CLK OR Tviol_IO13_CLK OR Tviol_IO14_CLK OR Tviol_IO15_CLK OR Tviol_IO16_CLK OR Tviol_IO17_CLK OR Tviol_IO18_CLK OR Tviol_IO19_CLK OR Tviol_IO20_CLK OR Tviol_IO21_CLK OR Tviol_IO22_CLK OR Tviol_IO23_CLK OR Tviol_IO24_CLK OR Tviol_IO25_CLK OR Tviol_IO26_CLK OR Tviol_IO27_CLK OR Tviol_IO28_CLK OR Tviol_IO29_CLK OR Tviol_IO30_CLK OR Tviol_IO31_CLK OR Tviol_IO32_CLK OR Tviol_IO33_CLK OR Tviol_IO34_CLK OR Tviol_IO35_CLK OR Tviol_A0_CLK OR Tviol_A1_CLK OR Tviol_A2_CLK OR Tviol_A3_CLK OR Tviol_A4_CLK OR Tviol_A5_CLK OR Tviol_A6_CLK OR Tviol_A7_CLK OR Tviol_A8_CLK OR Tviol_A9_CLK OR Tviol_A10_CLK OR Tviol_A11_CLK OR Tviol_A12_CLK OR Tviol_A13_CLK OR Tviol_A14_CLK OR Tviol_A15_CLK OR Tviol_A16_CLK OR Tviol_CLKEN_CLK OR Tviol_R_CLK OR Tviol_ADV_CLK OR Tviol_CE1_CLK OR Tviol_CE2_CLK OR Tviol_CE2Neg_CLK; ASSERT Violation = '0' REPORT InstancePath & ": simulation may be" & " inaccurate due to timing violations" SEVERITY Error; END IF; -- Timing Check Section ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ addr := (A16_ipd, A15_ipd, A14_ipd, A13_ipd, A12_ipd, A11_ipd, A10_ipd, A9_ipd, A8_ipd, A7_ipd, A6_ipd, A5_ipd, A4_ipd, A3_ipd, A2_ipd, A1_ipd, A0_ipd); Dq := (IO35_ipd, IO34_ipd, IO33_ipd, IO32_ipd, IO31_ipd, IO30_ipd, IO29_ipd, IO28_ipd, IO27_ipd, IO26_ipd, IO25_ipd, IO24_ipd, IO23_ipd, IO22_ipd, IO21_ipd, IO20_ipd, IO19_ipd, IO18_ipd, IO17_ipd, IO16_ipd, IO15_ipd, IO14_ipd, IO13_ipd, IO12_ipd, IO11_ipd, IO10_ipd, IO9_ipd, IO8_ipd, IO7_ipd, IO6_ipd, IO5_ipd, IO4_ipd, IO3_ipd, IO2_ipd, IO1_ipd, IO0_ipd); IF rising_edge(CLK_ipd) AND (To_X01(ZZ_ipd) = '0') THEN -- Write Registry and Data Coherency Control Logic bwa_in(1) <= To_X01(BW1Neg_ipd); bwb_in(1) <= To_X01(BW2Neg_ipd); bwc_in(1) <= To_X01(BW3Neg_ipd); bwd_in(1) <= To_X01(BW4Neg_ipd); bwa_in(0) <= bwa_in(1); bwb_in(0) <= bwb_in(1); bwc_in(0) <= bwc_in(1); bwd_in(0) <= bwd_in(1); -- Read Logic IF ADV_nwv = '0' THEN ce_in(1) <= ce; rw_in(1) <= ce AND NOT(R_ipd); END IF; ce_in(0) <= ce_in(1); rw_in(0) <= rw_in(1); -- Capture Address Register IF ADV_nwv = '0' and ce = '1' THEN addr_in <= Addr; END IF; addr_out(16 DOWNTO 2) <= addr_in(16 DOWNTO 2); addr_out(1) <= bcount(1); addr_out(0) <= bcount(0); -- Burst Logic Decode IF BONeg_nwv = '1' AND ADV_nwv = '0' THEN bcount (1 DOWNTO 0) <= Addr (1 DOWNTO 0); btemp := "00"; ELSIF BONeg_nwv = '0' AND ADV_nwv ='0' THEN bcount (1 DOWNTO 0) <= Addr (1 DOWNTO 0); ELSIF BONeg_nwv = '1' AND ADV_nwv = '1' THEN btemp(1) := btemp(0) XOR btemp(1); btemp(0) := NOT(btemp(0)); bcount(0) <= btemp(0) XOR addr_in(0); bcount(1) <= btemp(1) XOR addr_in(1); ELSIF BONeg_nwv = '0' AND ADV_nwv = '1' THEN bcount(0) <= NOT(bcount(0)); bcount(1) <= bcount(0) XOR bcount(1); END IF; -- Write Data to Memory IF rw_in(0) = '1' AND bwa_in(0) = '0' THEN ram0(addr_nat) := Dq (8 DOWNTO 0); END IF; IF rw_in(0) = '1' AND bwb_in(0) = '0' THEN ram1(addr_nat) := Dq (17 DOWNTO 9); END IF; IF rw_in(0) = '1' AND bwc_in(0) = '0' THEN ram2(addr_nat) := Dq (26 DOWNTO 18); END IF; IF rw_in(0) = '1' AND bwd_in(0) = '0' THEN ram3(addr_nat) := Dq (35 DOWNTO 27); END IF; --END IF; END IF; -- Read Data from Memory IF doe = '1' THEN IO_zd ( 8 DOWNTO 0) := ram0(addr_nat); IO_zd (17 DOWNTO 9) := ram1(addr_nat); IO_zd (26 DOWNTO 18) := ram2(addr_nat); IO_zd (35 DOWNTO 27) := ram3(addr_nat); ELSE IO_zd := HiZ; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01Z ( OutSignal => IO0, OutSignalName => "IO0", OutTemp => IO_zd(0), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO1, OutSignalName => "IO1", OutTemp => IO_zd(1), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO2, OutSignalName => "IO2", OutTemp => IO_zd(2), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO3, OutSignalName => "IO3", OutTemp => IO_zd(3), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO4, OutSignalName => "IO4", OutTemp => IO_zd(4), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO5, OutSignalName => "IO5", OutTemp => IO_zd(5), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO6, OutSignalName => "IO6", OutTemp => IO_zd(6), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO7, OutSignalName => "IO7", OutTemp => IO_zd(7), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO8, OutSignalName => "IO8", OutTemp => IO_zd(8), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO9, OutSignalName => "IO9", OutTemp => IO_zd(9), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO10, OutSignalName => "IO10", OutTemp => IO_zd(10), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO11, OutSignalName => "IO11", OutTemp => IO_zd(11), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO12, OutSignalName => "IO12", OutTemp => IO_zd(12), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO13, OutSignalName => "IO13", OutTemp => IO_zd(13), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO14, OutSignalName => "IO14", OutTemp => IO_zd(14), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO15, OutSignalName => "IO15", OutTemp => IO_zd(15), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO16, OutSignalName => "IO16", OutTemp => IO_zd(16), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO17, OutSignalName => "IO17", OutTemp => IO_zd(17), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO18, OutSignalName => "IO18", OutTemp => IO_zd(18), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO19, OutSignalName => "IO19", OutTemp => IO_zd(19), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO20, OutSignalName => "IO20", OutTemp => IO_zd(20), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO21, OutSignalName => "IO21", OutTemp => IO_zd(21), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO22, OutSignalName => "IO22", OutTemp => IO_zd(22), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO23, OutSignalName => "IO23", OutTemp => IO_zd(23), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO24, OutSignalName => "IO24", OutTemp => IO_zd(24), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO25, OutSignalName => "IO25", OutTemp => IO_zd(25), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO26, OutSignalName => "IO26", OutTemp => IO_zd(26), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO27, OutSignalName => "IO27", OutTemp => IO_zd(27), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO28, OutSignalName => "IO28", OutTemp => IO_zd(28), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO29, OutSignalName => "IO29", OutTemp => IO_zd(29), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO30, OutSignalName => "IO30", OutTemp => IO_zd(30), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO31, OutSignalName => "IO31", OutTemp => IO_zd(31), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO32, OutSignalName => "IO32", OutTemp => IO_zd(32), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO33, OutSignalName => "IO33", OutTemp => IO_zd(33), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO34, OutSignalName => "IO34", OutTemp => IO_zd(34), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IO35, OutSignalName => "IO35", OutTemp => IO_zd(35), GlitchData => IO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK'LAST_EVENT, PathDelay => tpd_CLK_IO0, PathCondition => TRUE), 1 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE) ) ); END PROCESS VitalBehavior; END vhdl_behavioral;