-------------------------------------------------------------------------------- -- File Name: mt4lc4m16r6.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1999-2003 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 99 AUG 23 Initial release -- V1.1 R. Munden 00 FEB 07 Changed type of cas to UX01 -- V1.2 R. Munden 02 APR 04 Corrected type used with VitalBuf -- V1.3 R. Munden 03 MAR 15 Changed type of some _nwv signals to -- satisfy ncvhdl -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: DRAM -- Part: MT4LC4M16R6 -- -- Description: EDO DRAM 4M x 16 -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY mt4lc4m16r6 IS GENERIC ( -- tipd delays: interconnect path delays tipd_IO15 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0 : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_CASLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CASHNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tAA tpd_A0_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tCAC, tCLZ, tCOH, tOFF tpd_CASLNeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tRAC, tOFF tpd_RASNeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tOE, tOD tpd_OENeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tWHZ tpd_WENeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tCP tpw_CASLNeg_posedge : VitalDelayType := UnitDelay; -- tWP tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tCAS tpw_CASLNeg_negedge : VitalDelayType := UnitDelay; -- tRAS tpw_RASNeg_negedge : VitalDelayType := UnitDelay; -- tRP tpw_RASNeg_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tASC tsetup_A0_CASLNeg : VitalDelayType := UnitDelay; -- tASR tsetup_A0_RASNeg : VitalDelayType := UnitDelay; -- tDS tsetup_IO0_WENeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tRAH thold_A0_RASNeg : VitalDelayType := UnitDelay; -- tCAH thold_A0_CASLNeg : VitalDelayType := UnitDelay; -- tDH thold_IO0_WENeg : VitalDelayType := UnitDelay; -- trecovery values: setup times -- tCSR trecovery_CASLNeg_RASNeg : VitalDelayType := UnitDelay; -- tCWD trecovery_CASLNeg_WENeg : VitalDelayType := UnitDelay; -- tWRP trecovery_WENeg_RASNeg : VitalDelayType := UnitDelay; -- tWCS trecovery_WENeg_CASLNeg : VitalDelayType := UnitDelay; -- tremoval values: hold times -- tCHR tremoval_CASLNeg_RASNeg : VitalDelayType := UnitDelay; -- tWRH tremoval_WENeg_RASNeg : VitalDelayType := UnitDelay; -- tWCH tremoval_WENeg_CASLNeg : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays -- time between refresh tdevice_REF : VitalDelayType := 15_625 ns; -- tpowerup: Power up initialization time. Data sheets say 100-200 us. -- May be shortened during simulation debug. tpowerup : TIME := 100 us; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( IO15 : INOUT std_logic := 'U'; IO14 : INOUT std_logic := 'U'; IO13 : INOUT std_logic := 'U'; IO12 : INOUT std_logic := 'U'; IO11 : INOUT std_logic := 'U'; IO10 : INOUT std_logic := 'U'; IO9 : INOUT std_logic := 'U'; IO8 : INOUT std_logic := 'U'; IO7 : INOUT std_logic := 'U'; IO6 : INOUT std_logic := 'U'; IO5 : INOUT std_logic := 'U'; IO4 : INOUT std_logic := 'U'; IO3 : INOUT std_logic := 'U'; IO2 : INOUT std_logic := 'U'; IO1 : INOUT std_logic := 'U'; IO0 : INOUT std_logic := 'U'; A0 : IN std_logic := 'U'; A1 : IN std_logic := 'U'; A2 : IN std_logic := 'U'; A3 : IN std_logic := 'U'; A4 : IN std_logic := 'U'; A5 : IN std_logic := 'U'; A6 : IN std_logic := 'U'; A7 : IN std_logic := 'U'; A8 : IN std_logic := 'U'; A9 : IN std_logic := 'U'; A10 : IN std_logic := 'U'; A11 : IN std_logic := 'U'; CASLNeg : IN std_logic := 'U'; CASHNeg : IN std_logic := 'U'; RASNeg : IN std_logic := 'U'; WENeg : IN std_logic := 'U'; OENeg : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of mt4lc4m16r6 : ENTITY IS TRUE; END mt4lc4m16r6; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of mt4lc4m16r6 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE; CONSTANT partID : STRING := "mt4lc4m16r6"; SIGNAL PoweredUp : boolean := false; SIGNAL IO15_ipd : std_ulogic := 'X'; SIGNAL IO14_ipd : std_ulogic := 'X'; SIGNAL IO13_ipd : std_ulogic := 'X'; SIGNAL IO12_ipd : std_ulogic := 'X'; SIGNAL IO11_ipd : std_ulogic := 'X'; SIGNAL IO10_ipd : std_ulogic := 'X'; SIGNAL IO9_ipd : std_ulogic := 'X'; SIGNAL IO8_ipd : std_ulogic := 'X'; SIGNAL IO7_ipd : std_ulogic := 'X'; SIGNAL IO6_ipd : std_ulogic := 'X'; SIGNAL IO5_ipd : std_ulogic := 'X'; SIGNAL IO4_ipd : std_ulogic := 'X'; SIGNAL IO3_ipd : std_ulogic := 'X'; SIGNAL IO2_ipd : std_ulogic := 'X'; SIGNAL IO1_ipd : std_ulogic := 'X'; SIGNAL IO0_ipd : std_ulogic := 'X'; SIGNAL A0_ipd : std_ulogic := 'X'; SIGNAL A1_ipd : std_ulogic := 'X'; SIGNAL A2_ipd : std_ulogic := 'X'; SIGNAL A3_ipd : std_ulogic := 'X'; SIGNAL A4_ipd : std_ulogic := 'X'; SIGNAL A5_ipd : std_ulogic := 'X'; SIGNAL A6_ipd : std_ulogic := 'X'; SIGNAL A7_ipd : std_ulogic := 'X'; SIGNAL A8_ipd : std_ulogic := 'X'; SIGNAL A9_ipd : std_ulogic := 'X'; SIGNAL A10_ipd : std_ulogic := 'X'; SIGNAL A11_ipd : std_ulogic := 'X'; SIGNAL CASLNeg_ipd : std_ulogic := 'X'; SIGNAL CASHNeg_ipd : std_ulogic := 'X'; SIGNAL RASNeg_ipd : std_ulogic := 'X'; SIGNAL WENeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL CASLNeg_nwv : std_ulogic := 'X'; SIGNAL CASHNeg_nwv : std_ulogic := 'X'; SIGNAL IO0_nwv : UX01 := 'X'; SIGNAL IO1_nwv : UX01 := 'X'; SIGNAL IO2_nwv : UX01 := 'X'; SIGNAL IO3_nwv : UX01 := 'X'; SIGNAL IO4_nwv : UX01 := 'X'; SIGNAL IO5_nwv : UX01 := 'X'; SIGNAL IO6_nwv : UX01 := 'X'; SIGNAL IO7_nwv : UX01 := 'X'; SIGNAL IO8_nwv : UX01 := 'X'; SIGNAL IO9_nwv : UX01 := 'X'; SIGNAL IO10_nwv : UX01 := 'X'; SIGNAL IO11_nwv : UX01 := 'X'; SIGNAL IO12_nwv : UX01 := 'X'; SIGNAL IO13_nwv : UX01 := 'X'; SIGNAL IO14_nwv : UX01 := 'X'; SIGNAL IO15_nwv : UX01 := 'X'; SIGNAL A0_nwv : UX01 := 'X'; SIGNAL A1_nwv : UX01 := 'X'; SIGNAL A2_nwv : UX01 := 'X'; SIGNAL A3_nwv : UX01 := 'X'; SIGNAL A4_nwv : UX01 := 'X'; SIGNAL A5_nwv : UX01 := 'X'; SIGNAL A6_nwv : UX01 := 'X'; SIGNAL A7_nwv : UX01 := 'X'; SIGNAL A8_nwv : UX01 := 'X'; SIGNAL A9_nwv : UX01 := 'X'; SIGNAL A10_nwv : UX01 := 'X'; SIGNAL A11_nwv : UX01 := 'X'; SIGNAL WENeg_nwv : std_ulogic := 'X'; SIGNAL RASNeg_nwv : std_ulogic := 'X'; SIGNAL OENeg_nwv : std_ulogic := 'X'; SIGNAL refreshed_in : std_ulogic := '0'; SIGNAL refreshed_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays REF : VitalBuf (refreshed_out, refreshed_in, (UnitDelay, tdevice_REF)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (IO15_ipd, IO15, tipd_IO15); w_2 : VitalWireDelay (IO14_ipd, IO14, tipd_IO14); w_3 : VitalWireDelay (IO13_ipd, IO13, tipd_IO13); w_4 : VitalWireDelay (IO12_ipd, IO12, tipd_IO12); w_5 : VitalWireDelay (IO11_ipd, IO11, tipd_IO11); w_6 : VitalWireDelay (IO10_ipd, IO10, tipd_IO10); w_7 : VitalWireDelay (IO9_ipd, IO9, tipd_IO9); w_8 : VitalWireDelay (IO8_ipd, IO8, tipd_IO8); w_9 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7); w_10 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6); w_11 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5); w_12 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4); w_13 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3); w_14 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2); w_15 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1); w_16 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0); w_17 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_18 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_19 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_20 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_21 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_22 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_23 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_24 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_25 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_26 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_27 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_28 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_30 : VitalWireDelay (CASLNeg_ipd, CASLNeg, tipd_CASLNeg); w_31 : VitalWireDelay (CASHNeg_ipd, CASHNeg, tipd_CASHNeg); w_32 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg); w_33 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_34 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); END BLOCK; CASHNeg_nwv <= To_UX01(CASHNeg_ipd); CASLNeg_nwv <= To_UX01(CASLNeg_ipd); WENeg_nwv <= To_UX01(WENeg_ipd); RASNeg_nwv <= To_UX01(RASNeg_ipd); OENeg_nwv <= To_UX01(OENeg_ipd); IO0_nwv <= To_UX01(IO0_ipd); IO1_nwv <= To_UX01(IO1_ipd); IO2_nwv <= To_UX01(IO2_ipd); IO3_nwv <= To_UX01(IO3_ipd); IO4_nwv <= To_UX01(IO4_ipd); IO5_nwv <= To_UX01(IO5_ipd); IO6_nwv <= To_UX01(IO6_ipd); IO7_nwv <= To_UX01(IO7_ipd); IO8_nwv <= To_UX01(IO8_ipd); IO9_nwv <= To_UX01(IO9_ipd); IO10_nwv <= To_UX01(IO10_ipd); IO11_nwv <= To_UX01(IO11_ipd); IO12_nwv <= To_UX01(IO12_ipd); IO13_nwv <= To_UX01(IO13_ipd); IO14_nwv <= To_UX01(IO14_ipd); IO15_nwv <= To_UX01(IO15_ipd); A0_nwv <= To_UX01(A0_ipd); A1_nwv <= To_UX01(A1_ipd); A2_nwv <= To_UX01(A2_ipd); A3_nwv <= To_UX01(A3_ipd); A4_nwv <= To_UX01(A4_ipd); A5_nwv <= To_UX01(A5_ipd); A6_nwv <= To_UX01(A6_ipd); A7_nwv <= To_UX01(A7_ipd); A8_nwv <= To_UX01(A8_ipd); A9_nwv <= To_UX01(A9_ipd); A10_nwv <= To_UX01(A10_ipd); A11_nwv <= To_UX01(A11_ipd); ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( CASLIn : IN std_ulogic := 'X'; CASHIn : IN std_ulogic := 'X'; DataInH : IN std_logic_vector(7 downto 0); DataInL : IN std_logic_vector(7 downto 0); DataOutH : OUT std_logic_vector(7 downto 0) := (others => 'Z'); DataOutL : OUT std_logic_vector(7 downto 0) := (others => 'Z'); AddressIn : IN std_logic_vector(11 downto 0); WENegIn : IN std_ulogic := 'X'; RASNegIn : IN std_ulogic := 'X'; OENegIn : IN std_ulogic := 'X' ); PORT MAP ( CASLIn => CASLNeg_nwv, CASHIn => CASHNeg_nwv, DataOutL(0) => IO0, DataOutL(1) => IO1, DataOutL(2) => IO2, DataOutL(3) => IO3, DataOutL(4) => IO4, DataOutL(5) => IO5, DataOutL(6) => IO6, DataOutL(7) => IO7, DataOutH(0) => IO8, DataOutH(1) => IO9, DataOutH(2) => IO10, DataOutH(3) => IO11, DataOutH(4) => IO12, DataOutH(5) => IO13, DataOutH(6) => IO14, DataOutH(7) => IO15, DataInL(0) => IO0_nwv, DataInL(1) => IO1_nwv, DataInL(2) => IO2_nwv, DataInL(3) => IO3_nwv, DataInL(4) => IO4_nwv, DataInL(5) => IO5_nwv, DataInL(6) => IO6_nwv, DataInL(7) => IO7_nwv, DataInH(0) => IO8_nwv, DataInH(1) => IO9_nwv, DataInH(2) => IO10_nwv, DataInH(3) => IO11_nwv, DataInH(4) => IO12_nwv, DataInH(5) => IO13_nwv, DataInH(6) => IO14_nwv, DataInH(7) => IO15_nwv, AddressIn(0) => A0_nwv, AddressIn(1) => A1_nwv, AddressIn(2) => A2_nwv, AddressIn(3) => A3_nwv, AddressIn(4) => A4_nwv, AddressIn(5) => A5_nwv, AddressIn(6) => A6_nwv, AddressIn(7) => A7_nwv, AddressIn(8) => A8_nwv, AddressIn(9) => A9_nwv, AddressIn(10) => A10_nwv, AddressIn(11) => A11_nwv, WENegIn => WENeg_nwv, RASNegIn => RASNeg_nwv, OENegIn => OENeg_nwv ); SIGNAL DH_zd : std_logic_vector(7 DOWNTO 0); SIGNAL DL_zd : std_logic_vector(7 DOWNTO 0); BEGIN PoweredUp <= true after tpowerup; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- Behavior : PROCESS (CASLIn, CASHIn, DataInH, DataInL, AddressIn, WENegIn, RASNegIn, OENegIn) -- Timing Check Variables VARIABLE Tviol_Address_CASL : X01 := '0'; VARIABLE TD_Address_CASL : VitalTimingDataType; VARIABLE Tviol_Address_CASH : X01 := '0'; VARIABLE TD_Address_CASH : VitalTimingDataType; VARIABLE Tviol_Address_RAS : X01 := '0'; VARIABLE TD_Address_RAS : VitalTimingDataType; VARIABLE Tviol_Data_CASL : X01 := '0'; VARIABLE TD_Data_CASL : VitalTimingDataType; VARIABLE Tviol_Data_CASH : X01 := '0'; VARIABLE TD_Data_CASH : VitalTimingDataType; VARIABLE Tviol_DataH_WE : X01 := '0'; VARIABLE TD_DataH_WE : VitalTimingDataType; VARIABLE Tviol_DataL_WE : X01 := '0'; VARIABLE TD_DataL_WE : VitalTimingDataType; VARIABLE Tviol_WE_RAS : X01 := '0'; VARIABLE TD_WE_RAS : VitalTimingDataType; VARIABLE Tviol_WE_CASL : X01 := '0'; VARIABLE TD_WE_CASL : VitalTimingDataType; VARIABLE Tviol_WE_CASH : X01 := '0'; VARIABLE TD_WE_CASH : VitalTimingDataType; VARIABLE Tviol_CASL_RAS : X01 := '0'; VARIABLE TD_CASL_RAS : VitalTimingDataType; VARIABLE Tviol_CASH_RAS : X01 := '0'; VARIABLE TD_CASH_RAS : VitalTimingDataType; VARIABLE Pviol_CASH : X01 := '0'; VARIABLE PD_CASH : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASL : X01 := '0'; VARIABLE PD_CASL : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WE : X01 := '0'; VARIABLE PD_WE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RAS : X01 := '0'; VARIABLE PD_RAS : VitalPeriodDataType := VitalPeriodDataInit; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE DataDriveH : std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataDriveL : std_logic_vector(7 DOWNTO 0) := (OTHERS => 'Z'); -- Type definition for wirtes TYPE write_type is (early, late ); VARIABLE write : write_type; -- Memory array declaration TYPE MemStore IS ARRAY (0 to 4194303) OF NATURAL RANGE 0 TO 255; VARIABLE MemH : MemStore; VARIABLE MemL : MemStore; VARIABLE MemAddr : std_logic_vector(21 DOWNTO 0) := (OTHERS => 'X'); VARIABLE Location : NATURAL RANGE 0 TO 4194303 := 0; VARIABLE CBR : boolean := FALSE; VARIABLE Ref_Cnt : NATURAL RANGE 0 TO 4096 := 1; VARIABLE next_ref : TIME; VARIABLE cas : UX01 := 'U'; VARIABLE written : boolean := false; VARIABLE ready : boolean := false; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN -- tASC, tCAH VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CASLIn, RefSignalName => "CASL", SetupHigh => tsetup_A0_CASLNeg, SetupLow => tsetup_A0_CASLNeg, HoldHigh => thold_A0_CASLNeg, HoldLow => thold_A0_CASLNeg, CheckEnabled => (RASNegIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_Address_CASL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Address_CASL ); -- tASC, tCAH VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CASHIn, RefSignalName => "CASH", SetupHigh => tsetup_A0_CASLNeg, SetupLow => tsetup_A0_CASLNeg, HoldHigh => thold_A0_CASLNeg, HoldLow => thold_A0_CASLNeg, CheckEnabled => (RASNegIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_Address_CASH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Address_CASH ); -- tASR, tRAH VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => RASNegIn, RefSignalName => "RASNeg", SetupHigh => tsetup_A0_RASNeg, SetupLow => tsetup_A0_RASNeg, HoldHigh => thold_A0_RASNeg, HoldLow => thold_A0_RASNeg, CheckEnabled => (CASLIn = '1' AND CASHIn = '1'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_Address_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Address_RAS ); -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DataInH, TestSignalName => "DataInH", RefSignal => CASHIn, RefSignalName => "CASH", SetupHigh => tsetup_IO0_WENeg, SetupLow => tsetup_IO0_WENeg, HoldHigh => thold_IO0_WENeg, HoldLow => thold_IO0_WENeg, CheckEnabled => (write = early), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_Data_CASH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Data_CASH ); -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DataInL, TestSignalName => "DataInL", RefSignal => CASLIn, RefSignalName => "CASL", SetupHigh => tsetup_IO0_WENeg, SetupLow => tsetup_IO0_WENeg, HoldHigh => thold_IO0_WENeg, HoldLow => thold_IO0_WENeg, CheckEnabled => (write = early), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_Data_CASL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Data_CASL ); -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DataInL, TestSignalName => "DataInL", RefSignal => WENegIn, RefSignalName => "WENeg", SetupHigh => tsetup_IO0_WENeg, SetupLow => tsetup_IO0_WENeg, HoldHigh => thold_IO0_WENeg, HoldLow => thold_IO0_WENeg, CheckEnabled => (write = late), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DataL_WE, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DataL_WE ); -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DataInH, TestSignalName => "DataInH", RefSignal => WENegIn, RefSignalName => "WENeg", SetupHigh => tsetup_IO0_WENeg, SetupLow => tsetup_IO0_WENeg, HoldHigh => thold_IO0_WENeg, HoldLow => thold_IO0_WENeg, CheckEnabled => (write = late), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DataH_WE, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DataH_WE ); -- tWRP, tWRH VitalRecoveryRemovalCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", RefSignal => RASNegIn, RefSignalName => "RASNeg", Recovery => trecovery_WENeg_RASNeg, Removal => tremoval_WENeg_RASNeg, ActiveLow => TRUE, CheckEnabled => CBR, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WE_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WE_RAS ); -- tWCS, tWCH VitalRecoveryRemovalCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", RefSignal => CASLIn, RefSignalName => "CASL", Recovery => trecovery_WENeg_CASLNeg, Removal => tremoval_WENeg_CASLNeg, ActiveLow => TRUE, CheckEnabled => (write = early), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WE_CASL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WE_CASL ); -- tWCS, tWCH VitalRecoveryRemovalCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", RefSignal => CASHIn, RefSignalName => "CASH", Recovery => trecovery_WENeg_CASLNeg, Removal => tremoval_WENeg_CASLNeg, ActiveLow => TRUE, CheckEnabled => (write = early), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WE_CASH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WE_CASH ); -- tCSR, tCHR VitalRecoveryRemovalCheck ( TestSignal => CASLIn, TestSignalName => "CASL", RefSignal => RASNegIn, RefSignalName => "RASNeg", Recovery => trecovery_CASLNeg_RASNeg, Removal => tremoval_CASLNeg_RASNeg, ActiveLow => TRUE, CheckEnabled => CBR, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASL_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CASL_RAS ); -- tCSR, tCHR VitalRecoveryRemovalCheck ( TestSignal => CASHIn, TestSignalName => "CASH", RefSignal => RASNegIn, RefSignalName => "RASNeg", Recovery => trecovery_CASLNeg_RASNeg, Removal => tremoval_CASLNeg_RASNeg, ActiveLow => TRUE, CheckEnabled => CBR, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASH_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CASH_RAS ); -- tRAS, tRP VitalPeriodPulseCheck ( TestSignal => RASNegIn, TestSignalName => "RASNeg", PulseWidthLow => tpw_RASNeg_negedge, PulseWidthHigh => tpw_RASNeg_posedge, PeriodData => PD_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RAS, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); -- tCAS, tCP VitalPeriodPulseCheck ( TestSignal => CASLIn, TestSignalName => "CASLNeg", PulseWidthLow => tpw_CASLNeg_negedge, PulseWidthHigh => tpw_CASLNeg_posedge, PeriodData => PD_CASL, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CASL, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); -- tCAS, tCP VitalPeriodPulseCheck ( TestSignal => CASHIn, TestSignalName => "CASHNeg", PulseWidthLow => tpw_CASLNeg_negedge, PulseWidthHigh => tpw_CASLNeg_posedge, PeriodData => PD_CASH, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CASH, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); -- tWP VitalPeriodPulseCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", PulseWidthLow => tpw_WENeg_negedge, PeriodData => PD_WE, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WE, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); Violation := Tviol_Address_CASL OR Tviol_Address_CASH OR Tviol_Address_RAS OR Pviol_CASL OR Pviol_CASH OR Tviol_CASL_RAS OR Tviol_CASH_RAS OR Tviol_WE_RAS OR Pviol_WE OR Pviol_RAS OR Tviol_DataH_WE OR Tviol_DataL_WE OR Tviol_Data_CASL OR Tviol_Data_CASH OR Tviol_WE_CASH OR Tviol_WE_CASL; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- cas := VitalAND2(a => CASHIn, b => CASLIn); IF (NOW > Next_Ref AND PoweredUp = true AND Ref_Cnt > 0) THEN Ref_Cnt := Ref_Cnt - 1; Next_Ref := NOW + tdevice_REF; END IF; IF (falling_edge(RASNegIn)) THEN IF (CASHIn = '0' AND CASLIn = '0') THEN IF (WENegIn = '1') THEN CBR := TRUE; Ref_Cnt := Ref_Cnt + 1; IF (not(ready) AND PoweredUp AND Ref_Cnt = 8) THEN ready := TRUE; END IF; ELSE ASSERT FALSE REPORT InstancePath & partID & ": Unknown operation;" & " WENeg must be high for CBR" SEVERITY SeverityMode; END IF; ELSIF (cas = '1') THEN ASSERT (not(Is_X(AddressIn))) REPORT InstancePath & partID & ": Unusable value for address" SEVERITY SeverityMode; MemAddr(21 downto 10) := AddressIn; CBR := FALSE; END IF; END IF; IF ((falling_edge(CASHIn) OR falling_edge(CASLIn)) AND RASNegIn = '0') THEN ASSERT (not(Is_X(WENegIn))) REPORT InstancePath & partID & ": Unusable value for WENeg" SEVERITY SeverityMode; ASSERT (not(Is_X(AddressIn))) REPORT InstancePath & partID & ": Unusable value for address" SEVERITY SeverityMode; MemAddr(9 downto 0) := AddressIn(9 downto 0); Location := to_nat(MemAddr); -- Read Cycle IF (WENegIn = '1') THEN IF (CASHIn = '0') THEN DataDriveH := to_slv(MemH(Location),8); END IF; IF (CASLIn = '0') THEN DataDriveL := to_slv(MemL(Location),8); END IF; -- Early Write Cycle ELSE ASSERT ready REPORT InstancePath & partID & ": memory is not ready for" & " use - must be powered up and refreshed" SEVERITY SeverityMode; IF (CASHIn = '0') THEN MemH(Location) := to_nat(DataInH); END IF; IF (CASLIn = '0') THEN MemL(Location) := to_nat(DataInL); END IF; written := true; write := early; END IF; END IF; IF (falling_edge(WENegIn)) THEN DataDriveL := (others => 'Z'); DataDriveH := (others => 'Z'); -- Late Write Cycle IF (RASNegIn = '0') THEN ASSERT ready REPORT InstancePath & partID & ": memory is not ready for" & " use - must be powered up and refreshed" SEVERITY SeverityMode; IF (CASHIn = '0') THEN MemH(Location) := to_nat(DataInH); END IF; IF (CASLIn = '0') THEN MemL(Location) := to_nat(DataInL); END IF; written := true; write := late; END IF; END IF; -- Check Refresh Status IF (written = true) THEN ASSERT Ref_Cnt > 0 REPORT InstancePath & partID & ": memory not refreshed (by ref_cnt)" SEVERITY SeverityMode; IF (Ref_Cnt < 1) THEN ready := FALSE; END IF; END IF; -------------------------------------------------------------------- -- Output Section -------------------------------------------------------------------- IF (OENegIn = '0' AND (cas = '0' OR RASNegIn = '0')) THEN DH_zd <= DataDriveH; DL_zd <= DataDriveL; ELSE DH_zd <= (others => 'Z'); DL_zd <= (others => 'Z'); END IF; END PROCESS; ------------------------------------------------------------------------ -- Path Delay Process ------------------------------------------------------------------------ DataOutLBlk : FOR i IN 7 DOWNTO 0 GENERATE DataOut_Delay : PROCESS (DL_zd(i)) VARIABLE DL_GlitchData:VitalGlitchDataArrayType(7 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataOutL(i), OutSignalName => "DataL", OutTemp => DL_zd(i), Mode => OnEvent, GlitchData => DL_GlitchData(i), Paths => ( 1 => (InputChangeTime => CASLIn'LAST_EVENT, PathDelay => tpd_CASLNeg_IO0, PathCondition => CASLIn = '0'), 2 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE), 3 => (InputChangeTime => WENegIn'LAST_EVENT, PathDelay => tpd_WENeg_IO0, PathCondition => TRUE), 4 => (InputChangeTime => CASLIn'LAST_EVENT, PathDelay => tpd_RASNeg_IO0, -- tOFF PathCondition => RASNegIn = '1' AND CASLIn = '1'), 5 => (InputChangeTime => RASNegIn'LAST_EVENT, PathDelay => tpd_RASNeg_IO0, -- tOFF PathCondition => RASNegIn = '1' AND CASLIn = '1') ) ); END PROCESS; END GENERATE; DataOutHBlk : FOR i IN 7 DOWNTO 0 GENERATE DataOut_Delay : PROCESS (DH_zd(i)) VARIABLE DH_GlitchData:VitalGlitchDataArrayType(7 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataOutH(i), OutSignalName => "DataH", OutTemp => DH_zd(i), Mode => OnEvent, GlitchData => DH_GlitchData(i), Paths => ( 1 => (InputChangeTime => CASHIn'LAST_EVENT, PathDelay => tpd_CASLNeg_IO0, PathCondition => TRUE), 2 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => TRUE), 3 => (InputChangeTime => WENegIn'LAST_EVENT, PathDelay => tpd_WENeg_IO0, PathCondition => TRUE), 4 => (InputChangeTime => CASHIn'LAST_EVENT, PathDelay => tpd_RASNeg_IO0, -- tOFF PathCondition => RASNegIn = '1' AND CASHIn = '1'), 5 => (InputChangeTime => RASNegIn'LAST_EVENT, PathDelay => tpd_RASNeg_IO0, -- tOFF PathCondition => RASNegIn = '1' AND CASHIn = '1') ) ); END PROCESS; END GENERATE; END BLOCK; END vhdl_behavioral;