------------------------------------------------------------------------------- -- File Name: idt71421.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version: | author: | mod date: | changes made: -- V1.0 N.Makljenovic 05 Feb 17 Initial release -- ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: idt71421 -- -- Description: Dual Port RAM 2K x 8 Slave ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY idt71421 IS GENERIC ( -- tipd delays: interconnect path delays tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BUSYRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BUSYLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_CERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR10 : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL10 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_AL0_IOL0 : VitalDelayType01 := UnitDelay01; tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; tpd_CELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; tpd_RWL_INTRNeg : VitalDelayType01Z := UnitDelay01Z; tpd_RWL_IOL0 : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_AL0_AR0 : VitalDelayType := UnitDelay; tsetup_AL0_OELNeg : VitalDelayType := UnitDelay; tsetup_AL0_CELNeg : VitalDelayType := UnitDelay; tsetup_AL0_RWL : VitalDelayType := UnitDelay; tsetup_CELNeg_RWL : VitalDelayType := UnitDelay; tsetup_IOL0_RWL : VitalDelayType := UnitDelay; tsetup_BUSYRNeg_RWL : VitalDelayType := UnitDelay; -- thold values: hold times thold_IOL0_RWL : VitalDelayType := UnitDelay; thold_RWL_BUSYLNeg : VitalDelayType := UnitDelay; thold_AL0_CELNeg : VitalDelayType := UnitDelay; -- pulse width tpw_RWL_negedge : VitalDelayType := UnitDelay; tpw_AL0_negedge : VitalDelayType := UnitDelay; tpw_AL0_posedge : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays tdevice_TWDD : VitalDelayType := UnitDelay; tdevice_TDDD : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none"; UserPreload : BOOLEAN := FALSE; InterruptEnable : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( IOR7 : INOUT std_ulogic := 'U'; IOR6 : INOUT std_ulogic := 'U'; IOR5 : INOUT std_ulogic := 'U'; IOR4 : INOUT std_ulogic := 'U'; IOR3 : INOUT std_ulogic := 'U'; IOR2 : INOUT std_ulogic := 'U'; IOR1 : INOUT std_ulogic := 'U'; IOR0 : INOUT std_ulogic := 'U'; IOL7 : INOUT std_ulogic := 'U'; IOL6 : INOUT std_ulogic := 'U'; IOL5 : INOUT std_ulogic := 'U'; IOL4 : INOUT std_ulogic := 'U'; IOL3 : INOUT std_ulogic := 'U'; IOL2 : INOUT std_ulogic := 'U'; IOL1 : INOUT std_ulogic := 'U'; IOL0 : INOUT std_ulogic := 'U'; OERNeg : IN std_ulogic := 'U'; OELNeg : IN std_ulogic := 'U'; RWR : IN std_ulogic := 'U'; RWL : IN std_ulogic := 'U'; CERNeg : IN std_ulogic := 'U'; CELNeg : IN std_ulogic := 'U'; BUSYLNeg : IN std_ulogic := 'U'; BUSYRNeg : IN std_ulogic := 'U'; INTLNeg : OUT std_ulogic := 'U'; INTRNeg : OUT std_ulogic := 'U'; AR0 : IN std_ulogic := 'U'; AR1 : IN std_ulogic := 'U'; AR2 : IN std_ulogic := 'U'; AR3 : IN std_ulogic := 'U'; AR4 : IN std_ulogic := 'U'; AR5 : IN std_ulogic := 'U'; AR6 : IN std_ulogic := 'U'; AR7 : IN std_ulogic := 'U'; AR8 : IN std_ulogic := 'U'; AR9 : IN std_ulogic := 'U'; AR10 : IN std_ulogic := 'U'; AL0 : IN std_ulogic := 'U'; AL1 : IN std_ulogic := 'U'; AL2 : IN std_ulogic := 'U'; AL3 : IN std_ulogic := 'U'; AL4 : IN std_ulogic := 'U'; AL5 : IN std_ulogic := 'U'; AL6 : IN std_ulogic := 'U'; AL7 : IN std_ulogic := 'U'; AL8 : IN std_ulogic := 'U'; AL9 : IN std_ulogic := 'U'; AL10 : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt71421 : ENTITY IS TRUE; END idt71421; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt71421 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "idt71421"; CONSTANT MaxData : NATURAL := 16#FF#; CONSTANT TotalLOC : NATURAL := 2047; CONSTANT HiAbit : NATURAL := 10; CONSTANT HiDbit : NATURAL := 7; CONSTANT DataWidth : NATURAL := 8; SIGNAL IOR7_ipd : std_ulogic := 'U'; SIGNAL IOR6_ipd : std_ulogic := 'U'; SIGNAL IOR5_ipd : std_ulogic := 'U'; SIGNAL IOR4_ipd : std_ulogic := 'U'; SIGNAL IOR3_ipd : std_ulogic := 'U'; SIGNAL IOR2_ipd : std_ulogic := 'U'; SIGNAL IOR1_ipd : std_ulogic := 'U'; SIGNAL IOR0_ipd : std_ulogic := 'U'; SIGNAL IOL7_ipd : std_ulogic := 'U'; SIGNAL IOL6_ipd : std_ulogic := 'U'; SIGNAL IOL5_ipd : std_ulogic := 'U'; SIGNAL IOL4_ipd : std_ulogic := 'U'; SIGNAL IOL3_ipd : std_ulogic := 'U'; SIGNAL IOL2_ipd : std_ulogic := 'U'; SIGNAL IOL1_ipd : std_ulogic := 'U'; SIGNAL IOL0_ipd : std_ulogic := 'U'; SIGNAL OERNeg_ipd : std_ulogic := 'U'; SIGNAL OELNeg_ipd : std_ulogic := 'U'; SIGNAL RWR_ipd : std_ulogic := 'U'; SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL BUSYRNeg_ipd : std_ulogic := 'U'; SIGNAL BUSYLNeg_ipd : std_ulogic := 'U'; SIGNAL CERNeg_ipd : std_ulogic := 'U'; SIGNAL CELNeg_ipd : std_ulogic := 'U'; SIGNAL AR0_ipd : std_ulogic := 'U'; SIGNAL AR1_ipd : std_ulogic := 'U'; SIGNAL AR2_ipd : std_ulogic := 'U'; SIGNAL AR3_ipd : std_ulogic := 'U'; SIGNAL AR4_ipd : std_ulogic := 'U'; SIGNAL AR5_ipd : std_ulogic := 'U'; SIGNAL AR6_ipd : std_ulogic := 'U'; SIGNAL AR7_ipd : std_ulogic := 'U'; SIGNAL AR8_ipd : std_ulogic := 'U'; SIGNAL AR9_ipd : std_ulogic := 'U'; SIGNAL AR10_ipd : std_ulogic := 'U'; SIGNAL AL0_ipd : std_ulogic := 'U'; SIGNAL AL1_ipd : std_ulogic := 'U'; SIGNAL AL2_ipd : std_ulogic := 'U'; SIGNAL AL3_ipd : std_ulogic := 'U'; SIGNAL AL4_ipd : std_ulogic := 'U'; SIGNAL AL5_ipd : std_ulogic := 'U'; SIGNAL AL6_ipd : std_ulogic := 'U'; SIGNAL AL7_ipd : std_ulogic := 'U'; SIGNAL AL8_ipd : std_ulogic := 'U'; SIGNAL AL9_ipd : std_ulogic := 'U'; SIGNAL AL10_ipd : std_ulogic := 'U'; SIGNAL TWDD_in : std_ulogic := '0'; SIGNAL TWDD_out : std_ulogic := '0'; SIGNAL TDDD_in : std_ulogic := '0'; SIGNAL TDDD_out : std_ulogic := '0'; BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays TWDD :VitalBuf(TWDD_out, TWDD_in, (tdevice_TWDD ,UnitDelay)); TDDD :VitalBuf(TDDD_out, TDDD_in, (tdevice_TDDD ,UnitDelay)); --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_0 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR); w_1 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL); w_2 : VitalWireDelay (CERNeg_ipd, CERNeg, tipd_CERNeg); w_3 : VitalWireDelay (CELNeg_ipd, CELNeg, tipd_CELNeg); w_4 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg); w_6 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg); w_7 : VitalWireDelay (BUSYRNeg_ipd, OERNeg, tipd_BUSYRNeg); w_8 : VitalWireDelay (BUSYLNeg_ipd, OELNeg, tipd_BUSYLNeg); w_9 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0); w_10: VitalWireDelay (AR1_ipd, AR1, tipd_AR1); w_11 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2); w_12 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3); w_13 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4); w_14 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5); w_15 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6); w_16 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7); w_17 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8); w_18 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9); w_19 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10); w_20 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0); w_21 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1); w_22 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2); w_23 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3); w_24 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4); w_25 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5); w_26 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6); w_27 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7); w_28 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8); w_29 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9); w_30 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10); w_31 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7); w_32 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6); w_33 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5); w_34 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4); w_35 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3); w_36 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2); w_37 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1); w_38 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0); w_39 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7); w_40 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6); w_41 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5); w_42 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4); w_43 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3); w_44 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2); w_45 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1); w_46 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( ALIn : IN std_logic_vector(HiAbit downto 0); ARIn : IN std_logic_vector(HiAbit downto 0); IOLIn : IN std_logic_vector(HiDbit downto 0); IORIn : IN std_logic_vector(HiDbit downto 0); IOLOut : OUT std_logic_vector(HiDbit downto 0); IOROut : OUT std_logic_vector(HiDbit downto 0); OERNeg : IN std_ulogic := 'U'; OELNeg : IN std_ulogic := 'U'; RWR : IN std_ulogic := 'U'; RWL : IN std_ulogic := 'U'; CERNeg : IN std_ulogic := 'U'; CELNeg : IN std_ulogic := 'U'; BUSYLNeg : IN std_ulogic := 'U'; BUSYRNeg : IN std_ulogic := 'U'; INTLNeg : OUT std_ulogic := 'U'; INTRNeg : OUT std_ulogic := 'U' ); PORT MAP ( ALIn(0) => AL0_ipd, ALIn(1) => AL1_ipd, ALIn(2) => AL2_ipd, ALIn(3) => AL3_ipd, ALIn(4) => AL4_ipd, ALIn(5) => AL5_ipd, ALIn(6) => AL6_ipd, ALIn(7) => AL7_ipd, ALIn(8) => AL8_ipd, ALIn(9) => AL9_ipd, ALIn(10) => AL10_ipd, ARIn(0) => AR0_ipd, ARIn(1) => AR1_ipd, ARIn(2) => AR2_ipd, ARIn(3) => AR3_ipd, ARIn(4) => AR4_ipd, ARIn(5) => AR5_ipd, ARIn(6) => AR6_ipd, ARIn(7) => AR7_ipd, ARIn(8) => AR8_ipd, ARIn(9) => AR9_ipd, ARIn(10) => AR10_ipd, IOLIn(0) => IOL0_ipd, IOLIn(1) => IOL1_ipd, IOLIn(2) => IOL2_ipd, IOLIn(3) => IOL3_ipd, IOLIn(4) => IOL4_ipd, IOLIn(5) => IOL5_ipd, IOLIn(6) => IOL6_ipd, IOLIn(7) => IOL7_ipd, IORIn(0) => IOR0_ipd, IORIn(1) => IOR1_ipd, IORIn(2) => IOR2_ipd, IORIn(3) => IOR3_ipd, IORIn(4) => IOR4_ipd, IORIn(5) => IOR5_ipd, IORIn(6) => IOR6_ipd, IORIn(7) => IOR7_ipd, IOROut(0) => IOR0, IOROut(1) => IOR1, IOROut(2) => IOR2, IOROut(3) => IOR3, IOROut(4) => IOR4, IOROut(5) => IOR5, IOROut(6) => IOR6, IOROut(7) => IOR7, IOLOut(0) => IOL0, IOLOut(1) => IOL1, IOLOut(2) => IOL2, IOLOut(3) => IOL3, IOLOut(4) => IOL4, IOLOut(5) => IOL5, IOLOut(6) => IOL6, IOLOut(7) => IOL7, OELNeg => OELNeg_ipd, OERNeg => OERNeg_ipd, RWL => RWL_ipd, RWR => RWR_ipd, CELNeg => CELNeg_ipd, CERNeg => CERNeg_ipd, BUSYLNeg => BUSYLNeg, BUSYRNeg => BUSYRNeg, INTLNeg => INTLNeg, INTRNeg => INTRNeg ); SIGNAL IOL_zd : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); SIGNAL IOR_zd : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); SIGNAL IOL_pass: std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); SIGNAL IOR_pass: std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); SIGNAL INTLNeg_zd : std_logic := '1'; SIGNAL INTRNeg_zd : std_logic := '1'; SIGNAL INTLNeg_t : std_logic := '1'; SIGNAL INTRNeg_t : std_logic := '1'; SIGNAL RRead : std_logic := '0'; SIGNAL LRead : std_logic := '0'; SIGNAL RWrite : std_logic := '0'; SIGNAL LWrite : std_logic := '0'; SIGNAL SetIntR : std_logic := '0'; SIGNAL SetIntL : std_logic := '0'; SIGNAL ClearIntR : std_logic := '0'; SIGNAL ClearIntL : std_logic := '0'; SIGNAL reinvoke : std_logic := '0'; SIGNAL ALIn_t : std_logic_vector(HiAbit DOWNTO 0); SIGNAL ARIn_t : std_logic_vector(HiAbit DOWNTO 0); SIGNAL IOLIn_t : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IORIn_t : std_logic_vector(HiDbit DOWNTO 0); SIGNAL ToggleWR : BOOLEAN := FALSE; SIGNAL ToggleWL : BOOLEAN := FALSE; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER RANGE 0 TO MaxData; SHARED VARIABLE MemData : MemStore := (OTHERS => 0); SIGNAL Viol : X01 := '0'; -- tpd enable variable SHARED VARIABLE tpd_CER : BOOLEAN := FALSE; SHARED VARIABLE tpd_OER : BOOLEAN := FALSE; SHARED VARIABLE tpd_CEL : BOOLEAN := FALSE; SHARED VARIABLE tpd_OEL : BOOLEAN := FALSE; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- VITALTimingCheck: PROCESS(CELNeg, CERNeg, RWL, RWR, OELNeg, OERNeg, INTLNeg_t,INTRNeg_t, ALIn, ARIn, IOLIn, IORIn, BUSYLNeg, BUSYRNeg) --Setup/Hold checks variables VARIABLE Tviol_RWR_BUSYRNeg : X01 := '0'; VARIABLE Tviol_RWL_BUSYLNeg : X01 := '0'; VARIABLE Tviol_AL_OELNeg : X01 := '0'; VARIABLE Tviol_AR_OERNeg : X01 := '0'; VARIABLE Tviol_AR_RWR_s : X01 := '0'; VARIABLE Tviol_AL_RWL_s : X01 := '0'; VARIABLE Tviol_AL_CELNeg_s : X01 := '0'; VARIABLE Tviol_AR_CERNeg_s : X01 := '0'; VARIABLE Tviol_AL_CELNeg : X01 := '0'; VARIABLE Tviol_AR_CERNeg : X01 := '0'; VARIABLE Tviol_CELNeg_RWL : X01 := '0'; VARIABLE Tviol_CERNeg_RWR : X01 := '0'; VARIABLE Tviol_BUSYRNeg_RWL : X01 := '0'; VARIABLE Tviol_BUSYLNeg_RWR : X01 := '0'; VARIABLE Tviol_AL_RWL : X01 := '0'; VARIABLE Tviol_AR_RWR : X01 := '0'; VARIABLE Tviol_IOL0_CELNeg : X01 := '0'; VARIABLE Tviol_IOR_CERNeg : X01 := '0'; VARIABLE Tviol_IOL0_RWL : X01 := '0'; VARIABLE Tviol_IOR_RWR : X01 := '0'; VARIABLE TD_RWR_BUSYRNeg : VitalTimingDataType; VARIABLE TD_RWL_BUSYLNeg : VitalTimingDataType; VARIABLE TD_AL_OELNeg : VitalTimingDataType; VARIABLE TD_AR_OERNeg : VitalTimingDataType; VARIABLE TD_AR_RWR_s : VitalTimingDataType; VARIABLE TD_AL_RWL_s : VitalTimingDataType; VARIABLE TD_AL_CELNeg_s : VitalTimingDataType; VARIABLE TD_AR_CERNeg_s : VitalTimingDataType; VARIABLE TD_AL_CELNeg : VitalTimingDataType; VARIABLE TD_AR_CERNeg : VitalTimingDataType; VARIABLE TD_AL_RWL : VitalTimingDataType; VARIABLE TD_AR_RWR : VitalTimingDataType; VARIABLE TD_CELNeg_RWL : VitalTimingDataType; VARIABLE TD_CERNeg_RWR : VitalTimingDataType; VARIABLE TD_BUSYRNeg_RWL : VitalTimingDataType; VARIABLE TD_BUSYLNeg_RWR : VitalTimingDataType; VARIABLE TD_IOL0_CELNeg : VitalTimingDataType; VARIABLE TD_IOR_CERNeg : VitalTimingDataType; VARIABLE TD_IOL0_RWL : VitalTimingDataType; VARIABLE TD_IOR_RWR : VitalTimingDataType; -- Pulse width cheks variables VARIABLE Pviol_AL0 : X01 := '0'; VARIABLE Pviol_AL1 : X01 := '0'; VARIABLE Pviol_AL2 : X01 := '0'; VARIABLE Pviol_AL3 : X01 := '0'; VARIABLE Pviol_AL4 : X01 := '0'; VARIABLE Pviol_AL5 : X01 := '0'; VARIABLE Pviol_AL6 : X01 := '0'; VARIABLE Pviol_AL7 : X01 := '0'; VARIABLE Pviol_AL8 : X01 := '0'; VARIABLE Pviol_AL9 : X01 := '0'; VARIABLE Pviol_AL10 : X01 := '0'; VARIABLE Pviol_AR0 : X01 := '0'; VARIABLE Pviol_AR1 : X01 := '0'; VARIABLE Pviol_AR2 : X01 := '0'; VARIABLE Pviol_AR3 : X01 := '0'; VARIABLE Pviol_AR4 : X01 := '0'; VARIABLE Pviol_AR5 : X01 := '0'; VARIABLE Pviol_AR6 : X01 := '0'; VARIABLE Pviol_AR7 : X01 := '0'; VARIABLE Pviol_AR8 : X01 := '0'; VARIABLE Pviol_AR9 : X01 := '0'; VARIABLE Pviol_AR10 : X01 := '0'; VARIABLE Pviol_CELNeg : X01 := '0'; VARIABLE Pviol_CERNeg : X01 := '0'; VARIABLE Pviol_RWL : X01 := '0'; VARIABLE Pviol_RWR : X01 := '0'; VARIABLE PD_AL0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL3 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL4 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AL10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR3 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR4 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_AR10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_CELNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_CERNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_RWL : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE PD_RWR : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01; BEGIN IF TimingChecksOn THEN -- Setup/Hold Checks Violation := '0'; VitalSetupHoldCheck ( TestSignal => IOLIn, TestSignalName => "IOL", RefSignal => RWL, RefSignalName => "RWL", SetupLow => tsetup_IOL0_RWL, SetupHigh => tsetup_IOL0_RWL, HoldLow => thold_IOL0_RWL, HoldHigh => thold_IOL0_RWL, CheckEnabled => CELNeg = '0' AND OELNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOL0_RWL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL0_RWL ); VitalSetupHoldCheck ( TestSignal => IORIn, TestSignalName => "IOR", RefSignal => RWR, RefSignalName => "RWR", SetupLow => tsetup_IOL0_RWL, SetupHigh => tsetup_IOL0_RWL, HoldLow => thold_IOL0_RWL, HoldHigh => thold_IOL0_RWL, CheckEnabled => CERNeg = '0' AND OERNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOR_RWR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR_RWR ); VitalSetupHoldCheck ( TestSignal => IOLIn, TestSignalName => "IOL", RefSignal => CELNeg, RefSignalName => "CELNeg", SetupLow => tsetup_IOL0_RWL, SetupHigh => tsetup_IOL0_RWL, HoldLow => thold_IOL0_RWL, HoldHigh => thold_IOL0_RWL, CheckEnabled => RWL = '0' AND OELNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOL0_CELNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL0_CELNeg ); VitalSetupHoldCheck ( TestSignal => IORIn, TestSignalName => "IOR", RefSignal => CERNeg, RefSignalName => "CERNeg", SetupLow => tsetup_IOL0_RWL, SetupHigh => tsetup_IOL0_RWL, HoldLow => thold_IOL0_RWL, HoldHigh => thold_IOL0_RWL, CheckEnabled => RWR = '0' AND OERNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOR_CERNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR_CERNeg ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => RWL, RefSignalName => "RWL", SetupLow => tsetup_AL0_RWL, SetupHigh => tsetup_AL0_RWL, CheckEnabled => CELNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AL_RWL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_RWL ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => RWR, RefSignalName => "RWR", SetupLow => tsetup_AL0_RWL, SetupHigh => tsetup_AL0_RWL, CheckEnabled => CELNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AR_RWR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_RWR ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CELNeg, RefSignalName => "CELNeg", SetupLow => tsetup_AL0_RWL, SetupHigh => tsetup_AL0_RWL, CheckEnabled => RWL = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AL_CELNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_CELNeg ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CERNeg, RefSignalName => "CERNeg", SetupLow => tsetup_AL0_RWL, SetupHigh => tsetup_AL0_RWL, CheckEnabled => RWR = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AR_CERNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_CERNeg ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CELNeg, RefSignalName => "CELNeg", SetupLow => tsetup_AL0_CELNeg, SetupHigh => tsetup_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, HoldHigh => thold_AL0_CELNeg, CheckEnabled => RWL = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AL_CELNeg_s, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_CELNeg_s ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CELNeg, RefSignalName => "CELNeg", SetupLow => tsetup_AL0_CELNeg, SetupHigh => tsetup_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, HoldHigh => thold_AL0_CELNeg, CheckEnabled => RWR = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AR_CERNeg_s, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_CERNeg_s ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => RWL, RefSignalName => "RWL", SetupLow => tsetup_AL0_CELNeg, SetupHigh => tsetup_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, HoldHigh => thold_AL0_CELNeg, CheckEnabled => CELNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AL_RWL_s, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_RWL_s ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => RWR, RefSignalName => "RWR", SetupLow => tsetup_AL0_CELNeg, SetupHigh => tsetup_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, HoldHigh => thold_AL0_CELNeg, CheckEnabled => CERNeg = '0', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AR_RWR_s, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_RWR_s ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => OELNeg, RefSignalName => "OELNeg", SetupLow => tsetup_AL0_OELNeg, SetupHigh => tsetup_AL0_OELNeg, CheckEnabled => INTRNeg_t = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AL_OELNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_OELNeg ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => OERNeg, RefSignalName => "OERNeg", SetupLow => tsetup_AL0_OELNeg, SetupHigh => tsetup_AL0_OELNeg, CheckEnabled => INTLNeg_t = '0', RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_AR_OERNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_OERNeg ); VitalSetupHoldCheck ( TestSignal => CELNeg, TestSignalName => "CELNeg", RefSignal => RWL, RefSignalName => "RWL", SetupLow => tsetup_CELNeg_RWL, CheckEnabled => LWrite = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CELNeg_RWL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CELNeg_RWL ); VitalSetupHoldCheck ( TestSignal => BUSYRNeg, TestSignalName => "BUSYRNeg", RefSignal => RWL, RefSignalName => "RWL", SetupLow => tsetup_BUSYRNeg_RWL, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_BUSYRNeg_RWL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BUSYRNeg_RWL ); VitalSetupHoldCheck ( TestSignal => BUSYLNeg, TestSignalName => "BUSYLNeg", RefSignal => RWR, RefSignalName => "RWR", SetupLow => tsetup_BUSYRNeg_RWL, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_BUSYLNeg_RWR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BUSYLNeg_RWR ); VitalSetupHoldCheck ( TestSignal => CERNeg, TestSignalName => "CERNeg", RefSignal => RWR, RefSignalName => "RWR", SetupLow => tsetup_CELNeg_RWL, CheckEnabled => RWrite = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CERNeg_RWR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CERNeg_RWR ); VitalSetupHoldCheck ( TestSignal => RWL, TestSignalName => "RWL", RefSignal => BUSYLNeg, RefSignalName => "BUSYLNeg", HoldLow => thold_RWL_BUSYLNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RWL_BUSYLNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWL_BUSYLNeg ); VitalSetupHoldCheck ( TestSignal => RWR, TestSignalName => "RWR", RefSignal => BUSYRNeg, RefSignalName => "BUSYRNeg", HoldLow => thold_RWL_BUSYLNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RWR_BUSYRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWR_BUSYRNeg ); VitalPeriodPulseCheck ( TestSignal => CELNeg, TestSignalName => "CELNeg", PulseWidthLow => tsetup_CELNeg_RWL, CheckEnabled => RWL = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_CELNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CELNeg ); VitalPeriodPulseCheck ( TestSignal => CERNeg, TestSignalName => "CERNeg", PulseWidthLow => tsetup_CELNeg_RWL, CheckEnabled => RWR = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_CERNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CERNeg ); VitalPeriodPulseCheck ( TestSignal => RWL, TestSignalName => "RWL", PulseWidthLow => tpw_RWL_negedge, CheckEnabled => CELNeg = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_RWL, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RWL ); VitalPeriodPulseCheck ( TestSignal => RWR, TestSignalName => "RWR", PulseWidthLow => tpw_RWL_negedge, CheckEnabled => CERNeg = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_RWR, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RWR ); VitalPeriodPulseCheck ( TestSignal => ALIn(0), TestSignalName => "Address 0", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL0, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL0 ); VitalPeriodPulseCheck ( TestSignal => ALIn(1), TestSignalName => "Address 1", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL1 ); VitalPeriodPulseCheck ( TestSignal => ALIn(2), TestSignalName => "Address 2", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL2 ); VitalPeriodPulseCheck ( TestSignal => ALIn(3), TestSignalName => "Address 3", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL3, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL3 ); VitalPeriodPulseCheck ( TestSignal => ALIn(4), TestSignalName => "Address 4", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL4, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL4 ); VitalPeriodPulseCheck ( TestSignal => ALIn(5), TestSignalName => "Address 5", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL5, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL5 ); VitalPeriodPulseCheck ( TestSignal => ALIn(6), TestSignalName => "Address 6", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL6, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL6 ); VitalPeriodPulseCheck ( TestSignal => ALIn(7), TestSignalName => "Address 7", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL7, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL7 ); VitalPeriodPulseCheck ( TestSignal => ALIn(8), TestSignalName => "Address 8", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL8, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL8 ); VitalPeriodPulseCheck ( TestSignal => ALIn(9), TestSignalName => "Address 9", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL9, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL9 ); VitalPeriodPulseCheck ( TestSignal => ALIn(10), TestSignalName => "Address 10", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AL10, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AL10 ); VitalPeriodPulseCheck ( TestSignal => ARIn(0), TestSignalName => "Address 0", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR0, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR0 ); VitalPeriodPulseCheck ( TestSignal => ARIn(1), TestSignalName => "Address 1", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR1 ); VitalPeriodPulseCheck ( TestSignal => ARIn(2), TestSignalName => "Address 2", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR2 ); VitalPeriodPulseCheck ( TestSignal => ARIn(3), TestSignalName => "Address 3", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR3, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR3 ); VitalPeriodPulseCheck ( TestSignal => ARIn(4), TestSignalName => "Address 4", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR4, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR4 ); VitalPeriodPulseCheck ( TestSignal => ARIn(5), TestSignalName => "Address 5", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR5, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR5 ); VitalPeriodPulseCheck ( TestSignal => ARIn(6), TestSignalName => "Address 6", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR6, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR6 ); VitalPeriodPulseCheck ( TestSignal => ARIn(7), TestSignalName => "Address 7", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR7, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR7 ); VitalPeriodPulseCheck ( TestSignal => ARIn(8), TestSignalName => "Address 8", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR8, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR8 ); VitalPeriodPulseCheck ( TestSignal => ARIn(9), TestSignalName => "Address 9", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR9, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR9 ); VitalPeriodPulseCheck ( TestSignal => ARIn(10), TestSignalName => "Address 10", PulseWidthLow => tpw_AL0_negedge, PulseWidthHigh => tpw_AL0_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_AR10, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_AR10 ); Violation := Tviol_RWR_BUSYRNeg OR Tviol_RWL_BUSYLNeg OR Tviol_AL_OELNeg OR Tviol_AR_OERNeg OR Tviol_AR_RWR_s OR Tviol_AL_RWL_s OR Tviol_AL_CELNeg_s OR Tviol_AR_CERNeg_s OR Tviol_AL_CELNeg OR Tviol_AR_CERNeg OR Tviol_AL_RWL OR Tviol_AR_RWR OR Tviol_CELNeg_RWL OR Tviol_BUSYRNeg_RWL OR Tviol_BUSYLNeg_RWR OR Tviol_CERNeg_RWR OR Tviol_IOL0_CELNeg OR Tviol_IOR_CERNeg OR Tviol_IOL0_RWL OR Tviol_IOR_RWR OR Pviol_AL0 OR Pviol_AL1 OR Pviol_AL2 OR Pviol_AL3 OR Pviol_AL4 OR Pviol_AL5 OR Pviol_AL6 OR Pviol_AL7 OR Pviol_AL8 OR Pviol_AL9 OR Pviol_AL10 OR Pviol_AR0 OR Pviol_AR1 OR Pviol_AR2 OR Pviol_AR3 OR Pviol_AR4 OR Pviol_AR5 OR Pviol_AR6 OR Pviol_AR7 OR Pviol_AR8 OR Pviol_AR9 OR Pviol_AR10 OR Pviol_CELNeg OR Pviol_CERNeg OR Pviol_RWL OR Pviol_RWR; ASSERT Violation = '0' REPORT InstancePath & partID & " simulation may be inaccurate due to timing violations" SEVERITY WARNING; viol <= violation; END IF; -- TimingChecksOn END PROCESS VITALTimingCheck; -------------------------------------------------------------------- -- Control Process -------------------------------------------------------------------- SRAM_COMMAND : PROCESS(CELNeg, OELNeg, RWL, CERNeg, OERNeg, RWR, ALIn, ARIn) BEGIN RRead <= '0'; LRead <= '0'; RWrite <= '0'; LWrite <= '0'; IF CELNeg = '0' THEN IF RWL = '0' THEN IF BUSYLNeg /= '0'THEN LWrite <= '1'; ELSE LWrite <= '0'; END IF; ELSIF RWL = '1' AND OELNeg = '0' THEN LRead <= '1'; END IF; END IF; IF CERNeg = '0' THEN IF RWR = '0' THEN IF BUSYRNeg /= '0'THEN RWrite <= '1'; ELSE RWrite <= '0'; END IF; ELSIF RWR = '1' AND OERNeg = '0' THEN RRead <= '1'; END IF; END IF; END PROCESS SRAM_COMMAND; -------------------------------------------------------------------- -- Write Process -------------------------------------------------------------------- ToggleW : PROCESS(RWR, RWL) BEGIN IF falling_edge(RWR) THEN ToggleWR <= NOT ToggleWR; END IF; IF falling_edge(RWL) THEN ToggleWL <= NOT ToggleWL; END IF; END PROCESS ToggleW; -- delay 1 ns because hold time is 0 ns for write cycle ALIn_t <= ALIn AFTER 1 ns; ARIn_t <= ARIn AFTER 1 ns; IOLIn_t <= IOLIn AFTER 1 ns; IORIn_t <= IORIn AFTER 1 ns; WriteP : PROCESS(LWrite, RWrite) VARIABLE Address : INTEGER RANGE 0 TO TotalLOC:= 0; VARIABLE Data : INTEGER RANGE 0 TO MaxData:= 0; VARIABLE tDD : TIME := 0 ns; VARIABLE tWD : TIME := 0 ns; BEGIN IF falling_edge(LWrite) THEN Address := to_nat(ALIn_t); Data := to_nat(IOLIn_t); MemData(Address) := Data; IF Address = 16#7FF# AND InterruptEnable THEN SetIntR <= '1', '0' AFTER 1 ns; END IF; IF BUSYRNeg = '0' THEN tDD := -IOLIn'LAST_EVENT + tdevice_TDDD; tWD := -ToggleWL'LAST_EVENT + tdevice_TWDD; IF tDD >= tWD AND tDD > 0 ns THEN reinvoke <= '1' AFTER tDD, '0' AFTER tDD + 1 ns; ELSIF tWD >= tWD AND tWD > 0 ns THEN reinvoke <= '1' AFTER tWD, '0' AFTER tWD + 1 ns; ELSE reinvoke <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; IF falling_edge(RWrite) THEN Address := to_nat(ARIn_t); Data := to_nat(IORIn_t); MemData(Address) := Data; IF Address = 16#7FE# AND InterruptEnable THEN SetIntL <= '1', '0' AFTER 1 ns; END IF; IF BUSYLNeg = '0' THEN tDD := -IORIn'LAST_EVENT + tdevice_TDDD; tWD := -ToggleWR'LAST_EVENT + tdevice_TWDD; IF tDD >= tWD AND tDD > 0 ns THEN reinvoke <= '1' AFTER tDD, '0' AFTER tDD + 1 ns; ELSIF tWD >= tWD AND tWD > 0 ns THEN reinvoke <= '1' AFTER tWD, '0' AFTER tWD + 1 ns; ELSE reinvoke <= '1', '0' AFTER 1 ns; END IF; END IF; END IF; END PROCESS WriteP; -------------------------------------------------------------------- -- Read Process -------------------------------------------------------------------- ReadL : PROCESS(LRead, ALIn, reinvoke) VARIABLE Address : INTEGER := 0; VARIABLE Data : INTEGER := 0; BEGIN IF LRead = '1' THEN Address := to_nat(ALIn); IOL_zd <= to_slv(MemData(Address), DataWidth); IF Address = 16#7FE# THEN ClearIntL <= '1', '0' AFTER 1 ns; END IF; ELSE IOL_zd <= (OTHERS => 'Z'); END IF; END PROCESS ReadL; ReadR : PROCESS(RRead, ARIn, reinvoke) VARIABLE Address : INTEGER := 0; VARIABLE Data : INTEGER := 0; BEGIN IF RRead = '1' THEN Address := to_nat(ARIn); IOR_zd <= to_slv(MemData(Address), DataWidth); IF Address = 16#7FF# THEN ClearIntR <= '1', '0' AFTER 1 ns; END IF; ELSE IOR_zd <= (OTHERS => 'Z'); END IF; END PROCESS ReadR; ---------------------------------------------------------------------- ---- Interrupt section ---------------------------------------------------------------------- InterruptProc : PROCESS(ClearIntR, ClearIntL, SetIntR, SetIntL) BEGIN IF rising_edge(SetIntR) THEN INTRNeg_zd <= '0'; END IF; IF rising_edge(SetIntL) THEN INTLNeg_zd <= '0'; END IF; IF rising_edge(ClearIntL) THEN INTLNeg_zd <= '1'; END IF; IF rising_edge(ClearIntR) THEN INTRNeg_zd <= '1'; END IF; END PROCESS InterruptProc; ----------------------------------------------------------------------- ---- File read Section - Preload Control ----------------------------------------------------------------------- MemPreload : PROCESS -- text file input variables FILE mem_f : text is mem_file_name; VARIABLE addr_ind : NATURAL; VARIABLE buf : line; VARIABLE line : NATURAL :=0; VARIABLE report_err : BOOLEAN := FALSE; BEGIN ---------------------------------------------------------------------- -- idt71421 memory preload file format -- / - comment -- @aaa - stands for address within sector -- dd -
is word to be written at Mem(aaa++) -- (aaa is incremented at every load) -- only first 1-4 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ---------------------------------------------------------------------- IF UserPreload AND (mem_file_name /= "none" ) THEN MemData := (OTHERS => 0); addr_ind := 0; WHILE (not ENDFILE (mem_f)) LOOP READLINE (mem_f, buf); line := line +1; IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN addr_ind := h(buf(2 to 4)); ELSE IF addr_ind <= TotalLOC THEN MemData(addr_ind):= h(buf(1 to 2)); addr_ind := (addr_ind + 1); ELSE IF report_err = FALSE THEN REPORT "Memory file:" & mem_file_name & " Address range overflow"& " at line "&to_int_str(line) SEVERITY warning; report_err := TRUE; END IF; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS; IOLPassThrough : PROCESS(IOL_zd) VARIABLE tOLD : time := 0 ns; VARIABLE tCLD : time := 0 ns; VARIABLE tALD : time := 0 ns; VARIABLE IOL_x : std_logic_vector(HiDbit DOWNTO 0); BEGIN IOL_x := (OTHERS => 'X'); IF IOL_zd(0) /= 'Z' THEN tpd_OEL := FALSE; tpd_CEL := FALSE; tOLD := -OELNeg'LAST_EVENT + tpd_OELNeg_IOL0(trz1); tCLD := -CELNeg'LAST_EVENT + tpd_CELNeg_IOL0(trz1); tALD := -ALIn'LAST_EVENT + tpd_AL0_IOL0(tr01); IF tOLD >= tCLD AND tOLD > 0 ns THEN tpd_OEL := TRUE; ELSIF tCLD >= tOLD AND tCLD > 0 ns THEN tpd_CEL := TRUE; END IF; IF tALD > 0 ns AND ((tALD >= tOLD AND tpd_OEL = TRUE) OR (tALD >= tCLD AND tpd_CEL = TRUE)) THEN IOL_pass <= IOL_x, IOL_zd AFTER tALD; ELSE IOL_pass <= IOL_zd; END IF; ELSE tpd_OEL := TRUE; tpd_CEL := TRUE; IOL_Pass <= IOL_zd; END IF; END PROCESS IOLPassThrough; IORPassThrough : PROCESS(IOR_zd) VARIABLE tORD : time := 0 ns; VARIABLE tCRD : time := 0 ns; VARIABLE tARD : time := 0 ns; VARIABLE IOR_x : std_logic_vector(HiDbit DOWNTO 0); BEGIN IOR_x := (OTHERS => 'X'); IF IOR_zd(0) /= 'Z' THEN tpd_OER := FALSE; tpd_CER := FALSE; tORD := -OERNeg'LAST_EVENT + tpd_OELNeg_IOL0(trz1); tCRD := -CERNeg'LAST_EVENT + tpd_CELNeg_IOL0(trz1); tARD := -ARIn'LAST_EVENT + tpd_AL0_IOL0(tr01); IF tORD >= tCRD AND tORD > 0 ns THEN tpd_OER := TRUE; ELSIF tCRD >= tORD AND tCRD > 0 ns THEN tpd_CER := TRUE; END IF; IF tARD > 0 ns AND ((tARD >= tORD AND tpd_OER = TRUE) OR (tARD >= tCRD AND tpd_CER = TRUE)) THEN IOR_pass <= IOR_x, IOR_zd AFTER tARD; ELSE IOR_pass <= IOR_zd; END IF; ELSE tpd_OER := TRUE; tpd_CER := TRUE; IOR_Pass <= IOR_zd; END IF; END PROCESS IORPassThrough; ----------------------------------------------------------------------- -- Path Delay Section for Interrupt ----------------------------------------------------------------------- INTL_OUT: PROCESS(INTLNeg_zd) VARIABLE INTLNeg_GlitchData : VitalGlitchDataType; VARIABLE INT_var : std_logic := 'Z'; BEGIN IF INTLNeg_zd = '0' THEN INT_var := '0'; ELSE INT_var := 'Z'; END IF; VitalPathDelay01Z( OutSignal => INTLNeg_t, OutSignalName => "INTLNeg", OutTemp => INT_var, Mode => VitalTransport, GlitchData => INTLNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RWR'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 1 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 2 => (InputChangeTime => OELNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE)) ); END PROCESS INTL_Out; INTLNeg <= INTLNeg_t; INTR_OUT: PROCESS(INTRNeg_zd) VARIABLE INTRNeg_GlitchData : VitalGlitchDataType; VARIABLE INT_var : std_logic := 'Z'; BEGIN IF INTRNeg_zd = '0' THEN INT_var := '0'; ELSE INT_var := 'Z'; END IF; VitalPathDelay01Z( OutSignal => INTRNeg_t, OutSignalName => "INTRNeg", OutTemp => INT_var, Mode => VitalTransport, GlitchData => INTRNeg_GlitchData, Paths => ( 0 => (InputChangeTime => RWL'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 1 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 2 => (InputChangeTime => OERNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE)) ); END PROCESS INTR_OUT; INTRNeg <= INTRNeg_t; ----------------------------------------------------------------------- -- Path Delay Processes generated as a function of data width ----------------------------------------------------------------------- DataOutR_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOutR_Delay : PROCESS (IOR_pass(i)) VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => IOROut(i), OutSignalName => "IOR", OutTemp => IOR_pass(i), Mode => OnEvent, GlitchData => IOR_GlitchData(i), Paths => ( 0 => (InputChangeTime => OERNeg'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => tpd_OER), 1 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_CELNeg_IOL0, PathCondition => tpd_CER), 2 => (InputChangeTime => RWR'LAST_EVENT, PathDelay => tpd_RWL_IOL0, PathCondition => TRUE), 3 => (InputChangeTime => ARIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_AL0_IOL0), PathCondition => NOT (tpd_CER OR tpd_OER)) ) ); END PROCESS DataOutR_Delay; END GENERATE; DataOutL_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOutL_Delay : PROCESS (IOL_pass(i)) VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => IOLOut(i), OutSignalName => "IOL", OutTemp => IOL_pass(i), Mode => OnEvent, GlitchData => IOL_GlitchData(i), Paths => ( 0 => (InputChangeTime => OELNeg'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => tpd_OEL), 1 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_CELNeg_IOL0, PathCondition => tpd_CEL), 2 => (InputChangeTime => RWL'LAST_EVENT, PathDelay => tpd_RWL_IOL0, PathCondition => TRUE), 3 => (InputChangeTime => ALIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_AL0_IOL0), PathCondition => NOT (tpd_CEL OR tpd_OEL)) ) ); END PROCESS DataOutL_Delay; END GENERATE; END BLOCK; END vhdl_behavioral;