-------------------------------------------------------------------------------- -- File Name: idt70v5388.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2003-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -------------------------------------------------------------------------------- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 M.Radmanovic 03 Aug 28 Inital Release -- V1.1 R. Munden 08 Jul 31 corrected VITAL generic names -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: -- Part: IDT70V5388 -- -- Description: 64K x 18 SYNCHRONOUS FOURPORT STATIC RAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.vital_timing.ALL; USE IEEE.vital_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt70v5388 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A15P1 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A15P2 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A15P3 : VitalDelayType01 := VitalZeroDelay01; tipd_A0P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A2P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A3P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A4P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A6P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A7P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A8P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A9P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A10P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A11P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A12P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A13P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A14P4 : VitalDelayType01 := VitalZeroDelay01; tipd_A15P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO8P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO9P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO10P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO11P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO12P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO13P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO14P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO15P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO16P4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO17P4 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP1 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP2 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP3 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKP4 : VitalDelayType01 := VitalZeroDelay01; tipd_MRSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RWP1 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP2 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP3 : VitalDelayType01 := VitalZeroDelay01; tipd_RWP4 : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0P4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P1 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P2 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P3 : VitalDelayType01 := VitalZeroDelay01; tipd_CE1P4 : VitalDelayType01 := VitalZeroDelay01; tipd_OEP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OEP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_UBP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_LBP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTLDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTINCP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKLDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKLDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKLDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKLDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKRDP1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKRDP2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKRDP3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_MKRDP4Neg : VitalDelayType01 := VitalZeroDelay01; tipd_TMS : VitalDelayType01 := VitalZeroDelay01; tipd_TRSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_TCK : VitalDelayType01 := VitalZeroDelay01; tipd_TDI : VitalDelayType01 := VitalZeroDelay01; tipd_CLKMBIST : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_TCK_TDO : VitalDelayType01 := UnitDelay01; tpd_CLKP1_IO0P1 : VitalDelayType01Z := UnitDelay01Z; tpd_CLKP1_A0P1 : VitalDelayType01 := UnitDelay01; tpd_CLKP1_INTP1Neg : VitalDelayType01 := UnitDelay01; tpd_CLKP1_CNTINTP1Neg : VitalDelayType01 := UnitDelay01; tpd_OEP1Neg_IO0P1 : VitalDelayType01Z := UnitDelay01Z; tpd_MRSTNeg_INTP1Neg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths tpw_CLKP1_posedge : VitalDelayType := UnitDelay; tpw_CLKP1_negedge : VitalDelayType := UnitDelay; tpw_TCK_posedge : VitalDelayType := UnitDelay; tpw_TCK_negedge : VitalDelayType := UnitDelay; tpw_MRSTNeg_negedge : VitalDelayType := UnitDelay; tpw_TRSTNeg_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) tperiod_CLKP1_posedge : VitalDelayType := UnitDelay; tperiod_TCK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_A0P1_CLKP1 : VitalDelayType := UnitDelay; tsetup_IO0P1_CLKP1 : VitalDelayType := UnitDelay; tsetup_RWP1_CLKP1 : VitalDelayType := UnitDelay; tsetup_CE1P1_CLKP1 : VitalDelayType := UnitDelay; tsetup_LBP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_CNTLDP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_CNTINCP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_CNTRSTP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_CNTRDP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_MKLDP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_MKRDP1Neg_CLKP1 : VitalDelayType := UnitDelay; tsetup_TDI_TCK : VitalDelayType := UnitDelay; -- thold values: hold times thold_A0P1_CLKP1 : VitalDelayType := UnitDelay; thold_IO0P1_CLKP1 : VitalDelayType := UnitDelay; thold_RWP1_CLKP1 : VitalDelayType := UnitDelay; thold_CE1P1_CLKP1 : VitalDelayType := UnitDelay; thold_LBP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_CNTLDP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_CNTINCP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_CNTRSTP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_CNTRDP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_MKLDP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_MKRDP1Neg_CLKP1 : VitalDelayType := UnitDelay; thold_TDI_TCK : VitalDelayType := UnitDelay; -- trecovery values : recovery times trecovery_MRSTNeg_CLKP1 : VitalDelayType := UnitDelay; trecovery_TRSTNeg_TCK : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays tdevice_TCCS : VitalDelayType := 5 ns; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING := "none"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A0P1 : INOUT std_logic := 'U'; A1P1 : INOUT std_logic := 'U'; A2P1 : INOUT std_logic := 'U'; A3P1 : INOUT std_logic := 'U'; A4P1 : INOUT std_logic := 'U'; A5P1 : INOUT std_logic := 'U'; A6P1 : INOUT std_logic := 'U'; A7P1 : INOUT std_logic := 'U'; A8P1 : INOUT std_logic := 'U'; A9P1 : INOUT std_logic := 'U'; A10P1 : INOUT std_logic := 'U'; A11P1 : INOUT std_logic := 'U'; A12P1 : INOUT std_logic := 'U'; A13P1 : INOUT std_logic := 'U'; A14P1 : INOUT std_logic := 'U'; A15P1 : INOUT std_logic := 'U'; A0P2 : INOUT std_logic := 'U'; A1P2 : INOUT std_logic := 'U'; A2P2 : INOUT std_logic := 'U'; A3P2 : INOUT std_logic := 'U'; A4P2 : INOUT std_logic := 'U'; A5P2 : INOUT std_logic := 'U'; A6P2 : INOUT std_logic := 'U'; A7P2 : INOUT std_logic := 'U'; A8P2 : INOUT std_logic := 'U'; A9P2 : INOUT std_logic := 'U'; A10P2 : INOUT std_logic := 'U'; A11P2 : INOUT std_logic := 'U'; A12P2 : INOUT std_logic := 'U'; A13P2 : INOUT std_logic := 'U'; A14P2 : INOUT std_logic := 'U'; A15P2 : INOUT std_logic := 'U'; A0P3 : INOUT std_logic := 'U'; A1P3 : INOUT std_logic := 'U'; A2P3 : INOUT std_logic := 'U'; A3P3 : INOUT std_logic := 'U'; A4P3 : INOUT std_logic := 'U'; A5P3 : INOUT std_logic := 'U'; A6P3 : INOUT std_logic := 'U'; A7P3 : INOUT std_logic := 'U'; A8P3 : INOUT std_logic := 'U'; A9P3 : INOUT std_logic := 'U'; A10P3 : INOUT std_logic := 'U'; A11P3 : INOUT std_logic := 'U'; A12P3 : INOUT std_logic := 'U'; A13P3 : INOUT std_logic := 'U'; A14P3 : INOUT std_logic := 'U'; A15P3 : INOUT std_logic := 'U'; A0P4 : INOUT std_logic := 'U'; A1P4 : INOUT std_logic := 'U'; A2P4 : INOUT std_logic := 'U'; A3P4 : INOUT std_logic := 'U'; A4P4 : INOUT std_logic := 'U'; A5P4 : INOUT std_logic := 'U'; A6P4 : INOUT std_logic := 'U'; A7P4 : INOUT std_logic := 'U'; A8P4 : INOUT std_logic := 'U'; A9P4 : INOUT std_logic := 'U'; A10P4 : INOUT std_logic := 'U'; A11P4 : INOUT std_logic := 'U'; A12P4 : INOUT std_logic := 'U'; A13P4 : INOUT std_logic := 'U'; A14P4 : INOUT std_logic := 'U'; A15P4 : INOUT std_logic := 'U'; IO0P1 : INOUT std_logic := 'U'; IO1P1 : INOUT std_logic := 'U'; IO2P1 : INOUT std_logic := 'U'; IO3P1 : INOUT std_logic := 'U'; IO4P1 : INOUT std_logic := 'U'; IO5P1 : INOUT std_logic := 'U'; IO6P1 : INOUT std_logic := 'U'; IO7P1 : INOUT std_logic := 'U'; IO8P1 : INOUT std_logic := 'U'; IO9P1 : INOUT std_logic := 'U'; IO10P1 : INOUT std_logic := 'U'; IO11P1 : INOUT std_logic := 'U'; IO12P1 : INOUT std_logic := 'U'; IO13P1 : INOUT std_logic := 'U'; IO14P1 : INOUT std_logic := 'U'; IO15P1 : INOUT std_logic := 'U'; IO16P1 : INOUT std_logic := 'U'; IO17P1 : INOUT std_logic := 'U'; IO0P2 : INOUT std_logic := 'U'; IO1P2 : INOUT std_logic := 'U'; IO2P2 : INOUT std_logic := 'U'; IO3P2 : INOUT std_logic := 'U'; IO4P2 : INOUT std_logic := 'U'; IO5P2 : INOUT std_logic := 'U'; IO6P2 : INOUT std_logic := 'U'; IO7P2 : INOUT std_logic := 'U'; IO8P2 : INOUT std_logic := 'U'; IO9P2 : INOUT std_logic := 'U'; IO10P2 : INOUT std_logic := 'U'; IO11P2 : INOUT std_logic := 'U'; IO12P2 : INOUT std_logic := 'U'; IO13P2 : INOUT std_logic := 'U'; IO14P2 : INOUT std_logic := 'U'; IO15P2 : INOUT std_logic := 'U'; IO16P2 : INOUT std_logic := 'U'; IO17P2 : INOUT std_logic := 'U'; IO0P3 : INOUT std_logic := 'U'; IO1P3 : INOUT std_logic := 'U'; IO2P3 : INOUT std_logic := 'U'; IO3P3 : INOUT std_logic := 'U'; IO4P3 : INOUT std_logic := 'U'; IO5P3 : INOUT std_logic := 'U'; IO6P3 : INOUT std_logic := 'U'; IO7P3 : INOUT std_logic := 'U'; IO8P3 : INOUT std_logic := 'U'; IO9P3 : INOUT std_logic := 'U'; IO10P3 : INOUT std_logic := 'U'; IO11P3 : INOUT std_logic := 'U'; IO12P3 : INOUT std_logic := 'U'; IO13P3 : INOUT std_logic := 'U'; IO14P3 : INOUT std_logic := 'U'; IO15P3 : INOUT std_logic := 'U'; IO16P3 : INOUT std_logic := 'U'; IO17P3 : INOUT std_logic := 'U'; IO0P4 : INOUT std_logic := 'U'; IO1P4 : INOUT std_logic := 'U'; IO2P4 : INOUT std_logic := 'U'; IO3P4 : INOUT std_logic := 'U'; IO4P4 : INOUT std_logic := 'U'; IO5P4 : INOUT std_logic := 'U'; IO6P4 : INOUT std_logic := 'U'; IO7P4 : INOUT std_logic := 'U'; IO8P4 : INOUT std_logic := 'U'; IO9P4 : INOUT std_logic := 'U'; IO10P4 : INOUT std_logic := 'U'; IO11P4 : INOUT std_logic := 'U'; IO12P4 : INOUT std_logic := 'U'; IO13P4 : INOUT std_logic := 'U'; IO14P4 : INOUT std_logic := 'U'; IO15P4 : INOUT std_logic := 'U'; IO16P4 : INOUT std_logic := 'U'; IO17P4 : INOUT std_logic := 'U'; CLKP1 : IN std_logic := 'U'; CLKP2 : IN std_logic := 'U'; CLKP3 : IN std_logic := 'U'; CLKP4 : IN std_logic := 'U'; MRSTNeg : IN std_logic := 'U'; RWP1 : IN std_logic := 'U'; RWP2 : IN std_logic := 'U'; RWP3 : IN std_logic := 'U'; RWP4 : IN std_logic := 'U'; CE0P1Neg : IN std_logic := 'U'; CE0P2Neg : IN std_logic := 'U'; CE0P3Neg : IN std_logic := 'U'; CE0P4Neg : IN std_logic := 'U'; CE1P1 : IN std_logic := 'U'; CE1P2 : IN std_logic := 'U'; CE1P3 : IN std_logic := 'U'; CE1P4 : IN std_logic := 'U'; OEP1Neg : IN std_logic := 'U'; OEP2Neg : IN std_logic := 'U'; OEP3Neg : IN std_logic := 'U'; OEP4Neg : IN std_logic := 'U'; UBP1Neg : IN std_logic := 'U'; UBP2Neg : IN std_logic := 'U'; UBP3Neg : IN std_logic := 'U'; UBP4Neg : IN std_logic := 'U'; LBP1Neg : IN std_logic := 'U'; LBP2Neg : IN std_logic := 'U'; LBP3Neg : IN std_logic := 'U'; LBP4Neg : IN std_logic := 'U'; CNTLDP1Neg : IN std_logic := 'U'; CNTLDP2Neg : IN std_logic := 'U'; CNTLDP3Neg : IN std_logic := 'U'; CNTLDP4Neg : IN std_logic := 'U'; CNTINCP1Neg : IN std_logic := 'U'; CNTINCP2Neg : IN std_logic := 'U'; CNTINCP3Neg : IN std_logic := 'U'; CNTINCP4Neg : IN std_logic := 'U'; CNTRDP1Neg : IN std_logic := 'U'; CNTRDP2Neg : IN std_logic := 'U'; CNTRDP3Neg : IN std_logic := 'U'; CNTRDP4Neg : IN std_logic := 'U'; CNTRSTP1Neg : IN std_logic := 'U'; CNTRSTP2Neg : IN std_logic := 'U'; CNTRSTP3Neg : IN std_logic := 'U'; CNTRSTP4Neg : IN std_logic := 'U'; CNTINTP1Neg : OUT std_logic := 'U'; CNTINTP2Neg : OUT std_logic := 'U'; CNTINTP3Neg : OUT std_logic := 'U'; CNTINTP4Neg : OUT std_logic := 'U'; MKLDP1Neg : IN std_logic := 'U'; MKLDP2Neg : IN std_logic := 'U'; MKLDP3Neg : IN std_logic := 'U'; MKLDP4Neg : IN std_logic := 'U'; MKRDP1Neg : IN std_logic := 'U'; MKRDP2Neg : IN std_logic := 'U'; MKRDP3Neg : IN std_logic := 'U'; MKRDP4Neg : IN std_logic := 'U'; INTP1Neg : OUT std_logic := 'U'; INTP2Neg : OUT std_logic := 'U'; INTP3Neg : OUT std_logic := 'U'; INTP4Neg : OUT std_logic := 'U'; TMS : IN std_logic := 'U'; TRSTNeg : IN std_logic := 'U'; TCK : IN std_logic := 'U'; TDI : IN std_logic := 'U'; TDO : OUT std_logic := 'U'; CLKMBIST : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt70v5388 : ENTITY IS TRUE; END idt70v5388; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt70v5388 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "idt70v5388"; SIGNAL A0P1_ipd : std_ulogic := 'U'; SIGNAL A1P1_ipd : std_ulogic := 'U'; SIGNAL A2P1_ipd : std_ulogic := 'U'; SIGNAL A3P1_ipd : std_ulogic := 'U'; SIGNAL A4P1_ipd : std_ulogic := 'U'; SIGNAL A5P1_ipd : std_ulogic := 'U'; SIGNAL A6P1_ipd : std_ulogic := 'U'; SIGNAL A7P1_ipd : std_ulogic := 'U'; SIGNAL A8P1_ipd : std_ulogic := 'U'; SIGNAL A9P1_ipd : std_ulogic := 'U'; SIGNAL A10P1_ipd : std_ulogic := 'U'; SIGNAL A11P1_ipd : std_ulogic := 'U'; SIGNAL A12P1_ipd : std_ulogic := 'U'; SIGNAL A13P1_ipd : std_ulogic := 'U'; SIGNAL A14P1_ipd : std_ulogic := 'U'; SIGNAL A15P1_ipd : std_ulogic := 'U'; SIGNAL A16P1_ipd : std_ulogic := 'U'; SIGNAL A17P1_ipd : std_ulogic := 'U'; SIGNAL A0P2_ipd : std_ulogic := 'U'; SIGNAL A1P2_ipd : std_ulogic := 'U'; SIGNAL A2P2_ipd : std_ulogic := 'U'; SIGNAL A3P2_ipd : std_ulogic := 'U'; SIGNAL A4P2_ipd : std_ulogic := 'U'; SIGNAL A5P2_ipd : std_ulogic := 'U'; SIGNAL A6P2_ipd : std_ulogic := 'U'; SIGNAL A7P2_ipd : std_ulogic := 'U'; SIGNAL A8P2_ipd : std_ulogic := 'U'; SIGNAL A9P2_ipd : std_ulogic := 'U'; SIGNAL A10P2_ipd : std_ulogic := 'U'; SIGNAL A11P2_ipd : std_ulogic := 'U'; SIGNAL A12P2_ipd : std_ulogic := 'U'; SIGNAL A13P2_ipd : std_ulogic := 'U'; SIGNAL A14P2_ipd : std_ulogic := 'U'; SIGNAL A15P2_ipd : std_ulogic := 'U'; SIGNAL A0P3_ipd : std_ulogic := 'U'; SIGNAL A1P3_ipd : std_ulogic := 'U'; SIGNAL A2P3_ipd : std_ulogic := 'U'; SIGNAL A3P3_ipd : std_ulogic := 'U'; SIGNAL A4P3_ipd : std_ulogic := 'U'; SIGNAL A5P3_ipd : std_ulogic := 'U'; SIGNAL A6P3_ipd : std_ulogic := 'U'; SIGNAL A7P3_ipd : std_ulogic := 'U'; SIGNAL A8P3_ipd : std_ulogic := 'U'; SIGNAL A9P3_ipd : std_ulogic := 'U'; SIGNAL A10P3_ipd : std_ulogic := 'U'; SIGNAL A11P3_ipd : std_ulogic := 'U'; SIGNAL A12P3_ipd : std_ulogic := 'U'; SIGNAL A13P3_ipd : std_ulogic := 'U'; SIGNAL A14P3_ipd : std_ulogic := 'U'; SIGNAL A15P3_ipd : std_ulogic := 'U'; SIGNAL A0P4_ipd : std_ulogic := 'U'; SIGNAL A1P4_ipd : std_ulogic := 'U'; SIGNAL A2P4_ipd : std_ulogic := 'U'; SIGNAL A3P4_ipd : std_ulogic := 'U'; SIGNAL A4P4_ipd : std_ulogic := 'U'; SIGNAL A5P4_ipd : std_ulogic := 'U'; SIGNAL A6P4_ipd : std_ulogic := 'U'; SIGNAL A7P4_ipd : std_ulogic := 'U'; SIGNAL A8P4_ipd : std_ulogic := 'U'; SIGNAL A9P4_ipd : std_ulogic := 'U'; SIGNAL A10P4_ipd : std_ulogic := 'U'; SIGNAL A11P4_ipd : std_ulogic := 'U'; SIGNAL A12P4_ipd : std_ulogic := 'U'; SIGNAL A13P4_ipd : std_ulogic := 'U'; SIGNAL A14P4_ipd : std_ulogic := 'U'; SIGNAL A15P4_ipd : std_ulogic := 'U'; SIGNAL IO0P1_ipd : std_ulogic := 'U'; SIGNAL IO1P1_ipd : std_ulogic := 'U'; SIGNAL IO2P1_ipd : std_ulogic := 'U'; SIGNAL IO3P1_ipd : std_ulogic := 'U'; SIGNAL IO4P1_ipd : std_ulogic := 'U'; SIGNAL IO5P1_ipd : std_ulogic := 'U'; SIGNAL IO6P1_ipd : std_ulogic := 'U'; SIGNAL IO7P1_ipd : std_ulogic := 'U'; SIGNAL IO8P1_ipd : std_ulogic := 'U'; SIGNAL IO9P1_ipd : std_ulogic := 'U'; SIGNAL IO10P1_ipd : std_ulogic := 'U'; SIGNAL IO11P1_ipd : std_ulogic := 'U'; SIGNAL IO12P1_ipd : std_ulogic := 'U'; SIGNAL IO13P1_ipd : std_ulogic := 'U'; SIGNAL IO14P1_ipd : std_ulogic := 'U'; SIGNAL IO15P1_ipd : std_ulogic := 'U'; SIGNAL IO16P1_ipd : std_ulogic := 'U'; SIGNAL IO17P1_ipd : std_ulogic := 'U'; SIGNAL IO0P2_ipd : std_ulogic := 'U'; SIGNAL IO1P2_ipd : std_ulogic := 'U'; SIGNAL IO2P2_ipd : std_ulogic := 'U'; SIGNAL IO3P2_ipd : std_ulogic := 'U'; SIGNAL IO4P2_ipd : std_ulogic := 'U'; SIGNAL IO5P2_ipd : std_ulogic := 'U'; SIGNAL IO6P2_ipd : std_ulogic := 'U'; SIGNAL IO7P2_ipd : std_ulogic := 'U'; SIGNAL IO8P2_ipd : std_ulogic := 'U'; SIGNAL IO9P2_ipd : std_ulogic := 'U'; SIGNAL IO10P2_ipd : std_ulogic := 'U'; SIGNAL IO11P2_ipd : std_ulogic := 'U'; SIGNAL IO12P2_ipd : std_ulogic := 'U'; SIGNAL IO13P2_ipd : std_ulogic := 'U'; SIGNAL IO14P2_ipd : std_ulogic := 'U'; SIGNAL IO15P2_ipd : std_ulogic := 'U'; SIGNAL IO16P2_ipd : std_ulogic := 'U'; SIGNAL IO17P2_ipd : std_ulogic := 'U'; SIGNAL IO0P3_ipd : std_ulogic := 'U'; SIGNAL IO1P3_ipd : std_ulogic := 'U'; SIGNAL IO2P3_ipd : std_ulogic := 'U'; SIGNAL IO3P3_ipd : std_ulogic := 'U'; SIGNAL IO4P3_ipd : std_ulogic := 'U'; SIGNAL IO5P3_ipd : std_ulogic := 'U'; SIGNAL IO6P3_ipd : std_ulogic := 'U'; SIGNAL IO7P3_ipd : std_ulogic := 'U'; SIGNAL IO8P3_ipd : std_ulogic := 'U'; SIGNAL IO9P3_ipd : std_ulogic := 'U'; SIGNAL IO10P3_ipd : std_ulogic := 'U'; SIGNAL IO11P3_ipd : std_ulogic := 'U'; SIGNAL IO12P3_ipd : std_ulogic := 'U'; SIGNAL IO13P3_ipd : std_ulogic := 'U'; SIGNAL IO14P3_ipd : std_ulogic := 'U'; SIGNAL IO15P3_ipd : std_ulogic := 'U'; SIGNAL IO16P3_ipd : std_ulogic := 'U'; SIGNAL IO17P3_ipd : std_ulogic := 'U'; SIGNAL IO0P4_ipd : std_ulogic := 'U'; SIGNAL IO1P4_ipd : std_ulogic := 'U'; SIGNAL IO2P4_ipd : std_ulogic := 'U'; SIGNAL IO3P4_ipd : std_ulogic := 'U'; SIGNAL IO4P4_ipd : std_ulogic := 'U'; SIGNAL IO5P4_ipd : std_ulogic := 'U'; SIGNAL IO6P4_ipd : std_ulogic := 'U'; SIGNAL IO7P4_ipd : std_ulogic := 'U'; SIGNAL IO8P4_ipd : std_ulogic := 'U'; SIGNAL IO9P4_ipd : std_ulogic := 'U'; SIGNAL IO10P4_ipd : std_ulogic := 'U'; SIGNAL IO11P4_ipd : std_ulogic := 'U'; SIGNAL IO12P4_ipd : std_ulogic := 'U'; SIGNAL IO13P4_ipd : std_ulogic := 'U'; SIGNAL IO14P4_ipd : std_ulogic := 'U'; SIGNAL IO15P4_ipd : std_ulogic := 'U'; SIGNAL IO16P4_ipd : std_ulogic := 'U'; SIGNAL IO17P4_ipd : std_ulogic := 'U'; SIGNAL CLKP1_ipd : std_ulogic := 'U'; SIGNAL CLKP2_ipd : std_ulogic := 'U'; SIGNAL CLKP3_ipd : std_ulogic := 'U'; SIGNAL CLKP4_ipd : std_ulogic := 'U'; SIGNAL MRSTNeg_ipd : std_ulogic := 'U'; SIGNAL RWP1_ipd : std_ulogic := 'U'; SIGNAL RWP2_ipd : std_ulogic := 'U'; SIGNAL RWP3_ipd : std_ulogic := 'U'; SIGNAL RWP4_ipd : std_ulogic := 'U'; SIGNAL OEP1Neg_ipd : std_ulogic := 'U'; SIGNAL OEP2Neg_ipd : std_ulogic := 'U'; SIGNAL OEP3Neg_ipd : std_ulogic := 'U'; SIGNAL OEP4Neg_ipd : std_ulogic := 'U'; SIGNAL CE0P1Neg_ipd : std_ulogic := 'U'; SIGNAL CE0P2Neg_ipd : std_ulogic := 'U'; SIGNAL CE0P3Neg_ipd : std_ulogic := 'U'; SIGNAL CE0P4Neg_ipd : std_ulogic := 'U'; SIGNAL CE1P1_ipd : std_ulogic := 'U'; SIGNAL CE1P2_ipd : std_ulogic := 'U'; SIGNAL CE1P3_ipd : std_ulogic := 'U'; SIGNAL CE1P4_ipd : std_ulogic := 'U'; SIGNAL UBP1Neg_ipd : std_ulogic := 'U'; SIGNAL UBP2Neg_ipd : std_ulogic := 'U'; SIGNAL UBP3Neg_ipd : std_ulogic := 'U'; SIGNAL UBP4Neg_ipd : std_ulogic := 'U'; SIGNAL LBP1Neg_ipd : std_ulogic := 'U'; SIGNAL LBP2Neg_ipd : std_ulogic := 'U'; SIGNAL LBP3Neg_ipd : std_ulogic := 'U'; SIGNAL LBP4Neg_ipd : std_ulogic := 'U'; SIGNAL CNTLDP1Neg_ipd : std_ulogic := 'U'; SIGNAL CNTLDP2Neg_ipd : std_ulogic := 'U'; SIGNAL CNTLDP3Neg_ipd : std_ulogic := 'U'; SIGNAL CNTLDP4Neg_ipd : std_ulogic := 'U'; SIGNAL CNTINCP1Neg_ipd : std_ulogic := 'U'; SIGNAL CNTINCP2Neg_ipd : std_ulogic := 'U'; SIGNAL CNTINCP3Neg_ipd : std_ulogic := 'U'; SIGNAL CNTINCP4Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRDP1Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRDP2Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRDP3Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRDP4Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTP1Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTP2Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTP3Neg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTP4Neg_ipd : std_ulogic := 'U'; SIGNAL MKLDP1Neg_ipd : std_ulogic := 'U'; SIGNAL MKLDP2Neg_ipd : std_ulogic := 'U'; SIGNAL MKLDP3Neg_ipd : std_ulogic := 'U'; SIGNAL MKLDP4Neg_ipd : std_ulogic := 'U'; SIGNAL MKRDP1Neg_ipd : std_ulogic := 'U'; SIGNAL MKRDP2Neg_ipd : std_ulogic := 'U'; SIGNAL MKRDP3Neg_ipd : std_ulogic := 'U'; SIGNAL MKRDP4Neg_ipd : std_ulogic := 'U'; SIGNAL TMS_ipd : std_ulogic := 'U'; SIGNAL TRSTNeg_ipd : std_ulogic := 'U'; SIGNAL TCK_ipd : std_ulogic := 'U'; SIGNAL TDI_ipd : std_ulogic := 'U'; SIGNAL CLKMBIST_ipd : std_ulogic := 'U'; SIGNAL ccs_in : std_ulogic_vector(3 downto 0) := (others => '0'); SIGNAL ccs_out : std_ulogic_vector(3 downto 0) := (others => '0'); BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays TCCS : VitalBuf (ccs_out(0), ccs_in(0), (VitalZeroDelay,tdevice_TCCS)); TCCS1 : VitalBuf (ccs_out(1), ccs_in(1), (VitalZeroDelay,tdevice_TCCS)); TCCS2 : VitalBuf (ccs_out(2), ccs_in(2), (VitalZeroDelay,tdevice_TCCS)); TCCS3 : VitalBuf (ccs_out(3), ccs_in(3), (VitalZeroDelay,tdevice_TCCS)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (A0P1_ipd, A0P1, tipd_A0P1); w_2 : VitalWireDelay (A1P1_ipd, A1P1, tipd_A1P1); w_3 : VitalWireDelay (A2P1_ipd, A2P1, tipd_A2P1); w_4 : VitalWireDelay (A3P1_ipd, A3P1, tipd_A3P1); w_5 : VitalWireDelay (A4P1_ipd, A4P1, tipd_A4P1); w_6 : VitalWireDelay (A5P1_ipd, A5P1, tipd_A5P1); w_7 : VitalWireDelay (A6P1_ipd, A6P1, tipd_A6P1); w_8 : VitalWireDelay (A7P1_ipd, A7P1, tipd_A7P1); w_9 : VitalWireDelay (A8P1_ipd, A8P1, tipd_A8P1); w_10 : VitalWireDelay (A9P1_ipd, A9P1, tipd_A9P1); w_11 : VitalWireDelay (A10P1_ipd, A10P1, tipd_A10P1); w_12 : VitalWireDelay (A11P1_ipd, A11P1, tipd_A11P1); w_13 : VitalWireDelay (A12P1_ipd, A12P1, tipd_A12P1); w_14 : VitalWireDelay (A13P1_ipd, A13P1, tipd_A13P1); w_15 : VitalWireDelay (A14P1_ipd, A14P1, tipd_A14P1); w_16 : VitalWireDelay (A15P1_ipd, A15P1, tipd_A15P1); w_17 : VitalWireDelay (A0P2_ipd, A0P2, tipd_A0P2); w_18 : VitalWireDelay (A1P2_ipd, A1P2, tipd_A1P2); w_19 : VitalWireDelay (A2P2_ipd, A2P2, tipd_A2P2); w_20 : VitalWireDelay (A3P2_ipd, A3P2, tipd_A3P2); w_21 : VitalWireDelay (A4P2_ipd, A4P2, tipd_A4P2); w_22 : VitalWireDelay (A5P2_ipd, A5P2, tipd_A5P2); w_23 : VitalWireDelay (A6P2_ipd, A6P2, tipd_A6P2); w_24 : VitalWireDelay (A7P2_ipd, A7P2, tipd_A7P2); w_25 : VitalWireDelay (A8P2_ipd, A8P2, tipd_A8P2); w_26 : VitalWireDelay (A9P2_ipd, A9P2, tipd_A9P2); w_27 : VitalWireDelay (A10P2_ipd, A10P2, tipd_A10P2); w_28 : VitalWireDelay (A11P2_ipd, A11P2, tipd_A11P2); w_29 : VitalWireDelay (A12P2_ipd, A12P2, tipd_A12P2); w_30 : VitalWireDelay (A13P2_ipd, A13P2, tipd_A13P2); w_31 : VitalWireDelay (A14P2_ipd, A14P2, tipd_A14P2); w_32 : VitalWireDelay (A15P2_ipd, A15P2, tipd_A15P2); w_33 : VitalWireDelay (A0P3_ipd, A0P3, tipd_A0P3); w_34 : VitalWireDelay (A1P3_ipd, A1P3, tipd_A1P3); w_35 : VitalWireDelay (A2P3_ipd, A2P3, tipd_A2P3); w_36 : VitalWireDelay (A3P3_ipd, A3P3, tipd_A3P3); w_37 : VitalWireDelay (A4P3_ipd, A4P3, tipd_A4P3); w_38 : VitalWireDelay (A5P3_ipd, A5P3, tipd_A5P3); w_39 : VitalWireDelay (A6P3_ipd, A6P3, tipd_A6P3); w_40 : VitalWireDelay (A7P3_ipd, A7P3, tipd_A7P3); w_41 : VitalWireDelay (A8P3_ipd, A8P3, tipd_A8P3); w_42 : VitalWireDelay (A9P3_ipd, A9P3, tipd_A9P3); w_43 : VitalWireDelay (A10P3_ipd, A10P3, tipd_A10P3); w_44 : VitalWireDelay (A11P3_ipd, A11P3, tipd_A11P3); w_45 : VitalWireDelay (A12P3_ipd, A12P3, tipd_A12P3); w_46 : VitalWireDelay (A13P3_ipd, A13P3, tipd_A13P3); w_47 : VitalWireDelay (A14P3_ipd, A14P3, tipd_A14P3); w_48 : VitalWireDelay (A15P3_ipd, A15P3, tipd_A15P3); w_49 : VitalWireDelay (A0P4_ipd, A0P4, tipd_A0P4); w_50 : VitalWireDelay (A1P4_ipd, A1P4, tipd_A1P4); w_51 : VitalWireDelay (A2P4_ipd, A2P4, tipd_A2P4); w_52 : VitalWireDelay (A3P4_ipd, A3P4, tipd_A3P4); w_53 : VitalWireDelay (A4P4_ipd, A4P4, tipd_A4P4); w_54 : VitalWireDelay (A5P4_ipd, A5P4, tipd_A5P4); w_55 : VitalWireDelay (A6P4_ipd, A6P4, tipd_A6P4); w_56 : VitalWireDelay (A7P4_ipd, A7P4, tipd_A7P4); w_57 : VitalWireDelay (A8P4_ipd, A8P4, tipd_A8P4); w_58 : VitalWireDelay (A9P4_ipd, A9P4, tipd_A9P4); w_59 : VitalWireDelay (A10P4_ipd, A10P4, tipd_A10P4); w_60 : VitalWireDelay (A11P4_ipd, A11P4, tipd_A11P4); w_61 : VitalWireDelay (A12P4_ipd, A12P4, tipd_A12P4); w_62 : VitalWireDelay (A13P4_ipd, A13P4, tipd_A13P4); w_63 : VitalWireDelay (A14P4_ipd, A14P4, tipd_A14P4); w_64 : VitalWireDelay (A15P4_ipd, A15P4, tipd_A15P4); w_65 : VitalWireDelay (IO0P1_ipd, IO0P1, tipd_IO0P1); w_66 : VitalWireDelay (IO1P1_ipd, IO1P1, tipd_IO1P1); w_67 : VitalWireDelay (IO2P1_ipd, IO2P1, tipd_IO2P1); w_68 : VitalWireDelay (IO3P1_ipd, IO3P1, tipd_IO3P1); w_69 : VitalWireDelay (IO4P1_ipd, IO4P1, tipd_IO4P1); w_70 : VitalWireDelay (IO5P1_ipd, IO5P1, tipd_IO5P1); w_71 : VitalWireDelay (IO6P1_ipd, IO6P1, tipd_IO6P1); w_72 : VitalWireDelay (IO7P1_ipd, IO7P1, tipd_IO7P1); w_73 : VitalWireDelay (IO8P1_ipd, IO8P1, tipd_IO8P1); w_74 : VitalWireDelay (IO9P1_ipd, IO9P1, tipd_IO9P1); w_75 : VitalWireDelay (IO10P1_ipd, IO10P1, tipd_IO10P1); w_76 : VitalWireDelay (IO11P1_ipd, IO11P1, tipd_IO11P1); w_77 : VitalWireDelay (IO12P1_ipd, IO12P1, tipd_IO12P1); w_78 : VitalWireDelay (IO13P1_ipd, IO13P1, tipd_IO13P1); w_79 : VitalWireDelay (IO14P1_ipd, IO14P1, tipd_IO14P1); w_80 : VitalWireDelay (IO15P1_ipd, IO15P1, tipd_IO15P1); w_81 : VitalWireDelay (IO16P1_ipd, IO16P1, tipd_IO16P1); w_82 : VitalWireDelay (IO17P1_ipd, IO17P1, tipd_IO17P1); w_83 : VitalWireDelay (IO0P2_ipd, IO0P2, tipd_IO0P2); w_84 : VitalWireDelay (IO1P2_ipd, IO1P2, tipd_IO1P2); w_85 : VitalWireDelay (IO2P2_ipd, IO2P2, tipd_IO2P2); w_86 : VitalWireDelay (IO3P2_ipd, IO3P2, tipd_IO3P2); w_87 : VitalWireDelay (IO4P2_ipd, IO4P2, tipd_IO4P2); w_88 : VitalWireDelay (IO5P2_ipd, IO5P2, tipd_IO5P2); w_89 : VitalWireDelay (IO6P2_ipd, IO6P2, tipd_IO6P2); w_90 : VitalWireDelay (IO7P2_ipd, IO7P2, tipd_IO7P2); w_91 : VitalWireDelay (IO8P2_ipd, IO8P2, tipd_IO8P2); w_92 : VitalWireDelay (IO9P2_ipd, IO9P2, tipd_IO9P2); w_93 : VitalWireDelay (IO10P2_ipd, IO10P2, tipd_IO10P2); w_94 : VitalWireDelay (IO11P2_ipd, IO11P2, tipd_IO11P2); w_95 : VitalWireDelay (IO12P2_ipd, IO12P2, tipd_IO12P2); w_96 : VitalWireDelay (IO13P2_ipd, IO13P2, tipd_IO13P2); w_97 : VitalWireDelay (IO14P2_ipd, IO14P2, tipd_IO14P2); w_98 : VitalWireDelay (IO15P2_ipd, IO15P2, tipd_IO15P2); w_99 : VitalWireDelay (IO16P2_ipd, IO16P2, tipd_IO16P2); w_100 : VitalWireDelay (IO17P2_ipd, IO17P2, tipd_IO17P2); w_101 : VitalWireDelay (IO0P3_ipd, IO0P3, tipd_IO0P3); w_102 : VitalWireDelay (IO1P3_ipd, IO1P3, tipd_IO1P3); w_103 : VitalWireDelay (IO2P3_ipd, IO2P3, tipd_IO2P3); w_104 : VitalWireDelay (IO3P3_ipd, IO3P3, tipd_IO3P3); w_105 : VitalWireDelay (IO4P3_ipd, IO4P3, tipd_IO4P3); w_106 : VitalWireDelay (IO5P3_ipd, IO5P3, tipd_IO5P3); w_107 : VitalWireDelay (IO6P3_ipd, IO6P3, tipd_IO6P3); w_108 : VitalWireDelay (IO7P3_ipd, IO7P3, tipd_IO7P3); w_109 : VitalWireDelay (IO8P3_ipd, IO8P3, tipd_IO8P3); w_110 : VitalWireDelay (IO9P3_ipd, IO9P3, tipd_IO9P3); w_111 : VitalWireDelay (IO10P3_ipd, IO10P3, tipd_IO10P3); w_112 : VitalWireDelay (IO11P3_ipd, IO11P3, tipd_IO11P3); w_113 : VitalWireDelay (IO12P3_ipd, IO12P3, tipd_IO12P3); w_114 : VitalWireDelay (IO13P3_ipd, IO13P3, tipd_IO13P3); w_115 : VitalWireDelay (IO14P3_ipd, IO14P3, tipd_IO14P3); w_116 : VitalWireDelay (IO15P3_ipd, IO15P3, tipd_IO15P3); w_117 : VitalWireDelay (IO16P3_ipd, IO16P3, tipd_IO16P3); w_118 : VitalWireDelay (IO17P3_ipd, IO17P3, tipd_IO17P3); w_119 : VitalWireDelay (IO0P4_ipd, IO0P4, tipd_IO0P4); w_120 : VitalWireDelay (IO1P4_ipd, IO1P4, tipd_IO1P4); w_121 : VitalWireDelay (IO2P4_ipd, IO2P4, tipd_IO2P4); w_122 : VitalWireDelay (IO3P4_ipd, IO3P4, tipd_IO3P4); w_123 : VitalWireDelay (IO4P4_ipd, IO4P4, tipd_IO4P4); w_124 : VitalWireDelay (IO5P4_ipd, IO5P4, tipd_IO5P4); w_125 : VitalWireDelay (IO6P4_ipd, IO6P4, tipd_IO6P4); w_126 : VitalWireDelay (IO7P4_ipd, IO7P4, tipd_IO7P4); w_127 : VitalWireDelay (IO8P4_ipd, IO8P4, tipd_IO8P4); w_128 : VitalWireDelay (IO9P4_ipd, IO9P4, tipd_IO9P4); w_129 : VitalWireDelay (IO10P4_ipd, IO10P4, tipd_IO10P4); w_130 : VitalWireDelay (IO11P4_ipd, IO11P4, tipd_IO11P4); w_131 : VitalWireDelay (IO12P4_ipd, IO12P4, tipd_IO12P4); w_132 : VitalWireDelay (IO13P4_ipd, IO13P4, tipd_IO13P4); w_133 : VitalWireDelay (IO14P4_ipd, IO14P4, tipd_IO14P4); w_134 : VitalWireDelay (IO15P4_ipd, IO15P4, tipd_IO15P4); w_135 : VitalWireDelay (IO16P4_ipd, IO16P4, tipd_IO16P4); w_136 : VitalWireDelay (IO17P4_ipd, IO17P4, tipd_IO17P4); w_137 : VitalWireDelay (CLKP1_ipd, CLKP1, tipd_CLKP1); w_138 : VitalWireDelay (CLKP2_ipd, CLKP2, tipd_CLKP2); w_139 : VitalWireDelay (CLKP3_ipd, CLKP3, tipd_CLKP3); w_140 : VitalWireDelay (CLKP4_ipd, CLKP4, tipd_CLKP4); w_141 : VitalWireDelay (MRSTNeg_ipd, MRSTNeg, tipd_MRSTNeg); w_142 : VitalWireDelay (RWP1_ipd, RWP1, tipd_RWP1); w_143 : VitalWireDelay (RWP2_ipd, RWP2, tipd_RWP2); w_144 : VitalWireDelay (RWP3_ipd, RWP3, tipd_RWP3); w_145 : VitalWireDelay (RWP4_ipd, RWP4, tipd_RWP4); w_146 : VitalWireDelay (OEP1Neg_ipd, OEP1Neg, tipd_OEP1Neg); w_147 : VitalWireDelay (OEP2Neg_ipd, OEP2Neg, tipd_OEP2Neg); w_148 : VitalWireDelay (OEP3Neg_ipd, OEP3Neg, tipd_OEP3Neg); w_149 : VitalWireDelay (OEP4Neg_ipd, OEP4Neg, tipd_OEP4Neg); w_150 : VitalWireDelay (CE0P1Neg_ipd, CE0P1Neg, tipd_CE0P1Neg); w_151 : VitalWireDelay (CE0P2Neg_ipd, CE0P2Neg, tipd_CE0P2Neg); w_152 : VitalWireDelay (CE0P3Neg_ipd, CE0P3Neg, tipd_CE0P3Neg); w_153 : VitalWireDelay (CE0P4Neg_ipd, CE0P4Neg, tipd_CE0P4Neg); w_154 : VitalWireDelay (CE1P1_ipd, CE1P1, tipd_CE1P1); w_155 : VitalWireDelay (CE1P2_ipd, CE1P2, tipd_CE1P2); w_156 : VitalWireDelay (CE1P3_ipd, CE1P3, tipd_CE1P3); w_157 : VitalWireDelay (CE1P4_ipd, CE1P4, tipd_CE1P4); w_158 : VitalWireDelay (UBP1Neg_ipd, UBP1Neg, tipd_UBP1Neg); w_159 : VitalWireDelay (UBP2Neg_ipd, UBP2Neg, tipd_UBP2Neg); w_160 : VitalWireDelay (UBP3Neg_ipd, UBP3Neg, tipd_UBP3Neg); w_161 : VitalWireDelay (UBP4Neg_ipd, UBP4Neg, tipd_UBP4Neg); w_162 : VitalWireDelay (LBP1Neg_ipd, LBP1Neg, tipd_LBP1Neg); w_163 : VitalWireDelay (LBP2Neg_ipd, LBP2Neg, tipd_LBP2Neg); w_164 : VitalWireDelay (LBP3Neg_ipd, LBP3Neg, tipd_LBP3Neg); w_165 : VitalWireDelay (LBP4Neg_ipd, LBP4Neg, tipd_LBP4Neg); w_166 : VitalWireDelay (CNTLDP1Neg_ipd, CNTLDP1Neg, tipd_CNTLDP1Neg); w_167 : VitalWireDelay (CNTLDP2Neg_ipd, CNTLDP2Neg, tipd_CNTLDP2Neg); w_168 : VitalWireDelay (CNTLDP3Neg_ipd, CNTLDP3Neg, tipd_CNTLDP3Neg); w_169 : VitalWireDelay (CNTLDP4Neg_ipd, CNTLDP4Neg, tipd_CNTLDP4Neg); w_170 : VitalWireDelay (CNTINCP1Neg_ipd, CNTINCP1Neg, tipd_CNTINCP1Neg); w_171 : VitalWireDelay (CNTINCP2Neg_ipd, CNTINCP2Neg, tipd_CNTINCP2Neg); w_172 : VitalWireDelay (CNTINCP3Neg_ipd, CNTINCP3Neg, tipd_CNTINCP3Neg); w_173 : VitalWireDelay (CNTINCP4Neg_ipd, CNTINCP4Neg, tipd_CNTINCP4Neg); w_174 : VitalWireDelay (CNTRDP1Neg_ipd, CNTRDP1Neg, tipd_CNTRDP1Neg); w_175 : VitalWireDelay (CNTRDP2Neg_ipd, CNTRDP2Neg, tipd_CNTRDP2Neg); w_176 : VitalWireDelay (CNTRDP3Neg_ipd, CNTRDP3Neg, tipd_CNTRDP3Neg); w_177 : VitalWireDelay (CNTRDP4Neg_ipd, CNTRDP4Neg, tipd_CNTRDP4Neg); w_178 : VitalWireDelay (CNTRSTP1Neg_ipd, CNTRSTP1Neg, tipd_CNTRSTP1Neg); w_179 : VitalWireDelay (CNTRSTP2Neg_ipd, CNTRSTP2Neg, tipd_CNTRSTP2Neg); w_180 : VitalWireDelay (CNTRSTP3Neg_ipd, CNTRSTP3Neg, tipd_CNTRSTP3Neg); w_181 : VitalWireDelay (CNTRSTP4Neg_ipd, CNTRSTP4Neg, tipd_CNTRSTP4Neg); w_186 : VitalWireDelay (MKLDP1Neg_ipd, MKLDP1Neg, tipd_MKLDP1Neg); w_187 : VitalWireDelay (MKLDP2Neg_ipd, MKLDP2Neg, tipd_MKLDP2Neg); w_188 : VitalWireDelay (MKLDP3Neg_ipd, MKLDP3Neg, tipd_MKLDP3Neg); w_189 : VitalWireDelay (MKLDP4Neg_ipd, MKLDP4Neg, tipd_MKLDP4Neg); w_190 : VitalWireDelay (MKRDP1Neg_ipd, MKRDP1Neg, tipd_MKRDP1Neg); w_191 : VitalWireDelay (MKRDP2Neg_ipd, MKRDP2Neg, tipd_MKRDP2Neg); w_192 : VitalWireDelay (MKRDP3Neg_ipd, MKRDP3Neg, tipd_MKRDP3Neg); w_193 : VitalWireDelay (MKRDP4Neg_ipd, MKRDP4Neg, tipd_MKRDP4Neg); w_198 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS); w_199 : VitalWireDelay (TRSTNeg_ipd, TRSTNeg, tipd_TRSTNeg); w_200 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK); w_201 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI); w_202 : VitalWireDelay (CLKMBIST_ipd, CLKMBIST, tipd_CLKMBIST); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( AddressP1In : IN std_logic_vector(15 downto 0); AddressP1Out : OUT std_logic_vector(15 downto 0); AddressP2In : IN std_logic_vector(15 downto 0); AddressP2Out : OUT std_logic_vector(15 downto 0); AddressP3In : IN std_logic_vector(15 downto 0); AddressP3Out : OUT std_logic_vector(15 downto 0); AddressP4In : IN std_logic_vector(15 downto 0); AddressP4Out : OUT std_logic_vector(15 downto 0); DatA1In : IN std_logic_vector(8 downto 0); DatB1In : IN std_logic_vector(8 downto 0); DataP1Out : OUT std_logic_vector(17 downto 0) := (others => 'Z'); DatA2In : IN std_logic_vector(8 downto 0); DatB2In : IN std_logic_vector(8 downto 0); DataP2Out : OUT std_logic_vector(17 downto 0) := (others => 'Z'); DatA3In : IN std_logic_vector(8 downto 0); DatB3In : IN std_logic_vector(8 downto 0); DataP3Out : OUT std_logic_vector(17 downto 0) := (others => 'Z'); DatA4In : IN std_logic_vector(8 downto 0); DatB4In : IN std_logic_vector(8 downto 0); DataP4Out : OUT std_logic_vector(17 downto 0) := (others => 'Z'); CLKIn : IN std_logic_vector(3 downto 0); MRSTNegIn : IN std_ulogic := 'U'; RWIn : IN std_logic_vector(3 downto 0); OENegIn : IN std_logic_vector(3 downto 0); CE0NegIn : IN std_logic_vector(3 downto 0); CE1In : IN std_logic_vector(3 downto 0); UBNegIn : IN std_logic_vector(3 downto 0); LBNegIn : IN std_logic_vector(3 downto 0); CNTLDNegIn : IN std_logic_vector(3 downto 0); CNTINCNegIn : IN std_logic_vector(3 downto 0); CNTRDNegIn : IN std_logic_vector(3 downto 0); CNTRSTNegIn : IN std_logic_vector(3 downto 0); CNTINTNegOut : OUT std_logic_vector(3 downto 0) := (others => 'Z'); MKLDNegIn : IN std_logic_vector(3 downto 0); MKRDNegIn : IN std_logic_vector(3 downto 0); INTNegOut : OUT std_logic_vector(3 downto 0) := (others => 'Z'); TMSIn : IN std_ulogic := 'U'; TRSTNegIn : IN std_ulogic := 'U'; TCKIn : IN std_ulogic := 'U'; TDIIn : IN std_ulogic := 'U'; TDOOut : OUT std_ulogic := 'U'; CLKMBISTIn : IN std_ulogic := 'U' ); PORT MAP ( AddressP1In(0) => A0P1_ipd, AddressP1In(1) => A1P1_ipd, AddressP1In(2) => A2P1_ipd, AddressP1In(3) => A3P1_ipd, AddressP1In(4) => A4P1_ipd, AddressP1In(5) => A5P1_ipd, AddressP1In(6) => A6P1_ipd, AddressP1In(7) => A7P1_ipd, AddressP1In(8) => A8P1_ipd, AddressP1In(9) => A9P1_ipd, AddressP1In(10) => A10P1_ipd, AddressP1In(11) => A11P1_ipd, AddressP1In(12) => A12P1_ipd, AddressP1In(13) => A13P1_ipd, AddressP1In(14) => A14P1_ipd, AddressP1In(15) => A15P1_ipd, AddressP2In(0) => A0P2_ipd, AddressP2In(1) => A1P2_ipd, AddressP2In(2) => A2P2_ipd, AddressP2In(3) => A3P2_ipd, AddressP2In(4) => A4P2_ipd, AddressP2In(5) => A5P2_ipd, AddressP2In(6) => A6P2_ipd, AddressP2In(7) => A7P2_ipd, AddressP2In(8) => A8P2_ipd, AddressP2In(9) => A9P2_ipd, AddressP2In(10) => A10P2_ipd, AddressP2In(11) => A11P2_ipd, AddressP2In(12) => A12P2_ipd, AddressP2In(13) => A13P2_ipd, AddressP2In(14) => A14P2_ipd, AddressP2In(15) => A15P2_ipd, AddressP3In(0) => A0P3_ipd, AddressP3In(1) => A1P3_ipd, AddressP3In(2) => A2P3_ipd, AddressP3In(3) => A3P3_ipd, AddressP3In(4) => A4P3_ipd, AddressP3In(5) => A5P3_ipd, AddressP3In(6) => A6P3_ipd, AddressP3In(7) => A7P3_ipd, AddressP3In(8) => A8P3_ipd, AddressP3In(9) => A9P3_ipd, AddressP3In(10) => A10P3_ipd, AddressP3In(11) => A11P3_ipd, AddressP3In(12) => A12P3_ipd, AddressP3In(13) => A13P3_ipd, AddressP3In(14) => A14P3_ipd, AddressP3In(15) => A15P3_ipd, AddressP4In(0) => A0P4_ipd, AddressP4In(1) => A1P4_ipd, AddressP4In(2) => A2P4_ipd, AddressP4In(3) => A3P4_ipd, AddressP4In(4) => A4P4_ipd, AddressP4In(5) => A5P4_ipd, AddressP4In(6) => A6P4_ipd, AddressP4In(7) => A7P4_ipd, AddressP4In(8) => A8P4_ipd, AddressP4In(9) => A9P4_ipd, AddressP4In(10) => A10P4_ipd, AddressP4In(11) => A11P4_ipd, AddressP4In(12) => A12P4_ipd, AddressP4In(13) => A13P4_ipd, AddressP4In(14) => A14P4_ipd, AddressP4In(15) => A15P4_ipd, AddressP1Out(0) => A0P1, AddressP1Out(1) => A1P1, AddressP1Out(2) => A2P1, AddressP1Out(3) => A3P1, AddressP1Out(4) => A4P1, AddressP1Out(5) => A5P1, AddressP1Out(6) => A6P1, AddressP1Out(7) => A7P1, AddressP1Out(8) => A8P1, AddressP1Out(9) => A9P1, AddressP1Out(10) => A10P1, AddressP1Out(11) => A11P1, AddressP1Out(12) => A12P1, AddressP1Out(13) => A13P1, AddressP1Out(14) => A14P1, AddressP1Out(15) => A15P1, AddressP2Out(0) => A0P2, AddressP2Out(1) => A1P2, AddressP2Out(2) => A2P2, AddressP2Out(3) => A3P2, AddressP2Out(4) => A4P2, AddressP2Out(5) => A5P2, AddressP2Out(6) => A6P2, AddressP2Out(7) => A7P2, AddressP2Out(8) => A8P2, AddressP2Out(9) => A9P2, AddressP2Out(10) => A10P2, AddressP2Out(11) => A11P2, AddressP2Out(12) => A12P2, AddressP2Out(13) => A13P2, AddressP2Out(14) => A14P2, AddressP2Out(15) => A15P2, AddressP3Out(0) => A0P3, AddressP3Out(1) => A1P3, AddressP3Out(2) => A2P3, AddressP3Out(3) => A3P3, AddressP3Out(4) => A4P3, AddressP3Out(5) => A5P3, AddressP3Out(6) => A6P3, AddressP3Out(7) => A7P3, AddressP3Out(8) => A8P3, AddressP3Out(9) => A9P3, AddressP3Out(10) => A10P3, AddressP3Out(11) => A11P3, AddressP3Out(12) => A12P3, AddressP3Out(13) => A13P3, AddressP3Out(14) => A14P3, AddressP3Out(15) => A15P3, AddressP4Out(0) => A0P4, AddressP4Out(1) => A1P4, AddressP4Out(2) => A2P4, AddressP4Out(3) => A3P4, AddressP4Out(4) => A4P4, AddressP4Out(5) => A5P4, AddressP4Out(6) => A6P4, AddressP4Out(7) => A7P4, AddressP4Out(8) => A8P4, AddressP4Out(9) => A9P4, AddressP4Out(10) => A10P4, AddressP4Out(11) => A11P4, AddressP4Out(12) => A12P4, AddressP4Out(13) => A13P4, AddressP4Out(14) => A14P4, AddressP4Out(15) => A15P4, DatA1In(0) => IO0P1_ipd, DatA1In(1) => IO1P1_ipd, DatA1In(2) => IO2P1_ipd, DatA1In(3) => IO3P1_ipd, DatA1In(4) => IO4P1_ipd, DatA1In(5) => IO5P1_ipd, DatA1In(6) => IO6P1_ipd, DatA1In(7) => IO7P1_ipd, DatA1In(8) => IO8P1_ipd, DatB1In(0) => IO9P1_ipd, DatB1In(1) => IO10P1_ipd, DatB1In(2) => IO11P1_ipd, DatB1In(3) => IO12P1_ipd, DatB1In(4) => IO13P1_ipd, DatB1In(5) => IO14P1_ipd, DatB1In(6) => IO15P1_ipd, DatB1In(7) => IO16P1_ipd, DatB1In(8) => IO17P1_ipd, DatA2In(0) => IO0P2_ipd, DatA2In(1) => IO1P2_ipd, DatA2In(2) => IO2P2_ipd, DatA2In(3) => IO3P2_ipd, DatA2In(4) => IO4P2_ipd, DatA2In(5) => IO5P2_ipd, DatA2In(6) => IO6P2_ipd, DatA2In(7) => IO7P2_ipd, DatA2In(8) => IO8P2_ipd, DatB2In(0) => IO9P2_ipd, DatB2In(1) => IO10P2_ipd, DatB2In(2) => IO11P2_ipd, DatB2In(3) => IO12P2_ipd, DatB2In(4) => IO13P2_ipd, DatB2In(5) => IO14P2_ipd, DatB2In(6) => IO15P2_ipd, DatB2In(7) => IO16P2_ipd, DatB2In(8) => IO17P2_ipd, DatA3In(0) => IO0P3_ipd, DatA3In(1) => IO1P3_ipd, DatA3In(2) => IO2P3_ipd, DatA3In(3) => IO3P3_ipd, DatA3In(4) => IO4P3_ipd, DatA3In(5) => IO5P3_ipd, DatA3In(6) => IO6P3_ipd, DatA3In(7) => IO7P3_ipd, DatA3In(8) => IO8P3_ipd, DatB3In(0) => IO9P3_ipd, DatB3In(1) => IO10P3_ipd, DatB3In(2) => IO11P3_ipd, DatB3In(3) => IO12P3_ipd, DatB3In(4) => IO13P3_ipd, DatB3In(5) => IO14P3_ipd, DatB3In(6) => IO15P3_ipd, DatB3In(7) => IO16P3_ipd, DatB3In(8) => IO17P3_ipd, DatA4In(0) => IO0P4_ipd, DatA4In(1) => IO1P4_ipd, DatA4In(2) => IO2P4_ipd, DatA4In(3) => IO3P4_ipd, DatA4In(4) => IO4P4_ipd, DatA4In(5) => IO5P4_ipd, DatA4In(6) => IO6P4_ipd, DatA4In(7) => IO7P4_ipd, DatA4In(8) => IO8P4_ipd, DatB4In(0) => IO9P4_ipd, DatB4In(1) => IO10P4_ipd, DatB4In(2) => IO11P4_ipd, DatB4In(3) => IO12P4_ipd, DatB4In(4) => IO13P4_ipd, DatB4In(5) => IO14P4_ipd, DatB4In(6) => IO15P4_ipd, DatB4In(7) => IO16P4_ipd, DatB4In(8) => IO17P4_ipd, DataP1Out(0) => IO0P1, DataP1Out(1) => IO1P1, DataP1Out(2) => IO2P1, DataP1Out(3) => IO3P1, DataP1Out(4) => IO4P1, DataP1Out(5) => IO5P1, DataP1Out(6) => IO6P1, DataP1Out(7) => IO7P1, DataP1Out(8) => IO8P1, DataP1Out(9) => IO9P1, DataP1Out(10) => IO10P1, DataP1Out(11) => IO11P1, DataP1Out(12) => IO12P1, DataP1Out(13) => IO13P1, DataP1Out(14) => IO14P1, DataP1Out(15) => IO15P1, DataP1Out(16) => IO16P1, DataP1Out(17) => IO17P1, DataP2Out(0) => IO0P2, DataP2Out(1) => IO1P2, DataP2Out(2) => IO2P2, DataP2Out(3) => IO3P2, DataP2Out(4) => IO4P2, DataP2Out(5) => IO5P2, DataP2Out(6) => IO6P2, DataP2Out(7) => IO7P2, DataP2Out(8) => IO8P2, DataP2Out(9) => IO9P2, DataP2Out(10) => IO10P2, DataP2Out(11) => IO11P2, DataP2Out(12) => IO12P2, DataP2Out(13) => IO13P2, DataP2Out(14) => IO14P2, DataP2Out(15) => IO15P2, DataP2Out(16) => IO16P2, DataP2Out(17) => IO17P2, DataP3Out(0) => IO0P3, DataP3Out(1) => IO1P3, DataP3Out(2) => IO2P3, DataP3Out(3) => IO3P3, DataP3Out(4) => IO4P3, DataP3Out(5) => IO5P3, DataP3Out(6) => IO6P3, DataP3Out(7) => IO7P3, DataP3Out(8) => IO8P3, DataP3Out(9) => IO9P3, DataP3Out(10) => IO10P3, DataP3Out(11) => IO11P3, DataP3Out(12) => IO12P3, DataP3Out(13) => IO13P3, DataP3Out(14) => IO14P3, DataP3Out(15) => IO15P3, DataP3Out(16) => IO16P3, DataP3Out(17) => IO17P3, DataP4Out(0) => IO0P4, DataP4Out(1) => IO1P4, DataP4Out(2) => IO2P4, DataP4Out(3) => IO3P4, DataP4Out(4) => IO4P4, DataP4Out(5) => IO5P4, DataP4Out(6) => IO6P4, DataP4Out(7) => IO7P4, DataP4Out(8) => IO8P4, DataP4Out(9) => IO9P4, DataP4Out(10) => IO10P4, DataP4Out(11) => IO11P4, DataP4Out(12) => IO12P4, DataP4Out(13) => IO13P4, DataP4Out(14) => IO14P4, DataP4Out(15) => IO15P4, DataP4Out(16) => IO16P4, DataP4Out(17) => IO17P4, CLKIn(0) => CLKP1_ipd, CLKIn(1) => CLKP2_ipd, CLKIn(2) => CLKP3_ipd, CLKIn(3) => CLKP4_ipd, MRSTNegIn => MRSTNeg_ipd, RWIn(0) => RWP1_ipd, RWIn(1) => RWP2_ipd, RWIn(2) => RWP3_ipd, RWIn(3) => RWP4_ipd, OENegIn(0) => OEP1Neg_ipd, OENegIn(1) => OEP2Neg_ipd, OENegIn(2) => OEP3Neg_ipd, OENegIn(3) => OEP4Neg_ipd, CE0NegIn(0) => CE0P1Neg_ipd, CE0NegIn(1) => CE0P2Neg_ipd, CE0NegIn(2) => CE0P3Neg_ipd, CE0NegIn(3) => CE0P4Neg_ipd, CE1In(0) => CE1P1_ipd, CE1In(1) => CE1P2_ipd, CE1In(2) => CE1P3_ipd, CE1In(3) => CE1P4_ipd, UBNegIn(0) => UBP1Neg_ipd, UBNegIn(1) => UBP2Neg_ipd, UBNegIn(2) => UBP3Neg_ipd, UBNegIn(3) => UBP4Neg_ipd, LBNegIn(0) => LBP1Neg_ipd, LBNegIn(1) => LBP2Neg_ipd, LBNegIn(2) => LBP3Neg_ipd, LBNegIn(3) => LBP4Neg_ipd, CNTLDNegIn(0) => CNTLDP1Neg_ipd, CNTLDNegIn(1) => CNTLDP2Neg_ipd, CNTLDNegIn(2) => CNTLDP3Neg_ipd, CNTLDNegIn(3) => CNTLDP4Neg_ipd, CNTINCNegIn(0) => CNTINCP1Neg_ipd, CNTINCNegIn(1) => CNTINCP2Neg_ipd, CNTINCNegIn(2) => CNTINCP3Neg_ipd, CNTINCNegIn(3) => CNTINCP4Neg_ipd, CNTRDNegIn(0) => CNTRDP1Neg_ipd, CNTRDNegIn(1) => CNTRDP2Neg_ipd, CNTRDNegIn(2) => CNTRDP3Neg_ipd, CNTRDNegIn(3) => CNTRDP4Neg_ipd, CNTRSTNegIn(0) => CNTRSTP1Neg_ipd, CNTRSTNegIn(1) => CNTRSTP2Neg_ipd, CNTRSTNegIn(2) => CNTRSTP3Neg_ipd, CNTRSTNegIn(3) => CNTRSTP4Neg_ipd, CNTINTNegOut(0) => CNTINTP1Neg, CNTINTNegOut(1) => CNTINTP2Neg, CNTINTNegOut(2) => CNTINTP3Neg, CNTINTNegOut(3) => CNTINTP4Neg, MKLDNegIn(0) => MKLDP1Neg_ipd, MKLDNegIn(1) => MKLDP2Neg_ipd, MKLDNegIn(2) => MKLDP3Neg_ipd, MKLDNegIn(3) => MKLDP4Neg_ipd, MKRDNegIn(0) => MKRDP1Neg_ipd, MKRDNegIn(1) => MKRDP2Neg_ipd, MKRDNegIn(2) => MKRDP3Neg_ipd, MKRDNegIn(3) => MKRDP4Neg_ipd, INTNegOut(0) => INTP1Neg, INTNegOut(1) => INTP2Neg, INTNegOut(2) => INTP3Neg, INTNegOut(3) => INTP4Neg, TMSIn => TMS_ipd, TRSTNegIn => TRSTNeg_ipd, TCKIn => TCK_ipd, TDIIn => TDI_ipd, TDOOut => TDO, CLKMBISTIn => CLKMBIST_ipd ); TYPE Instruction IS (idcode, extest, bypass, highz, sample_preload, mbistmode, runbist, int_scan, clamp, reserved ); -- Memory array declaration TYPE MemStore IS ARRAY (0 to 65536) OF INTEGER RANGE -2 TO 511; SHARED VARIABLE MemDatA : MemStore; SHARED VARIABLE MemDatB : MemStore; SIGNAL Instruct : Instruction; SIGNAL BSReg : std_logic_vector(391 downto 0) := (OTHERS => '1'); SIGNAL D1_zd : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL D2_zd : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL D3_zd : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL D4_zd : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL A1_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL A2_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL A3_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL A4_zd : std_logic_vector(15 DOWNTO 0) := (OTHERS => 'Z'); BEGIN ----------------------------------------------------------------------- -- Main Behavior Process ----------------------------------------------------------------------- BEHAVIOR : PROCESS (AddressP1In, AddressP2In, AddressP3In, AddressP4In, DatA1In, DatA2In, DatA3In, DatA4In, DatB1In, DatB2In, DatB3In, DatB4In, CLKIn, MRSTNegIn, RWIn, OENegIn, CE0NegIn, CE1In, UBNegIn, LBNegIn, CNTLDNegIn, CNTRSTNegIn, CNTRDNegIn, CNTINCNegIn, MKLDNegIn, MKRDNegIn, TDIIn, TRSTNegIN, TMSIn, TCKIn, Instruct) TYPE mem_state IS (desel, write, read ); -- Timing Check Variables VARIABLE Tviol_AddressP1In_CLK : X01 := '0'; VARIABLE TD_AddressP1In_CLK : VitalTimingDataType; VARIABLE Tviol_AddressP2In_CLK : X01 := '0'; VARIABLE TD_AddressP2In_CLK : VitalTimingDataType; VARIABLE Tviol_AddressP3In_CLK : X01 := '0'; VARIABLE TD_AddressP3In_CLK : VitalTimingDataType; VARIABLE Tviol_AddressP4In_CLK : X01 := '0'; VARIABLE TD_AddressP4In_CLK : VitalTimingDataType; VARIABLE Tviol_DatA1In_CLK : X01 := '0'; VARIABLE TD_DatA1In_CLK : VitalTimingDataType; VARIABLE Tviol_DatA2In_CLK : X01 := '0'; VARIABLE TD_DatA2In_CLK : VitalTimingDataType; VARIABLE Tviol_DatA3In_CLK : X01 := '0'; VARIABLE TD_DatA3In_CLK : VitalTimingDataType; VARIABLE Tviol_DatA4In_CLK : X01 := '0'; VARIABLE TD_DatA4In_CLK : VitalTimingDataType; VARIABLE Tviol_DatB1In_CLK : X01 := '0'; VARIABLE TD_DatB1In_CLK : VitalTimingDataType; VARIABLE Tviol_DatB2In_CLK : X01 := '0'; VARIABLE TD_DatB2In_CLK : VitalTimingDataType; VARIABLE Tviol_DatB3In_CLK : X01 := '0'; VARIABLE TD_DatB3In_CLK : VitalTimingDataType; VARIABLE Tviol_DatB4In_CLK : X01 := '0'; VARIABLE TD_DatB4In_CLK : VitalTimingDataType; VARIABLE Tviol_RW1In_CLK : X01 := '0'; VARIABLE TD_RW1In_CLK : VitalTimingDataType; VARIABLE Tviol_RW2In_CLK : X01 := '0'; VARIABLE TD_RW2In_CLK : VitalTimingDataType; VARIABLE Tviol_RW3In_CLK : X01 := '0'; VARIABLE TD_RW3In_CLK : VitalTimingDataType; VARIABLE Tviol_RW4In_CLK : X01 := '0'; VARIABLE TD_RW4In_CLK : VitalTimingDataType; VARIABLE Tviol_CE0Neg1In_CLK : X01 := '0'; VARIABLE TD_CE0Neg1In_CLK : VitalTimingDataType; VARIABLE Tviol_CE0Neg2In_CLK : X01 := '0'; VARIABLE TD_CE0Neg2In_CLK : VitalTimingDataType; VARIABLE Tviol_CE0Neg3In_CLK : X01 := '0'; VARIABLE TD_CE0Neg3In_CLK : VitalTimingDataType; VARIABLE Tviol_CE0Neg4In_CLK : X01 := '0'; VARIABLE TD_CE0Neg4In_CLK : VitalTimingDataType; VARIABLE Tviol_CE1P1In_CLK : X01 := '0'; VARIABLE TD_CE1P1In_CLK : VitalTimingDataType; VARIABLE Tviol_CE1P2In_CLK : X01 := '0'; VARIABLE TD_CE1P2In_CLK : VitalTimingDataType; VARIABLE Tviol_CE1P3In_CLK : X01 := '0'; VARIABLE TD_CE1P3In_CLK : VitalTimingDataType; VARIABLE Tviol_CE1P4In_CLK : X01 := '0'; VARIABLE TD_CE1P4In_CLK : VitalTimingDataType; VARIABLE Tviol_LB1NegIn_CLK : X01 := '0'; VARIABLE TD_LB1NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_LB2NegIn_CLK : X01 := '0'; VARIABLE TD_LB2NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_LB3NegIn_CLK : X01 := '0'; VARIABLE TD_LB3NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_LB4NegIn_CLK : X01 := '0'; VARIABLE TD_LB4NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_UB1NegIn_CLK : X01 := '0'; VARIABLE TD_UB1NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_UB2NegIn_CLK : X01 := '0'; VARIABLE TD_UB2NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_UB3NegIn_CLK : X01 := '0'; VARIABLE TD_UB3NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_UB4NegIn_CLK : X01 := '0'; VARIABLE TD_UB4NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_CNTLDNeg1In_CLK : X01 := '0'; VARIABLE TD_CNTLDNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTLDNeg2In_CLK : X01 := '0'; VARIABLE TD_CNTLDNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTLDNeg3In_CLK : X01 := '0'; VARIABLE TD_CNTLDNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTLDNeg4In_CLK : X01 := '0'; VARIABLE TD_CNTLDNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTINCNeg1In_CLK : X01 := '0'; VARIABLE TD_CNTINCNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTINCNeg2In_CLK : X01 := '0'; VARIABLE TD_CNTINCNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTINCNeg3In_CLK : X01 := '0'; VARIABLE TD_CNTINCNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTINCNeg4In_CLK : X01 := '0'; VARIABLE TD_CNTINCNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRSTNeg1In_CLK : X01 := '0'; VARIABLE TD_CNTRSTNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRSTNeg2In_CLK : X01 := '0'; VARIABLE TD_CNTRSTNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRSTNeg3In_CLK : X01 := '0'; VARIABLE TD_CNTRSTNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRSTNeg4In_CLK : X01 := '0'; VARIABLE TD_CNTRSTNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRDNeg1In_CLK : X01 := '0'; VARIABLE TD_CNTRDNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRDNeg2In_CLK : X01 := '0'; VARIABLE TD_CNTRDNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRDNeg3In_CLK : X01 := '0'; VARIABLE TD_CNTRDNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_CNTRDNeg4In_CLK : X01 := '0'; VARIABLE TD_CNTRDNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_MKLDNeg1In_CLK : X01 := '0'; VARIABLE TD_MKLDNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_MKLDNeg2In_CLK : X01 := '0'; VARIABLE TD_MKLDNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_MKLDNeg3In_CLK : X01 := '0'; VARIABLE TD_MKLDNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_MKLDNeg4In_CLK : X01 := '0'; VARIABLE TD_MKLDNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_MKRDNeg1In_CLK : X01 := '0'; VARIABLE TD_MKRDNeg1In_CLK : VitalTimingDataType; VARIABLE Tviol_MKRDNeg2In_CLK : X01 := '0'; VARIABLE TD_MKRDNeg2In_CLK : VitalTimingDataType; VARIABLE Tviol_MKRDNeg3In_CLK : X01 := '0'; VARIABLE TD_MKRDNeg3In_CLK : VitalTimingDataType; VARIABLE Tviol_MKRDNeg4In_CLK : X01 := '0'; VARIABLE TD_MKRDNeg4In_CLK : VitalTimingDataType; VARIABLE Tviol_TDIIn_TCK : X01 := '0'; VARIABLE TD_TDIIn_TCK : VitalTimingDataType; VARIABLE Tviol_TMSIn_TCK : X01 := '0'; VARIABLE TD_TMSIn_TCK : VitalTimingDataType; VARIABLE Rviol_MRSTNeg_CLKP1 : X01 := '0'; VARIABLE RD_MRSTNeg_CLKP1 : VitalTimingDataType; VARIABLE Rviol_MRSTNeg_CLKP2 : X01 := '0'; VARIABLE RD_MRSTNeg_CLKP2 : VitalTimingDataType; VARIABLE Rviol_MRSTNeg_CLKP3 : X01 := '0'; VARIABLE RD_MRSTNeg_CLKP3 : VitalTimingDataType; VARIABLE Rviol_MRSTNeg_CLKP4 : X01 := '0'; VARIABLE RD_MRSTNeg_CLKP4 : VitalTimingDataType; VARIABLE Rviol_TRSTNeg_TCK : X01 := '0'; VARIABLE RD_TRSTNeg_TCK : VitalTimingDataType; VARIABLE Pviol_TCK : X01 := '0'; VARIABLE PD_TCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_MRSTNeg : X01 := '0'; VARIABLE PD_MRSTNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_TRSTNeg : X01 := '0'; VARIABLE PD_TRSTNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP1 : X01 := '0'; VARIABLE PD_CLKP1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP2 : X01 := '0'; VARIABLE PD_CLKP2 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP3 : X01 := '0'; VARIABLE PD_CLKP3 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP4 : X01 := '0'; VARIABLE PD_CLKP4 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; VARIABLE state1 : mem_state; VARIABLE state2 : mem_state; VARIABLE state3 : mem_state; VARIABLE state4 : mem_state; VARIABLE prev_state1 : mem_state; VARIABLE prev_state2 : mem_state; VARIABLE prev_state3 : mem_state; VARIABLE prev_state4 : mem_state; VARIABLE Clk11 : BOOLEAN := false; VARIABLE Clk12 : BOOLEAN := false; VARIABLE Clk13 : BOOLEAN := false; VARIABLE Clk14 : BOOLEAN := false; VARIABLE Clk21 : BOOLEAN := false; VARIABLE Clk22 : BOOLEAN := false; VARIABLE Clk23 : BOOLEAN := false; VARIABLE Clk24 : BOOLEAN := false; VARIABLE Clk31 : BOOLEAN := false; VARIABLE Clk32 : BOOLEAN := false; VARIABLE Clk33 : BOOLEAN := false; VARIABLE Clk34 : BOOLEAN := false; VARIABLE Clk41 : BOOLEAN := false; VARIABLE Clk42 : BOOLEAN := false; VARIABLE Clk43 : BOOLEAN := false; VARIABLE Clk44 : BOOLEAN := false; VARIABLE CntTmp1 : std_logic_vector(15 downto 0); VARIABLE Cnt1 : std_logic_vector(15 downto 0); VARIABLE MaskReg1 : std_logic_vector(15 downto 0); VARIABLE Tmp1 : NATURAL RANGE 0 TO 65535; VARIABLE MSB1 : NATURAL RANGE 0 TO 15; VARIABLE rdbc1cnt1 : BOOLEAN := false; VARIABLE rdbc1cnt2 : BOOLEAN := false; VARIABLE rdbc1mk1 : BOOLEAN := false; VARIABLE rdbc1mk2 : BOOLEAN := false; VARIABLE cntinr1 : BOOLEAN := false; VARIABLE OP1Buf1 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE OP1Buf2 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE CntTmp2 : std_logic_vector(15 downto 0); VARIABLE Cnt2 : std_logic_vector(15 downto 0); VARIABLE MaskReg2 : std_logic_vector(15 downto 0); VARIABLE Tmp2 : NATURAL RANGE 0 TO 65535; VARIABLE MSB2 : NATURAL RANGE 0 TO 15; VARIABLE rdbc2cnt1 : BOOLEAN := false; VARIABLE rdbc2cnt2 : BOOLEAN := false; VARIABLE rdbc2mk1 : BOOLEAN := false; VARIABLE rdbc2mk2 : BOOLEAN := false; VARIABLE cntinr2 : BOOLEAN := false; VARIABLE OP2Buf1 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE OP2Buf2 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE CntTmp3 : std_logic_vector(15 downto 0); VARIABLE Cnt3 : std_logic_vector(15 downto 0); VARIABLE MaskReg3 : std_logic_vector(15 downto 0); VARIABLE Tmp3 : NATURAL RANGE 0 TO 65535; VARIABLE MSB3 : NATURAL RANGE 0 TO 15; VARIABLE rdbc3cnt1 : BOOLEAN := false; VARIABLE rdbc3cnt2 : BOOLEAN := false; VARIABLE rdbc3mk1 : BOOLEAN := false; VARIABLE rdbc3mk2 : BOOLEAN := false; VARIABLE cntinr3 : BOOLEAN := false; VARIABLE OP3Buf1 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE OP3Buf2 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE CntTmp4 : std_logic_vector(15 downto 0); VARIABLE Cnt4 : std_logic_vector(15 downto 0); VARIABLE MaskReg4 : std_logic_vector(15 downto 0); VARIABLE Tmp4 : NATURAL RANGE 0 TO 65535; VARIABLE MSB4 : NATURAL RANGE 0 TO 15; VARIABLE rdbc4cnt1 : BOOLEAN := false; VARIABLE rdbc4cnt2 : BOOLEAN := false; VARIABLE rdbc4mk1 : BOOLEAN := false; VARIABLE rdbc4mk2 : BOOLEAN := false; VARIABLE cntinr4 : BOOLEAN := false; VARIABLE OP4Buf1 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE OP4Buf2 : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'Z'); VARIABLE Collision1 : BOOLEAN := false; VARIABLE Collision2 : BOOLEAN := false; VARIABLE Collision3 : BOOLEAN := false; VARIABLE Collision4 : BOOLEAN := false; -- Output Glitch Detection Variables VARIABLE INT1_GlitchData : VitalGlitchDataType; VARIABLE INT2_GlitchData : VitalGlitchDataType; VARIABLE INT3_GlitchData : VitalGlitchDataType; VARIABLE INT4_GlitchData : VitalGlitchDataType; VARIABLE CNTINT1_GlitchData : VitalGlitchDataType; VARIABLE CNTINT2_GlitchData : VitalGlitchDataType; VARIABLE CNTINT3_GlitchData : VitalGlitchDataType; VARIABLE CNTINT4_GlitchData : VitalGlitchDataType; VARIABLE INT1_zd : std_logic := 'Z'; VARIABLE INT2_zd : std_logic := 'Z'; VARIABLE INT3_zd : std_logic := 'Z'; VARIABLE INT4_zd : std_logic := 'Z'; VARIABLE CNTINT1_zd : std_logic := 'Z'; VARIABLE CNTINT2_zd : std_logic := 'Z'; VARIABLE CNTINT3_zd : std_logic := 'Z'; VARIABLE CNTINT4_zd : std_logic := 'Z'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => AddressP1In, TestSignalName => "AddressP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_A0P1_CLKP1, SetupLow => tsetup_A0P1_CLKP1, HoldHigh => thold_A0P1_CLKP1, HoldLow => thold_A0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressP1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressP1In_CLK ); VitalSetupHoldCheck ( TestSignal => AddressP2In, TestSignalName => "AddressP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_A0P1_CLKP1, SetupLow => tsetup_A0P1_CLKP1, HoldHigh => thold_A0P1_CLKP1, HoldLow => thold_A0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressP2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressP2In_CLK ); VitalSetupHoldCheck ( TestSignal => AddressP3In, TestSignalName => "AddressP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_A0P1_CLKP1, SetupLow => tsetup_A0P1_CLKP1, HoldHigh => thold_A0P1_CLKP1, HoldLow => thold_A0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressP3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressP3In_CLK ); VitalSetupHoldCheck ( TestSignal => AddressP4In, TestSignalName => "AddressP4", RefSignal => CLKIn(3), RefSignalName => "CLKP1", SetupHigh => tsetup_A0P1_CLKP1, SetupLow => tsetup_A0P1_CLKP1, HoldHigh => thold_A0P1_CLKP1, HoldLow => thold_A0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressP4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressP4In_CLK ); VitalSetupHoldCheck ( TestSignal => DatA1In, TestSignalName => "DatA1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatA1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatA1In_CLK ); VitalSetupHoldCheck ( TestSignal => DatA2In, TestSignalName => "DatA2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatA2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatA2In_CLK ); VitalSetupHoldCheck ( TestSignal => DatA3In, TestSignalName => "DatA3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatA3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatA3In_CLK ); VitalSetupHoldCheck ( TestSignal => DatA4In, TestSignalName => "DatA4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatA4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatA4In_CLK ); VitalSetupHoldCheck ( TestSignal => DatB1In, TestSignalName => "DatB1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatB1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatB1In_CLK ); VitalSetupHoldCheck ( TestSignal => DatB2In, TestSignalName => "DatB2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatB2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatB2In_CLK ); VitalSetupHoldCheck ( TestSignal => DatB3In, TestSignalName => "DatB3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatB3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatB3In_CLK ); VitalSetupHoldCheck ( TestSignal => DatB4In, TestSignalName => "DatB4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_IO0P1_CLKP1, SetupLow => tsetup_IO0P1_CLKP1, HoldHigh => thold_IO0P1_CLKP1, HoldLow => thold_IO0P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatB4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatB4In_CLK ); VitalSetupHoldCheck ( TestSignal => RWIn(0), TestSignalName => "RWP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_RWP1_CLKP1, SetupLow => tsetup_RWP1_CLKP1, HoldHigh => thold_RWP1_CLKP1, HoldLow => thold_RWP1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RW1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RW1In_CLK ); VitalSetupHoldCheck ( TestSignal => RWIn(1), TestSignalName => "RWP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_RWP1_CLKP1, SetupLow => tsetup_RWP1_CLKP1, HoldHigh => thold_RWP1_CLKP1, HoldLow => thold_RWP1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RW2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RW2In_CLK ); VitalSetupHoldCheck ( TestSignal => RWIn(2), TestSignalName => "RWP2", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_RWP1_CLKP1, SetupLow => tsetup_RWP1_CLKP1, HoldHigh => thold_RWP1_CLKP1, HoldLow => thold_RWP1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RW3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RW3In_CLK ); VitalSetupHoldCheck ( TestSignal => RWIn(3), TestSignalName => "RWP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_RWP1_CLKP1, SetupLow => tsetup_RWP1_CLKP1, HoldHigh => thold_RWP1_CLKP1, HoldLow => thold_RWP1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RW4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RW4In_CLK ); VitalSetupHoldCheck ( TestSignal => CE0NegIn(0), TestSignalName => "CE3NegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0Neg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0Neg1In_CLK ); VitalSetupHoldCheck ( TestSignal => CE0NegIn(1), TestSignalName => "CE3NegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0Neg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0Neg2In_CLK ); VitalSetupHoldCheck ( TestSignal => CE0NegIn(2), TestSignalName => "CE3NegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0Neg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0Neg3In_CLK ); VitalSetupHoldCheck ( TestSignal => CE0NegIn(3), TestSignalName => "CE3NegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0Neg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0Neg4In_CLK ); VitalSetupHoldCheck ( TestSignal => CE1In(0), TestSignalName => "CE1P1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1P1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1P1In_CLK ); VitalSetupHoldCheck ( TestSignal => CE1In(1), TestSignalName => "CE1P1", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1P2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1P2In_CLK ); VitalSetupHoldCheck ( TestSignal => CE1In(2), TestSignalName => "CE1P3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1P3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1P3In_CLK ); VitalSetupHoldCheck ( TestSignal => CE1In(3), TestSignalName => "CE1P4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CE1P1_CLKP1, SetupLow => tsetup_CE1P1_CLKP1, HoldHigh => thold_CE1P1_CLKP1, HoldLow => thold_CE1P1_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1P4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1P4In_CLK ); VitalSetupHoldCheck ( TestSignal => LBNegIn(0), TestSignalName => "LBNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LB1NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LB1NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => LBNegIn(1), TestSignalName => "LBNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LB2NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LB2NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => LBNegIn(2), TestSignalName => "LBNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LB3NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LB3NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => LBNegIn(3), TestSignalName => "LBNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LB4NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LB4NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => UBNegIn(0), TestSignalName => "UBNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UB1NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UB1NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => UBNegIn(1), TestSignalName => "UBNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UB2NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UB2NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => UBNegIn(2), TestSignalName => "UBNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UB3NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UB3NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => UBNegIn(3), TestSignalName => "UBNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_LBP1Neg_CLKP1, SetupLow => tsetup_LBP1Neg_CLKP1, HoldHigh => thold_LBP1Neg_CLKP1, HoldLow => thold_LBP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UB4NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UB4NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => CNTLDNegIn(0), TestSignalName => "CNTLDNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CNTLDP1Neg_CLKP1, SetupLow => tsetup_CNTLDP1Neg_CLKP1, HoldHigh => thold_CNTLDP1Neg_CLKP1, HoldLow => thold_CNTLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTLDNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTLDNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTLDNegIn(1), TestSignalName => "CNTLDNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CNTLDP1Neg_CLKP1, SetupLow => tsetup_CNTLDP1Neg_CLKP1, HoldHigh => thold_CNTLDP1Neg_CLKP1, HoldLow => thold_CNTLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTLDNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTLDNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTLDNegIn(2), TestSignalName => "CNTLDNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CNTLDP1Neg_CLKP1, SetupLow => tsetup_CNTLDP1Neg_CLKP1, HoldHigh => thold_CNTLDP1Neg_CLKP1, HoldLow => thold_CNTLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTLDNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTLDNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTLDNegIn(3), TestSignalName => "CNTLDNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CNTLDP1Neg_CLKP1, SetupLow => tsetup_CNTLDP1Neg_CLKP1, HoldHigh => thold_CNTLDP1Neg_CLKP1, HoldLow => thold_CNTLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTLDNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTLDNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTINCNegIn(0), TestSignalName => "CNTINCNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CNTINCP1Neg_CLKP1, SetupLow => tsetup_CNTINCP1Neg_CLKP1, HoldHigh => thold_CNTINCP1Neg_CLKP1, HoldLow => thold_CNTINCP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTINCNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTINCNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTINCNegIn(1), TestSignalName => "CNTINCNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CNTINCP1Neg_CLKP1, SetupLow => tsetup_CNTINCP1Neg_CLKP1, HoldHigh => thold_CNTINCP1Neg_CLKP1, HoldLow => thold_CNTINCP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTINCNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTINCNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTINCNegIn(2), TestSignalName => "CNTINCNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CNTINCP1Neg_CLKP1, SetupLow => tsetup_CNTINCP1Neg_CLKP1, HoldHigh => thold_CNTINCP1Neg_CLKP1, HoldLow => thold_CNTINCP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTINCNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTINCNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTINCNegIn(3), TestSignalName => "CNTINCNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CNTINCP1Neg_CLKP1, SetupLow => tsetup_CNTINCP1Neg_CLKP1, HoldHigh => thold_CNTINCP1Neg_CLKP1, HoldLow => thold_CNTINCP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTINCNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTINCNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRSTNegIn(0), TestSignalName => "CNTRSTNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CNTRSTP1Neg_CLKP1, SetupLow => tsetup_CNTRSTP1Neg_CLKP1, HoldHigh => thold_CNTRSTP1Neg_CLKP1, HoldLow => thold_CNTRSTP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRSTNegIn(1), TestSignalName => "CNTRSTNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CNTRSTP1Neg_CLKP1, SetupLow => tsetup_CNTRSTP1Neg_CLKP1, HoldHigh => thold_CNTRSTP1Neg_CLKP1, HoldLow => thold_CNTRSTP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRSTNegIn(2), TestSignalName => "CNTRSTNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CNTRSTP1Neg_CLKP1, SetupLow => tsetup_CNTRSTP1Neg_CLKP1, HoldHigh => thold_CNTRSTP1Neg_CLKP1, HoldLow => thold_CNTRSTP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRSTNegIn(3), TestSignalName => "CNTRSTNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CNTRSTP1Neg_CLKP1, SetupLow => tsetup_CNTRSTP1Neg_CLKP1, HoldHigh => thold_CNTRSTP1Neg_CLKP1, HoldLow => thold_CNTRSTP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRDNegIn(0), TestSignalName => "CNTRDNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_CNTRDP1Neg_CLKP1, SetupLow => tsetup_CNTRDP1Neg_CLKP1, HoldHigh => thold_CNTRDP1Neg_CLKP1, HoldLow => thold_CNTRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRDNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRDNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRDNegIn(1), TestSignalName => "CNTRDNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_CNTRDP1Neg_CLKP1, SetupLow => tsetup_CNTRDP1Neg_CLKP1, HoldHigh => thold_CNTRDP1Neg_CLKP1, HoldLow => thold_CNTRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRDNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRDNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRDNegIn(2), TestSignalName => "CNTRDNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_CNTRDP1Neg_CLKP1, SetupLow => tsetup_CNTRDP1Neg_CLKP1, HoldHigh => thold_CNTRDP1Neg_CLKP1, HoldLow => thold_CNTRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRDNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRDNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => CNTRDNegIn(3), TestSignalName => "CNTRDNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_CNTRDP1Neg_CLKP1, SetupLow => tsetup_CNTRDP1Neg_CLKP1, HoldHigh => thold_CNTRDP1Neg_CLKP1, HoldLow => thold_CNTRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRDNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRDNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => MKLDNegIn(0), TestSignalName => "MKLDNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_MKLDP1Neg_CLKP1, SetupLow => tsetup_MKLDP1Neg_CLKP1, HoldHigh => thold_MKLDP1Neg_CLKP1, HoldLow => thold_MKLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKLDNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKLDNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => MKLDNegIn(1), TestSignalName => "MKLDNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_MKLDP1Neg_CLKP1, SetupLow => tsetup_MKLDP1Neg_CLKP1, HoldHigh => thold_MKLDP1Neg_CLKP1, HoldLow => thold_MKLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKLDNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKLDNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => MKLDNegIn(2), TestSignalName => "MKLDNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_MKLDP1Neg_CLKP1, SetupLow => tsetup_MKLDP1Neg_CLKP1, HoldHigh => thold_MKLDP1Neg_CLKP1, HoldLow => thold_MKLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKLDNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKLDNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => MKLDNegIn(3), TestSignalName => "MKLDNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_MKLDP1Neg_CLKP1, SetupLow => tsetup_MKLDP1Neg_CLKP1, HoldHigh => thold_MKLDP1Neg_CLKP1, HoldLow => thold_MKLDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKLDNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKLDNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => MKRDNegIn(0), TestSignalName => "MKRDNegP1", RefSignal => CLKIn(0), RefSignalName => "CLKP1", SetupHigh => tsetup_MKRDP1Neg_CLKP1, SetupLow => tsetup_MKRDP1Neg_CLKP1, HoldHigh => thold_MKRDP1Neg_CLKP1, HoldLow => thold_MKRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKRDNeg1In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKRDNeg1In_CLK ); VitalSetupHoldCheck ( TestSignal => MKRDNegIn(1), TestSignalName => "MKRDNegP2", RefSignal => CLKIn(1), RefSignalName => "CLKP2", SetupHigh => tsetup_MKRDP1Neg_CLKP1, SetupLow => tsetup_MKRDP1Neg_CLKP1, HoldHigh => thold_MKRDP1Neg_CLKP1, HoldLow => thold_MKRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKRDNeg2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKRDNeg2In_CLK ); VitalSetupHoldCheck ( TestSignal => MKRDNegIn(2), TestSignalName => "MKRDNegP3", RefSignal => CLKIn(2), RefSignalName => "CLKP3", SetupHigh => tsetup_MKRDP1Neg_CLKP1, SetupLow => tsetup_MKRDP1Neg_CLKP1, HoldHigh => thold_MKRDP1Neg_CLKP1, HoldLow => thold_MKRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKRDNeg3In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKRDNeg3In_CLK ); VitalSetupHoldCheck ( TestSignal => MKRDNegIn(3), TestSignalName => "MKRDNegP4", RefSignal => CLKIn(3), RefSignalName => "CLKP4", SetupHigh => tsetup_MKRDP1Neg_CLKP1, SetupLow => tsetup_MKRDP1Neg_CLKP1, HoldHigh => thold_MKRDP1Neg_CLKP1, HoldLow => thold_MKRDP1Neg_CLKP1, CheckEnabled => (MRSTNegIn = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_MKRDNeg4In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MKRDNeg4In_CLK ); VitalSetupHoldCheck ( TestSignal => TDIIn, TestSignalName => "TDI", RefSignal => TCKIn, RefSignalName => "TCK", SetupHigh => tsetup_TDI_TCK, SetupLow => tsetup_TDI_TCK, HoldHigh => thold_TDI_TCK, HoldLow => thold_TDI_TCK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_TDIIn_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TDIIn_TCK ); VitalSetupHoldCheck ( TestSignal => TMSIn, TestSignalName => "TMS", RefSignal => TCKIn, RefSignalName => "TCK", SetupHigh => tsetup_TDI_TCK, SetupLow => tsetup_TDI_TCK, HoldHigh => thold_TDI_TCK, HoldLow => thold_TDI_TCK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_TMSIn_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TMSIn_TCK ); VitalRecoveryRemovalCheck ( TestSignal => MRSTNegIn, TestSignalName => "MRSTNeg", RefSignal => CLKIn(0), RefSignalName => "CLKP1", Recovery => trecovery_MRSTNeg_CLKP1, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_MRSTNeg_CLKP1, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MRSTNeg_CLKP1 ); VitalRecoveryRemovalCheck ( TestSignal => MRSTNegIn, TestSignalName => "MRSTNeg", RefSignal => CLKIn(1), RefSignalName => "CLKP2", Recovery => trecovery_MRSTNeg_CLKP1, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_MRSTNeg_CLKP2, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MRSTNeg_CLKP2 ); VitalRecoveryRemovalCheck ( TestSignal => MRSTNegIn, TestSignalName => "MRSTNeg", RefSignal => CLKIn(2), RefSignalName => "CLKP3", Recovery => trecovery_MRSTNeg_CLKP1, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_MRSTNeg_CLKP3, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MRSTNeg_CLKP3 ); VitalRecoveryRemovalCheck ( TestSignal => MRSTNegIn, TestSignalName => "MRSTNeg", RefSignal => CLKIn(3), RefSignalName => "CLKP4", Recovery => trecovery_MRSTNeg_CLKP1, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_MRSTNeg_CLKP4, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_MRSTNeg_CLKP4 ); VitalRecoveryRemovalCheck ( TestSignal => TRSTNegIn, TestSignalName => "TRSTNeg", RefSignal => TCKIn, RefSignalName => "TCK", Recovery => trecovery_TRSTNeg_TCK, ActiveLow => true, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => RD_TRSTNeg_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_TRSTNeg_TCK ); VitalPeriodPulseCheck ( TestSignal => CLKIn(0), TestSignalName => "CLKP1", Period => tperiod_CLKP1_posedge, PulseWidthLow => tpw_CLKP1_negedge, PulseWidthHigh => tpw_CLKP1_posedge, PeriodData => PD_CLKP1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP1, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => CLKIn(1), TestSignalName => "CLKP2", Period => tperiod_CLKP1_posedge, PulseWidthLow => tpw_CLKP1_negedge, PulseWidthHigh => tpw_CLKP1_posedge, PeriodData => PD_CLKP2, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP2, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => CLKIn(2), TestSignalName => "CLKP3", Period => tperiod_CLKP1_posedge, PulseWidthLow => tpw_CLKP1_negedge, PulseWidthHigh => tpw_CLKP1_posedge, PeriodData => PD_CLKP3, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP3, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => CLKIn(3), TestSignalName => "CLKP4", Period => tperiod_CLKP1_posedge, PulseWidthLow => tpw_CLKP1_negedge, PulseWidthHigh => tpw_CLKP1_posedge, PeriodData => PD_CLKP4, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP4, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => TCKIn, TestSignalName => "TCK", Period => tperiod_TCK_posedge, PulseWidthLow => tpw_TCK_negedge, PulseWidthHigh => tpw_TCK_posedge, PeriodData => PD_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_TCK, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => MRSTNegIn, TestSignalName => "MRSTNeg", PulseWidthLow => tpw_MRSTNeg_negedge, PeriodData => PD_MRSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSTNeg, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); VitalPeriodPulseCheck ( TestSignal => TRSTNegIn, TestSignalName => "TRSTNeg", PulseWidthLow => tpw_TRSTNeg_negedge, PeriodData => PD_TRSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_TRSTNeg, HeaderMsg => InstancePath & PartID, CheckEnabled => true ); Violation := Tviol_AddressP1In_CLK OR Tviol_AddressP2In_CLK OR Tviol_AddressP3In_CLK OR Tviol_AddressP4In_CLK OR Tviol_DatA1In_CLK OR Tviol_DatA2In_CLK OR Tviol_DatA3In_CLK OR Tviol_DatA4In_CLK OR Tviol_DatB1In_CLK OR Tviol_DatB2In_CLK OR Tviol_DatB3In_CLK OR Tviol_DatB4In_CLK OR Tviol_RW1In_CLK OR Tviol_RW2In_CLK OR Tviol_RW3In_CLK OR Tviol_RW4In_CLK OR Tviol_CE0Neg1In_CLK OR Tviol_CE0Neg2In_CLK OR Tviol_CE0Neg3In_CLK OR Tviol_CE0Neg4In_CLK OR Tviol_CE1P1In_CLK OR Tviol_CE1P2In_CLK OR Tviol_CE1P3In_CLK OR Tviol_CE1P4In_CLK OR Tviol_LB1NegIn_CLK OR Tviol_LB2NegIn_CLK OR Tviol_LB3NegIn_CLK OR Tviol_LB4NegIn_CLK OR Tviol_UB1NegIn_CLK OR Tviol_UB2NegIn_CLK OR Tviol_UB3NegIn_CLK OR Tviol_UB4NegIn_CLK OR Tviol_CNTLDNeg1In_CLK OR Tviol_CNTLDNeg2In_CLK OR Tviol_CNTLDNeg3In_CLK OR Tviol_CNTRSTNeg4In_CLK OR Tviol_CNTINCNeg1In_CLK OR Tviol_CNTINCNeg2In_CLK OR Tviol_CNTINCNeg3In_CLK OR Tviol_CNTRDNeg4In_CLK OR Tviol_CNTRDNeg1In_CLK OR Tviol_CNTINCNeg4In_CLK OR Tviol_CNTRDNeg2In_CLK OR Tviol_CNTRSTNeg2In_CLK OR Tviol_CNTRSTNeg1In_CLK OR Tviol_CNTRDNeg3In_CLK OR Tviol_CNTRSTNeg3In_CLK OR Tviol_CNTLDNeg4In_CLK OR Tviol_MKLDNeg1In_CLK OR Tviol_MKLDNeg2In_CLK OR Tviol_MKLDNeg3In_CLK OR Tviol_MKLDNeg4In_CLK OR Tviol_MKRDNeg1In_CLK OR Tviol_MKRDNeg2In_CLK OR Tviol_MKRDNeg3In_CLK OR Tviol_MKRDNeg4In_CLK OR Tviol_TDIIn_TCK OR Tviol_TMSIn_TCK OR Pviol_CLKP1 OR Pviol_CLKP2 OR Pviol_CLKP3 OR Pviol_CLKP4 OR Pviol_TCK OR Pviol_MRSTNeg OR Pviol_TRSTNeg OR Rviol_TRSTNeg_TCK OR Rviol_MRSTNeg_CLKP1 OR Rviol_MRSTNeg_CLKP2 OR Rviol_MRSTNeg_CLKP3 OR Rviol_MRSTNeg_CLKP4; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; ---------------------------------------------------------------------------- -- Functional Section ---------------------------------------------------------------------------- -- Port1 Address counter IF rising_edge(CLKIn(0)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(CNTLDNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for CNTLD1" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTINCNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for CNTINC1" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRDNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for CNTRD1" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRSTNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for CNTRST1" SEVERITY SeverityMode; ASSERT (not(Is_X(MKLDNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for MKLD1" SEVERITY SeverityMode; ASSERT (not(Is_X(MKRDNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for MKRD1" SEVERITY SeverityMode; ASSERT (not(Is_X(RWIn(0)))) REPORT InstancePath & partID & ": Unusable value for RW1" SEVERITY SeverityMode; ASSERT (not(Is_X(CE0NegIn(0)))) REPORT InstancePath & partID & ": Unusable value for CE01" SEVERITY SeverityMode; ASSERT (not(Is_X(CE1In(0)))) REPORT InstancePath & partID & ": Unusable value for CE11" SEVERITY SeverityMode; rdbc1cnt2 := rdbc1cnt1; rdbc1cnt1 := false; rdbc1mk2 := rdbc1mk1; rdbc1mk1 := false; IF rdbc1cnt2 = true THEN A1_zd <= CntTmp1; ELSIF rdbc1mk2 = true THEN A1_zd <= MaskReg1; ELSE A1_zd <= (others => 'Z'); END IF; IF cntinr1 = true THEN CNTINT1_zd := '1'; cntinr1 := false; ELSE CNTINT1_zd := '1'; END IF; IF CNTRSTNegIn(0) = '0' THEN CntTmp1 := "0000000000000000"; ELSIF MKLDNegIn(0) = '0' THEN MaskReg1 := AddressP1In; ELSIF CNTLDNegIn(0) = '0' THEN CntTmp1 := AddressP1In; ELSIF CNTINCNegIn(0) = '0' THEN IF CntTmp1 = MaskReg1 THEN CNTINT1_zd := '0'; cntinr1 := true; END IF; Tmp1 := to_nat(CntTmp1) + 1; Cnt1 := to_slv(Tmp1,16); -- wrap around FOR I IN 0 TO 15 LOOP IF Cnt1(i) = '1' THEN MSB1 := i; END IF; END LOOP; FOR I IN 0 TO 15 LOOP IF MaskReg1(i) = '0' THEN IF MSB1 = i AND Cnt1(i) = '1' AND CntTmp1(i) = '0' THEN IF i < 15 THEN MSB1 := i+1; Cnt1(i+1) := '1'; END IF; Cnt1(i) := '0'; ELSE Cnt1(i) := CntTmp1(i); END IF; END IF; END LOOP; CntTmp1 := Cnt1; END IF; IF CNTRDNegIn(0) = '0' THEN rdbc1cnt1 := true; ELSIF MKRDNegIn(0) = '0' THEN rdbc1mk1 := true; END IF; IF CE0NegIn(0) = '0' AND CE1In(0) = '1' THEN IF RWIn(0) = '0' THEN -- write state1 := write; ELSE state1 := read; END IF; ELSE state1 := desel; END IF; END IF; -- Port2 Address counter IF rising_edge(CLKIn(1)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(CNTLDNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for CNTLD2" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTINCNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for CNTINC2" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRDNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for CNTRD2" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRSTNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for CNTRST2" SEVERITY SeverityMode; ASSERT (not(Is_X(MKLDNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for MKLD2" SEVERITY SeverityMode; ASSERT (not(Is_X(MKRDNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for MKRD2" SEVERITY SeverityMode; ASSERT (not(Is_X(RWIn(1)))) REPORT InstancePath & partID & ": Unusable value for RW2" SEVERITY SeverityMode; ASSERT (not(Is_X(CE0NegIn(1)))) REPORT InstancePath & partID & ": Unusable value for CE02" SEVERITY SeverityMode; ASSERT (not(Is_X(CE1In(1)))) REPORT InstancePath & partID & ": Unusable value for CE12" SEVERITY SeverityMode; rdbc2cnt2 := rdbc2cnt1; rdbc2cnt1 := false; rdbc2mk2 := rdbc2mk1; rdbc2mk1 := false; IF rdbc2cnt2 = true THEN A2_zd <= CntTmp2; ELSIF rdbc2mk2 = true THEN A2_zd <= MaskReg2; ELSE A2_zd <= (others => 'Z'); END IF; IF cntinr2 = true THEN CNTINT2_zd := '1'; cntinr2 := false; ELSE CNTINT2_zd := '1'; END IF; IF CNTRSTNegIn(1) = '0' THEN CntTmp2 := "0000000000000000"; ELSIF MKLDNegIn(1) = '0' THEN MaskReg2 := AddressP2In; ELSIF CNTLDNegIn(1) = '0' THEN CntTmp2 := AddressP2In; ELSIF CNTINCNegIn(1) = '0' THEN IF CntTmp2 = MaskReg2 THEN CNTINT2_zd := '0'; cntinr2 := true; END IF; Tmp2 := to_nat(CntTmp2) + 1; Cnt2 := to_slv(Tmp2,16); -- wrap around FOR I IN 0 TO 15 LOOP IF Cnt2(i) = '1' THEN MSB2 := i; END IF; END LOOP; FOR I IN 0 TO 15 LOOP IF MaskReg2(i) = '0' THEN IF MSB2 = i AND Cnt2(i) = '1' AND CntTmp2(i) = '0' THEN IF i < 15 THEN MSB2 := i+1; Cnt2(i+1) := '1'; END IF; Cnt2(i) := '0'; ELSE Cnt2(i) := CntTmp2(i); END IF; END IF; END LOOP; CntTmp2 := Cnt2; END IF; IF CNTRDNegIn(1) = '0' THEN rdbc2cnt1 := true; ELSIF MKRDNegIn(1) = '0' THEN rdbc2mk1 := true; END IF; IF CE0NegIn(1) = '0' AND CE1In(1) = '1' THEN IF RWIn(1) = '0' THEN state2 := write; ELSE state2 := read; END IF; ELSE state2 := desel; END IF; END IF; -- Port3 Address counter IF rising_edge(CLKIn(2)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(RWIn(2)))) REPORT InstancePath & partID & ": Unusable value for RW3" SEVERITY SeverityMode; ASSERT (not(Is_X(CE0NegIn(2)))) REPORT InstancePath & partID & ": Unusable value for CE03" SEVERITY SeverityMode; ASSERT (not(Is_X(CE1In(2)))) REPORT InstancePath & partID & ": Unusable value for CE13" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTLDNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for CNTLD3" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTINCNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for CNTINC3" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRDNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for CNTRD3" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRSTNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for CNTRST3" SEVERITY SeverityMode; ASSERT (not(Is_X(MKLDNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for MKLD3" SEVERITY SeverityMode; ASSERT (not(Is_X(MKRDNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for MKRD3" SEVERITY SeverityMode; rdbc3cnt2 := rdbc3cnt1; rdbc3cnt1 := false; rdbc3mk2 := rdbc3mk1; rdbc3mk1 := false; IF rdbc3cnt2 = true THEN A3_zd <= CntTmp3; ELSIF rdbc3mk2 = true THEN A3_zd <= MaskReg3; ELSE A3_zd <= (others => 'Z'); END IF; IF cntinr3 = true THEN CNTINT3_zd := '1'; cntinr3 := false; ELSE CNTINT3_zd := '1'; END IF; IF CNTRSTNegIn(2) = '0' THEN CntTmp3 := "0000000000000000"; ELSIF MKLDNegIn(2) = '0' THEN MaskReg3 := AddressP3In; ELSIF CNTLDNegIn(2) = '0' THEN CntTmp3 := AddressP3In; ELSIF CNTINCNegIn(2) = '0' THEN IF CntTmp3 = MaskReg3 THEN CNTINT3_zd := '0'; cntinr3 := true; END IF; Tmp3 := to_nat(CntTmp3) + 1; Cnt3 := to_slv(Tmp3,16); -- wrap around FOR I IN 0 TO 15 LOOP IF Cnt3(i) = '1' THEN MSB3 := i; END IF; END LOOP; FOR I IN 0 TO 15 LOOP IF MaskReg3(i) = '0' THEN IF MSB3 = i AND Cnt3(i) = '1' AND CntTmp3(i) = '0' THEN IF i < 15 THEN MSB3 := i+1; Cnt3(i+1) := '1'; END IF; Cnt3(i) := '0'; ELSE Cnt3(i) := CntTmp3(i); END IF; END IF; END LOOP; CntTmp3 := Cnt3; END IF; IF CNTRDNegIn(2) = '0' THEN rdbc3cnt1 := true; ELSIF MKRDNegIn(2) = '0' THEN rdbc3mk1 := true; END IF; IF CE0NegIn(2) = '0' AND CE1In(2) = '1' THEN IF RWIn(2) = '0' THEN state3 := write; ELSE state3 := read; END IF; ELSE state3 := desel; END IF; END IF; -- Port4 Address counter IF rising_edge(CLKIn(3)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(RWIn(3)))) REPORT InstancePath & partID & ": Unusable value for RW4" SEVERITY SeverityMode; ASSERT (not(Is_X(CE0NegIn(3)))) REPORT InstancePath & partID & ": Unusable value for CE04" SEVERITY SeverityMode; ASSERT (not(Is_X(CE1In(3)))) REPORT InstancePath & partID & ": Unusable value for CE14" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTLDNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for CNTLD4" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTINCNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for CNTINC4" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRDNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for CNTRD4" SEVERITY SeverityMode; ASSERT (not(Is_X(CNTRSTNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for CNTRST4" SEVERITY SeverityMode; ASSERT (not(Is_X(MKLDNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for MKLD4" SEVERITY SeverityMode; ASSERT (not(Is_X(MKRDNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for MKRD4" SEVERITY SeverityMode; rdbc4cnt2 := rdbc4cnt1; rdbc4cnt1 := false; rdbc4mk2 := rdbc4mk1; rdbc4mk1 := false; IF rdbc4cnt2 = true THEN A4_zd <= CntTmp4; ELSIF rdbc4mk2 = true THEN A4_zd <= MaskReg4; ELSE A4_zd <= (others => 'Z'); END IF; IF cntinr4 = true THEN CNTINT4_zd := '1'; cntinr4 := false; ELSE CNTINT4_zd := '1'; END IF; IF CNTRSTNegIn(3) = '0' THEN CntTmp4 := "0000000000000000"; ELSIF MKLDNegIn(3) = '0' THEN MaskReg4 := AddressP4In; ELSIF CNTLDNegIn(3) = '0' THEN CntTmp4 := AddressP4In; ELSIF CNTINCNegIn(3) = '0' THEN IF CntTmp4 = MaskReg4 THEN CNTINT4_zd := '0'; cntinr4 := true; END IF; Tmp4 := to_nat(CntTmp4) + 1; Cnt4 := to_slv(Tmp4,16); -- wrap around FOR I IN 0 TO 15 LOOP IF Cnt4(i) = '1' THEN MSB4 := i; END IF; END LOOP; FOR I IN 0 TO 15 LOOP IF MaskReg4(i) = '0' THEN IF MSB4 = i AND Cnt4(i) = '1' AND CntTmp4(i) = '0' THEN IF i < 15 THEN MSB4 := i+1; Cnt4(i+1) := '1'; END IF; Cnt4(i) := '0'; ELSE Cnt4(i) := CntTmp4(i); END IF; END IF; END LOOP; CntTmp4 := Cnt4; END IF; IF CNTRDNegIn(3) = '0' THEN rdbc4cnt1 := true; ELSIF MKRDNegIn(3) = '0' THEN rdbc4mk1 := true; END IF; IF CE0NegIn(3) = '0' AND CE1In(3) = '1' THEN IF RWIn(3) = '0' THEN state4 := write; ELSE state4 := read; END IF; ELSE state4 := desel; END IF; END IF; -- Port1 IF rising_edge(CLKIn(0)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(LBNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for LB1" SEVERITY SeverityMode; ASSERT (not(Is_X(UBNegIn(0)))) REPORT InstancePath & partID & ": Unusable value for UB1" SEVERITY SeverityMode; OP1Buf2 := OP1Buf1; IF state1 = write THEN OP1Buf1 := (others => 'Z'); IF OENegIn(0) = '0' AND prev_state1 = read THEN OP1Buf2 := (others => 'Z'); ELSE Collision1 := false; IF CntTmp1 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 /= desel)) THEN Collision1 := true; ELSIF CntTmp1 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 /= desel)) THEN Collision1 := true; ELSIF CntTmp1 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 /= desel)) THEN Collision1 := true; ELSE Collision1 := false; END IF; IF LBNegIn(0) = '0' THEN ccs_in(0) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision1 THEN MemDatA(to_nat(CntTmp1)) := -1; ELSE MemDatA(to_nat(CntTmp1)) := to_nat(DatA1In); END IF; END IF; IF UBNegIn(0) = '0' THEN ccs_in(0) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision1 THEN MemDatB(to_nat(CntTmp1)) := -1; ELSE MemDatB(to_nat(CntTmp1)) := to_nat(DatB1In); END IF; END IF; IF CntTmp1 = "1111111111111110" THEN INT2_zd := '0'; Clk21 := true; Clk22 := false; ELSIF CntTmp1 = "1111111111111101" THEN INT3_zd := '0'; Clk31 := true; Clk33 := false; ELSIF CntTmp1 = "1111111111111100" THEN INT4_zd := '0'; Clk41 := true; Clk44 := false; END IF; END IF; ELSIF state1 = read THEN Collision1 := false; IF CntTmp1 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 = write)) THEN Collision1 := true; ELSIF CntTmp1 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 = write)) THEN Collision1 := true; ELSIF CntTmp1 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 = write)) THEN Collision1 := true; ELSE Collision1 := false; END IF; IF LBNegIn(0) = '0' THEN IF MemDatA(to_nat(CntTmp1)) = -2 THEN OP1Buf1(8 downto 0) := (others => 'U'); ELSIF MemDatA(to_nat(CntTmp1)) = -1 OR Collision1 THEN OP1Buf1(8 downto 0) := (others => 'X'); ELSE OP1Buf1(8 downto 0) := to_slv(MemDatA(to_nat(CntTmp1)),9); END IF; END IF; IF UBNegIn(0) = '0' THEN IF MemDatB(to_nat(CntTmp1)) = -2 THEN OP1Buf1(17 downto 9) := (others => 'U'); ELSIF MemDatB(to_nat(CntTmp1)) = -1 OR Collision1 THEN OP1Buf1(17 downto 9) := (others => 'X'); ELSE OP1Buf1(17 downto 9) := to_slv(MemDatB(to_nat(CntTmp1)),9); END IF; END IF; IF CntTmp1 = "1111111111111111" THEN INT1_zd := '1'; Clk11 := true; Clk12 := false; Clk13 := false; Clk14 := false; END IF; ELSE -- deselect OP1Buf1 := (others => 'Z'); END IF; prev_state1 := state1; IF (OENegIn(0) = '0') THEN D1_zd <= (others => 'Z'), OP1Buf2 AFTER 1 ns; END IF; END IF; IF (OENegIn(0) = '1') THEN D1_zd <= (others => 'Z'); ELSE D1_zd <= OP1Buf2; END IF; -- Port2 IF rising_edge(CLKIn(1)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(LBNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for LB2" SEVERITY SeverityMode; ASSERT (not(Is_X(UBNegIn(1)))) REPORT InstancePath & partID & ": Unusable value for UB2" SEVERITY SeverityMode; OP2Buf2 := OP2Buf1; IF state2 = write Then OP2Buf1 := (others => 'Z'); IF OENegIn(1) = '0' AND prev_state2 = read THEN OP2Buf2 := (others => 'Z'); ELSE Collision2 := false; IF CntTmp2 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 /= desel)) THEN Collision2 := true; ELSIF CntTmp2 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 /= desel)) THEN Collision2 := true; ELSIF CntTmp2 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 /= desel)) THEN Collision2 := true; ELSE Collision2 := false; END IF; IF LBNegIn(1) = '0' THEN ccs_in(1) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision2 THEN MemDatA(to_nat(CntTmp2)) := -1; ELSE MemDatA(to_nat(CntTmp2)) := to_nat(DatA2In); END IF; END IF; IF UBNegIn(1) = '0' THEN ccs_in(1) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision2 THEN MemDatB(to_nat(CntTmp2)) := -1; ELSE MemDatB(to_nat(CntTmp2)) := to_nat(DatB2In); END IF; END IF; IF CntTmp2 = "1111111111111111" THEN INT1_zd := '0'; Clk12 := true; Clk11 := false; ELSIF CntTmp2 = "1111111111111101" THEN INT3_zd := '0'; Clk32 := true; Clk33 := false; ELSIF CntTmp2 = "1111111111111100" THEN INT4_zd := '0'; Clk42 := true; Clk44 := false; END IF; END IF; ELSIF state2 = read THEN IF CntTmp2 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 = write)) THEN Collision2 := true; ELSIF CntTmp2 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 = write)) THEN Collision2 := true; ELSIF CntTmp2 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 = write)) THEN Collision2 := true; ELSE Collision2 := false; END IF; IF LBNegIn(1) = '0' THEN IF MemDatA(to_nat(CntTmp2)) = -2 THEN OP2Buf1(8 downto 0) := (others => 'U'); ELSIF MemDatA(to_nat(CntTmp2)) = -1 OR Collision2 THEN OP2Buf1(8 downto 0) := (others => 'X'); ELSE OP2Buf1(8 downto 0) := to_slv(MemDatA(to_nat(CntTmp2)),9); END IF; END IF; IF UBNegIn(1) = '0' THEN IF MemDatB(to_nat(CntTmp2)) = -2 THEN OP2Buf1(17 downto 9) := (others => 'U'); ELSIF MemDatB(to_nat(CntTmp2)) = -1 OR Collision2 THEN OP2Buf1(17 downto 9) := (others => 'X'); ELSE OP2Buf1(17 downto 9) := to_slv(MemDatB(to_nat(CntTmp2)),9); END IF; END IF; IF CntTmp2 = "1111111111111110" THEN INT2_zd := '1'; Clk21 := false; Clk23 := false; Clk24 := false; Clk22 := true; END IF; ELSE -- deselect OP2Buf1 := (others => 'Z'); END IF; prev_state2 := state2; IF (OENegIn(1) = '0') THEN D2_zd <= (others => 'Z'), OP2Buf2 AFTER 1 ns; END IF; END IF; IF (OENegIn(1) = '1') THEN D2_zd <= (others => 'Z'); ELSE D2_zd <= OP2Buf2; END IF; -- Port3 IF rising_edge(CLKIn(2)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(LBNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for LB3" SEVERITY SeverityMode; ASSERT (not(Is_X(UBNegIn(2)))) REPORT InstancePath & partID & ": Unusable value for UB3" SEVERITY SeverityMode; OP3Buf2 := OP3Buf1; IF state3 = write THEN OP3Buf1 := (others => 'Z'); IF OENegIn(2) = '0' AND prev_state3 = read THEN OP3Buf2 := (others => 'Z'); ELSE IF CntTmp3 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 /= desel)) THEN Collision3 := true; ELSIF CntTmp3 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 /= desel)) THEN Collision3 := true; ELSIF CntTmp3 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 /= desel)) THEN Collision3 := true; ELSE Collision3 := false; END IF; IF LBNegIn(2) = '0' THEN ccs_in(2) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision3 THEN MemDatA(to_nat(CntTmp3)) := -1; ELSE MemDatA(to_nat(CntTmp3)) := to_nat(DatA3In); END IF; END IF; IF UBNegIn(2) = '0' THEN ccs_in(2) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision3 THEN MemDatB(to_nat(CntTmp3)) := -1; ELSE MemDatB(to_nat(CntTmp3)) := to_nat(DatB3In); END IF; END IF; IF CntTmp3 = "1111111111111111" THEN INT1_zd := '0'; Clk31 := true; Clk33 := false; ELSIF CntTmp3 = "1111111111111110" THEN INT2_zd := '0'; Clk32 := true; Clk33 := false; ELSIF CntTmp3 = "1111111111111100" THEN INT4_zd := '0'; Clk34 := true; Clk33 := false; END IF; END IF; ELSIF state3 = read THEN IF CntTmp3 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 = write)) THEN Collision3 := true; ELSIF CntTmp3 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 = write)) THEN Collision3 := true; ELSIF CntTmp3 = CntTmp4 AND (ccs_out(3) = '1' OR (rising_edge(CLKIn(3)) AND state4 = write)) THEN Collision3 := true; ELSE Collision3 := false; END IF; IF LBNegIn(2) = '0' THEN IF MemDatA(to_nat(CntTmp3)) = -2 THEN OP3Buf1(8 downto 0) := (others => 'U'); ELSIF MemDatA(to_nat(CntTmp3)) = -1 OR Collision3 THEN OP3Buf1(8 downto 0) := (others => 'X'); ELSE OP3Buf1(8 downto 0) := to_slv(MemDatA(to_nat(CntTmp3)),9); END IF; END IF; IF UBNegIn(2) = '0' THEN IF MemDatB(to_nat(CntTmp3)) = -2 THEN OP3Buf1(17 downto 9) := (others => 'U'); ELSIF MemDatB(to_nat(CntTmp3)) = -1 OR Collision3 THEN OP3Buf1(17 downto 9) := (others => 'X'); ELSE OP3Buf1(17 downto 9) := to_slv(MemDatB(to_nat(CntTmp3)),9); END IF; END IF; IF CntTmp3 = "1111111111111101" THEN INT3_zd := '1'; Clk33 := true; Clk31 := false; Clk32 := false; Clk34 := false; END IF; ELSE -- deselect OP3Buf1 := (others => 'Z'); END IF; prev_state3 := state3; IF (OENegIn(2) = '0') THEN D3_zd <= (others => 'Z'), OP3Buf2 AFTER 1 ns; END IF; END IF; IF (OENegIn(2) = '1') THEN D3_zd <= (others => 'Z'); ELSE D3_zd <= OP3Buf2; END IF; -- Port4 IF rising_edge(CLKIn(3)) AND MRSTNegIn = '1' THEN ASSERT (not(Is_X(LBNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for LB4" SEVERITY SeverityMode; ASSERT (not(Is_X(UBNegIn(3)))) REPORT InstancePath & partID & ": Unusable value for UB4" SEVERITY SeverityMode; OP4Buf2 := OP4Buf1; IF state4 = write THEN OP4Buf1 := (others => 'Z'); IF OENegIn(3) = '0' AND prev_state4 = read THEN OP4Buf2 := (others => 'Z'); ELSE IF CntTmp4 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 /= desel)) THEN Collision4 := true; ELSIF CntTmp4 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 /= desel)) THEN Collision4 := true; ELSIF CntTmp4 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 /= desel)) THEN Collision4 := true; ELSE Collision4 := false; END IF; IF LBNegIn(3) = '0' THEN ccs_in(3) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision4 THEN MemDatA(to_nat(CntTmp4)) := -1; ELSE MemDatA(to_nat(CntTmp4)) := to_nat(DatA4In); END IF; END IF; IF UBNegIn(3) = '0' THEN ccs_in(3) <= '1', '0' AFTER 1 ns; IF Violation = 'X' OR Collision4 THEN MemDatB(to_nat(CntTmp4)) := -1; ELSE MemDatB(to_nat(CntTmp4)) := to_nat(DatB4In); END IF; END IF; IF CntTmp4 = "1111111111111111" THEN INT1_zd := '0'; Clk41 := true; Clk44 := false; ELSIF CntTmp4 = "1111111111111110" THEN INT2_zd := '0'; Clk42 := true; Clk44 := false; ELSIF CntTmp4 = "1111111111111101" THEN INT3_zd := '0'; Clk43 := true; Clk44 := false; END IF; END IF; ELSIF state4 = read THEN IF CntTmp4 = CntTmp1 AND (ccs_out(0) = '1' OR (rising_edge(CLKIn(0)) AND state1 = write)) THEN Collision4 := true; ELSIF CntTmp4 = CntTmp2 AND (ccs_out(1) = '1' OR (rising_edge(CLKIn(1)) AND state2 = write)) THEN Collision4 := true; ELSIF CntTmp4 = CntTmp3 AND (ccs_out(2) = '1' OR (rising_edge(CLKIn(2)) AND state3 = write)) THEN Collision4 := true; ELSE Collision4 := false; END IF; IF LBNegIn(3) = '0' THEN IF MemDatA(to_nat(CntTmp4)) = -2 THEN OP4Buf1(8 downto 0) := (others => 'U'); ELSIF MemDatA(to_nat(CntTmp4)) = -1 OR Collision4 THEN OP4Buf1(8 downto 0) := (others => 'X'); ELSE OP4Buf1(8 downto 0) := to_slv(MemDatA(to_nat(CntTmp4)),9); END IF; END IF; IF UBNegIn(3) = '0' THEN IF MemDatB(to_nat(CntTmp4)) = -2 THEN OP4Buf1(17 downto 9) := (others => 'U'); ELSIF MemDatB(to_nat(CntTmp4)) = -1 OR Collision4 THEN OP4Buf1(17 downto 9) := (others => 'X'); ELSE OP4Buf1(17 downto 9) := to_slv(MemDatB(to_nat(CntTmp4)),9); END IF; END IF; IF CntTmp4 = "1111111111111100" THEN INT4_zd := '1'; Clk44 := true; Clk41 := false; Clk42 := false; Clk43 := false; END IF; ELSE -- deselect OP4Buf1 := (others => 'Z'); END IF; prev_state4 := state4; IF (OENegIn(3) = '0') THEN D4_zd <= (others => 'Z'), OP4Buf2 AFTER 1 ns; END IF; END IF; IF (OENegIn(3) = '1') THEN D4_zd <= (others => 'Z'); ELSE D4_zd <= OP4Buf2; END IF; -- Reset IF MRSTNegIn = '0' THEN CntTmp1 := "0000000000000000"; MaskReg1 := "1111111111111111"; INT1_zd := '1'; CNTINT1_zd := '1'; D1_zd <= (others => 'Z'); A1_zd <= (others => 'Z'); CntTmp2 := "0000000000000000"; MaskReg2 := "1111111111111111"; INT2_zd := '1'; CNTINT2_zd := '1'; D2_zd <= (others => 'Z'); A2_zd <= (others => 'Z'); CntTmp3 := "0000000000000000"; MaskReg3 := "1111111111111111"; INT3_zd := '1'; CNTINT3_zd := '1'; D3_zd <= (others => 'Z'); A3_zd <= (others => 'Z'); CntTmp4 := "0000000000000000"; MaskReg4 := "1111111111111111"; INT4_zd := '1'; CNTINT4_zd := '1'; D4_zd <= (others => 'Z'); A4_zd <= (others => 'Z'); END IF; IF Instruct = extest OR Instruct = clamp THEN A1_zd(0) <= BSReg(259); A1_zd(1) <= BSReg(261); A1_zd(2) <= BSReg(263); A1_zd(3) <= BSReg(265); A1_zd(4) <= BSReg(267); A1_zd(5) <= BSReg(269); A1_zd(6) <= BSReg(271); A1_zd(7) <= BSReg(273); A1_zd(8) <= BSReg(275); A1_zd(9) <= BSReg(277); A1_zd(10) <= BSReg(279); A1_zd(11) <= BSReg(281); A1_zd(12) <= BSReg(283); A1_zd(13) <= BSReg(285); A1_zd(14) <= BSReg(287); A1_zd(15) <= BSReg(289); D1_zd(0) <= BSReg(161); D1_zd(1) <= BSReg(163); D1_zd(2) <= BSReg(165); D1_zd(3) <= BSReg(167); D1_zd(4) <= BSReg(169); D1_zd(5) <= BSReg(171); D1_zd(6) <= BSReg(173); D1_zd(7) <= BSReg(175); D1_zd(8) <= BSReg(177); D1_zd(9) <= BSReg(339); D1_zd(10) <= BSReg(341); D1_zd(11) <= BSReg(343); D1_zd(12) <= BSReg(345); D1_zd(13) <= BSReg(347); D1_zd(14) <= BSReg(349); D1_zd(15) <= BSReg(351); D1_zd(16) <= BSReg(353); D1_zd(17) <= BSReg(355); INT1_zd := BSReg(317); CNTINT1_zd := BSReg(291); A2_zd(0) <= BSReg(197); A2_zd(1) <= BSReg(199); A2_zd(2) <= BSReg(201); A2_zd(3) <= BSReg(203); A2_zd(4) <= BSReg(205); A2_zd(5) <= BSReg(207); A2_zd(6) <= BSReg(209); A2_zd(7) <= BSReg(211); A2_zd(8) <= BSReg(213); A2_zd(9) <= BSReg(215); A2_zd(10) <= BSReg(217); A2_zd(11) <= BSReg(219); A2_zd(12) <= BSReg(221); A2_zd(13) <= BSReg(223); A2_zd(14) <= BSReg(225); A2_zd(15) <= BSReg(227); D2_zd(0) <= BSReg(179); D2_zd(1) <= BSReg(181); D2_zd(2) <= BSReg(183); D2_zd(3) <= BSReg(185); D2_zd(4) <= BSReg(187); D2_zd(5) <= BSReg(189); D2_zd(6) <= BSReg(191); D2_zd(7) <= BSReg(193); D2_zd(8) <= BSReg(195); D2_zd(9) <= BSReg(321); D2_zd(10) <= BSReg(323); D2_zd(11) <= BSReg(325); D2_zd(12) <= BSReg(327); D2_zd(13) <= BSReg(329); D2_zd(14) <= BSReg(331); D2_zd(15) <= BSReg(333); D2_zd(16) <= BSReg(335); D2_zd(17) <= BSReg(337); INT2_zd := BSReg(255); CNTINT2_zd := BSReg(229); A3_zd(0) <= BSReg(63); A3_zd(1) <= BSReg(65); A3_zd(2) <= BSReg(67); A3_zd(3) <= BSReg(69); A3_zd(4) <= BSReg(71); A3_zd(5) <= BSReg(73); A3_zd(6) <= BSReg(75); A3_zd(7) <= BSReg(77); A3_zd(8) <= BSReg(79); A3_zd(9) <= BSReg(81); A3_zd(10) <= BSReg(83); A3_zd(11) <= BSReg(85); A3_zd(12) <= BSReg(87); A3_zd(13) <= BSReg(89); A3_zd(14) <= BSReg(91); A3_zd(15) <= BSReg(93); D3_zd(0) <= BSReg(143); D3_zd(1) <= BSReg(145); D3_zd(2) <= BSReg(147); D3_zd(3) <= BSReg(149); D3_zd(4) <= BSReg(151); D3_zd(5) <= BSReg(153); D3_zd(6) <= BSReg(155); D3_zd(7) <= BSReg(157); D3_zd(8) <= BSReg(159); D3_zd(9) <= BSReg(357); D3_zd(10) <= BSReg(359); D3_zd(11) <= BSReg(361); D3_zd(12) <= BSReg(363); D3_zd(13) <= BSReg(365); D3_zd(14) <= BSReg(367); D3_zd(15) <= BSReg(369); D3_zd(16) <= BSReg(371); D3_zd(17) <= BSReg(373); INT3_zd := BSReg(121); CNTINT3_zd := BSReg(95); A4_zd(0) <= BSReg(1); A4_zd(1) <= BSReg(3); A4_zd(2) <= BSReg(5); A4_zd(3) <= BSReg(7); A4_zd(4) <= BSReg(9); A4_zd(5) <= BSReg(11); A4_zd(6) <= BSReg(13); A4_zd(7) <= BSReg(15); A4_zd(8) <= BSReg(17); A4_zd(9) <= BSReg(19); A4_zd(10) <= BSReg(21); A4_zd(11) <= BSReg(23); A4_zd(12) <= BSReg(25); A4_zd(13) <= BSReg(27); A4_zd(14) <= BSReg(29); A4_zd(15) <= BSReg(31); D4_zd(0) <= BSReg(125); D4_zd(1) <= BSReg(127); D4_zd(2) <= BSReg(129); D4_zd(3) <= BSReg(131); D4_zd(4) <= BSReg(133); D4_zd(5) <= BSReg(135); D4_zd(6) <= BSReg(137); D4_zd(7) <= BSReg(139); D4_zd(8) <= BSReg(141); D4_zd(9) <= BSReg(375); D4_zd(10) <= BSReg(377); D4_zd(11) <= BSReg(379); D4_zd(12) <= BSReg(381); D4_zd(13) <= BSReg(383); D4_zd(14) <= BSReg(385); D4_zd(15) <= BSReg(387); D4_zd(16) <= BSReg(389); D4_zd(17) <= BSReg(391); INT4_zd := BSReg(59); CNTINT4_zd := BSReg(33); ELSIF Instruct = highz THEN A1_zd <= (others => 'Z'); D1_zd <= (others => 'Z'); INT1_zd := 'Z'; CNTINT1_zd := 'Z'; A2_zd <= (others => 'Z'); D2_zd <= (others => 'Z'); INT2_zd := 'Z'; CNTINT2_zd := 'Z'; A3_zd <= (others => 'Z'); D3_zd <= (others => 'Z'); INT3_zd := 'Z'; CNTINT3_zd := 'Z'; A4_zd <= (others => 'Z'); D4_zd <= (others => 'Z'); INT4_zd := 'Z'; CNTINT4_zd := 'Z'; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => INTNegOut(0), OutSignalName => "INTP1", OutTemp => INT1_zd, GlitchData => INT1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk11 = true), 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk12 = true), 2 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk13 = true), 3 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk14 = true), 4 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => INTNegOut(1), OutSignalName => "INTP2", OutTemp => INT2_zd, GlitchData => INT2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk21 = true), 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk22 = true), 2 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk23 = true), 3 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk24 = true), 4 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => INTNegOut(2), OutSignalName => "INTP3", OutTemp => INT3_zd, GlitchData => INT3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk31 = true), 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk32 = true), 2 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk33 = true), 3 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk34 = true), 4 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => INTNegOut(3), OutSignalName => "INTP4", OutTemp => INT4_zd, GlitchData => INT4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk41 = true), 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk42 = true), 2 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk43 = true), 3 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_INTP1Neg, PathCondition => MRSTNegIn = '1' AND Clk44 = true), 4 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => CNTINTNegOut(0), OutSignalName => "CNTINTP1", OutTemp => CNTINT1_zd, GlitchData => CNTINT1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_CNTINTP1Neg, PathCondition => MRSTNegIn = '1'), 1 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => CNTINTNegOut(1), OutSignalName => "CNTINTP2", OutTemp => CNTINT2_zd, GlitchData => CNTINT2_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_CNTINTP1Neg, PathCondition => MRSTNegIn = '1'), 1 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => CNTINTNegOut(2), OutSignalName => "CNTINTP3", OutTemp => CNTINT3_zd, GlitchData => CNTINT3_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_CNTINTP1Neg, PathCondition => MRSTNegIn = '1'), 1 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); VitalPathDelay01 ( OutSignal => CNTINTNegOut(3), OutSignalName => "CNTINTP4", OutTemp => CNTINT4_zd, GlitchData => CNTINT4_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_CNTINTP1Neg, PathCondition => MRSTNegIn = '1'), 1 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); END PROCESS BEHAVIOR; --------------------------------------------------------------------------- -- JTAG --------------------------------------------------------------------------- JTAG : PROCESS (TDIIn, TRSTNegIN, TMSIn, TCKIn) TYPE tap_state_type IS (Test_Logic_Reset, Run_Test_Idle, Select_DR_Scan, Capture_DR, Shift_DR, Exit1_DR, Pause_DR, Exit2_DR, Update_DR, Select_IR_Scan, Capture_IR, Shift_IR, Exit1_IR, Pause_IR, Exit2_IR, Update_IR ); VARIABLE TAP_state : tap_state_type; VARIABLE BYReg : std_logic := '0'; VARIABLE MSReg : std_logic_vector(1 downto 0) := "00"; VARIABLE IReg : std_logic_vector(3 downto 0); VARIABLE MRReg : std_logic_vector(25 downto 0) := (others => '0'); VARIABLE IDReg : std_logic_vector(31 downto 0); VARIABLE BYTmp : std_logic; VARIABLE MSTmp : std_logic_vector(1 downto 0); VARIABLE ITmp : std_logic_vector(3 downto 0); VARIABLE MRTmp : std_logic_vector(25 downto 0); VARIABLE IDTmp : std_logic_vector(31 downto 0); VARIABLE BSTmp : std_logic_vector(391 downto 0) := (others => '1'); VARIABLE TDOTmp : std_logic; VARIABLE Shift : BOOLEAN := false; VARIABLE UpdateIR : BOOLEAN := false; VARIABLE UpdateDR : BOOLEAN := false; -- Output Glitch Detection Variables VARIABLE TDO_GlitchData : VitalGlitchDataType; VARIABLE TDO_zd : std_logic := 'Z'; BEGIN -- Power Up & Reset JTAG IF NOW = 0 ns OR TRSTNegIn = '0' THEN TAP_state := Test_Logic_Reset; Shift := false; UpdateIR := false; UpdateDR := false; Instruct <= idcode; END IF; -- TAP State Machine IF rising_edge(TCKIn) THEN CASE TAP_state IS WHEN Test_Logic_Reset => IF TMSIn = '1' THEN TAP_state := Test_Logic_Reset; IReg := "0111"; IDReg := "00000000001100011101000001100111"; Instruct <= idcode; ELSE TAP_state := Run_Test_Idle; END IF; WHEN Run_Test_Idle => IF TMSIn = '1' THEN TAP_state := Select_DR_Scan; ELSE TAP_state := Run_Test_Idle; END IF; WHEN Select_DR_Scan => IF TMSIn = '1' THEN TAP_state := Select_IR_Scan; ELSE TAP_state := Capture_DR; CASE Instruct IS WHEN extest => BSTmp := BSReg; WHEN bypass => BYTmp := BYReg; WHEN idcode => IDTmp := IDReg; WHEN highz => BYTmp := BYReg; WHEN sample_preload => BSTmp(1) := AddressP4In(0); BSTmp(3) := AddressP4In(1); BSTmp(5) := AddressP4In(2); BSTmp(7) := AddressP4In(3); BSTmp(9) := AddressP4In(4); BSTmp(11) := AddressP4In(5); BSTmp(13) := AddressP4In(6); BSTmp(15) := AddressP4In(7); BSTmp(17) := AddressP4In(8); BSTmp(19) := AddressP4In(9); BSTmp(21) := AddressP4In(10); BSTmp(23) := AddressP4In(11); BSTmp(25) := AddressP4In(12); BSTmp(27) := AddressP4In(13); BSTmp(29) := AddressP4In(14); BSTmp(31) := AddressP4In(15); BSTmp(63) := AddressP3In(0); BSTmp(65) := AddressP3In(1); BSTmp(67) := AddressP3In(2); BSTmp(69) := AddressP3In(3); BSTmp(71) := AddressP3In(4); BSTmp(73) := AddressP3In(5); BSTmp(75) := AddressP3In(6); BSTmp(77) := AddressP3In(7); BSTmp(79) := AddressP3In(8); BSTmp(81) := AddressP3In(9); BSTmp(83) := AddressP3In(10); BSTmp(85) := AddressP3In(11); BSTmp(87) := AddressP3In(12); BSTmp(89) := AddressP3In(13); BSTmp(91) := AddressP3In(14); BSTmp(93) := AddressP3In(15); BSTmp(197) := AddressP2In(0); BSTmp(199) := AddressP2In(1); BSTmp(201) := AddressP2In(2); BSTmp(203) := AddressP2In(3); BSTmp(205) := AddressP2In(4); BSTmp(207) := AddressP2In(5); BSTmp(209) := AddressP2In(6); BSTmp(211) := AddressP2In(7); BSTmp(213) := AddressP2In(8); BSTmp(215) := AddressP2In(9); BSTmp(217) := AddressP2In(10); BSTmp(219) := AddressP2In(11); BSTmp(221) := AddressP2In(12); BSTmp(223) := AddressP2In(13); BSTmp(225) := AddressP2In(14); BSTmp(227) := AddressP2In(15); BSTmp(259) := AddressP1In(0); BSTmp(261) := AddressP1In(1); BSTmp(263) := AddressP1In(2); BSTmp(265) := AddressP1In(3); BSTmp(267) := AddressP1In(4); BSTmp(269) := AddressP1In(5); BSTmp(271) := AddressP1In(6); BSTmp(273) := AddressP1In(7); BSTmp(275) := AddressP1In(8); BSTmp(277) := AddressP1In(9); BSTmp(279) := AddressP1In(10); BSTmp(281) := AddressP1In(11); BSTmp(283) := AddressP1In(12); BSTmp(285) := AddressP1In(13); BSTmp(287) := AddressP1In(14); BSTmp(289) := AddressP1In(15); BSTmp(161) := DatA1In(0); BSTmp(163) := DatA1In(1); BSTmp(165) := DatA1In(2); BSTmp(167) := DatA1In(3); BSTmp(169) := DatA1In(4); BSTmp(171) := DatA1In(5); BSTmp(173) := DatA1In(6); BSTmp(175) := DatA1In(7); BSTmp(177) := DatA1In(8); BSTmp(339) := DatB1In(0); BSTmp(341) := DatB1In(1); BSTmp(343) := DatB1In(2); BSTmp(345) := DatB1In(3); BSTmp(347) := DatB1In(4); BSTmp(349) := DatB1In(5); BSTmp(351) := DatB1In(6); BSTmp(353) := DatB1In(7); BSTmp(355) := DatB1In(8); BSTmp(179) := DatA2In(0); BSTmp(181) := DatA2In(1); BSTmp(183) := DatA2In(2); BSTmp(185) := DatA2In(3); BSTmp(187) := DatA2In(4); BSTmp(189) := DatA2In(5); BSTmp(191) := DatA2In(6); BSTmp(193) := DatA2In(7); BSTmp(195) := DatA2In(8); BSTmp(321) := DatB2In(0); BSTmp(323) := DatB2In(1); BSTmp(325) := DatB2In(2); BSTmp(327) := DatB2In(3); BSTmp(329) := DatB2In(4); BSTmp(331) := DatB2In(5); BSTmp(333) := DatB2In(6); BSTmp(335) := DatB2In(7); BSTmp(337) := DatB2In(8); BSTmp(143) := DatA3In(0); BSTmp(145) := DatA3In(1); BSTmp(147) := DatA3In(2); BSTmp(149) := DatA3In(3); BSTmp(151) := DatA3In(4); BSTmp(153) := DatA3In(5); BSTmp(155) := DatA3In(6); BSTmp(157) := DatA3In(7); BSTmp(159) := DatA3In(8); BSTmp(357) := DatB3In(0); BSTmp(359) := DatB3In(1); BSTmp(361) := DatB3In(2); BSTmp(363) := DatB3In(3); BSTmp(365) := DatB3In(4); BSTmp(367) := DatB3In(5); BSTmp(369) := DatB3In(6); BSTmp(371) := DatB3In(7); BSTmp(373) := DatB3In(8); BSTmp(125) := DatA4In(0); BSTmp(127) := DatA4In(1); BSTmp(129) := DatA4In(2); BSTmp(131) := DatA4In(3); BSTmp(133) := DatA4In(4); BSTmp(135) := DatA4In(5); BSTmp(137) := DatA4In(6); BSTmp(139) := DatA4In(7); BSTmp(141) := DatA4In(8); BSTmp(375) := DatB4In(0); BSTmp(379) := DatB4In(2); BSTmp(381) := DatB4In(3); BSTmp(383) := DatB4In(4); BSTmp(385) := DatB4In(5); BSTmp(387) := DatB4In(6); BSTmp(389) := DatB4In(7); BSTmp(391) := DatB4In(8); BSTmp(35) := CNTRSTNegIn(3); BSTmp(97) := CNTRSTNegIn(2); BSTmp(231) := CNTRSTNegIn(1); BSTmp(293) := CNTRSTNegIn(0); BSTmp(41) := CNTINCNegIn(3); BSTmp(103) := CNTINCNegIn(2); BSTmp(237) := CNTINCNegIn(1); BSTmp(299) := CNTINCNegIn(0); BSTmp(39) := CNTLDNegIn(3); BSTmp(101) := CNTLDNegIn(2); BSTmp(235) := CNTLDNegIn(1); BSTmp(297) := CNTLDNegIn(0); BSTmp(43) := CNTRDNegIn(3); BSTmp(105) := CNTRDNegIn(2); BSTmp(239) := CNTRDNegIn(1); BSTmp(301) := CNTRDNegIn(0); BSTmp(37) := MKLDNegIn(3); BSTmp(99) := MKLDNegIn(2); BSTmp(233) := MKLDNegIn(1); BSTmp(295) := MKLDNegIn(0); BSTmp(45) := MKRDNegIn(3); BSTmp(107) := MKRDNegIn(2); BSTmp(241) := MKRDNegIn(1); BSTmp(303) := MKRDNegIn(0); BSTmp(51) := OENegIn(0); BSTmp(113) := OENegIn(3); BSTmp(247) := OENegIn(2); BSTmp(309) := OENegIn(1); BSTmp(49) := UBNegIn(3); BSTmp(111) := UBNegIn(2); BSTmp(245) := UBNegIn(1); BSTmp(307) := UBNegIn(0); BSTmp(47) := LBNegIn(3); BSTmp(109) := LBNegIn(2); BSTmp(243) := LBNegIn(1); BSTmp(305) := LBNegIn(0); BSTmp(57) := CE0NegIn(3); BSTmp(119) := CE0NegIn(2); BSTmp(253) := CE0NegIn(1); BSTmp(315) := CE0NegIn(0); BSTmp(55) := CE1In(3); BSTmp(117) := CE1In(2); BSTmp(251) := CE1In(1); BSTmp(313) := CE1In(0); BSTmp(53) := RWIn(3); BSTmp(115) := RWIn(2); BSTmp(249) := RWIn(1); BSTmp(311) := RWIn(0); BSTmp(61) := CLKIn(3); BSTmp(123) := CLKIn(2); BSTmp(257) := CLKIn(1); BSTmp(319) := CLKIn(0); BSReg <= BSTmp; WHEN mbistmode => MSTmp := MSReg; WHEN int_scan => MRTmp := MRReg; WHEN clamp => BYTmp := BYReg; WHEN others => NULL; END CASE; END IF; WHEN Capture_DR => IF TMSIn = '1' THEN TAP_state := Exit1_DR; Shift := false; ELSE TAP_state := Shift_DR; CASE Instruct IS WHEN extest => TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN bypass => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN idcode => TDOTmp := IDTmp(0); FOR I IN 0 TO 30 LOOP IDTmp(i) := IDTmp(i+1); END LOOP; IDTmp(31) := TDIIn; Shift := true; WHEN highz => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN sample_preload => BSTmp := BSReg; TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN mbistmode => TDOTmp := MSTmp(0); MSTmp(0) := MSTmp(1); MSTmp(1) := TDIIn; Shift := true; WHEN int_scan => TDOTmp := MRTmp(0); FOR I IN 0 TO 24 LOOP MRTmp(i) := MRTmp(i+1); END LOOP; MRTmp(25) := TDIIn; Shift := true; WHEN clamp => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN others => NULL; END CASE; END IF; WHEN Shift_DR => IF TMSIn = '1' THEN TAP_state := Exit1_DR; Shift := false; ELSE TAP_state := Shift_DR; CASE Instruct IS WHEN extest => TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN bypass => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN idcode => TDOTmp := IDTmp(0); FOR I IN 0 TO 30 LOOP IDTmp(i) := IDTmp(i+1); END LOOP; IDTmp(31) := TDIIn; Shift := true; WHEN highz => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN sample_preload => TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN mbistmode => TDOTmp := MSTmp(0); MSTmp(0) := MSTmp(1); MSTmp(1) := TDIIn; Shift := true; WHEN int_scan => TDOTmp := MRTmp(0); FOR I IN 0 TO 24 LOOP MRTmp(i) := MRTmp(i+1); END LOOP; MRTmp(25) := TDIIn; Shift := true; WHEN clamp => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN others => NULL; END CASE; END IF; WHEN Exit1_DR => IF TMSIn = '1' THEN TAP_state := Update_DR; UpdateDR := true; ELSE TAP_state := Pause_DR; END IF; WHEN Pause_DR => IF TMSIn = '1' THEN TAP_state := Exit2_DR; ELSE TAP_state := Pause_DR; END IF; WHEN Exit2_DR => IF TMSIn = '1' THEN TAP_state := Update_DR; UpdateDR := true; ELSE TAP_state := Shift_DR; CASE Instruct IS WHEN extest => TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN bypass => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN idcode => TDOTmp := IDTmp(0); FOR I IN 0 TO 30 LOOP IDTmp(i) := IDTmp(i+1); END LOOP; IDTmp(31) := TDIIn; Shift := true; WHEN highz => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN sample_preload => TDOTmp := BSTmp(0); FOR I IN 0 TO 390 LOOP BSTmp(i) := BSTmp(i+1); END LOOP; BSTmp(391) := TDIIn; Shift := true; WHEN mbistmode => TDOTmp := MSTmp(0); MSTmp(0) := MSTmp(1); MSTmp(1) := TDIIn; Shift := true; WHEN int_scan => TDOTmp := MRTmp(0); FOR I IN 0 TO 24 LOOP MRTmp(i) := MRTmp(i+1); END LOOP; MRTmp(25) := TDIIn; Shift := true; WHEN clamp => TDOTmp := BYTmp; BYTmp := TDIIn; Shift := true; WHEN others => NULL; END CASE; END IF; WHEN Update_DR => IF TMSIn = '1' THEN TAP_state := Select_DR_Scan; ELSE TAP_state := Run_Test_Idle; END IF; WHEN Select_IR_Scan => IF TMSIn = '1' THEN TAP_state := Test_Logic_Reset; IReg := "0111"; IDReg := "00000000001100011101000001100111"; Instruct <= idcode; ELSE TAP_state := Capture_IR; ITmp := IReg; TDO_zd := 'Z'; END IF; WHEN Capture_IR => IF TMSIn = '1' THEN TAP_state := Exit1_IR; Shift := false; ELSE TAP_state := Shift_IR; TDOTmp := ITmp(0); FOR I IN 0 TO 2 LOOP ITmp(i) := ITmp(i+1); END LOOP; ITmp(3) := TDIIn; Shift := true; END IF; WHEN Shift_IR => IF TMSIn = '1' THEN TAP_state := Exit1_IR; Shift := false; ELSE TAP_state := Shift_IR; TDOTmp := ITmp(0); FOR I IN 0 TO 2 LOOP ITmp(i) := ITmp(i+1); END LOOP; ITmp(3) := TDIIn; Shift := true; END IF; WHEN Exit1_IR => IF TMSIn = '1' THEN TAP_state := Update_IR; UpdateIR := true; ELSE TAP_state := Pause_IR; END IF; WHEN Pause_IR => IF TMSIn = '1' THEN TAP_state := Exit2_IR; ELSE TAP_state := Pause_IR; END IF; WHEN Exit2_IR => IF TMSIn = '1' THEN TAP_state := Update_IR; UpdateIR := true; ELSE TAP_state := Shift_IR; TDOTmp := ITmp(0); FOR I IN 0 TO 2 LOOP ITmp(i) := ITmp(i+1); END LOOP; ITmp(3) := TDIIn; Shift := true; END IF; WHEN Update_IR => IF TMSIn = '1' THEN TAP_state := Select_DR_Scan; ELSE TAP_state := Run_Test_Idle; END IF; END CASE; END IF; IF falling_edge(TCKIn) THEN IF Shift = true THEN TDO_zd := TDOTmp; ELSIF UpdateIR = true THEN TDO_zd := 'Z'; IReg:= ITmp; CASE IReg IS WHEN "0000" => Instruct <= extest; WHEN "1111" => Instruct <= bypass; WHEN "0111" => Instruct <= idcode; IDReg := "00000000001100011101000001100111"; WHEN "0110" => Instruct <= highz; WHEN "0001" => Instruct <= sample_preload; WHEN "1010" => Instruct <= mbistmode; WHEN "1000" => Instruct <= runbist; WHEN "0100" => Instruct <= int_scan; WHEN "0101" => Instruct <= clamp; WHEN others => Instruct <= reserved; END CASE; UpdateIR := false; ELSIF UpdateDR = true THEN TDO_zd := 'Z'; UpdateDR := false; CASE Instruct IS WHEN extest => BSReg <= BSTmp; WHEN bypass => BYReg := BYTmp; WHEN idcode => IDReg := IDTmp; WHEN highz => BYReg := BYTmp; WHEN sample_preload => BSReg <= BSTmp; WHEN mbistmode => MSReg := MSTmp; WHEN int_scan => MRREg := MRTmp; WHEN clamp => BYReg := BYTmp; WHEN others => NULL; END CASE; ELSE TDO_zd := 'Z'; END IF; END IF; ------------------------------------------------------------------------ -- JTAG Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => TDOOut, OutSignalName => "TDO", OutTemp => TDO_zd, GlitchData => TDO_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => TCKIn'LAST_EVENT, PathDelay => tpd_TCK_TDO, PathCondition => TRUE) ) ); END PROCESS JTAG; Preloadfile: PROCESS FILE mem_file : text is mem_file_name; VARIABLE ind : NATURAL := 0; VARIABLE buf : line; BEGIN ------------------------------------------------------------------------ -- File Read Section ------------------------------------------------------------------------ --memory load format --#format : @address --# data -> address --# data -> address+1 IF (mem_file_name /= "none") THEN ind := 0; WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '#' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 5)); ELSE MemDatA(ind) := h(buf(1 to 1)); MemDatB(ind) := h(buf(2 to 2)); ind := ind + 1; END IF; END LOOP; END IF; WAIT; END PROCESS Preloadfile; ------------------------------------------------------------------------ -- Path Delay Process ------------------------------------------------------------------------ DataOutPath1 : FOR I IN 17 DOWNTO 0 GENERATE DataOut_Delay1 : PROCESS (D1_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataP1Out(i), OutSignalName => "DataP1", OutTemp => D1_zd(i), Mode => VitalTransport, GlitchData => D_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_IO0P1, PathCondition => OENegIn(0) = '0' AND MRSTNegIn = '1'), 2 => (InputChangeTime => OENegIn(0)'LAST_EVENT, PathDelay => tpd_OEP1Neg_IO0P1, PathCondition => MRSTNegIn = '1'), 3 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSTNeg_INTP1Neg), PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; DataOutPath2 : FOR I IN 17 DOWNTO 0 GENERATE DataOut_Delay2 : PROCESS (D2_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataP2Out(i), OutSignalName => "DataP2", OutTemp => D2_zd(i), Mode => VitalTransport, GlitchData => D_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_IO0P1, PathCondition => OENegIn(1) = '0' AND MRSTNegIn = '1'), 2 => (InputChangeTime => OENegIn(1)'LAST_EVENT, PathDelay => tpd_OEP1Neg_IO0P1, PathCondition => MRSTNegIn = '1'), 3 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSTNeg_INTP1Neg), PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; DataOutPath3 : FOR I IN 17 DOWNTO 0 GENERATE DataOut_Delay3 : PROCESS (D3_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataP3Out(i), OutSignalName => "DataP3", OutTemp => D3_zd(i), Mode => VitalTransport, GlitchData => D_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_IO0P1, PathCondition => OENegIn(2) = '0' AND MRSTNegIn = '1'), 2 => (InputChangeTime => OENegIn(2)'LAST_EVENT, PathDelay => tpd_OEP1Neg_IO0P1, PathCondition => MRSTNegIn = '1'), 3 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSTNeg_INTP1Neg), PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; DataOutPath4 : FOR I IN 17 DOWNTO 0 GENERATE DataOut_Delay4 : PROCESS (D4_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(17 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataP4Out(i), OutSignalName => "Data41", OutTemp => D4_zd(i), Mode => VitalTransport, GlitchData => D_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_IO0P1, PathCondition => OENegIn(3) = '0' AND MRSTNegIn = '1'), 2 => (InputChangeTime => OENegIn(3)'LAST_EVENT, PathDelay => tpd_OEP1Neg_IO0P1, PathCondition => MRSTNegIn = '1'), 3 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_MRSTNeg_INTP1Neg), PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; AddressOutPath1 : FOR I IN 15 DOWNTO 0 GENERATE AddressOut_Delay1 : PROCESS (A1_zd(i)) VARIABLE A_GlitchData:VitalGlitchDataArrayType(15 Downto 0); BEGIN VitalPathDelay01 ( OutSignal => AddressP1Out(i), OutSignalName => "AddressP1", OutTemp => A1_zd(i), Mode => VitalTransport, GlitchData => A_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(0)'LAST_EVENT, PathDelay => tpd_CLKP1_A0P1, PathCondition => MRSTNegIn = '1'), 2 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; AddressOutPath2 : FOR I IN 15 DOWNTO 0 GENERATE AddressOut_Delay2 : PROCESS (A2_zd(i)) VARIABLE A_GlitchData:VitalGlitchDataArrayType(15 Downto 0); BEGIN VitalPathDelay01 ( OutSignal => AddressP2Out(i), OutSignalName => "AddressP2", OutTemp => A2_zd(i), Mode => VitalTransport, GlitchData => A_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(1)'LAST_EVENT, PathDelay => tpd_CLKP1_A0P1, PathCondition => MRSTNegIn = '1'), 2 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; AddressOutPath3 : FOR I IN 15 DOWNTO 0 GENERATE AddressOut_Delay3 : PROCESS (A3_zd(i)) VARIABLE A_GlitchData:VitalGlitchDataArrayType(15 Downto 0); BEGIN VitalPathDelay01 ( OutSignal => AddressP3Out(i), OutSignalName => "AddressP3", OutTemp => A3_zd(i), Mode => VitalTransport, GlitchData => A_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(2)'LAST_EVENT, PathDelay => tpd_CLKP1_A0P1, PathCondition => MRSTNegIn = '1'), 2 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; AddressOutPath4 : FOR I IN 15 DOWNTO 0 GENERATE AddressOut_Delay4 : PROCESS (A4_zd(i)) VARIABLE A_GlitchData:VitalGlitchDataArrayType(15 Downto 0); BEGIN VitalPathDelay01 ( OutSignal => AddressP4Out(i), OutSignalName => "AddressP4", OutTemp => A4_zd(i), Mode => VitalTransport, GlitchData => A_GlitchData(i), Paths => ( 1 => (InputChangeTime => CLKIn(3)'LAST_EVENT, PathDelay => tpd_CLKP1_A0P1, PathCondition => MRSTNegIn = '1'), 2 => (InputChangeTime => MRSTNegIn'LAST_EVENT, PathDelay => tpd_MRSTNeg_INTP1Neg, PathCondition => MRSTNegIn = '0') ) ); END PROCESS; END GENERATE; END BLOCK; END vhdl_behavioral;