-------------------------------------------------------------------------------- -- File Name: idt70t3509m.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com/ -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- 1.0 V.Ljubisavljevic 07 FEB 23 initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: IDT70T3509M -- -- Description: 1024K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL; USE ieee.std_logic_1164.ALL; LIBRARY fmf; USE fmf.gen_utils.ALL; USE fmf.conversions.all; USE STD.textio.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY idt70t3509m IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLKL : VitalDelayType01 := VitalZeroDelay01; tipd_CLKR : VitalDelayType01 := VitalZeroDelay01; tipd_CE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1L : VitalDelayType01 := VitalZeroDelay01; tipd_CE1R : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PLFTL : VitalDelayType01 := VitalZeroDelay01; tipd_PLFTR : VitalDelayType01 := VitalZeroDelay01; tipd_ADSLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BEL0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BEL1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BEL2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BEL3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BER0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BER1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BER2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_BER3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_ZZL : VitalDelayType01 := VitalZeroDelay01; tipd_ZZR : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL10 : VitalDelayType01 := VitalZeroDelay01; tipd_AL11 : VitalDelayType01 := VitalZeroDelay01; tipd_AL12 : VitalDelayType01 := VitalZeroDelay01; tipd_AL13 : VitalDelayType01 := VitalZeroDelay01; tipd_AL14 : VitalDelayType01 := VitalZeroDelay01; tipd_AL15 : VitalDelayType01 := VitalZeroDelay01; tipd_AL16 : VitalDelayType01 := VitalZeroDelay01; tipd_AL17 : VitalDelayType01 := VitalZeroDelay01; tipd_AL18 : VitalDelayType01 := VitalZeroDelay01; tipd_AL19 : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR10 : VitalDelayType01 := VitalZeroDelay01; tipd_AR11 : VitalDelayType01 := VitalZeroDelay01; tipd_AR12 : VitalDelayType01 := VitalZeroDelay01; tipd_AR13 : VitalDelayType01 := VitalZeroDelay01; tipd_AR14 : VitalDelayType01 := VitalZeroDelay01; tipd_AR15 : VitalDelayType01 := VitalZeroDelay01; tipd_AR16 : VitalDelayType01 := VitalZeroDelay01; tipd_AR17 : VitalDelayType01 := VitalZeroDelay01; tipd_AR18 : VitalDelayType01 := VitalZeroDelay01; tipd_AR19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL35 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR35 : VitalDelayType01 := VitalZeroDelay01; --tpd values tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; tpd_OERNeg_IOR0 : VitalDelayType01Z := UnitDelay01Z; tpd_CLKL_INTLNeg : VitalDelayType01 := UnitDelay01; tpd_CLKR_INTLNeg : VitalDelayType01 := UnitDelay01; tpd_CLKR_INTRNeg : VitalDelayType01 := UnitDelay01; tpd_CLKL_INTRNeg : VitalDelayType01 := UnitDelay01; tpd_CLKL_IOL0_PIPELINE_EQ_1 : VitalDelayType01Z := UnitDelay01Z; tpd_CLKL_IOL0_NOPIPELINE_EQ_1 : VitalDelayType01Z := UnitDelay01Z; tpd_CLKR_IOR0_PIPELINE_EQ_1 : VitalDelayType01Z := UnitDelay01Z; tpd_CLKR_IOR0_NOPIPELINE_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tsetup values: setup times tsetup_AL0_CLKL : VitalDelayType := UnitDelay; tsetup_AR0_CLKR : VitalDelayType := UnitDelay; tsetup_CE0LNeg_CLKL : VitalDelayType := UnitDelay; tsetup_CE0RNeg_CLKR : VitalDelayType := UnitDelay; tsetup_CE1L_CLKL : VitalDelayType := UnitDelay; tsetup_CE1R_CLKR : VitalDelayType := UnitDelay; tsetup_BEL0Neg_CLKL : VitalDelayType := UnitDelay; tsetup_BER0Neg_CLKR : VitalDelayType := UnitDelay; tsetup_RWL_CLKL : VitalDelayType := UnitDelay; tsetup_RWR_CLKR : VitalDelayType := UnitDelay; tsetup_IOL0_CLKL : VitalDelayType := UnitDelay; tsetup_IOR0_CLKR : VitalDelayType := UnitDelay; tsetup_ADSLNeg_CLKL : VitalDelayType := UnitDelay; tsetup_ADSRNeg_CLKR : VitalDelayType := UnitDelay; tsetup_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; tsetup_CNTENRNeg_CLKR : VitalDelayType := UnitDelay; tsetup_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; tsetup_REPEATRNeg_CLKR : VitalDelayType := UnitDelay; -- thold values: hold times thold_AL0_CLKL : VitalDelayType := UnitDelay; thold_AR0_CLKR : VitalDelayType := UnitDelay; thold_CE0LNeg_CLKL : VitalDelayType := UnitDelay; thold_CE0RNeg_CLKR : VitalDelayType := UnitDelay; thold_CE1L_CLKL : VitalDelayType := UnitDelay; thold_CE1R_CLKR : VitalDelayType := UnitDelay; thold_BEL0Neg_CLKL : VitalDelayType := UnitDelay; thold_BER0Neg_CLKR : VitalDelayType := UnitDelay; thold_RWL_CLKL : VitalDelayType := UnitDelay; thold_RWR_CLKR : VitalDelayType := UnitDelay; thold_IOL0_CLKL : VitalDelayType := UnitDelay; thold_IOR0_CLKR : VitalDelayType := UnitDelay; thold_ADSLNeg_CLKL : VitalDelayType := UnitDelay; thold_ADSRNeg_CLKR : VitalDelayType := UnitDelay; thold_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; thold_CNTENRNeg_CLKR : VitalDelayType := UnitDelay; thold_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; thold_REPEATRNeg_CLKR : VitalDelayType := UnitDelay; -- pulse width tpw_CLKL_PIPELINE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_CLKL_NOPIPELINE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_CLKR_PIPELINE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_CLKR_NOPIPELINE_EQ_1_negedge : VitalDelayType := UnitDelay; tpw_CLKL_PIPELINE_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_CLKL_NOPIPELINE_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_CLKR_PIPELINE_EQ_1_posedge : VitalDelayType := UnitDelay; tpw_CLKR_NOPIPELINE_EQ_1_posedge : VitalDelayType := UnitDelay; -- tperiod values tperiod_CLKL_PIPELINE_EQ_1 : VitalDelayType := UnitDelay; tperiod_CLKL_NOPIPELINE_EQ_1 : VitalDelayType := UnitDelay; tperiod_CLKR_PIPELINE_EQ_1 : VitalDelayType := UnitDelay; tperiod_CLKR_NOPIPELINE_EQ_1 : VitalDelayType := UnitDelay; -- tdevice values: values for internal delays tdevice_SKEW : VitalDelayType := 6 ns; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- memory file to be loaded mem_file_name : STRING := "none"; --"idt70t3509m.mem"; UserPreload : BOOLEAN := FALSE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( --Chip Enables 0 CE0LNeg : IN std_ulogic := 'U'; CE0RNeg : IN std_ulogic := 'U'; --Chip Enables 1 CE1L : IN std_ulogic := 'U'; CE1R : IN std_ulogic := 'U'; --Read/Write Enable RWL : IN std_ulogic := 'U'; RWR : IN std_ulogic := 'U'; -- Output Enable OELNeg : IN std_ulogic := 'U'; OERNeg : IN std_ulogic := 'U'; -- Clk CLKL : IN std_logic := 'U'; CLKR : IN std_logic := 'U'; --Pipeline/Flow-Through PLFTL : IN std_logic := 'U'; PLFTR : IN std_logic := 'U'; --Adress Strobe Enable ADSLNeg : IN std_logic := 'U'; ADSRNeg : IN std_logic := 'U'; --Counter Enable CNTENLNeg : IN std_logic := 'U'; CNTENRNeg : IN std_logic := 'U'; -- Counter Repeat REPEATLNeg : IN std_logic := 'U'; REPEATRNeg : IN std_logic := 'U'; --Left Byte Enables BEL0Neg : IN std_logic := 'U'; BEL1Neg : IN std_logic := 'U'; BEL2Neg : IN std_logic := 'U'; BEL3Neg : IN std_logic := 'U'; --Right Byte Enables BER0Neg : IN std_logic := 'U'; BER1Neg : IN std_logic := 'U'; BER2Neg : IN std_logic := 'U'; BER3Neg : IN std_logic := 'U'; -- Sleep mode pin ZZL : IN std_ulogic := 'U'; ZZR : IN std_ulogic := 'U'; --Left Adress AL0 : IN std_logic := 'U'; AL1 : IN std_logic := 'U'; AL2 : IN std_logic := 'U'; AL3 : IN std_logic := 'U'; AL4 : IN std_logic := 'U'; AL5 : IN std_logic := 'U'; AL6 : IN std_logic := 'U'; AL7 : IN std_logic := 'U'; AL8 : IN std_logic := 'U'; AL9 : IN std_logic := 'U'; AL10 : IN std_logic := 'U'; AL11 : IN std_logic := 'U'; AL12 : IN std_logic := 'U'; AL13 : IN std_logic := 'U'; AL14 : IN std_logic := 'U'; AL15 : IN std_logic := 'U'; AL16 : IN std_logic := 'U'; AL17 : IN std_logic := 'U'; AL18 : IN std_logic := 'U'; AL19 : IN std_logic := 'U'; -- Right Adress AR0 : IN std_logic := 'U'; AR1 : IN std_logic := 'U'; AR2 : IN std_logic := 'U'; AR3 : IN std_logic := 'U'; AR4 : IN std_logic := 'U'; AR5 : IN std_logic := 'U'; AR6 : IN std_logic := 'U'; AR7 : IN std_logic := 'U'; AR8 : IN std_logic := 'U'; AR9 : IN std_logic := 'U'; AR10 : IN std_logic := 'U'; AR11 : IN std_logic := 'U'; AR12 : IN std_logic := 'U'; AR13 : IN std_logic := 'U'; AR14 : IN std_logic := 'U'; AR15 : IN std_logic := 'U'; AR16 : IN std_logic := 'U'; AR17 : IN std_logic := 'U'; AR18 : IN std_logic := 'U'; AR19 : IN std_logic := 'U'; -- Data Input/Output Bus of Left Port IOL0 : INOUT std_logic := 'U'; IOL1 : INOUT std_logic := 'U'; IOL2 : INOUT std_logic := 'U'; IOL3 : INOUT std_logic := 'U'; IOL4 : INOUT std_logic := 'U'; IOL5 : INOUT std_logic := 'U'; IOL6 : INOUT std_logic := 'U'; IOL7 : INOUT std_logic := 'U'; IOL8 : INOUT std_logic := 'U'; IOL9 : INOUT std_logic := 'U'; IOL10 : INOUT std_logic := 'U'; IOL11 : INOUT std_logic := 'U'; IOL12 : INOUT std_logic := 'U'; IOL13 : INOUT std_logic := 'U'; IOL14 : INOUT std_logic := 'U'; IOL15 : INOUT std_logic := 'U'; IOL16 : INOUT std_logic := 'U'; IOL17 : INOUT std_logic := 'U'; IOL18 : INOUT std_logic := 'U'; IOL19 : INOUT std_logic := 'U'; IOL20 : INOUT std_logic := 'U'; IOL21 : INOUT std_logic := 'U'; IOL22 : INOUT std_logic := 'U'; IOL23 : INOUT std_logic := 'U'; IOL24 : INOUT std_logic := 'U'; IOL25 : INOUT std_logic := 'U'; IOL26 : INOUT std_logic := 'U'; IOL27 : INOUT std_logic := 'U'; IOL28 : INOUT std_logic := 'U'; IOL29 : INOUT std_logic := 'U'; IOL30 : INOUT std_logic := 'U'; IOL31 : INOUT std_logic := 'U'; IOL32 : INOUT std_logic := 'U'; IOL33 : INOUT std_logic := 'U'; IOL34 : INOUT std_logic := 'U'; IOL35 : INOUT std_logic := 'U'; -- Data Input/Output Bus of Right Port IOR0 : INOUT std_logic := 'U'; IOR1 : INOUT std_logic := 'U'; IOR2 : INOUT std_logic := 'U'; IOR3 : INOUT std_logic := 'U'; IOR4 : INOUT std_logic := 'U'; IOR5 : INOUT std_logic := 'U'; IOR6 : INOUT std_logic := 'U'; IOR7 : INOUT std_logic := 'U'; IOR8 : INOUT std_logic := 'U'; IOR9 : INOUT std_logic := 'U'; IOR10 : INOUT std_logic := 'U'; IOR11 : INOUT std_logic := 'U'; IOR12 : INOUT std_logic := 'U'; IOR13 : INOUT std_logic := 'U'; IOR14 : INOUT std_logic := 'U'; IOR15 : INOUT std_logic := 'U'; IOR16 : INOUT std_logic := 'U'; IOR17 : INOUT std_logic := 'U'; IOR18 : INOUT std_logic := 'U'; IOR19 : INOUT std_logic := 'U'; IOR20 : INOUT std_logic := 'U'; IOR21 : INOUT std_logic := 'U'; IOR22 : INOUT std_logic := 'U'; IOR23 : INOUT std_logic := 'U'; IOR24 : INOUT std_logic := 'U'; IOR25 : INOUT std_logic := 'U'; IOR26 : INOUT std_logic := 'U'; IOR27 : INOUT std_logic := 'U'; IOR28 : INOUT std_logic := 'U'; IOR29 : INOUT std_logic := 'U'; IOR30 : INOUT std_logic := 'U'; IOR31 : INOUT std_logic := 'U'; IOR32 : INOUT std_logic := 'U'; IOR33 : INOUT std_logic := 'U'; IOR34 : INOUT std_logic := 'U'; IOR35 : INOUT std_logic := 'U'; -- Interrup Flag INTLNeg : OUT std_ulogic := 'U'; INTRNeg : OUT std_ulogic := 'U' ); ATTRIBUTE vital_level0 OF idt70T3509m : ENTITY IS True; END idt70t3509m; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt70T3509m IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT MaxData : NATURAL := 16#1FF#; CONSTANT MemSize : NATURAL := 1048575; CONSTANT HiAbit : NATURAL := 19; CONSTANT HiDbit : NATURAL := 35; CONSTANT FF_ADDR : NATURAL := 16#FFFFF#; CONSTANT FE_ADDR : NATURAL := 16#FFFFe#; CONSTANT partID : STRING := "idt70t3509m"; SIGNAL CE0LNeg_ipd : std_ulogic := 'U'; SIGNAL CE0RNeg_ipd : std_ulogic := 'U'; SIGNAL CE1L_ipd : std_ulogic := 'U'; SIGNAL CE1R_ipd : std_ulogic := 'U'; --Read/Write Enable SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL RWR_ipd : std_ulogic := 'U'; -- Output Enable SIGNAL OELNeg_ipd : std_ulogic := 'U'; SIGNAL OERNeg_ipd : std_ulogic := 'U'; -- Clk SIGNAL CLKL_ipd : std_logic := 'U'; SIGNAL CLKR_ipd : std_logic := 'U'; --Pipeline/Flow-Through SIGNAL PLFTL_ipd : std_logic := 'U'; SIGNAL PLFTR_ipd : std_logic := 'U'; --Adress Strobe Enable SIGNAL ADSLNeg_ipd : std_logic := 'U'; SIGNAL ADSRNeg_ipd : std_logic := 'U'; --Counter Enable SIGNAL CNTENLNeg_ipd : std_logic := 'U'; SIGNAL CNTENRNeg_ipd : std_logic := 'U'; --Counter REPEAT SIGNAL REPEATLNeg_ipd : std_logic := 'U'; SIGNAL REPEATRNeg_ipd : std_logic := 'U'; --Left Byte Enables SIGNAL BEL0Neg_ipd : std_logic := 'U'; SIGNAL BEL1Neg_ipd : std_logic := 'U'; SIGNAL BEL2Neg_ipd : std_logic := 'U'; SIGNAL BEL3Neg_ipd : std_logic := 'U'; --Right Byte Enables SIGNAL BER0Neg_ipd : std_logic := 'U'; SIGNAL BER1Neg_ipd : std_logic := 'U'; SIGNAL BER2Neg_ipd : std_logic := 'U'; SIGNAL BER3Neg_ipd : std_logic := 'U'; -- Sleep bit SIGNAL ZZL_ipd : std_logic := 'U'; SIGNAL ZZR_ipd : std_logic := 'U'; --Left Adress SIGNAL AL0_ipd : std_logic := 'U'; SIGNAL AL1_ipd : std_logic := 'U'; SIGNAL AL2_ipd : std_logic := 'U'; SIGNAL AL3_ipd : std_logic := 'U'; SIGNAL AL4_ipd : std_logic := 'U'; SIGNAL AL5_ipd : std_logic := 'U'; SIGNAL AL6_ipd : std_logic := 'U'; SIGNAL AL7_ipd : std_logic := 'U'; SIGNAL AL8_ipd : std_logic := 'U'; SIGNAL AL9_ipd : std_logic := 'U'; SIGNAL AL10_ipd : std_logic := 'U'; SIGNAL AL11_ipd : std_logic := 'U'; SIGNAL AL12_ipd : std_logic := 'U'; SIGNAL AL13_ipd : std_logic := 'U'; SIGNAL AL14_ipd : std_logic := 'U'; SIGNAL AL15_ipd : std_logic := 'U'; SIGNAL AL16_ipd : std_logic := 'U'; SIGNAL AL17_ipd : std_logic := 'U'; SIGNAL AL18_ipd : std_logic := 'U'; SIGNAL AL19_ipd : std_logic := 'U'; -- Right Adress SIGNAL AR0_ipd : std_logic := 'U'; SIGNAL AR1_ipd : std_logic := 'U'; SIGNAL AR2_ipd : std_logic := 'U'; SIGNAL AR3_ipd : std_logic := 'U'; SIGNAL AR4_ipd : std_logic := 'U'; SIGNAL AR5_ipd : std_logic := 'U'; SIGNAL AR6_ipd : std_logic := 'U'; SIGNAL AR7_ipd : std_logic := 'U'; SIGNAL AR8_ipd : std_logic := 'U'; SIGNAL AR9_ipd : std_logic := 'U'; SIGNAL AR10_ipd : std_logic := 'U'; SIGNAL AR11_ipd : std_logic := 'U'; SIGNAL AR12_ipd : std_logic := 'U'; SIGNAL AR13_ipd : std_logic := 'U'; SIGNAL AR14_ipd : std_logic := 'U'; SIGNAL AR15_ipd : std_logic := 'U'; SIGNAL AR16_ipd : std_logic := 'U'; SIGNAL AR17_ipd : std_logic := 'U'; SIGNAL AR18_ipd : std_logic := 'U'; SIGNAL AR19_ipd : std_logic := 'U'; -- Data Input/Output Bus of Left Port SIGNAL IOL0_ipd : std_logic := 'U'; SIGNAL IOL1_ipd : std_logic := 'U'; SIGNAL IOL2_ipd : std_logic := 'U'; SIGNAL IOL3_ipd : std_logic := 'U'; SIGNAL IOL4_ipd : std_logic := 'U'; SIGNAL IOL5_ipd : std_logic := 'U'; SIGNAL IOL6_ipd : std_logic := 'U'; SIGNAL IOL7_ipd : std_logic := 'U'; SIGNAL IOL8_ipd : std_logic := 'U'; SIGNAL IOL9_ipd : std_logic := 'U'; SIGNAL IOL10_ipd : std_logic := 'U'; SIGNAL IOL11_ipd : std_logic := 'U'; SIGNAL IOL12_ipd : std_logic := 'U'; SIGNAL IOL13_ipd : std_logic := 'U'; SIGNAL IOL14_ipd : std_logic := 'U'; SIGNAL IOL15_ipd : std_logic := 'U'; SIGNAL IOL16_ipd : std_logic := 'U'; SIGNAL IOL17_ipd : std_logic := 'U'; SIGNAL IOL18_ipd : std_logic := 'U'; SIGNAL IOL19_ipd : std_logic := 'U'; SIGNAL IOL20_ipd : std_logic := 'U'; SIGNAL IOL21_ipd : std_logic := 'U'; SIGNAL IOL22_ipd : std_logic := 'U'; SIGNAL IOL23_ipd : std_logic := 'U'; SIGNAL IOL24_ipd : std_logic := 'U'; SIGNAL IOL25_ipd : std_logic := 'U'; SIGNAL IOL26_ipd : std_logic := 'U'; SIGNAL IOL27_ipd : std_logic := 'U'; SIGNAL IOL28_ipd : std_logic := 'U'; SIGNAL IOL29_ipd : std_logic := 'U'; SIGNAL IOL30_ipd : std_logic := 'U'; SIGNAL IOL31_ipd : std_logic := 'U'; SIGNAL IOL32_ipd : std_logic := 'U'; SIGNAL IOL33_ipd : std_logic := 'U'; SIGNAL IOL34_ipd : std_logic := 'U'; SIGNAL IOL35_ipd : std_logic := 'U'; -- Data Input/Output Bus of Right Port SIGNAL IOR0_ipd : std_logic := 'U'; SIGNAL IOR1_ipd : std_logic := 'U'; SIGNAL IOR2_ipd : std_logic := 'U'; SIGNAL IOR3_ipd : std_logic := 'U'; SIGNAL IOR4_ipd : std_logic := 'U'; SIGNAL IOR5_ipd : std_logic := 'U'; SIGNAL IOR6_ipd : std_logic := 'U'; SIGNAL IOR7_ipd : std_logic := 'U'; SIGNAL IOR8_ipd : std_logic := 'U'; SIGNAL IOR9_ipd : std_logic := 'U'; SIGNAL IOR10_ipd : std_logic := 'U'; SIGNAL IOR11_ipd : std_logic := 'U'; SIGNAL IOR12_ipd : std_logic := 'U'; SIGNAL IOR13_ipd : std_logic := 'U'; SIGNAL IOR14_ipd : std_logic := 'U'; SIGNAL IOR15_ipd : std_logic := 'U'; SIGNAL IOR16_ipd : std_logic := 'U'; SIGNAL IOR17_ipd : std_logic := 'U'; SIGNAL IOR18_ipd : std_logic := 'U'; SIGNAL IOR19_ipd : std_logic := 'U'; SIGNAL IOR20_ipd : std_logic := 'U'; SIGNAL IOR21_ipd : std_logic := 'U'; SIGNAL IOR22_ipd : std_logic := 'U'; SIGNAL IOR23_ipd : std_logic := 'U'; SIGNAL IOR24_ipd : std_logic := 'U'; SIGNAL IOR25_ipd : std_logic := 'U'; SIGNAL IOR26_ipd : std_logic := 'U'; SIGNAL IOR27_ipd : std_logic := 'U'; SIGNAL IOR28_ipd : std_logic := 'U'; SIGNAL IOR29_ipd : std_logic := 'U'; SIGNAL IOR30_ipd : std_logic := 'U'; SIGNAL IOR31_ipd : std_logic := 'U'; SIGNAL IOR32_ipd : std_logic := 'U'; SIGNAL IOR33_ipd : std_logic := 'U'; SIGNAL IOR34_ipd : std_logic := 'U'; SIGNAL IOR35_ipd : std_logic := 'U'; SIGNAL CLKL_in : std_ulogic := '0'; SIGNAL CLKL_out : std_ulogic := '0'; SIGNAL CLKR_in : std_ulogic := '0'; SIGNAL CLKR_out : std_ulogic := '0'; BEGIN -------------------------------------------------------------------------- -- Internal Delays -------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays SKEW : VitalBuf(CLKL_out, CLKL_in, (VitalZeroDelay, tdevice_SKEW)); SKEW1 : VitalBuf(CLKR_out, CLKR_in, (VitalZeroDelay, tdevice_SKEW)); -------------------------------------------------------------------------- -- Wire Delays -------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay ( CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg ); w_2 : VitalWireDelay ( CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg ); w_3 : VitalWireDelay ( RWL_ipd, RWL, tipd_RWL ); w_4 : VitalWireDelay ( RWR_ipd, RWR, tipd_RWR ); w_5 : VitalWireDelay ( OELNeg_ipd, OELNeg, tipd_OELNeg ); w_6 : VitalWireDelay ( OERNeg_ipd, OERNeg, tipd_OERNeg ); w_7 : VitalWireDelay ( CLKL_ipd, CLKL, tipd_CLKL ); w_8 : VitalWireDelay ( CLKR_ipd, CLKR, tipd_CLKR ); w_9 : VitalWireDelay ( PLFTL_ipd, PLFTL, tipd_PLFTL ); w_10 : VitalWireDelay ( PLFTR_ipd, PLFTR, tipd_PLFTR ); w_11 : VitalWireDelay ( ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg ); w_12 : VitalWireDelay ( ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg ); w_13 : VitalWireDelay ( BEL0Neg_ipd, BEL0Neg, tipd_BEL0Neg ); w_14 : VitalWireDelay ( BEL1Neg_ipd, BEL1Neg, tipd_BEL1Neg ); w_15 : VitalWireDelay ( BEL2Neg_ipd, BEL2Neg, tipd_BEL2Neg ); w_16 : VitalWireDelay ( BEL3Neg_ipd, BEL3Neg, tipd_BEL3Neg ); w_17 : VitalWireDelay ( BER0Neg_ipd, BER0Neg, tipd_BER0Neg ); w_18 : VitalWireDelay ( BER1Neg_ipd, BER1Neg, tipd_BER1Neg ); w_19 : VitalWireDelay ( BER2Neg_ipd, BER2Neg, tipd_BER2Neg ); w_20 : VitalWireDelay ( BER3Neg_ipd, BER3Neg, tipd_BER3Neg ); w_21 : VitalWireDelay ( AL0_ipd, AL0, tipd_AL0 ); w_22 : VitalWireDelay ( AL1_ipd, AL1, tipd_AL1 ); w_23 : VitalWireDelay ( AL2_ipd, AL2, tipd_AL3 ); w_24 : VitalWireDelay ( AL3_ipd, AL3, tipd_AL3 ); w_25 : VitalWireDelay ( AL4_ipd, AL4, tipd_AL4 ); w_26 : VitalWireDelay ( AL5_ipd, AL5, tipd_AL5 ); w_27 : VitalWireDelay ( AL6_ipd, AL6, tipd_AL6 ); w_28 : VitalWireDelay ( AL7_ipd, AL7, tipd_AL7 ); w_29 : VitalWireDelay ( AL8_ipd, AL8, tipd_AL8 ); w_30 : VitalWireDelay ( AL9_ipd, AL9, tipd_AL9 ); w_31 : VitalWireDelay ( AL10_ipd, AL10, tipd_AL10 ); w_32 : VitalWireDelay ( AL11_ipd, AL11, tipd_AL11 ); w_33 : VitalWireDelay ( AL12_ipd, AL12, tipd_AL12 ); w_34 : VitalWireDelay ( AL13_ipd, AL13, tipd_AL13 ); w_35 : VitalWireDelay ( AL14_ipd, AL14, tipd_AL14 ); w_36 : VitalWireDelay ( AL15_ipd, AL15, tipd_AL15 ); w_37 : VitalWireDelay ( AL16_ipd, AL16, tipd_AL16 ); w_38 : VitalWireDelay ( AL17_ipd, AL17, tipd_AL17 ); w_39 : VitalWireDelay ( AL18_ipd, AL18, tipd_AL18 ); w_40 : VitalWireDelay ( AL19_ipd, AL19, tipd_AL19 ); w_41 : VitalWireDelay ( AR0_ipd, AR0, tipd_AR0 ); w_42 : VitalWireDelay ( AR1_ipd, AR1, tipd_AR1 ); w_43 : VitalWireDelay ( AR2_ipd, AR2, tipd_AR2 ); w_44 : VitalWireDelay ( AR3_ipd, AR3, tipd_AR3 ); w_45 : VitalWireDelay ( AR4_ipd, AR4, tipd_AR4 ); w_46 : VitalWireDelay ( AR5_ipd, AR5, tipd_AR5 ); w_47 : VitalWireDelay ( AR6_ipd, AR6, tipd_AR6 ); w_48 : VitalWireDelay ( AR7_ipd, AR7, tipd_AR7 ); w_49 : VitalWireDelay ( AR8_ipd, AR8, tipd_AR8 ); w_50 : VitalWireDelay ( AR9_ipd, AR9, tipd_AR9 ); w_51 : VitalWireDelay ( AR10_ipd, AR10, tipd_AR10 ); w_52 : VitalWireDelay ( AR11_ipd, AR11, tipd_AR11 ); w_53 : VitalWireDelay ( AR12_ipd, AR12, tipd_AR12 ); w_54 : VitalWireDelay ( AR13_ipd, AR13, tipd_AR13 ); w_55 : VitalWireDelay ( AR14_ipd, AR14, tipd_AR14 ); w_56 : VitalWireDelay ( AR15_ipd, AR15, tipd_AR15 ); w_57 : VitalWireDelay ( AR16_ipd, AR16, tipd_AR16 ); w_58 : VitalWireDelay ( AR17_ipd, AR17, tipd_AR17 ); w_59 : VitalWireDelay ( AR18_ipd, AR18, tipd_AR18 ); w_60 : VitalWireDelay ( AR19_ipd, AR19, tipd_AR19 ); w_61 : VitalWireDelay ( IOL0_ipd, IOL0, tipd_IOL0 ); w_62 : VitalWireDelay ( IOL1_ipd, IOL1, tipd_IOL1 ); w_63 : VitalWireDelay ( IOL2_ipd, IOL2, tipd_IOL2 ); w_64 : VitalWireDelay ( IOL3_ipd, IOL3, tipd_IOL3 ); w_65 : VitalWireDelay ( IOL4_ipd, IOL4, tipd_IOL4 ); w_66 : VitalWireDelay ( IOL5_ipd, IOL5, tipd_IOL5 ); w_67 : VitalWireDelay ( IOL6_ipd, IOL6, tipd_IOL6 ); w_68 : VitalWireDelay ( IOL7_ipd, IOL7, tipd_IOL7 ); w_69 : VitalWireDelay ( IOL8_ipd, IOL8, tipd_IOL8 ); w_70 : VitalWireDelay ( IOL9_ipd, IOL9, tipd_IOL9 ); w_71 : VitalWireDelay ( IOL10_ipd, IOL10, tipd_IOL10); w_72 : VitalWireDelay ( IOL11_ipd, IOL11, tipd_IOL11); w_73 : VitalWireDelay ( IOL12_ipd, IOL12, tipd_IOL12); w_74 : VitalWireDelay ( IOL13_ipd, IOL13, tipd_IOL13); w_75 : VitalWireDelay ( IOL14_ipd, IOL14, tipd_IOL14); w_76 : VitalWireDelay ( IOL15_ipd, IOL15, tipd_IOL15); w_77 : VitalWireDelay ( IOL16_ipd, IOL16, tipd_IOL16); w_78 : VitalWireDelay ( IOL17_ipd, IOL17, tipd_IOL17); w_79 : VitalWireDelay ( IOL18_ipd, IOL18, tipd_IOL18); w_80 : VitalWireDelay ( IOL19_ipd, IOL19, tipd_IOL19); w_81 : VitalWireDelay ( IOL20_ipd, IOL20, tipd_IOL20); w_82 : VitalWireDelay ( IOL21_ipd, IOL21, tipd_IOL21); w_83 : VitalWireDelay ( IOL22_ipd, IOL22, tipd_IOL22); w_84 : VitalWireDelay ( IOL23_ipd, IOL23, tipd_IOL23); w_85 : VitalWireDelay ( IOL24_ipd, IOL24, tipd_IOL24); w_86 : VitalWireDelay ( IOL25_ipd, IOL25, tipd_IOL25); w_87 : VitalWireDelay ( IOL26_ipd, IOL26, tipd_IOL26); w_88 : VitalWireDelay ( IOL27_ipd, IOL27, tipd_IOL27); w_89 : VitalWireDelay ( IOL28_ipd, IOL28, tipd_IOL28); w_90 : VitalWireDelay ( IOL29_ipd, IOL29, tipd_IOL29); w_91 : VitalWireDelay ( IOL30_ipd, IOL30, tipd_IOL30); w_92 : VitalWireDelay ( IOL31_ipd, IOL31, tipd_IOL31); w_93 : VitalWireDelay ( IOL32_ipd, IOL32, tipd_IOL32); w_94 : VitalWireDelay ( IOL33_ipd, IOL33, tipd_IOL33); w_95 : VitalWireDelay ( IOL34_ipd, IOL34, tipd_IOL34); w_96 : VitalWireDelay ( IOL35_ipd, IOL35, tipd_IOL35); w_97 : VitalWireDelay ( IOR0_ipd, IOR0, tipd_IOR0 ); w_98 : VitalWireDelay ( IOR1_ipd, IOR1, tipd_IOR1 ); w_99 : VitalWireDelay ( IOR2_ipd, IOR2, tipd_IOR2 ); w_100 : VitalWireDelay ( IOR3_ipd, IOR3, tipd_IOR3 ); w_101 : VitalWireDelay ( IOR4_ipd, IOR4, tipd_IOR4 ); w_102 : VitalWireDelay ( IOR5_ipd, IOR5, tipd_IOR5 ); w_103 : VitalWireDelay ( IOR6_ipd, IOR6, tipd_IOR6 ); w_104 : VitalWireDelay ( IOR7_ipd, IOR7, tipd_IOR7 ); w_105 : VitalWireDelay ( IOR8_ipd, IOR8, tipd_IOR8 ); w_106 : VitalWireDelay ( IOR9_ipd, IOR9, tipd_IOR9 ); w_107 : VitalWireDelay ( IOR10_ipd, IOR10, tipd_IOR10); w_108 : VitalWireDelay ( IOR11_ipd, IOR11, tipd_IOR11); w_109 : VitalWireDelay ( IOR12_ipd, IOR12, tipd_IOR12); w_110 : VitalWireDelay ( IOR13_ipd, IOR13, tipd_IOR13); w_111 : VitalWireDelay ( IOR14_ipd, IOR14, tipd_IOR14); w_112 : VitalWireDelay ( IOR15_ipd, IOR15, tipd_IOR15); w_113 : VitalWireDelay ( IOR16_ipd, IOR16, tipd_IOR16); w_114 : VitalWireDelay ( IOR17_ipd, IOR17, tipd_IOR17); w_115 : VitalWireDelay ( IOR18_ipd, IOR18, tipd_IOR18); w_116 : VitalWireDelay ( IOR19_ipd, IOR19, tipd_IOR19); w_117 : VitalWireDelay ( IOR20_ipd, IOR20, tipd_IOR20); w_118 : VitalWireDelay ( IOR21_ipd, IOR21, tipd_IOR21); w_119 : VitalWireDelay ( IOR22_ipd, IOR22, tipd_IOR22); w_120 : VitalWireDelay ( IOR23_ipd, IOR23, tipd_IOR23); w_121 : VitalWireDelay ( IOR24_ipd, IOR24, tipd_IOR24); w_122 : VitalWireDelay ( IOR25_ipd, IOR25, tipd_IOR25); w_123 : VitalWireDelay ( IOR26_ipd, IOR26, tipd_IOR26); w_124 : VitalWireDelay ( IOR27_ipd, IOR27, tipd_IOR27); w_125 : VitalWireDelay ( IOR28_ipd, IOR28, tipd_IOR28); w_126 : VitalWireDelay ( IOR29_ipd, IOR29, tipd_IOR29); w_127 : VitalWireDelay ( IOR30_ipd, IOR30, tipd_IOR30); w_128 : VitalWireDelay ( IOR31_ipd, IOR31, tipd_IOR31); w_129 : VitalWireDelay ( IOR32_ipd, IOR32, tipd_IOR32); w_130 : VitalWireDelay ( IOR33_ipd, IOR33, tipd_IOR33); w_131 : VitalWireDelay ( IOR34_ipd, IOR34, tipd_IOR34); w_132 : VitalWireDelay ( IOR35_ipd, IOR35, tipd_IOR35); w_133 : VitalWireDelay ( CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg ); w_134 : VitalWireDelay ( CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg ); w_135 : VitalWireDelay ( CE1L_ipd, CE1L, tipd_CE1L ); w_136 : VitalWireDelay ( CE1R_ipd, CE1R, tipd_CE1R ); w_137 : VitalWireDelay ( REPEATLNeg_ipd, REPEATLNeg, tipd_REPEATLNeg ); w_138 : VitalWireDelay ( REPEATRNeg_ipd, REPEATRNeg, tipd_REPEATRNeg ); w_139 : VitalWireDelay ( ZZL_ipd, ZZL, tipd_ZZL); w_140 : VitalWireDelay ( ZZR_ipd, ZZR, tipd_ZZR); END BLOCK WireDelay; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior : BLOCK PORT ( ALIn : IN std_logic_vector(HiAbit downto 0); ARIn : IN std_logic_vector(HiAbit downto 0); IOLIn : IN std_logic_vector(HiDbit downto 0); IORIn : IN std_logic_vector(HiDbit downto 0); IOLOut : OUT std_logic_vector(HiDbit downto 0); IOROut : OUT std_logic_vector(HiDbit downto 0); CE0LNeg : IN std_ulogic; CE0RNeg : IN std_ulogic; CE1L : IN std_ulogic; CE1R : IN std_ulogic; RWL : IN std_ulogic; RWR : IN std_ulogic; OELNeg : IN std_ulogic; OERNeg : IN std_ulogic; CLKL : IN std_logic; CLKR : IN std_logic; PLFTL : IN std_logic; PLFTR : IN std_logic; ADSLNeg : IN std_logic; ADSRNeg : IN std_logic; CNTENLNeg : IN std_logic; CNTENRNeg : IN std_logic; REPEATLNeg : IN std_logic; REPEATRNeg : IN std_logic; BELInNeg : IN std_logic_vector( 3 downto 0 ); BERInNeg : IN std_logic_vector( 3 downto 0 ); ZZL : IN std_logic; ZZR : IN std_logic; INTLNeg : OUT std_logic; INTRNeg : OUT std_logic ); PORT MAP ( ALIn(0) => AL0_ipd, ALIn(1) => AL1_ipd, ALIn(2) => AL2_ipd, ALIn(3) => AL3_ipd, ALIn(4) => AL4_ipd, ALIn(5) => AL5_ipd, ALIn(6) => AL6_ipd, ALIn(7) => AL7_ipd, ALIn(8) => AL8_ipd, ALIn(9) => AL9_ipd, ALIn(10) => AL10_ipd, ALIn(11) => AL11_ipd, ALIn(12) => AL12_ipd, ALIn(13) => AL13_ipd, ALIn(14) => AL14_ipd, ALIn(15) => AL15_ipd, ALIn(16) => AL16_ipd, ALIn(17) => AL17_ipd, ALIn(18) => AL18_ipd, ALIn(19) => AL19_ipd, ARIn(0) => AR0_ipd, ARIn(1) => AR1_ipd, ARIn(2) => AR2_ipd, ARIn(3) => AR3_ipd, ARIn(4) => AR4_ipd, ARIn(5) => AR5_ipd, ARIn(6) => AR6_ipd, ARIn(7) => AR7_ipd, ARIn(8) => AR8_ipd, ARIn(9) => AR9_ipd, ARIn(10) => AR10_ipd, ARIn(11) => AR11_ipd, ARIn(12) => AR12_ipd, ARIn(13) => AR13_ipd, ARIn(14) => AR14_ipd, ARIn(15) => AR15_ipd, ARIn(16) => AR16_ipd, ARIn(17) => AR17_ipd, ARIn(18) => AR18_ipd, ARIn(19) => AR19_ipd, IOLIn(0) => IOL0_ipd, IOLIn(1) => IOL1_ipd, IOLIn(2) => IOL2_ipd, IOLIn(3) => IOL3_ipd, IOLIn(4) => IOL4_ipd, IOLIn(5) => IOL5_ipd, IOLIn(6) => IOL6_ipd, IOLIn(7) => IOL7_ipd, IOLIn(8) => IOL8_ipd, IOLIn(9) => IOL9_ipd, IOLIn(10) => IOL10_ipd, IOLIn(11) => IOL11_ipd, IOLIn(12) => IOL12_ipd, IOLIn(13) => IOL13_ipd, IOLIn(14) => IOL14_ipd, IOLIn(15) => IOL15_ipd, IOLIn(16) => IOL16_ipd, IOLIn(17) => IOL17_ipd, IOLIn(18) => IOL18_ipd, IOLIn(19) => IOL19_ipd, IOLIn(20) => IOL20_ipd, IOLIn(21) => IOL21_ipd, IOLIn(22) => IOL22_ipd, IOLIn(23) => IOL23_ipd, IOLIn(24) => IOL24_ipd, IOLIn(25) => IOL25_ipd, IOLIn(26) => IOL26_ipd, IOLIn(27) => IOL27_ipd, IOLIn(28) => IOL28_ipd, IOLIn(29) => IOL29_ipd, IOLIn(30) => IOL30_ipd, IOLIn(31) => IOL31_ipd, IOLIn(32) => IOL32_ipd, IOLIn(33) => IOL33_ipd, IOLIn(34) => IOL34_ipd, IOLIn(35) => IOL35_ipd, IORIn(0) => IOR0_ipd, IORIn(1) => IOR1_ipd, IORIn(2) => IOR2_ipd, IORIn(3) => IOR3_ipd, IORIn(4) => IOR4_ipd, IORIn(5) => IOR5_ipd, IORIn(6) => IOR6_ipd, IORIn(7) => IOR7_ipd, IORIn(8) => IOR8_ipd, IORIn(9) => IOR9_ipd, IORIn(10) => IOR10_ipd, IORIn(11) => IOR11_ipd, IORIn(12) => IOR12_ipd, IORIn(13) => IOR13_ipd, IORIn(14) => IOR14_ipd, IORIn(15) => IOR15_ipd, IORIn(16) => IOR16_ipd, IORIn(17) => IOR17_ipd, IORIn(18) => IOR18_ipd, IORIn(19) => IOR19_ipd, IORIn(20) => IOR20_ipd, IORIn(21) => IOR21_ipd, IORIn(22) => IOR22_ipd, IORIn(23) => IOR23_ipd, IORIn(24) => IOR24_ipd, IORIn(25) => IOR25_ipd, IORIn(26) => IOR26_ipd, IORIn(27) => IOR27_ipd, IORIn(28) => IOR28_ipd, IORIn(29) => IOR29_ipd, IORIn(30) => IOR30_ipd, IORIn(31) => IOR31_ipd, IORIn(32) => IOR32_ipd, IORIn(33) => IOR33_ipd, IORIn(34) => IOR34_ipd, IORIn(35) => IOR35_ipd, IOLOut(0) => IOL0, IOLOut(1) => IOL1, IOLOut(2) => IOL2, IOLOut(3) => IOL3, IOLOut(4) => IOL4, IOLOut(5) => IOL5, IOLOut(6) => IOL6, IOLOut(7) => IOL7, IOLOut(8) => IOL8, IOLOut(9) => IOL9, IOLOut(10) => IOL10, IOLOut(11) => IOL11, IOLOut(12) => IOL12, IOLOut(13) => IOL13, IOLOut(14) => IOL14, IOLOut(15) => IOL15, IOLOut(16) => IOL16, IOLOut(17) => IOL17, IOLOut(18) => IOL18, IOLOut(19) => IOL19, IOLOut(20) => IOL20, IOLOut(21) => IOL21, IOLOut(22) => IOL22, IOLOut(23) => IOL23, IOLOut(24) => IOL24, IOLOut(25) => IOL25, IOLOut(26) => IOL26, IOLOut(27) => IOL27, IOLOut(28) => IOL28, IOLOut(29) => IOL29, IOLOut(30) => IOL30, IOLOut(31) => IOL31, IOLOut(32) => IOL32, IOLOut(33) => IOL33, IOLOut(34) => IOL34, IOLOut(35) => IOL35, IOROut(0) => IOR0, IOROut(1) => IOR1, IOROut(2) => IOR2, IOROut(3) => IOR3, IOROut(4) => IOR4, IOROut(5) => IOR5, IOROut(6) => IOR6, IOROut(7) => IOR7, IOROut(8) => IOR8, IOROut(9) => IOR9, IOROut(10) => IOR10, IOROut(11) => IOR11, IOROut(12) => IOR12, IOROut(13) => IOR13, IOROut(14) => IOR14, IOROut(15) => IOR15, IOROut(16) => IOR16, IOROut(17) => IOR17, IOROut(18) => IOR18, IOROut(19) => IOR19, IOROut(20) => IOR20, IOROut(21) => IOR21, IOROut(22) => IOR22, IOROut(23) => IOR23, IOROut(24) => IOR24, IOROut(25) => IOR25, IOROut(26) => IOR26, IOROut(27) => IOR27, IOROut(28) => IOR28, IOROut(29) => IOR29, IOROut(30) => IOR30, IOROut(31) => IOR31, IOROut(32) => IOR32, IOROut(33) => IOR33, IOROut(34) => IOR34, IOROut(35) => IOR35, CE0LNeg => CE0LNeg_ipd, CE0RNeg => CE0RNeg_ipd, CE1L => CE1L_ipd, CE1R => CE1R_ipd, RWL => RWL_ipd, RWR => RWR_ipd, OELNeg => OELNeg_ipd, OERNeg => OERNeg_ipd, CLKL => CLKL_ipd, CLKR => CLKR_ipd, PLFTL => PLFTL_ipd, PLFTR => PLFTR_ipd, ADSLNeg => ADSLNeg_ipd, ADSRNeg => ADSRNeg_ipd, CNTENLNeg => CNTENLNeg_ipd, CNTENRNeg => CNTENRNeg_ipd, REPEATLNeg => REPEATLNeg_ipd, REPEATRNeg => REPEATRNeg_ipd, BELInNeg(0) => BEL0Neg_ipd, BELInNeg(1) => BEL1Neg_ipd, BELInNeg(2) => BEL2Neg_ipd, BELInNeg(3) => BEL3Neg_ipd, BERInNeg(0) => BER0Neg_ipd, BERInNeg(1) => BER1Neg_ipd, BERInNeg(2) => BER2Neg_ipd, BERInNeg(3) => BER3Neg_ipd, INTLNeg => INTLNeg, INTRNeg => INTRNeg, ZZL => ZZL_ipd, ZZR => ZZR_ipd ); SIGNAL RWLReg : std_logic; -- Registrated R/W signal... SIGNAL RWRReg : std_logic; -- Registrated R/W signal... SIGNAL CELReg : std_logic; -- Registrated CE signal... SIGNAL CERReg : std_logic; -- Registrated CE signal... SIGNAL BEL0NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BER0NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BEL1NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BER1NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BEL2NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BER2NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BEL3NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BER3NegPipe : std_logic; -- Pipeline BE0Neg... SIGNAL BEL0Mux : std_logic; -- BENeg from multiplexer... SIGNAL BER0Mux : std_logic; -- BENeg from multiplexer... SIGNAL BEL1Mux : std_logic; -- BENeg from multiplexer... SIGNAL BER1Mux : std_logic; -- BENeg from multiplexer... SIGNAL BEL2Mux : std_logic; -- BENeg from multiplexer... SIGNAL BER2Mux : std_logic; -- BENeg from multiplexer... SIGNAL BEL3Mux : std_logic; -- BENeg from multiplexer... SIGNAL BER3Mux : std_logic; -- BENeg from multiplexer... SIGNAL CELMuxIn : std_logic; -- Input to mux for CE SIGNAL CERMuxIn : std_logic; -- Input to mux for CE SIGNAL CELMux : std_logic; -- CE from mux... SIGNAL CERMux : std_logic; -- CE from mux... SIGNAL MemBEL0 : std_logic; -- BE for Memory array SIGNAL MemBER0 : std_logic; -- BE for Memory array SIGNAL MemBEL1 : std_logic; -- BE for Memory array SIGNAL MemBER1 : std_logic; -- BE for Memory array SIGNAL MemBEL2 : std_logic; -- BE for Memory array SIGNAL MemBER2 : std_logic; -- BE for Memory array SIGNAL MemBEL3 : std_logic; -- BE for Memory array SIGNAL MemBER3 : std_logic; -- BE for Memory array SIGNAL DoutL0Sel : std_logic; -- Output selection signal SIGNAL DoutR0Sel : std_logic; -- Output selection signal SIGNAL DoutL1Sel : std_logic; -- Output selection signal SIGNAL DoutR1Sel : std_logic; -- Output selection signal SIGNAL DoutL2Sel : std_logic; -- Output selection signal SIGNAL DoutR2Sel : std_logic; -- Output selection signal SIGNAL DoutL3Sel : std_logic; -- Output selection signal SIGNAL DoutR3Sel : std_logic; -- Output selection signal SIGNAL MemAddrInL : natural RANGE 0 TO MemSize; SIGNAL MemAddrInR : natural RANGE 0 TO MemSize; -- Sleep internal signals... SIGNAL ZZR_int : STD_LOGIC := '0'; SIGNAL ZZL_int : STD_LOGIC := '0'; -- Registrated BELInNeg signal SIGNAL BELNegReg : std_logic_vector(3 DOWNTO 0); -- Pipeline BELNegReg SIGNAL BELNegPipe : std_logic_vector(3 DOWNTO 0); -- Registrated BERInNeg signal SIGNAL BERNegReg : std_logic_vector(3 DOWNTO 0); -- Pipeline BERNegReg SIGNAL BERNegPipe : std_logic_vector(3 DOWNTO 0); -- Registrated Memory otput signals SIGNAL MemOutLReg : std_logic_vector(HiDbit DOWNTO 0); SIGNAL MemOutRReg : std_logic_vector(HiDbit DOWNTO 0); -- Memory output SIGNAL MemOutL : std_logic_vector(HiDbit DOWNTO 0); SIGNAL MemOutR : std_logic_vector(HiDbit DOWNTO 0); -- Outputs from buffers SIGNAL DOL_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL DOR_zd : std_logic_vector(HiDbit DOWNTO 0); -- Input signal registrated SIGNAL MemInRegL : std_logic_vector(HiDbit DOWNTO 0); SIGNAL MemInRegR : std_logic_vector(HiDbit DOWNTO 0); -- Signals needed for Interrupt signal delay SIGNAL INTLNeg_zd : STD_LOGIC := '1'; SIGNAL INTRNeg_zd : STD_LOGIC := '1'; SUBTYPE std_logic_vector9 IS std_logic_vector(8 DOWNTO 0); ALIAS outLZD0 : std_logic_vector9 IS DOL_zd(8 DOWNTO 0); ALIAS outRZD0 : std_logic_vector9 IS DOR_zd(8 DOWNTO 0); ALIAS outLZD1 : std_logic_vector9 IS DOL_zd(17 DOWNTO 9); ALIAS outRZD1 : std_logic_vector9 IS DOR_zd(17 DOWNTO 9); ALIAS outLZD2 : std_logic_vector9 IS DOL_zd(26 DOWNTO 18); ALIAS outRZD2 : std_logic_vector9 IS DOR_zd(26 DOWNTO 18); ALIAS outLZD3 : std_logic_vector9 IS DOL_zd(35 DOWNTO 27); ALIAS outRZD3 : std_logic_vector9 IS DOR_zd(35 DOWNTO 27); ALIAS MemOutL0 : std_logic_vector9 IS MemOutL(8 DOWNTO 0); ALIAS MemOutR0 : std_logic_vector9 IS MemOutR(8 DOWNTO 0); ALIAS MemOutL1 : std_logic_vector9 IS MemOutL(17 DOWNTO 9); ALIAS MemOutR1 : std_logic_vector9 IS MemOutR(17 DOWNTO 9); ALIAS MemOutL2 : std_logic_vector9 IS MemOutL(26 DOWNTO 18); ALIAS MemOutR2 : std_logic_vector9 IS MemOutR(26 DOWNTO 18); ALIAS MemOutL3 : std_logic_vector9 IS MemOutL(35 DOWNTO 27); ALIAS MemOutR3 : std_logic_vector9 IS MemOutR(35 DOWNTO 27); ALIAS MemOutL0Reg : std_logic_vector9 IS MemOutLReg(8 DOWNTO 0); ALIAS MemOutR0Reg : std_logic_vector9 IS MemOutRReg(8 DOWNTO 0); ALIAS MemOutL1Reg : std_logic_vector9 IS MemOutLReg(17 DOWNTO 9); ALIAS MemOutR1Reg : std_logic_vector9 IS MemOutRReg(17 DOWNTO 9); ALIAS MemOutL2Reg : std_logic_vector9 IS MemOutLReg(26 DOWNTO 18); ALIAS MemOutR2Reg : std_logic_vector9 IS MemOutRReg(26 DOWNTO 18); ALIAS MemOutL3Reg : std_logic_vector9 IS MemOutLReg(35 DOWNTO 27); ALIAS MemOutR3Reg : std_logic_vector9 IS MemOutRReg(35 DOWNTO 27); TYPE mem_type IS ARRAY(0 TO MemSize) OF integer RANGE -2 TO MaxData; SHARED VARIABLE MemDataA : mem_type := (OTHERS => -2); SHARED VARIABLE MemDataB : mem_type := (OTHERS => -2); SHARED VARIABLE MemDataC : mem_type := (OTHERS => -2); SHARED VARIABLE MemDataD : mem_type := (OTHERS => -2); SIGNAL writeL : std_logic := '0'; SIGNAL writeR : std_logic := '0'; SIGNAL readL : std_logic := '0'; SIGNAL readR : std_logic := '0'; SIGNAL chng_lp : STD_LOGIC := '0'; SIGNAL chng_rp : STD_LOGIC := '0'; TYPE mem_state IS (desel, read, write, collision); SHARED VARIABLE stateL : mem_state; SHARED VARIABLE stateR : mem_state; SIGNAL Viol : X01 := '0'; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- VITALTimingCheck : PROCESS (CLKL, CLKR, ALIn, ARIn, CE0LNeg, CE0RNeg, CE1R,CE1L, BELInNeg, BERInNeg, RWL, RWR, IOLIn, IORIn, ADSLNeg, ADSRNeg, CNTENLNeg, CNTENRNeg, REPEATLNeg, REPEATRNeg,PLFTR,PLFTL ) IS --Setup/Hold checks variables VARIABLE TD_AL0_CLKL : VitalTimingDataType; VARIABLE Tviol_AL0_CLKL : X01 := '0'; VARIABLE TD_AR0_CLKR : VitalTimingDataType; VARIABLE Tviol_AR0_CLKR : X01 := '0'; VARIABLE TD_CE0LNeg_CLKL : VitalTimingDataType; VARIABLE Tviol_CE0LNeg_CLKL : X01 := '0'; VARIABLE TD_CE0RNeg_CLKR : VitalTimingDataType; VARIABLE Tviol_CE0RNeg_CLKR : X01 := '0'; VARIABLE TD_CE1L_CLKL : VitalTimingDataType; VARIABLE Tviol_CE1L_CLKL : X01 := '0'; VARIABLE TD_CE1R_CLKR : VitalTimingDataType; VARIABLE Tviol_CE1R_CLKR : X01 := '0'; VARIABLE TD_BEL0Neg_CLKL : VitalTimingDataType; VARIABLE Tviol_BEL0Neg_CLKL : X01 := '0'; VARIABLE TD_BER0Neg_CLKR : VitalTimingDataType; VARIABLE Tviol_BER0Neg_CLKR : X01 := '0'; VARIABLE TD_RWL_CLKL : VitalTimingDataType; VARIABLE Tviol_RWL_CLKL : X01 := '0'; VARIABLE TD_RWR_CLKR : VitalTimingDataType; VARIABLE Tviol_RWR_CLKR : X01 := '0'; VARIABLE TD_IOL0_CLKL : VitalTimingDataType; VARIABLE Tviol_IOL0_CLKL : X01 := '0'; VARIABLE TD_IOR0_CLKR : VitalTimingDataType; VARIABLE Tviol_IOR0_CLKR : X01 := '0'; VARIABLE TD_ADSLNeg_CLKL : VitalTimingDataType; VARIABLE Tviol_ADSLNeg_CLKL : X01 := '0'; VARIABLE TD_ADSRNeg_CLKR : VitalTimingDataType; VARIABLE Tviol_ADSRNeg_CLKR : X01 := '0'; VARIABLE TD_CNTENLNeg_CLKL : VitalTimingDataType; VARIABLE Tviol_CNTENLNeg_CLKL : X01 := '0'; VARIABLE TD_CNTENRNeg_CLKR : VitalTimingDataType; VARIABLE Tviol_CNTENRNeg_CLKR : X01 := '0'; VARIABLE TD_REPEATLNeg_CLKL : VitalTimingDataType; VARIABLE Tviol_REPEATLNeg_CLKL : X01 := '0'; VARIABLE TD_REPEATRNeg_CLKR : VitalTimingDataType; VARIABLE Tviol_REPEATRNeg_CLKR : X01 := '0'; -- Pulse Width and Period Check Variables VARIABLE Pviol_CLKL_PIPELINE_EQ_1 : X01 := '0'; VARIABLE PD_CLKL_PIPELINE_EQ_1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKL_NOPIPELINE_EQ_1 : X01 := '0'; VARIABLE PD_CLKL_NOPIPELINE_EQ_1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKR_PIPELINE_EQ_1 : X01 := '0'; VARIABLE PD_CLKR_PIPELINE_EQ_1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKR_NOPIPELINE_EQ_1 : X01 := '0'; VARIABLE PD_CLKR_NOPIPELINE_EQ_1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN -------------------------------- -- Timing Check Section -------------------------------- IF TimingChecksOn THEN -- CLKL pulse ( low&high ) width and period check, -- WHEN PIPELINE VitalPeriodPulseCheck ( TestSignal => CLKL, TestSignalName => "CLKL", Period => tperiod_CLKL_PIPELINE_EQ_1, PulseWidthHigh => tpw_CLKL_PIPELINE_EQ_1_posedge, PulseWidthLow => tpw_CLKL_PIPELINE_EQ_1_negedge, CheckEnabled => PLFTL = '1', HeaderMsg => InstancePath & partID, PeriodData => PD_CLKL_PIPELINE_EQ_1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKL_PIPELINE_EQ_1); -- CLKL pulse ( low&high ) width and period check, -- WHEN NOPIPELINE VitalPeriodPulseCheck ( TestSignal => CLKL, TestSignalName => "CLKL", Period => tperiod_CLKL_NOPIPELINE_EQ_1, PulseWidthHigh => tpw_CLKL_NOPIPELINE_EQ_1_posedge, PulseWidthLow => tpw_CLKL_NOPIPELINE_EQ_1_negedge, CheckEnabled => PLFTL = '0', HeaderMsg => InstancePath & partID, PeriodData => PD_CLKL_NOPIPELINE_EQ_1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKL_NOPIPELINE_EQ_1); -- CLKR pulse ( low&high ) width and period check, -- WHEN PIPELINE VitalPeriodPulseCheck ( TestSignal => CLKR, TestSignalName => "CLKR", Period => tperiod_CLKR_PIPELINE_EQ_1, PulseWidthHigh => tpw_CLKR_PIPELINE_EQ_1_posedge, PulseWidthLow => tpw_CLKR_PIPELINE_EQ_1_negedge, CheckEnabled => PLFTR = '1', HeaderMsg => InstancePath & partID, PeriodData => PD_CLKR_PIPELINE_EQ_1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKR_PIPELINE_EQ_1); -- CLKR pulse ( low&high ) width and period check, -- WHEN NOPIPELINE VitalPeriodPulseCheck ( TestSignal => CLKR, TestSignalName => "CLKR", Period => tperiod_CLKR_NOPIPELINE_EQ_1, PulseWidthHigh => tpw_CLKR_NOPIPELINE_EQ_1_posedge, PulseWidthLow => tpw_CLKR_NOPIPELINE_EQ_1_negedge, CheckEnabled => PLFTR = '0', HeaderMsg => InstancePath & partID, PeriodData => PD_CLKR_NOPIPELINE_EQ_1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKR_NOPIPELINE_EQ_1); -- AL/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AL0_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL0_CLKL); -- AR/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_AR0_CLKR, SetupLow => tsetup_AR0_CLKR, HoldHigh => thold_AR0_CLKR, HoldLow => thold_AR0_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_AR0_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR0_CLKR); -- CE0LNeg/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => CE0LNeg, TestSignalName => "CE0LNeg", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_CE0LNeg_CLKL, SetupLow => tsetup_CE0LNeg_CLKL, HoldHigh => thold_CE0LNeg_CLKL, HoldLow => thold_CE0LNeg_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CE0LNeg_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0LNeg_CLKL); -- CE0RNeg/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => CE0RNeg, TestSignalName => "CE0RNeg", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_CE0RNeg_CLKR, SetupLow => tsetup_CE0RNeg_CLKR, HoldHigh => thold_CE0RNeg_CLKR, HoldLow => thold_CE0RNeg_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CE0RNeg_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0RNeg_CLKR); -- CE1L/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => CE1L, TestSignalName => "CE1L", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CE1L_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1L_CLKL); -- CE1R/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => CE1R, TestSignalName => "CE1R", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_CE1R_CLKR, SetupLow => tsetup_CE1R_CLKR, HoldHigh => thold_CE1R_CLKR, HoldLow => thold_CE1R_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CE1R_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1R_CLKR); -- BELNeg/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => BELInNeG, TestSignalName => "BELNeg", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_BEL0Neg_CLKL, SetupLow => tsetup_BEL0Neg_CLKL, HoldHigh => thold_BEL0Neg_CLKL, HoldLow => thold_BEL0Neg_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_BEL0Neg_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BEL0Neg_CLKL); -- BERNeg/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => BERInNeg, TestSignalName => "BERNeg", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_BER0Neg_CLKR, SetupLow => tsetup_BER0Neg_CLKR, HoldHigh => thold_BER0Neg_CLKR, HoldLow => thold_BER0Neg_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_BER0Neg_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BER0Neg_CLKR); -- RWL/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => RWL, TestSignalName => "RWL", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RWL_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWL_CLKL); -- RWR/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => RWR, TestSignalName => "RWR", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_RWR_CLKR, SetupLow => tsetup_RWR_CLKR, HoldHigh => thold_RWR_CLKR, HoldLow => thold_RWR_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RWR_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWR_CLKR); -- IOL/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => IOLIn, TestSignalName => "IOL", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOL0_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL0_CLKL); -- IOR/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => IORIn, TestSignalName => "IOR", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_IOR0_CLKR, SetupLow => tsetup_IOR0_CLKR, HoldHigh => thold_IOR0_CLKR, HoldLow => thold_IOR0_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_IOR0_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR0_CLKR); -- ADSLNeg/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => ADSLNeg, TestSignalName => "ADSLNeg", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ADSLNeg_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSLNeg_CLKL); -- ADSRNeg/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => ADSRNeg, TestSignalName => "ADSRNeg", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_ADSRNeg_CLKR, SetupLow => tsetup_ADSRNeg_CLKR, HoldHigh => thold_ADSRNeg_CLKR, HoldLow => thold_ADSRNeg_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ADSRNeg_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSRNeg_CLKR); -- CNTENLNeg/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => CNTENLNeg, TestSignalName => "CNTENLNeg", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_CNTENLNeg_CLKL, SetupLow => tsetup_CNTENLNeg_CLKL, HoldHigh => thold_CNTENLNeg_CLKL, HoldLow => thold_CNTENLNeg_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CNTENLNeg_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENLNeg_CLKL); -- CNTENRNeg/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => CNTENRNeg, TestSignalName => "CNTENRNeg", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_CNTENRNeg_CLKR, SetupLow => tsetup_CNTENRNeg_CLKR, HoldHigh => thold_CNTENRNeg_CLKR, HoldLow => thold_CNTENRNeg_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_CNTENRNeg_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENRNeg_CLKR); -- REPEATLNeg/CLKL setup/hold time check VitalSetupHoldCheck ( TestSignal => REPEATLNeg, TestSignalName => "REPEATLNeg", RefSignal => CLKL, RefSignalName => "CLKL", SetupHigh => tsetup_REPEATLNeg_CLKL, SetupLow => tsetup_REPEATLNeg_CLKL, HoldHigh => thold_REPEATLNeg_CLKL, HoldLow => thold_REPEATLNeg_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_REPEATLNeg_CLKL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_REPEATLNeg_CLKL); -- REPEATRNeg/CLKR setup/hold time check VitalSetupHoldCheck ( TestSignal => REPEATRNeg, TestSignalName => "REPEATRNeg", RefSignal => CLKR, RefSignalName => "CLKR", SetupHigh => tsetup_REPEATRNeg_CLKR, SetupLow => tsetup_REPEATRNeg_CLKR, HoldHigh => thold_REPEATRNeg_CLKR, HoldLow => thold_REPEATRNeg_CLKR, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_REPEATRNeg_CLKR, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_REPEATRNeg_CLKR); Violation := Pviol_CLKL_PIPELINE_EQ_1 OR Pviol_CLKL_NOPIPELINE_EQ_1 OR Pviol_CLKR_PIPELINE_EQ_1 OR Pviol_CLKR_NOPIPELINE_EQ_1 OR Tviol_AL0_CLKL OR Tviol_AR0_CLKR OR Tviol_CE0LNeg_CLKL OR Tviol_CE0RNeg_CLKR OR Tviol_CE1L_CLKL OR Tviol_CE1R_CLKR OR Tviol_BEL0Neg_CLKL OR Tviol_BER0Neg_CLKR OR Tviol_RWL_CLKL OR Tviol_RWR_CLKR OR Tviol_IOL0_CLKL OR Tviol_IOR0_CLKR OR Tviol_ADSLNeg_CLKL OR Tviol_ADSRNeg_CLKR OR Tviol_CNTENLNeg_CLKL OR Tviol_CNTENRNeg_CLKR OR Tviol_REPEATLNeg_CLKL OR Tviol_REPEATRNeg_CLKR; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END process VITALTimingCheck; -- purpose: Pipeline mux in for CEReg signal -- type : sequential -- inputs : CLKL, CELReg -- outputs: CELMuxIn CEPipeLP : PROCESS (CLKL) IS VARIABLE tmp : std_logic; VARIABLE sleap_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE wake_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE no_zz_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE allowZZ : BOOLEAN := TRUE; BEGIN -- PROCESS CEPipeP IF rising_edge(CLKL) THEN -- rising clock edge IF ZZL = '1' THEN IF sleap_cnt < 3 THEN sleap_cnt := sleap_cnt + 1; wake_cnt := 0; ELSE ZZL_int <= '1'; END IF; ELSE IF wake_cnt < 3 THEN wake_cnt := wake_cnt + 1; sleap_cnt := 0; ELSE ZZL_int <= '0'; stateL := read; END IF; END IF; CELMuxIn <= CELReg; tmp := CE1L OR ((NOT CE1L) AND (NOT CE0LNeg)); IF tmp = '0' THEN IF no_zz_cnt < 3 THEN no_zz_cnt := no_zz_cnt + 1; allowZZ := false; ELSE allowZZ := true; END IF; ELSE no_zz_cnt := 0; allowZZ := false; END IF; IF tmp='1' AND RWL = '0' THEN writeL <= NOT writeL; CLKL_in <= '1','0' AFTER 1 ns; stateL := write; IF CLKR_out ='1' AND stateR = write THEN stateL := collision; END IF; END IF; IF tmp = '1' AND RWL='1' THEN readL <= NOT readL; END IF; CELReg <= tmp; RWLReg <= RWL; CASE PLFTL IS WHEN '0' => IF tmp ='1' AND OELNeg='0' AND RWL='1' THEN stateL := read; IF (CLKR_out = '1' AND stateR=write) OR (ZZL = '1' AND NOT allowZZ) THEN stateL := collision; END IF; END IF; CELMux <= tmp; WHEN '1' => IF CELReg ='1' AND OELNeg='0' AND RWL='1' THEN stateL := read; IF (CLKR_out = '1' AND stateR=write) OR (ZZL = '1' AND NOT allowZZ) THEN stateL := collision; END IF; END IF; CELMux <= CELReg; WHEN OTHERS => CELMux <= tmp; END CASE; -- Seting internal pipeline registers MemOutLReg <= MemOutL; MemInRegL <= IOLIn; BELNegReg <= BELInNeg; BELNegPipe <= BELNegReg; MemBEL0 <= ((NOT BELInNeg(0)) AND (NOT RWL)) AND tmp; MemBEL1 <= ((NOT BELInNeg(1)) AND (NOT RWL)) AND tmp; MemBEL2 <= ((NOT BELInNeg(2)) AND (NOT RWL)) AND tmp; MemBEL3 <= ((NOT BELInNeg(3)) AND (NOT RWL)) AND tmp; END IF; END PROCESS CEPipeLP; -- purpose: Pipeline mux in for CEReg signal -- type : sequential -- inputs : CLKR, CERReg -- outputs: CERMuxIn CEPipeRP: PROCESS (CLKR) IS VARIABLE tmp : STD_LOGIC; VARIABLE sleap_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE wake_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE no_zz_cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE allowZZ : BOOLEAN := TRUE; BEGIN -- PROCESS CEPipeP IF rising_edge(CLKR) THEN -- rising clock edge IF ZZR = '1' THEN IF sleap_cnt < 3 THEN sleap_cnt := sleap_cnt + 1; wake_cnt := 0; ELSE ZZR_int <= '1'; END IF; ELSE IF wake_cnt < 3 THEN wake_cnt := wake_cnt + 1; sleap_cnt := 0; ELSE ZZR_int <= '0'; stateR := read; END IF; END IF; CERMuxIn <= CERReg; tmp := CE1R OR ((NOT CE1R) AND (NOT CE0RNeg)); IF tmp = '0' THEN IF no_zz_cnt < 3 THEN no_zz_cnt := no_zz_cnt + 1; allowZZ := false; ELSE allowZZ := true; END IF; ELSE no_zz_cnt := 0; allowZZ := false; END IF; IF tmp='1' AND RWR = '0' THEN writeR <= NOT writeR; CLKR_in <= '1','0' AFTER 1 ns; stateR := write; IF CLKL_out ='1' AND stateL = write THEN stateR := collision; END IF; END IF; IF tmp = '1' AND RWR='1' THEN readR <= NOT readR; END IF; CERReg <= tmp; RWRReg <= RWR; CASE PLFTR IS WHEN '0' => CERMux <= tmp; IF tmp = '1' AND OERNeg='0' AND RWR='1' THEN stateR := read; IF (CLKL_out = '1' AND stateL = write) OR (ZZR = '1' AND NOT allowZZ) THEN stateR := collision; END IF; END IF; WHEN '1' => CERMux <= CERReg; IF CERReg = '1' AND OERNeg='0' AND RWR='1' THEN stateR := read; IF (CLKL_out = '1' AND stateL = write) OR (ZZR = '1' AND NOT allowZZ) THEN stateR := collision; END IF; END IF; WHEN OTHERS => CERMux <= tmp; END CASE; -- Seting internal pipeline registers MemOutRReg <= MemOutR; MemInRegR <= IORIn; BERNegReg <= BERInNeg; BERNegPipe <= BERNegReg; MemBER0 <= ((NOT BERInNeg(0)) AND (NOT RWR)) AND tmp; MemBER1 <= ((NOT BERInNeg(1)) AND (NOT RWR)) AND tmp; MemBER2 <= ((NOT BERInNeg(2)) AND (NOT RWR)) AND tmp; MemBER3 <= ((NOT BERInNeg(3)) AND (NOT RWR)) AND tmp; END IF; END PROCESS CEPipeRP; -- purpose: BE signal multiplexer for fall through or pipeline -- type : combinational -- inputs : PLFTL, BEL0NegReg, BEL1NegReg, BEL2NegReg, BEL3NegReg, -- BEL0NegPipe, BEL1NegPipe, BEL2NegPipe, BEL3NegPipe -- outputs: BEL0Mux, BEL1Mux, BEL2Mux, BEL3Mux BELMUXP: PROCESS (PLFTL, BELNegReg,BELNegPipe) IS BEGIN -- PROCESS BELMUXP CASE PLFTL IS WHEN '0' => BEL0Mux <= BELNegReg(0); BEL1Mux <= BELNegReg(1); BEL2Mux <= BELNegReg(2); BEL3Mux <= BELNegReg(3); WHEN '1' => BEL0Mux <= BELNegPipe(0); BEL1Mux <= BELNegPipe(1); BEL2Mux <= BELNegPipe(2); BEL3Mux <= BELNegPipe(3); WHEN OTHERS => BEL0Mux <= BELNegReg(0); BEL1Mux <= BELNegReg(1); BEL2Mux <= BELNegReg(2); BEL3Mux <= BELNegReg(3); END CASE; END PROCESS BELMUXP; -- purpose: BE signal multiplexer for fall through or pipeline -- type : combinational -- inputs : PLFTR, BER0NegReg, BER1NegReg, BER2NegReg, BER3NegReg, -- BER0NegPipe, BER1NegPipe, BER2NegPipe, BER3NegPipe -- outputs: BER0Mux, BER1Mux, BER2Mux, BER3Mux BERMUXP: PROCESS (PLFTR, BERNegReg,BERNegPipe) IS BEGIN -- PROCESS BERMUXP CASE PLFTR IS WHEN '0' => BER0Mux <= BERNegReg(0); BER1Mux <= BERNegReg(1); BER2Mux <= BERNegReg(2); BER3Mux <= BERNegReg(3); WHEN '1' => BER0Mux <= BERNegPipe(0); BER1Mux <= BERNegPipe(1); BER2Mux <= BERNegPipe(2); BER3Mux <= BERNegPipe(3); WHEN OTHERS => BER0Mux <= BERNegReg(0); BER1Mux <= BERNegReg(1); BER2Mux <= BERNegReg(2); BER3Mux <= BERNegReg(3); END CASE; END PROCESS BERMUXP; -- Control signals for output generation DoutL0Sel <= (((NOT OELNeg) AND CELMux) AND NOT BEL0Mux) AND RWLReg; DoutR0Sel <= (((NOT OERNeg) AND CERMux) AND NOT BER0Mux) AND RWRReg; DoutL1Sel <= (((NOT OELNeg) AND CELMux) AND NOT BEL1Mux) AND RWLReg; DoutR1Sel <= (((NOT OERNeg) AND CERMux) AND NOT BER1Mux) AND RWRReg; DoutL2Sel <= (((NOT OELNeg) AND CELMux) AND NOT BEL2Mux) AND RWLReg; DoutR2Sel <= (((NOT OERNeg) AND CERMux) AND NOT BER2Mux) AND RWRReg; DoutL3Sel <= (((NOT OELNeg) AND CELMux) AND NOT BEL3Mux) AND RWLReg; DoutR3Sel <= (((NOT OERNeg) AND CERMux) AND NOT BER3Mux) AND RWRReg; ----------------------------------------------------------------------- -- Memory output control ----------------------------------------------------------------------- -- Registring outputs for pipeline -- purpose: Registring output for multiplexer pipeline -- type : sequential -- inputs : CLKL -- outputs: MemOutLReg MemOutRegP: PROCESS (DoutL0Sel,DoutL1Sel,DoutL2Sel,DoutL3Sel, chng_lp, PLFTL) IS VARIABLE OutMux0 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux1 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux2 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux3 : std_logic_vector(8 DOWNTO 0); BEGIN -- PROCESS MemOutRegP CASE PLFTL IS WHEN '0' => OutMux0 := MemOutL0; OutMux1 := MemOutL1; OutMux2 := MemOutL2; OutMux3 := MemOutL3; WHEN '1' => OutMux0 := MemOutL0Reg; OutMux1 := MemOutL1Reg; OutMux2 := MemOutL2Reg; OutMux3 := MemOutL3Reg; WHEN OTHERS => NULL; END CASE; -- Simulate output buffer IF DoutL0Sel = '1' THEN outLZD0 <= OutMux0; ELSE outLZD0 <= (OTHERS => 'Z'); END IF; IF DoutL1Sel = '1' THEN outLZD1 <= OutMux1; ELSE outLZD1 <= (OTHERS => 'Z'); END IF; IF DoutL2Sel = '1' THEN outLZD2 <= OutMux2; ELSE outLZD2 <= (OTHERS => 'Z'); END IF; IF DoutL3Sel = '1' THEN outLZD3 <= OutMux3; ELSE outLZD3 <= (OTHERS => 'Z'); END IF; END PROCESS MemOutRegP; MemOutRRegP: PROCESS (DoutR0Sel,DoutR1Sel,DoutR2Sel,DoutR3Sel, chng_rp, PLFTR) IS VARIABLE OutMux0 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux1 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux2 : std_logic_vector(8 DOWNTO 0); VARIABLE OutMux3 : std_logic_vector(8 DOWNTO 0); BEGIN -- PROCESS MemOutRegP CASE PLFTR IS WHEN '0' => OutMux0 := MemOutR0; OutMux1 := MemOutR1; OutMux2 := MemOutR2; OutMux3 := MemOutR3; WHEN '1' => OutMux0 := MemOutR0Reg; OutMux1 := MemOutR1Reg; OutMux2 := MemOutR2Reg; OutMux3 := MemOutR3Reg; WHEN OTHERS => NULL; END CASE; -- Simulate output buffer IF DoutR0Sel = '1' THEN outRZD0 <= OutMux0; ELSE outRZD0 <= (OTHERS => 'Z'); END IF; IF DoutR1Sel = '1' THEN outRZD1 <= OutMux1; ELSE outRZD1 <= (OTHERS => 'Z'); END IF; IF DoutR2Sel = '1' THEN outRZD2 <= OutMux2; ELSE outRZD2 <= (OTHERS => 'Z'); END IF; IF DoutR3Sel = '1' THEN outRZD3 <= OutMux3; ELSE outRZD3 <= (OTHERS => 'Z'); END IF; END PROCESS MemOutRRegP; -- Counters for address generation -- purpose: generating of address -- type : sequential -- inputs : CLKL, CLKR -- outputs: MemAddrInL, MemAddrInR counter : PROCESS (CLKL, CLKR) VARIABLE AddrL : natural RANGE 0 TO MemSize; VARIABLE AddrR : natural RANGE 0 TO MemSize; VARIABLE AddrLReg : natural RANGE 0 TO MemSize; VARIABLE AddrRReg : natural RANGE 0 TO MemSize; BEGIN -- PROCESS counterl IF rising_edge(CLKL) THEN -- rising clock edge IF REPEATLNeg = '0' THEN AddrL := AddrLReg; ELSIF ADSLNeg = '0' AND REPEATLNeg='1' THEN AddrL := to_nat(ALIn); AddrLReg := AddrL; ELSIF ADSLNeg = '1' AND REPEATLNeg ='1' AND CNTENLNeg = '0' THEN AddrL := AddrL + 1; END IF; MemAddrInL <= AddrL; -- Setting of interrupt signals... IF CE1L = '1' AND CE0LNeg = '0' THEN IF AddrL = FF_ADDR AND RWL = '0' THEN INTRNeg_zd <= '0'; END IF; IF AddrL = FE_ADDR AND RWL = '1' THEN INTLNeg_zd <= '1'; END IF; END IF; END IF; IF rising_edge(CLKR) THEN -- rising clock edge IF REPEATRNeg = '0' THEN AddrR := AddrRReg; ELSIF ADSRNeg = '0' AND REPEATRNeg='1' THEN AddrR := to_nat(ARIn); AddrRReg := AddrR; ELSIF ADSRNeg = '1' AND REPEATRNeg ='1' AND CNTENRNeg = '0' THEN AddrR := AddrR + 1; END IF; MemAddrInR <= AddrR; -- Setting of interrupt signals... IF CE1R = '1' AND CE0RNeg = '0' THEN IF AddrR = FF_ADDR AND RWR = '1' THEN INTRNeg_zd <= '1'; END IF; IF AddrR = FE_ADDR AND RWR = '0' THEN INTLNeg_zd <= '0'; END IF; END IF; END IF; END PROCESS counter; -- purpose: Write in memory by left port -- type : combinational -- inputs : writeL,MemBEL0,MemBEL1,MemBEL2,MemBEL3,MemAddrInL -- outputs: writeLP : PROCESS (MemBEL0, MemBEL1, MemBEL2, MemBEL3, MemAddrInL, MemInRegL) IS VARIABLE address : natural; VARIABLE data : integer RANGE -2 TO MaxData; BEGIN -- PROCESS writeLP address := MemAddrInL; IF MemBEL3 ='1' THEN IF stateL = collision OR Viol /= '0' THEN MemDataA(address) := -1; ELSE MemDataA(address) := to_nat(MemInRegL(35 DOWNTO 27)); END IF; END IF; IF MemBEL2 ='1' THEN IF stateL = collision OR Viol /= '0' THEN MemDataB(address) := -1; ELSE MemDataB(address) := to_nat(MemInRegL(26 DOWNTO 18)); END IF; END IF; IF MemBEL1 ='1' THEN IF stateL = collision OR Viol /= '0' THEN MemDataC(address) := -1; ELSE MemDataC(address) := to_nat(MemInRegL(17 DOWNTO 9)); END IF; END IF; IF MemBEL0 ='1' THEN IF stateL = collision OR Viol /= '0' THEN MemDataD(address) := -1; ELSE MemDataD(address) := to_nat(MemInRegL(8 DOWNTO 0)); END IF; END IF; END PROCESS writeLP; -- purpose: Write in memory by right port -- type : combinational -- inputs : writeR,MemBER0,MemBER1,MemBER2,MemBER3,MemAddrInR -- outputs: writeRP : PROCESS (MemBER0, MemBER1, MemBER2, MemBER3, MemAddrInR, MemInRegR) IS VARIABLE address : natural; BEGIN -- PROCESS writeRP address := MemAddrInR; IF MemBER3 ='1' THEN IF stateR = collision OR Viol /= '0' THEN MemDataA(address) := -1; ELSE MemDataA(address) := to_nat(MemInRegR(35 DOWNTO 27)); END IF; END IF; IF MemBER2 ='1' THEN IF stateR = collision OR Viol /= '0' THEN MemDataB(address) := -1; ELSE MemDataB(address) := to_nat(MemInRegR(26 DOWNTO 18)); END IF; END IF; IF MemBER1 ='1' THEN IF stateR = collision OR Viol /= '0' THEN MemDataC(address) := -1; ELSE MemDataC(address) := to_nat(MemInRegR(17 DOWNTO 9)); END IF; END IF; IF MemBER0 ='1' THEN IF stateR = collision OR Viol /= '0' THEN MemDataD(address) := -1; ELSE MemDataD(address) := to_nat(MemInRegR(8 DOWNTO 0)); END IF; END IF; END PROCESS writeRP; -- purpose: Read process on left port -- type : combinational -- inputs : readL,MemAddrInL,stateL -- outputs: MemOutL readLP: PROCESS (readL,MemAddrInL) IS VARIABLE address : NATURAL; BEGIN -- PROCESS readLP address := MemAddrInL; IF ZZL_int = '0' THEN IF MemDataA(address) = -1 OR stateL = collision THEN MemOutL3 <= (OTHERS => 'X'); ELSIF MemDataA(address) = -2 THEN MemOutL3 <= (OTHERS => 'U'); ELSE MemOutL3 <= to_slv(MemDataA(address),9); END IF; IF MemDataB(address) = -1 OR stateL = collision THEN MemOutL2 <= (OTHERS => 'X'); ELSIF MemDataB(address) = -2 THEN MemOutL2 <= (OTHERS => 'U'); ELSE MemOutL2 <= to_slv(MemDataB(address),9); END IF; IF MemDataC(address) = -1 OR stateL = collision THEN MemOutL1 <= (OTHERS => 'X'); ELSIF MemDataC(address) = -2 THEN MemOutL1 <= (OTHERS => 'U'); ELSE MemOutL1 <= to_slv(MemDataC(address),9); END IF; IF MemDataD(address) = -1 OR stateL = collision THEN MemOutL0 <= (OTHERS => 'X'); ELSIF MemDataD(address) = -2 THEN MemOutL0 <= (OTHERS => 'U'); ELSE MemOutL0 <= to_slv(MemDataD(address),9); END IF; chng_lp <= NOT chng_lp; ELSE MemOutL <= (OTHERS => 'Z'); END IF; END PROCESS readLP; -- purpose: Read process on right port -- type : combinational -- inputs : readR,MemAddrInR,stateR -- outputs: MemOutR readRP: PROCESS (readR,MemAddrInR) IS VARIABLE address : NATURAL; BEGIN -- PROCESS readRP address := MemAddrInR; IF ZZR_int = '0' THEN IF MemDataA(address) = -1 OR stateR = collision THEN MemOutR3 <= (OTHERS => 'X'); ELSIF MemDataA(address) = -2 THEN MemOutR3 <= (OTHERS => 'U'); ELSE MemOutR3 <= to_slv(MemDataA(address),9); END IF; IF MemDataB(address) = -1 OR stateR = collision THEN MemOutR2 <= (OTHERS => 'X'); ELSIF MemDataB(address) = -2 THEN MemOutR2 <= (OTHERS => 'U'); ELSE MemOutR2 <= to_slv(MemDataB(address),9); END IF; IF MemDataC(address) = -1 OR stateR = collision THEN MemOutR1 <= (OTHERS => 'X'); ELSIF MemDataC(address) = -2 THEN MemOutR1 <= (OTHERS => 'U'); ELSE MemOutR1 <= to_slv(MemDataC(address),9); END IF; IF MemDataD(address) = -1 OR stateR = collision THEN MemOutR0 <= (OTHERS => 'X'); ELSIF MemDataD(address) = -2 THEN MemOutR0 <= (OTHERS => 'U'); ELSE MemOutR0 <= to_slv(MemDataD(address),9); END IF; chng_rp <= NOT chng_rp; ELSE MemOutR <= (OTHERS => 'Z'); END IF; END PROCESS readRP; ----------------------------------------------------------------------- -- Path delay section for Left port signal ----------------------------------------------------------------------- Left_PathDelay_Gen: FOR i IN IOLOut'RANGE GENERATE PROCESS (DOL_zd(i)) IS VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN -- PROCESS VitalPathDelay01Z( OutSignal => IOLOut(i), OutSignalName => "IOLOut", OutTemp => DOL_zd(i), GlitchData => D_GlitchData, Mode => VitalTransport, Paths => ( 0 => ( InputChangeTime => CLKL'LAST_EVENT, PathDelay => tpd_CLKL_IOL0_NOPIPELINE_EQ_1, PathCondition => PLFTL = '0'), 1 => ( InputChangeTime => CLKL'LAST_EVENT, PathDelay => tpd_CLKL_IOL0_PIPELINE_EQ_1, PathCondition => PLFTL = '1'), 2 => ( InputChangeTime => OELNeg'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => true) ) ); END PROCESS; END GENERATE Left_PathDelay_Gen; -- purpose: interrupt signals delay -- type : combinational -- inputs : INTLNeg_zd, INTRNeg_zd -- outputs: Interrupt_del: PROCESS (INTLNeg_zd, INTRNeg_zd) IS VARIABLE IntL_GlitchData : VitalGlitchDataType; VARIABLE IntR_GlitchData : VitalGlitchDataType; BEGIN -- PROCESS Interrupt_del VitalPathDelay01( OutSignal => INTLNeg, OutSignalName => "INT#L", OutTemp => INTLNeg_zd, Mode => VitalTransport, GlitchData => IntL_GlitchData, Paths => ( 0 => (InputChangeTime => CLKL'LAST_EVENT, PathDelay => tpd_CLKL_INTLNeg, PathCondition => INTLNeg_zd= '1'), 1 => (InputChangeTime => CLKR'LAST_EVENT, PathDelay => tpd_CLKR_INTLNeg, PathCondition => INTLNeg_zd = '0') ) ); VitalPathDelay01( OutSignal => INTRNeg, OutSignalName => "INT#R", OutTemp => INTRNeg_zd, Mode => VitalTransport, GlitchData => IntR_GlitchData, Paths => ( 0 => (InputChangeTime => CLKL'LAST_EVENT, PathDelay => tpd_CLKL_INTRNeg, PathCondition => INTRNeg_zd = '0'), 1 => (InputChangeTime => CLKR'LAST_EVENT, PathDelay => tpd_CLKR_INTRNeg, PathCondition => INTRNeg_zd='1') ) ); END PROCESS Interrupt_del; ----------------------------------------------------------------------- -- Path delay section for right port signal ----------------------------------------------------------------------- Right_PathDelay_Gen: FOR i IN IOROut'RANGE GENERATE PROCESS (DOR_zd(i)) IS VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN -- PROCESS VitalPathDelay01Z( OutSignal => IOROut(i), OutSignalName => "IOROut", OutTemp => DOR_zd(i), GlitchData => D_GlitchData, Mode => VitalTransport, Paths => ( 0 => ( InputChangeTime => CLKR'LAST_EVENT, PathDelay => tpd_CLKR_IOR0_NOPIPELINE_EQ_1, PathCondition => PLFTR = '0'), 1 => ( InputChangeTime => CLKR'LAST_EVENT, PathDelay => tpd_CLKR_IOR0_PIPELINE_EQ_1, PathCondition => PLFTR = '1'), 2 => ( InputChangeTime => OERNeg'LAST_EVENT, PathDelay => tpd_OERNeg_IOR0, PathCondition => true) ) ); END PROCESS; END GENERATE Right_PathDelay_Gen; ----------------------------------------------------------------------- -- Preload process ----------------------------------------------------------------------- default : PROCESS -- text file input variables FILE mem_f : text is mem_file_name; VARIABLE ind : NATURAL; VARIABLE buf : line; BEGIN -------------------------------------------------------------- -- idt70t3509 memory preload file format -- / - comment -- @aaaaa - stands for address -- ddd ddd ddd ddd - is 9 bit to be written -- at Mem(aaaaa++) -- (aaaaa is incremented at every load) -- only first 1-5 columns are loaded. NO empty lines !!!!!!! -------------------------------------------------------------- IF UserPreload AND (mem_file_name /= "none" ) THEN ind := 0; WHILE (not ENDFILE (mem_f)) LOOP READLINE (mem_f, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 6)); ELSE IF ind <= MemSize THEN IF h(buf(1 to 3)) < 16#200# THEN MemDataA(ind) := h(buf(1 to 3)); END IF; IF h(buf(5 to 7)) < 16#200# THEN MemDataB(ind) := h(buf(5 to 7)); END IF; IF h(buf(9 to 11)) < 16#200# THEN MemDataC(ind) := h(buf(9 to 11)); END IF; IF h(buf(13 to 15)) < 16#200# THEN MemDataD(ind) := h(buf(13 to 15)); END IF; ind := ind + 1; ELSE REPORT "Memory address out of range"; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS default; END BLOCK Behavior; END vhdl_behavioral;