------------------------------------------------------------------------------- -- File Name: idt70t3319dd.vhd ------------------------------------------------------------------------------- -- Copyright (C) 2003-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 03 Oct 26 Inital Release -- V1.1 R. Munden 04 Feb 29 made address counters independent -- of chip enables -- V1.2 R. Munden 04 Mar 27 Fixed byte enable setup/hold -- V1.3 R. Munden 04 Nov 22 made output enable asynchronous -- V1.4 R. Munden 05 Aug 07 correct right port PL read -- V1.5 R. Munden 08 Jun 08 corrected timing generic names -- ------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: -- Part: IDT70T3319DD -- -- Description: 256K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM PQFP package ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.vital_timing.ALL; USE IEEE.vital_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------- -- ENTITY DECLARATION ------------------------------------------------------------------------------- ENTITY idt70t3319dd IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0L : VitalDelayType01 := VitalZeroDelay01; tipd_A1L : VitalDelayType01 := VitalZeroDelay01; tipd_A2L : VitalDelayType01 := VitalZeroDelay01; tipd_A3L : VitalDelayType01 := VitalZeroDelay01; tipd_A4L : VitalDelayType01 := VitalZeroDelay01; tipd_A5L : VitalDelayType01 := VitalZeroDelay01; tipd_A6L : VitalDelayType01 := VitalZeroDelay01; tipd_A7L : VitalDelayType01 := VitalZeroDelay01; tipd_A8L : VitalDelayType01 := VitalZeroDelay01; tipd_A9L : VitalDelayType01 := VitalZeroDelay01; tipd_A10L : VitalDelayType01 := VitalZeroDelay01; tipd_A11L : VitalDelayType01 := VitalZeroDelay01; tipd_A12L : VitalDelayType01 := VitalZeroDelay01; tipd_A13L : VitalDelayType01 := VitalZeroDelay01; tipd_A14L : VitalDelayType01 := VitalZeroDelay01; tipd_A15L : VitalDelayType01 := VitalZeroDelay01; tipd_A16L : VitalDelayType01 := VitalZeroDelay01; tipd_A17L : VitalDelayType01 := VitalZeroDelay01; tipd_IO0L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO1L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO2L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO3L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO4L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO5L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO6L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO7L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO8L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO9L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO10L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO11L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO12L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO13L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO14L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO15L : VitalDelayType01z := VitalZeroDelay01Z; tipd_IO16L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO17L : VitalDelayType01Z := VitalZeroDelay01Z; tipd_CE0NegL : VitalDelayType01 := VitalZeroDelay01; tipd_CE1L : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_CLKL : VitalDelayType01 := VitalZeroDelay01; tipd_ADSNegL : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENNegL : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATNegL : VitalDelayType01 := VitalZeroDelay01; tipd_UBNegL : VitalDelayType01 := VitalZeroDelay01; tipd_LBNegL : VitalDelayType01 := VitalZeroDelay01; tipd_ZZL : VitalDelayType01 := VitalZeroDelay01; tipd_A0R : VitalDelayType01 := VitalZeroDelay01; tipd_A1R : VitalDelayType01 := VitalZeroDelay01; tipd_A2R : VitalDelayType01 := VitalZeroDelay01; tipd_A3R : VitalDelayType01 := VitalZeroDelay01; tipd_A4R : VitalDelayType01 := VitalZeroDelay01; tipd_A5R : VitalDelayType01 := VitalZeroDelay01; tipd_A6R : VitalDelayType01 := VitalZeroDelay01; tipd_A7R : VitalDelayType01 := VitalZeroDelay01; tipd_A8R : VitalDelayType01 := VitalZeroDelay01; tipd_A9R : VitalDelayType01 := VitalZeroDelay01; tipd_A10R : VitalDelayType01 := VitalZeroDelay01; tipd_A11R : VitalDelayType01 := VitalZeroDelay01; tipd_A12R : VitalDelayType01 := VitalZeroDelay01; tipd_A13R : VitalDelayType01 := VitalZeroDelay01; tipd_A14R : VitalDelayType01 := VitalZeroDelay01; tipd_A15R : VitalDelayType01 := VitalZeroDelay01; tipd_A16R : VitalDelayType01 := VitalZeroDelay01; tipd_A17R : VitalDelayType01 := VitalZeroDelay01; tipd_IO0R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO1R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO2R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO3R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO4R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO5R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO6R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO7R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO8R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO9R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO10R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO11R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO12R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO13R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO14R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO15R : VitalDelayType01z := VitalZeroDelay01Z; tipd_IO16R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_IO17R : VitalDelayType01Z := VitalZeroDelay01Z; tipd_CE0NegR : VitalDelayType01 := VitalZeroDelay01; tipd_CE1R : VitalDelayType01 := VitalZeroDelay01; tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_CLKR : VitalDelayType01 := VitalZeroDelay01; tipd_ADSNegR : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENNegR : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATNegR : VitalDelayType01 := VitalZeroDelay01; tipd_UBNegR : VitalDelayType01 := VitalZeroDelay01; tipd_LBNegR : VitalDelayType01 := VitalZeroDelay01; tipd_ZZR : VitalDelayType01 := VitalZeroDelay01; tipd_OENegL : VitalDelayType01 := VitalZeroDelay01; tipd_OENegR : VitalDelayType01 := VitalZeroDelay01; tipd_PLNegL : VitalDelayType01 := VitalZeroDelay01; tipd_PLNegR : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLKL_COLNegL : VitalDelayType01 := UnitDelay01; --tCOLR,tCOLS tpd_CLKL_IntNegL : VitalDelayType01 := UnitDelay01; --tINR,tINS -- (tCD2,tCD2, tCKHZ,tCKHZ, tCKHZ, tCKHZ) tpd_CLKL_IO0L : VitalDelayType01Z := UnitDelay01Z; -- (tCD1,tCD1, tCKHZ,tCKHZ, tCKHZ, tCKHZ) tpd_CLKR_IO0R : VitalDelayType01Z := UnitDelay01Z; -- (tOE, tOE, tOHz, tOHZ, tOHZ, tOHZ) tpd_OENegL_IO0L : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths --pipeline mode tpw_CLKL_posedge : VitalDelayType := UnitDelay; --tCH2 tpw_CLKL_negedge : VitalDelayType := UnitDelay; --tCL2 --flowthrough tpw_CLKR_posedge : VitalDelayType := UnitDelay; --tCH1 tpw_CLKR_negedge : VitalDelayType := UnitDelay; --tCL1 -- tperiod min (calculated as 1/max freq) --pipeline tperiod_CLKL : VitalDelayType := UnitDelay; --tCYC2 --flowthrough tperiod_CLKR : VitalDelayType := UnitDelay; --tCYC1 -- tsetup values: setup times --tSA, tSC, tSB, tSW, tSD, tSAD, tSCN, tSRPT tsetup_A0L_CLKL : VitalDelayType := UnitDelay; -- thold values: hold times --tHA, tHC, tHB, tHW, tHD, tHAD, tHCN, tHRPT thold_A0L_CLKL : VitalDelayType := UnitDelay; --t device values tdevice_TCO : VitalDelayType := 5 ns; --tCO -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING := "none"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( --Left port Address lines A0L : IN std_logic := 'U'; A1L : IN std_logic := 'U'; A2L : IN std_logic := 'U'; A3L : IN std_logic := 'U'; A4L : IN std_logic := 'U'; A5L : IN std_logic := 'U'; A6L : IN std_logic := 'U'; A7L : IN std_logic := 'U'; A8L : IN std_logic := 'U'; A9L : IN std_logic := 'U'; A10L : IN std_logic := 'U'; A11L : IN std_logic := 'U'; A12L : IN std_logic := 'U'; A13L : IN std_logic := 'U'; A14L : IN std_logic := 'U'; A15L : IN std_logic := 'U'; A16L : IN std_logic := 'U'; A17L : IN std_logic := 'U'; --Left port IO lines IO0L : INOUT std_logic := 'U'; IO1L : INOUT std_logic := 'U'; IO2L : INOUT std_logic := 'U'; IO3L : INOUT std_logic := 'U'; IO4L : INOUT std_logic := 'U'; IO5L : INOUT std_logic := 'U'; IO6L : INOUT std_logic := 'U'; IO7L : INOUT std_logic := 'U'; IO8L : INOUT std_logic := 'U'; IO9L : INOUT std_logic := 'U'; IO10L : INOUT std_logic := 'U'; IO11L : INOUT std_logic := 'U'; IO12L : INOUT std_logic := 'U'; IO13L : INOUT std_logic := 'U'; IO14L : INOUT std_logic := 'U'; IO15L : INOUT std_logic := 'U'; IO16L : INOUT std_logic := 'U'; IO17L : INOUT std_logic := 'U'; --Left port control CE0NegL : IN std_logic := 'U'; CE1L : IN std_logic := 'U'; OENegL : IN std_logic := 'U'; RWL : IN std_logic := 'U'; CLKL : IN std_logic := 'U'; PLNegL : IN std_logic := 'U'; ADSNegL : IN std_logic := 'U'; CNTENNegL : IN std_logic := 'U'; REPEATNegL : IN std_logic := 'U'; UBNegL : IN std_logic := 'U'; LBNegL : IN std_logic := 'U'; ZZL : IN std_logic := 'U'; --Left port outputs INTNegL : OUT std_logic := 'U'; --INterrupt COLNegL : OUT std_logic := 'U'; --Collision Alert --Right port Address lines A0R : IN std_logic := 'U'; A1R : IN std_logic := 'U'; A2R : IN std_logic := 'U'; A3R : IN std_logic := 'U'; A4R : IN std_logic := 'U'; A5R : IN std_logic := 'U'; A6R : IN std_logic := 'U'; A7R : IN std_logic := 'U'; A8R : IN std_logic := 'U'; A9R : IN std_logic := 'U'; A10R : IN std_logic := 'U'; A11R : IN std_logic := 'U'; A12R : IN std_logic := 'U'; A13R : IN std_logic := 'U'; A14R : IN std_logic := 'U'; A15R : IN std_logic := 'U'; A16R : IN std_logic := 'U'; A17R : IN std_logic := 'U'; --Right port IO lines IO0R : INOUT std_logic := 'U'; IO1R : INOUT std_logic := 'U'; IO2R : INOUT std_logic := 'U'; IO3R : INOUT std_logic := 'U'; IO4R : INOUT std_logic := 'U'; IO5R : INOUT std_logic := 'U'; IO6R : INOUT std_logic := 'U'; IO7R : INOUT std_logic := 'U'; IO8R : INOUT std_logic := 'U'; IO9R : INOUT std_logic := 'U'; IO10R : INOUT std_logic := 'U'; IO11R : INOUT std_logic := 'U'; IO12R : INOUT std_logic := 'U'; IO13R : INOUT std_logic := 'U'; IO14R : INOUT std_logic := 'U'; IO15R : INOUT std_logic := 'U'; IO16R : INOUT std_logic := 'U'; IO17R : INOUT std_logic := 'U'; --Right port controml lines CE0NegR : IN std_logic := 'U'; CE1R : IN std_logic := 'U'; OENegR : IN std_logic := 'U'; RWR : IN std_logic := 'U'; CLKR : IN std_logic := 'U'; PLNegR : IN std_logic := 'U'; ADSNegR : IN std_logic := 'U'; CNTENNegR : IN std_logic := 'U'; REPEATNegR : IN std_logic := 'U'; UBNegR : IN std_logic := 'U'; LBNegR : IN std_logic := 'U'; ZZR : IN std_logic := 'U'; --Right port outputs INTNegR : OUT std_logic := 'U'; --INterrupt COLNegR : OUT std_logic := 'U' --Collision Alert ); ATTRIBUTE VITAL_LEVEL0 of idt70t3319dd : ENTITY IS TRUE; END idt70t3319dd; ------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION ------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt70t3319dd IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "idt70t3319dd"; CONSTANT HiAddrBit : NATURAL := 17; CONSTANT MaxData : NATURAL := 511; CONSTANT MemSize : NATURAL := (2**(HiAddrBit+1))-1;--0x3FFFF=256K CONSTANT MailBoxL : NATURAL := MemSize-1; CONSTANT MailBoxR : NATURAL := MemSize; SIGNAL A0L_ipd : std_ulogic := 'U'; SIGNAL A1L_ipd : std_ulogic := 'U'; SIGNAL A2L_ipd : std_ulogic := 'U'; SIGNAL A3L_ipd : std_ulogic := 'U'; SIGNAL A4L_ipd : std_ulogic := 'U'; SIGNAL A5L_ipd : std_ulogic := 'U'; SIGNAL A6L_ipd : std_ulogic := 'U'; SIGNAL A7L_ipd : std_ulogic := 'U'; SIGNAL A8L_ipd : std_ulogic := 'U'; SIGNAL A9L_ipd : std_ulogic := 'U'; SIGNAL A10L_ipd : std_ulogic := 'U'; SIGNAL A11L_ipd : std_ulogic := 'U'; SIGNAL A12L_ipd : std_ulogic := 'U'; SIGNAL A13L_ipd : std_ulogic := 'U'; SIGNAL A14L_ipd : std_ulogic := 'U'; SIGNAL A15L_ipd : std_ulogic := 'U'; SIGNAL A16L_ipd : std_ulogic := 'U'; SIGNAL A17L_ipd : std_ulogic := 'U'; --Left port IO lines SIGNAL IO0L_ipd : std_ulogic := 'U'; SIGNAL IO1L_ipd : std_ulogic := 'U'; SIGNAL IO2L_ipd : std_ulogic := 'U'; SIGNAL IO3L_ipd : std_ulogic := 'U'; SIGNAL IO4L_ipd : std_ulogic := 'U'; SIGNAL IO5L_ipd : std_ulogic := 'U'; SIGNAL IO6L_ipd : std_ulogic := 'U'; SIGNAL IO7L_ipd : std_ulogic := 'U'; SIGNAL IO8L_ipd : std_ulogic := 'U'; SIGNAL IO9L_ipd : std_ulogic := 'U'; SIGNAL IO10L_ipd : std_ulogic := 'U'; SIGNAL IO11L_ipd : std_ulogic := 'U'; SIGNAL IO12L_ipd : std_ulogic := 'U'; SIGNAL IO13L_ipd : std_ulogic := 'U'; SIGNAL IO14L_ipd : std_ulogic := 'U'; SIGNAL IO15L_ipd : std_ulogic := 'U'; SIGNAL IO16L_ipd : std_ulogic := 'U'; SIGNAL IO17L_ipd : std_ulogic := 'U'; --Left port control SIGNAL CE0NegL_ipd : std_ulogic := 'U'; SIGNAL CE1L_ipd : std_ulogic := 'U'; SIGNAL OENegL_ipd : std_ulogic := 'U'; SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL CLKL_ipd : std_ulogic := 'U'; SIGNAL PLNegL_ipd : std_ulogic := 'U'; SIGNAL ADSNegL_ipd : std_ulogic := 'U'; SIGNAL CNTENNegL_ipd : std_ulogic := 'U'; SIGNAL REPEATNegL_ipd : std_ulogic := 'U'; SIGNAL UBNegL_ipd : std_ulogic := 'U'; SIGNAL LBNegL_ipd : std_ulogic := 'U'; SIGNAL ZZL_ipd : std_ulogic := 'U'; --Right port Address lines SIGNAL A0R_ipd : std_ulogic := 'U'; SIGNAL A1R_ipd : std_ulogic := 'U'; SIGNAL A2R_ipd : std_ulogic := 'U'; SIGNAL A3R_ipd : std_ulogic := 'U'; SIGNAL A4R_ipd : std_ulogic := 'U'; SIGNAL A5R_ipd : std_ulogic := 'U'; SIGNAL A6R_ipd : std_ulogic := 'U'; SIGNAL A7R_ipd : std_ulogic := 'U'; SIGNAL A8R_ipd : std_ulogic := 'U'; SIGNAL A9R_ipd : std_ulogic := 'U'; SIGNAL A10R_ipd : std_ulogic := 'U'; SIGNAL A11R_ipd : std_ulogic := 'U'; SIGNAL A12R_ipd : std_ulogic := 'U'; SIGNAL A13R_ipd : std_ulogic := 'U'; SIGNAL A14R_ipd : std_ulogic := 'U'; SIGNAL A15R_ipd : std_ulogic := 'U'; SIGNAL A16R_ipd : std_ulogic := 'U'; SIGNAL A17R_ipd : std_ulogic := 'U'; --Right port IO lines SIGNAL IO0R_ipd : std_ulogic := 'U'; SIGNAL IO1R_ipd : std_ulogic := 'U'; SIGNAL IO2R_ipd : std_ulogic := 'U'; SIGNAL IO3R_ipd : std_ulogic := 'U'; SIGNAL IO4R_ipd : std_ulogic := 'U'; SIGNAL IO5R_ipd : std_ulogic := 'U'; SIGNAL IO6R_ipd : std_ulogic := 'U'; SIGNAL IO7R_ipd : std_ulogic := 'U'; SIGNAL IO8R_ipd : std_ulogic := 'U'; SIGNAL IO9R_ipd : std_ulogic := 'U'; SIGNAL IO10R_ipd : std_ulogic := 'U'; SIGNAL IO11R_ipd : std_ulogic := 'U'; SIGNAL IO12R_ipd : std_ulogic := 'U'; SIGNAL IO13R_ipd : std_ulogic := 'U'; SIGNAL IO14R_ipd : std_ulogic := 'U'; SIGNAL IO15R_ipd : std_ulogic := 'U'; SIGNAL IO16R_ipd : std_ulogic := 'U'; SIGNAL IO17R_ipd : std_ulogic := 'U'; --Right port controml lines SIGNAL CE0NegR_ipd : std_ulogic := 'U'; SIGNAL CE1R_ipd : std_ulogic := 'U'; SIGNAL OENegR_ipd : std_ulogic := 'U'; SIGNAL RWR_ipd : std_ulogic := 'U'; SIGNAL CLKR_ipd : std_ulogic := 'U'; SIGNAL PLNegR_ipd : std_ulogic := 'U'; SIGNAL ADSNegR_ipd : std_ulogic := 'U'; SIGNAL CNTENNegR_ipd : std_ulogic := 'U'; SIGNAL REPEATNegR_ipd : std_ulogic := 'U'; SIGNAL UBNegR_ipd : std_ulogic := 'U'; SIGNAL LBNegR_ipd : std_ulogic := 'U'; SIGNAL ZZR_ipd : std_ulogic := 'U'; SIGNAL left_in : std_ulogic := '0'; SIGNAL left : std_ulogic := '0'; SIGNAL right_in : std_ulogic := '0'; SIGNAL right : std_ulogic := '0'; BEGIN --------------------------------------------------------------------------- -- Internal Delays --------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays TCCS : VitalBuf (left , left_in , (VitalZeroDelay,tdevice_TCO)); --left TCCS1: VitalBuf (right, right_in, (VitalZeroDelay,tdevice_TCO)); --right --------------------------------------------------------------------------- -- Wire Delays --------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (OENegL_ipd , OENegL , tipd_OENegL ); w_2 : VitalWireDelay (A0L_ipd , A0L , tipd_A0L ); w_3 : VitalWireDelay (A1L_ipd , A1L , tipd_A1L ); w_4 : VitalWireDelay (A2L_ipd , A2L , tipd_A2L ); w_5 : VitalWireDelay (A3L_ipd , A3L , tipd_A3L ); w_6 : VitalWireDelay (A4L_ipd , A4L , tipd_A4L ); w_7 : VitalWireDelay (A5L_ipd , A5L , tipd_A5L ); w_8 : VitalWireDelay (A6L_ipd , A6L , tipd_A6L ); w_9 : VitalWireDelay (A7L_ipd , A7L , tipd_A7L ); w_10 : VitalWireDelay (A8L_ipd , A8L , tipd_A8L ); w_11 : VitalWireDelay (A9L_ipd , A9L , tipd_A9L ); w_12 : VitalWireDelay (A10L_ipd , A10L , tipd_A10L ); w_13 : VitalWireDelay (A11L_ipd , A11L , tipd_A11L ); w_14 : VitalWireDelay (A12L_ipd , A12L , tipd_A12L ); w_15 : VitalWireDelay (A13L_ipd , A13L , tipd_A13L ); w_16 : VitalWireDelay (A14L_ipd , A14L , tipd_A14L ); w_17 : VitalWireDelay (A15L_ipd , A15L , tipd_A15L ); w_18 : VitalWireDelay (A16L_ipd , A16L , tipd_A16L ); w_19 : VitalWireDelay (A17L_ipd , A17L , tipd_A17L ); w_20 : VitalWireDelay (IO0L_ipd , IO0L , tipd_IO0L ); w_21 : VitalWireDelay (IO1L_ipd , IO1L , tipd_IO1L ); w_22 : VitalWireDelay (IO2L_ipd , IO2L , tipd_IO2L ); w_23 : VitalWireDelay (IO3L_ipd , IO3L , tipd_IO3L ); w_24 : VitalWireDelay (IO4L_ipd , IO4L , tipd_IO4L ); w_25 : VitalWireDelay (IO5L_ipd , IO5L , tipd_IO5L ); w_26 : VitalWireDelay (IO6L_ipd , IO6L , tipd_IO6L ); w_27 : VitalWireDelay (IO7L_ipd , IO7L , tipd_IO7L ); w_28 : VitalWireDelay (IO8L_ipd , IO8L , tipd_IO8L ); w_29 : VitalWireDelay (IO9L_ipd , IO9L , tipd_IO9L ); w_30 : VitalWireDelay (IO10L_ipd , IO10L , tipd_IO10L); w_31 : VitalWireDelay (IO11L_ipd , IO11L , tipd_IO11L); w_32 : VitalWireDelay (IO12L_ipd , IO12L , tipd_IO12L); w_33 : VitalWireDelay (IO13L_ipd , IO13L , tipd_IO13L); w_34 : VitalWireDelay (IO14L_ipd , IO14L , tipd_IO14L); w_35 : VitalWireDelay (IO15L_ipd , IO15L , tipd_IO15L); w_36 : VitalWireDelay (IO16L_ipd , IO16L , tipd_IO16L); w_37 : VitalWireDelay (IO17L_ipd , IO17L , tipd_IO17L); w_56 : VitalWireDelay (CE0NegL_ipd , CE0NegL , tipd_CE0NegL ); w_57 : VitalWireDelay (CE1L_ipd , CE1L , tipd_CE1L ); w_58 : VitalWireDelay (RWL_ipd , RWL , tipd_RWL ); w_59 : VitalWireDelay (CLKL_ipd , CLKL , tipd_CLKL ); w_60 : VitalWireDelay (ADSNegL_ipd , ADSNegL , tipd_ADSNegL ); w_61 : VitalWireDelay (CNTENNegL_ipd , CNTENNegL , tipd_CNTENNegL ); w_62 : VitalWireDelay (REPEATNegL_ipd, REPEATNegL, tipd_REPEATNegL); w_65 : VitalWireDelay (UBNegL_ipd , UBNegL , tipd_UBNegL ); w_66 : VitalWireDelay (LBNegL_ipd , LBNegL , tipd_LBNegL ); w_67 : VitalWireDelay (ZZL_ipd , ZZL , tipd_ZZL ); w_68 : VitalWireDelay (A0R_ipd , A0R , tipd_A0R ); w_69 : VitalWireDelay (A1R_ipd , A1R , tipd_A1R ); w_70 : VitalWireDelay (A2R_ipd , A2R , tipd_A2R ); w_71 : VitalWireDelay (A3R_ipd , A3R , tipd_A3R ); w_72 : VitalWireDelay (A4R_ipd , A4R , tipd_A4R ); w_73 : VitalWireDelay (A5R_ipd , A5R , tipd_A5R ); w_74 : VitalWireDelay (A6R_ipd , A6R , tipd_A6R ); w_75 : VitalWireDelay (A7R_ipd , A7R , tipd_A7R ); w_76 : VitalWireDelay (A8R_ipd , A8R , tipd_A8R ); w_77 : VitalWireDelay (A9R_ipd , A9R , tipd_A9R ); w_78 : VitalWireDelay (A10R_ipd , A10R , tipd_A10R); w_79 : VitalWireDelay (A11R_ipd , A11R , tipd_A11R); w_80 : VitalWireDelay (A12R_ipd , A12R , tipd_A12R); w_81 : VitalWireDelay (A13R_ipd , A13R , tipd_A13R); w_82 : VitalWireDelay (A14R_ipd , A14R , tipd_A14R); w_83 : VitalWireDelay (A15R_ipd , A15R , tipd_A15R); w_84 : VitalWireDelay (A16R_ipd , A16R , tipd_A16R); w_85 : VitalWireDelay (A17R_ipd , A17R , tipd_A17R); w_86 : VitalWireDelay (IO0R_ipd , IO0R , tipd_IO0R); w_87 : VitalWireDelay (IO1R_ipd , IO1R , tipd_IO1R); w_88 : VitalWireDelay (IO2R_ipd , IO2R , tipd_IO2R); w_89 : VitalWireDelay (IO3R_ipd , IO3R , tipd_IO3R); w_90 : VitalWireDelay (IO4R_ipd , IO4R , tipd_IO4R); w_91 : VitalWireDelay (IO5R_ipd , IO5R , tipd_IO5R); w_92 : VitalWireDelay (IO6R_ipd , IO6R , tipd_IO6R ); w_93 : VitalWireDelay (IO7R_ipd , IO7R , tipd_IO7R ); w_94 : VitalWireDelay (IO8R_ipd , IO8R , tipd_IO8R ); w_95 : VitalWireDelay (IO9R_ipd , IO9R , tipd_IO9R ); w_96 : VitalWireDelay (IO10R_ipd , IO10R , tipd_IO10R); w_97 : VitalWireDelay (IO11R_ipd , IO11R , tipd_IO11R); w_98 : VitalWireDelay (IO12R_ipd , IO12R , tipd_IO12R); w_99 : VitalWireDelay (IO13R_ipd , IO13R , tipd_IO13R); w_100 : VitalWireDelay (IO14R_ipd , IO14R , tipd_IO14R); w_101 : VitalWireDelay (IO15R_ipd , IO15R , tipd_IO15R); w_102 : VitalWireDelay (IO16R_ipd , IO16R , tipd_IO16R); w_103 : VitalWireDelay (IO17R_ipd , IO17R , tipd_IO17R); w_123 : VitalWireDelay (CE0NegR_ipd , CE0NegR , tipd_CE0NegR); w_124 : VitalWireDelay (CE1R_ipd , CE1R , tipd_CE1R ); w_125 : VitalWireDelay (RWR_ipd , RWR , tipd_RWR ); w_126 : VitalWireDelay (CLKR_ipd , CLKR , tipd_CLKR ); w_127 : VitalWireDelay (ADSNegR_ipd , ADSNegR , tipd_ADSNegR); w_128 : VitalWireDelay (CNTENNegR_ipd , CNTENNegR , tipd_CNTENNegR); w_129 : VitalWireDelay (REPEATNegR_ipd, REPEATNegR, tipd_REPEATNegR); w_132 : VitalWireDelay (UBNegR_ipd , UBNegR , tipd_UBNegR); w_133 : VitalWireDelay (LBNegR_ipd , LBNegR , tipd_LBNegR); w_134 : VitalWireDelay (ZZR_ipd , ZZR , tipd_ZZR ); w_139 : VitalWireDelay (OENegR_ipd , OENegR , tipd_OENegR ); w_140 : VitalWireDelay (PLNegL_ipd , PLNegL , tipd_PLNegL ); w_141 : VitalWireDelay (PLNegR_ipd , PLNegR , tipd_PLNegR ); END BLOCK; --------------------------------------------------------------------------- -- Main Behavior Block --------------------------------------------------------------------------- Behavior: BLOCK PORT ( AddressL : IN std_logic_vector(HiAddrBit downto 0); DataInL : IN std_logic_vector(17 downto 0); DataOutL : OUT std_logic_vector(17 downto 0); RWL : IN std_logic; CEL : IN std_logic_vector(1 downto 0); OEL : IN std_logic; ClockL : IN std_logic; PLNegL : IN std_logic; ADSNegL : IN std_logic; CNTENNegL : IN std_logic; REPEATNegL : IN std_logic; BENegL : IN std_logic_vector(1 downto 0); ZZL : IN std_logic; INTNegL : OUT std_logic; COLNegL : OUT std_logic; AddressR : IN std_logic_vector(HiAddrBit downto 0); DataInR : IN std_logic_vector(17 downto 0); DataOutR : OUT std_logic_vector(17 downto 0); RWR : IN std_logic; CER : IN std_logic_vector(1 downto 0); OER : IN std_logic; ClockR : IN std_logic; PLNegR : IN std_logic; ADSNegR : IN std_logic; CNTENNegR : IN std_logic; REPEATNegR : IN std_logic; BENegR : IN std_logic_vector(1 downto 0); ZZR : IN std_logic; INTNegR : OUT std_logic; COLNegR : OUT std_logic ); PORT MAP ( AddressL(0 ) => A0L_ipd , AddressL(1 ) => A1L_ipd , AddressL(2 ) => A2L_ipd , AddressL(3 ) => A3L_ipd , AddressL(4 ) => A4L_ipd , AddressL(5 ) => A5L_ipd , AddressL(6 ) => A6L_ipd , AddressL(7 ) => A7L_ipd , AddressL(8 ) => A8L_ipd , AddressL(9 ) => A9L_ipd , AddressL(10) => A10L_ipd , AddressL(11) => A11L_ipd , AddressL(12) => A12L_ipd , AddressL(13) => A13L_ipd , AddressL(14) => A14L_ipd , AddressL(15) => A15L_ipd , AddressL(16) => A16L_ipd , AddressL(17) => A17L_ipd , DataInL(0 ) => IO0L_ipd , DataInL(1 ) => IO1L_ipd , DataInL(2 ) => IO2L_ipd , DataInL(3 ) => IO3L_ipd , DataInL(4 ) => IO4L_ipd , DataInL(5 ) => IO5L_ipd , DataInL(6 ) => IO6L_ipd , DataInL(7 ) => IO7L_ipd , DataInL(8 ) => IO8L_ipd , DataInL(9 ) => IO9L_ipd , DataInL(10) => IO10L_ipd , DataInL(11) => IO11L_ipd , DataInL(12) => IO12L_ipd , DataInL(13) => IO13L_ipd , DataInL(14) => IO14L_ipd , DataInL(15) => IO15L_ipd , DataInL(16) => IO16L_ipd , DataInL(17) => IO17L_ipd , DataOutL(0 ) => IO0L , DataOutL(1 ) => IO1L , DataOutL(2 ) => IO2L , DataOutL(3 ) => IO3L , DataOutL(4 ) => IO4L , DataOutL(5 ) => IO5L , DataOutL(6 ) => IO6L , DataOutL(7 ) => IO7L , DataOutL(8 ) => IO8L , DataOutL(9 ) => IO9L , DataOutL(10) => IO10L , DataOutL(11) => IO11L , DataOutL(12) => IO12L , DataOutL(13) => IO13L , DataOutL(14) => IO14L , DataOutL(15) => IO15L , DataOutL(16) => IO16L , DataOutL(17) => IO17L , RWL => RWL_ipd , CEL(0) => CE0NegL_ipd , CEL(1) => CE1L_ipd , OEL => OENegL_ipd , ClockL => CLKL_ipd , CNTENNegL => CNTENNegL_ipd , PLNegL => PLNegL_ipd , ADSNegL => ADSNegL_ipd , REPEATNegL => REPEATNegL_ipd, BENegL(1) => UBNegL_ipd , BENegL(0) => LBNegL_ipd , ZZL => ZZL_ipd , INTNegL => INTNegL , COLNegL => COLNegL , AddressR(0 ) => A0R_ipd , AddressR(1 ) => A1R_ipd , AddressR(2 ) => A2R_ipd , AddressR(3 ) => A3R_ipd , AddressR(4 ) => A4R_ipd , AddressR(5 ) => A5R_ipd , AddressR(6 ) => A6R_ipd , AddressR(7 ) => A7R_ipd , AddressR(8 ) => A8R_ipd , AddressR(9 ) => A9R_ipd , AddressR(10) => A10R_ipd , AddressR(11) => A11R_ipd , AddressR(12) => A12R_ipd , AddressR(13) => A13R_ipd , AddressR(14) => A14R_ipd , AddressR(15) => A15R_ipd , AddressR(16) => A16R_ipd , AddressR(17) => A17R_ipd , DataInR(0 ) => IO0R_ipd , DataInR(1 ) => IO1R_ipd , DataInR(2 ) => IO2R_ipd , DataInR(3 ) => IO3R_ipd , DataInR(4 ) => IO4R_ipd , DataInR(5 ) => IO5R_ipd , DataInR(6 ) => IO6R_ipd , DataInR(7 ) => IO7R_ipd , DataInR(8 ) => IO8R_ipd , DataInR(9 ) => IO9R_ipd , DataInR(10) => IO10R_ipd , DataInR(11) => IO11R_ipd , DataInR(12) => IO12R_ipd , DataInR(13) => IO13R_ipd , DataInR(14) => IO14R_ipd , DataInR(15) => IO15R_ipd , DataInR(16) => IO16R_ipd , DataInR(17) => IO17R_ipd , DataOutR(0 ) => IO0R , DataOutR(1 ) => IO1R , DataOutR(2 ) => IO2R , DataOutR(3 ) => IO3R , DataOutR(4 ) => IO4R , DataOutR(5 ) => IO5R , DataOutR(6 ) => IO6R , DataOutR(7 ) => IO7R , DataOutR(8 ) => IO8R , DataOutR(9 ) => IO9R , DataOutR(10) => IO10R , DataOutR(11) => IO11R , DataOutR(12) => IO12R , DataOutR(13) => IO13R , DataOutR(14) => IO14R , DataOutR(15) => IO15R , DataOutR(16) => IO16R , DataOutR(17) => IO17R , RWR => RWR_ipd , CER(0) => CE0NegR_ipd , CER(1) => CE1R_ipd , OER => OENegR_ipd , ClockR => CLKR_ipd , CNTENNegR => CNTENNegR_ipd , PLNegR => PLNegR_ipd , ADSNegR => ADSNegR_ipd , REPEATNegR => REPEATNegR_ipd, BENegR(1) => UBNegR_ipd , BENegR(0) => LBNegR_ipd , ZZR => ZZR_ipd , INTNegR => INTNegR , COLNegR => COLNegR ); SIGNAL DOL_zd : std_logic_vector(17 downto 0); SIGNAL DOR_zd : std_logic_vector(17 downto 0); SIGNAL Viol : X01 := '0'; BEGIN ------------------------------------------------------------------------------- -- Timing Check ------------------------------------------------------------------------------- TimingCheckP: PROCESS(AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL, ADSNegL, CNTENNegL, REPEATNegL, BENegL, AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR, ADSNegR, CNTENNegR, REPEATNegR, UBNegR, LBNegR) -- VARIABLE VARIABLE Violation : X01 := '0'; VARIABLE TD_AL_CLK : VitalTimingDataType; VARIABLE Tviol_AL_CLK : X01 := '0'; VARIABLE TD_AR_CLK : VitalTimingDataType; VARIABLE Tviol_AR_CLK : X01 := '0'; VARIABLE TD_DL_CLK : VitalTimingDataType; VARIABLE Tviol_DL_CLK : X01 := '0'; VARIABLE TD_DR_CLK : VitalTimingDataType; VARIABLE Tviol_DR_CLK : X01 := '0'; VARIABLE TD_CEL_CLK : VitalTimingDataType; VARIABLE Tviol_CEL_CLK : X01 := '0'; VARIABLE TD_CER_CLK : VitalTimingDataType; VARIABLE Tviol_CER_CLK : X01 := '0'; VARIABLE TD_UBEL_CLK : VitalTimingDataType; VARIABLE Tviol_UBEL_CLK : X01 := '0'; VARIABLE TD_LBEL_CLK : VitalTimingDataType; VARIABLE Tviol_LBEL_CLK : X01 := '0'; VARIABLE TD_UBER_CLK : VitalTimingDataType; VARIABLE Tviol_UBER_CLK : X01 := '0'; VARIABLE TD_LBER_CLK : VitalTimingDataType; VARIABLE Tviol_LBER_CLK : X01 := '0'; VARIABLE TD_RWL_CLK : VitalTimingDataType; VARIABLE Tviol_RWL_CLK : X01 := '0'; VARIABLE TD_RWR_CLK : VitalTimingDataType; VARIABLE Tviol_RWR_CLK : X01 := '0'; VARIABLE TD_ADSL_CLK : VitalTimingDataType; VARIABLE Tviol_ADSL_CLK : X01 := '0'; VARIABLE TD_ADSR_CLK : VitalTimingDataType; VARIABLE Tviol_ADSR_CLK : X01 := '0'; VARIABLE TD_CNTL_CLK : VitalTimingDataType; VARIABLE Tviol_CNTL_CLK : X01 := '0'; VARIABLE TD_CNTR_CLK : VitalTimingDataType; VARIABLE Tviol_CNTR_CLK : X01 := '0'; VARIABLE TD_RPTL_CLK : VitalTimingDataType; VARIABLE Tviol_RPTL_CLK : X01 := '0'; VARIABLE TD_RPTR_CLK : VitalTimingDataType; VARIABLE Tviol_RPTR_CLK : X01 := '0'; VARIABLE TD_TDI_TCK : VitalTimingDataType; VARIABLE Tviol_TDI_TCK : X01 := '0'; VARIABLE PD_CLKP : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP : X01 := '0'; VARIABLE PD_CLKF : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKF : X01 := '0'; VARIABLE PD_CLKP1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKP1 : X01 := '0'; VARIABLE PD_CLKF1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKF1 : X01 := '0'; VARIABLE PD_TCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_TCK : X01 := '0'; VARIABLE PD_TRST : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_TRST : X01 := '0'; BEGIN IF TimingChecksOn THEN VitalSetupHoldCheck ( TestSignal => AddressL, TestSignalName => "Left Address", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AL_CLK ); VitalSetupHoldCheck ( TestSignal => AddressR, TestSignalName => "Right Address", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AR_CLK ); VitalSetupHoldCheck ( TestSignal => DataInL, TestSignalName => "Left Data", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DL_CLK ); VitalSetupHoldCheck ( TestSignal => DataInR, TestSignalName => "Right Data", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DR_CLK ); VitalSetupHoldCheck ( TestSignal => CEL, TestSignalName => "CE Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CEL_CLK ); VitalSetupHoldCheck ( TestSignal => CER, TestSignalName => "CE Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CER_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CER_CLK ); VitalSetupHoldCheck ( TestSignal => BENegL(1), TestSignalName => "UB Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UBEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UBEL_CLK ); VitalSetupHoldCheck ( TestSignal => BENegL(0), TestSignalName => "LB Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LBEL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LBEL_CLK ); VitalSetupHoldCheck ( TestSignal => BENegR(1), TestSignalName => "UB Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_UBER_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_UBER_CLK ); VitalSetupHoldCheck ( TestSignal => BENegR(0), TestSignalName => "LB Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LBER_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LBER_CLK ); VitalSetupHoldCheck ( TestSignal => RWL, TestSignalName => "R/W Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWL_CLK ); VitalSetupHoldCheck ( TestSignal => RWR, TestSignalName => "R/W Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWR_CLK ); VitalSetupHoldCheck ( TestSignal => ADSNegL, TestSignalName => "ADS Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSL_CLK ); VitalSetupHoldCheck ( TestSignal => ADSNegR, TestSignalName => "ADS Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSR_CLK ); VitalSetupHoldCheck ( TestSignal => CNTENNegL, TestSignalName => "CntEn Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTL_CLK ); VitalSetupHoldCheck ( TestSignal => CNTENNegR, TestSignalName => "CntEn Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTR_CLK ); VitalSetupHoldCheck ( TestSignal => REPEATNegL, TestSignalName => "REPEAT Left", RefSignal => ClockL, RefSignalName => "ClockL", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RPTL_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RPTL_CLK ); VitalSetupHoldCheck ( TestSignal => REPEATNegR, TestSignalName => "REPEAT Right", RefSignal => ClockR, RefSignalName => "ClockR", SetupHigh => tsetup_A0L_CLKL, SetupLow => tsetup_A0L_CLKL, HoldHigh => thold_A0L_CLKL, HoldLow => thold_A0L_CLKL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RPTR_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RPTR_CLK ); VitalPeriodPulseCheck ( TestSignal => ClockL, TestSignalName => "Left Clock", Period => tperiod_CLKL, PulseWidthLow => tpw_CLKL_negedge, PulseWidthHigh => tpw_CLKL_posedge, PeriodData => PD_CLKP, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP, HeaderMsg => InstancePath & PartID, CheckEnabled => PLNegL='1' ); VitalPeriodPulseCheck ( TestSignal => ClockL, TestSignalName => "Left Clock", Period => tperiod_CLKR, PulseWidthLow => tpw_CLKR_negedge, PulseWidthHigh => tpw_CLKR_posedge, PeriodData => PD_CLKF, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKF, HeaderMsg => InstancePath & PartID, CheckEnabled => PLNegL='0' ); VitalPeriodPulseCheck ( TestSignal => ClockR, TestSignalName => "Right Clock", Period => tperiod_CLKL, PulseWidthLow => tpw_CLKL_negedge, PulseWidthHigh => tpw_CLKL_posedge, PeriodData => PD_CLKP1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKP1, HeaderMsg => InstancePath & PartID, CheckEnabled => PLNegL='1' ); VitalPeriodPulseCheck ( TestSignal => ClockL, TestSignalName => "Left Clock", Period => tperiod_CLKR, PulseWidthLow => tpw_CLKR_negedge, PulseWidthHigh => tpw_CLKR_posedge, PeriodData => PD_CLKF1, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLKF1, HeaderMsg => InstancePath & PartID, CheckEnabled => PLNegL='0' ); Violation := Tviol_AL_CLK OR Tviol_AR_CLK OR Tviol_DL_CLK OR Tviol_DR_CLK OR Tviol_CEL_CLK OR Tviol_CER_CLK OR Tviol_UBEL_CLK OR Tviol_UBER_CLK OR Tviol_RWL_CLK OR Tviol_RWR_CLK OR Tviol_ADSL_CLK OR Tviol_ADSR_CLK OR Tviol_CNTL_CLK OR Tviol_CNTR_CLK OR Tviol_RPTL_CLK OR Tviol_RPTR_CLK OR Pviol_CLKP OR Pviol_CLKF OR Pviol_CLKP1 OR Pviol_CLKF1 OR Tviol_LBEL_CLK OR Tviol_LBER_CLK; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS TimingCheckP; --------------------------------------------------------------------------- -- register input data for left port --------------------------------------------------------------------------- BothPort : PROCESS (AddressL, DataInL, RWL, CEL, OEL, ClockL, PLNegL, ADSNegL, CNTENNegL, REPEATNegL, BENegL, ZZL, AddressR, DataInR, RWR, CER, OER, ClockR, PLNegR, ADSNegR, CNTENNegR, REPEATNegR, UBNegR, LBNegR, ZZR) FILE mem_file : text is mem_file_name; VARIABLE ind : NATURAL RANGE 0 TO MemSize := 0; VARIABLE buf : line; VARIABLE L_cntS, L_cntR : NATURAL RANGE 0 TO 4 := 0; VARIABLE R_cntS, R_cntR : NATURAL RANGE 0 TO 4 := 0; VARIABLE L_BE_reg1, L_BE_reg2 : std_logic_vector(1 downto 0) := "00"; VARIABLE L_BE_out, L_BE_mux : std_logic_vector(1 downto 0) := "00"; VARIABLE L_CE_reg1, L_CE_reg2 : std_logic := '0'; VARIABLE L_CE_mux : std_logic := '0'; VARIABLE L_DOut_reg, L_D_mux: std_logic_vector(17 downto 0); VARIABLE L_RW_reg : std_logic := '0'; VARIABLE Addr_reg_L : NATURAL RANGE 0 TO MemSize := 0; VARIABLE R_BE_reg1, R_BE_reg2 : std_logic_vector(1 downto 0) := "00"; VARIABLE R_BE_out, R_BE_mux : std_logic_vector(1 downto 0) := "00"; VARIABLE R_CE_reg1, R_CE_reg2 : std_logic := '0'; VARIABLE R_CE_mux : std_logic := '0'; VARIABLE R_DOut_reg, R_D_mux : std_logic_vector(17 downto 0); VARIABLE R_RW_reg : std_logic := '0'; VARIABLE Addr_reg_R : NATURAL RANGE 0 TO MemSize := 0; VARIABLE CollisionL : boolean := FALSE; VARIABLE CollisionR : boolean := FALSE; TYPE mem_state IS ( desel, -- port not selected read, -- read from port write, -- write to port collision); -- memory collision VARIABLE L_state : mem_state; VARIABLE Addr_L : NATURAL RANGE 0 TO MemSize := 0; VARIABLE R_state : mem_state; VARIABLE Addr_R : NATURAL RANGE 0 TO MemSize := 0; --registers VARIABLE ColL_pipe1 : std_logic := '1'; VARIABLE ColL_pipe2 : std_logic := '1'; VARIABLE ColL_zd : std_logic; VARIABLE ColR_pipe1 : std_logic := '1'; VARIABLE ColR_pipe2 : std_logic := '1'; VARIABLE ColR_zd : std_logic; VARIABLE Linterrupt : std_logic := '1'; VARIABLE Rinterrupt : std_logic := '1'; VARIABLE ColL_GlitchData : VitalGlitchDataType; VARIABLE ColR_GlitchData : VitalGlitchDataType; VARIABLE IntL_GlitchData : VitalGlitchDataType; VARIABLE IntR_GlitchData : VitalGlitchDataType; -- Memory array declaration TYPE mem_type IS ARRAY(0 to MemSize) OF INTEGER RANGE -2 TO MaxData; VARIABLE MemDatA : mem_type := (OTHERS => -2); --(17 : 9) VARIABLE MemDatB : mem_type := (OTHERS => -2); --(8 : 0) VARIABLE int_ZZL : std_logic := '0'; VARIABLE int_ZZR : std_logic := '0'; VARIABLE DataOutL_zd : std_logic_vector(17 downto 0); VARIABLE DataOutR_zd : std_logic_vector(17 downto 0); VARIABLE DL_out : std_logic_vector(17 downto 0); VARIABLE DL_in : std_logic_vector(17 downto 0); VARIABLE BEL_in : std_logic_vector(1 downto 0); VARIABLE CEL_reg : std_logic; VARIABLE RWL_reg : std_logic; VARIABLE DR_out : std_logic_vector(17 downto 0); VARIABLE DR_in : std_logic_vector(17 downto 0); VARIABLE BER_in : std_logic_vector(1 downto 0); VARIABLE CER_reg : std_logic; VARIABLE RWR_reg : std_logic; BEGIN --left sleep ctrl IF rising_edge(ClockL) THEN IF ZZL='1' THEN IF L_cntS < 3 THEN L_cntS := L_cntS +1; L_cntR := 0; ELSE int_ZZL := '1'; END IF; ELSE IF L_cntR < 4 THEN L_cntR := L_cntR +1; L_cntS := 0; ELSE int_ZZL := '0'; END IF; END IF; END IF; --right sleep ctrl IF rising_edge(ClockR) THEN IF ZZR='1' THEN IF R_cntS < 3 THEN R_cntS := R_cntS +1; R_cntR := 0; ELSE int_ZZR := '1'; END IF; ELSE IF R_cntR < 4 THEN R_cntR := R_cntR +1; R_cntS := 0; ELSE int_ZZR := '0'; END IF; END IF; END IF; --left PL/F selection IF rising_edge(ClockL) THEN L_RW_reg := RWL; L_CE_reg2 := L_CE_reg1; L_CE_reg1 := CEL(1) AND (NOT CEL(0)); L_DOut_reg := DL_Out; L_BE_reg2 := L_BE_reg1; L_BE_reg1 := BENegL; -- control signals for memory BEL_in(0) := (NOT L_BE_reg1(0)) AND L_CE_reg1 AND (NOT L_RW_reg); BEL_in(1) := (NOT L_BE_reg1(1)) AND L_CE_reg1 AND (NOT L_RW_reg); RWL_reg := L_RW_reg; CEL_reg := L_CE_reg1; -- IF PLNegL='1' THEN L_BE_mux := L_BE_reg2; L_CE_mux := L_CE_reg2; ELSE L_BE_mux := L_BE_reg1; L_CE_mux := L_CE_reg1; END IF; END IF; --right PL/F selection IF rising_edge(ClockR) THEN R_RW_reg := RWR; R_CE_reg2 := R_CE_reg1; R_CE_reg1 := CER(1) AND (NOT CER(0)); R_BE_reg2 := R_BE_reg1; R_BE_reg1 := BENegR; -- control signals for memory BER_in(0) := (NOT R_BE_reg1(0)) AND R_CE_reg1 AND (NOT R_RW_reg); BER_in(1) := (NOT R_BE_reg1(1)) AND R_CE_reg1 AND (NOT R_RW_reg); RWR_reg := R_RW_reg; CER_reg := R_CE_reg1; -- IF PLNegR='1' THEN R_BE_mux := R_BE_reg2; R_CE_mux := R_CE_reg2; ELSE R_BE_mux := R_BE_reg1; R_CE_mux := R_CE_reg1; END IF; END IF; -- left address counter IF rising_edge(ClockL) AND int_ZZL /= '1' THEN IF REPEATNegL='0' THEN -- set counter to last valid ADS load Addr_L := Addr_reg_L; ELSIF ADSNegL='0' AND REPEATNegL='1' THEN --load address Addr_L := to_nat(AddressL); Addr_reg_L := to_nat(AddressL); ELSIF ADSNegL='1' AND REPEATNegL='1' AND CNTEnNegL='0' THEN --count Addr_L := Addr_L + 1; END IF; IF RWL_reg='1' THEN -- read L_state := read; ELSE L_state := write; END IF; ELSE L_state := desel; END IF; -- right address counter IF rising_edge(ClockR) AND int_ZZR /= '1' THEN IF REPEATNegR='0' THEN -- set counter to last valid ADS load Addr_R := Addr_reg_R; ELSIF ADSNegR='0' AND REPEATNegR='1' THEN --load address Addr_R := to_nat(AddressR); Addr_reg_R := to_nat(AddressR); ELSIF ADSNegR='1' AND REPEATNegR='1' AND CNTEnNegR='0' THEN --count Addr_R := Addr_R + 1; END IF; IF RWR_reg='1' THEN -- read R_state := read; ELSE R_state := write; END IF; ELSE R_state := desel; END IF; IF rising_edge(ClockL) AND CEL_reg = '1' AND int_ZZL /= '1' THEN IF Addr_L = Addr_R THEN IF (L_state=read OR L_state=write) AND (R_state=write OR right='1') THEN CollisionL := TRUE; ELSE CollisionL := FALSE; END IF; ELSE CollisionL := FALSE; END IF; END IF; IF rising_edge(ClockR) AND CER_reg = '1' AND int_ZZR /= '1' THEN IF Addr_L = Addr_R THEN IF (R_state=read OR R_state=write) AND (L_state=write OR left='1') THEN CollisionR := TRUE; ELSE CollisionR := FALSE; END IF; ELSE CollisionR := FALSE; END IF; END IF; --left access IF rising_edge(ClockL) THEN IF L_state = read THEN -- read IF MemDatA(Addr_L)=-2 THEN DL_out(17 downto 9) := (OTHERS=>'U'); ELSIF MemDatA(Addr_L)=-1 OR CollisionL THEN DL_out(17 downto 9) := (OTHERS=>'X'); ELSE DL_out(17 downto 9) := to_slv(MemDatA(Addr_L),9); END IF; IF MemDatB(Addr_L)=-2 THEN DL_out(8 downto 0) := (OTHERS=>'U'); ELSIF MemDatB(Addr_L)=-1 OR CollisionL THEN DL_out(8 downto 0) := (OTHERS=>'X'); ELSE DL_out(8 downto 0) := to_slv(MemDatB(Addr_L),9); END IF; IF CollisionL THEN L_state := collision; ELSE L_state := read; END IF; ELSIF L_state = write THEN --write L_state := write; left_in <= '1', '0' AFTER 1 ns; -- signal a write to the -- Right port IF CollisionL THEN L_state := collision; -- Signal collision to both ports ELSE L_state := write; END IF; IF BEL_in(1)='1' THEN IF CollisionL OR Viol/='0' THEN MemDatA(Addr_L) := -1; ELSE MemDatA(Addr_L) := to_nat(DataInL(17 downto 9)); END IF; END IF; IF BEL_in(0)='1' THEN IF CollisionL OR Viol/='0' THEN MemDatB(Addr_L) := -1; ELSE MemDatB(Addr_L) := to_nat(DataInL(8 downto 0)); END IF; END IF; END IF; END IF; --right access IF rising_edge(ClockR) AND int_ZZR /= '1' THEN IF CER_reg /= '1' THEN R_state := desel; ELSIF RWR_reg='1' THEN -- read IF MemDatA(Addr_R)=-2 THEN DR_out(17 downto 9) := (OTHERS=>'U'); ELSIF MemDatA(Addr_R)=-1 OR CollisionR THEN DR_out(17 downto 9) := (OTHERS=>'X'); ELSE DR_out(17 downto 9) := to_slv(MemDatA(Addr_R),9); END IF; IF MemDatB(Addr_R)=-2 THEN DR_out(8 downto 0) := (OTHERS=>'U'); ELSIF MemDatB(Addr_R)=-1 OR CollisionR THEN DR_out(8 downto 0) := (OTHERS=>'X'); ELSE DR_out(8 downto 0) := to_slv(MemDatB(Addr_R),9); END IF; IF CollisionR THEN R_state := collision; ELSE R_state := read; END IF; ELSE --write R_state := write; right_in <= '1', '0' AFTER 1 ns; -- signal a write to the -- Right port IF CollisionR THEN R_state := collision; -- Signal collision to both ports ELSE R_state := write; END IF; IF BER_in(1)='1' THEN IF CollisionR OR Viol/='0' THEN MemDatA(Addr_R) := -1; ELSE MemDatA(Addr_R) := to_nat(DataInR(17 downto 9)); END IF; END IF; IF BER_in(0)='1' THEN IF CollisionR OR Viol/='0' THEN MemDatB(Addr_R) := -1; ELSE MemDatB(Addr_R) := to_nat(DataInR(8 downto 0)); END IF; END IF; END IF; END IF; -- left collision pipe-line IF rising_edge(ClockL) AND int_ZZL /= '1' THEN ColL_zd := ColL_pipe2; ColL_pipe2 := ColL_pipe1; IF L_state = collision OR CollisionL THEN ColL_pipe1 := '0'; ELSE ColL_pipe1 := '1'; END IF; IF Addr_L = MailBoxR AND L_state = write THEN Rinterrupt := '0'; --set interrupt ELSIF Addr_L = MailBoxL AND L_state = read THEN Linterrupt := '1'; -- clear interrupt END IF; END IF; -- right collision pipe-line IF rising_edge(ClockR) AND int_ZZR /= '1' THEN ColR_zd := ColR_pipe2; ColR_pipe2 := ColR_pipe1; IF R_state = collision OR CollisionR THEN ColR_pipe1 := '0'; ELSE ColR_pipe1 := '1'; END IF; IF Addr_R = MailBoxL AND R_state = write THEN Linterrupt := '0'; -- set interrupt ELSIF Addr_R = MailBoxR AND R_state = read THEN Rinterrupt := '1'; -- clear interrupt END IF; END IF; -- left data out IF rising_edge(ClockL) THEN IF PLNegL='1' THEN L_D_mux := L_DOut_reg; ELSE L_D_mux := DL_Out; END IF; L_DOut_reg := DL_Out; L_BE_Out(0) := (NOT L_BE_mux(0)) AND L_RW_reg AND L_CE_mux; L_BE_Out(1) := (NOT L_BE_mux(1)) AND L_RW_reg AND L_CE_mux; IF L_BE_Out(1)='1' AND int_ZZL /= '1' THEN DataOutL_zd(17 downto 9) := L_D_mux(17 downto 9); ELSE DataOutL_zd(17 downto 9) := (OTHERS => 'Z'); END IF; IF L_BE_Out(0)='1' AND int_ZZL /= '1' THEN DataOutL_zd(8 downto 0) := L_D_mux(8 downto 0); ELSE DataOutL_zd(8 downto 0) := (OTHERS => 'Z'); END IF; END IF; -- right data out IF rising_edge(ClockR) THEN IF PLNegR='1' THEN R_D_mux := R_DOut_reg; ELSE R_D_mux := DR_Out; END IF; R_DOut_reg := DR_Out; R_BE_Out(0) := (NOT R_BE_mux(0)) AND R_RW_reg AND R_CE_mux; R_BE_Out(1) := (NOT R_BE_mux(1)) AND R_RW_reg AND R_CE_mux; IF R_BE_Out(1)='1' AND int_ZZR /= '1' THEN DataOutR_zd(17 downto 9) := R_D_mux(17 downto 9); ELSE DataOutR_zd(17 downto 9) := (OTHERS => 'Z'); END IF; IF R_BE_Out(0)='1' AND int_ZZR /= '1' THEN DataOutR_zd(8 downto 0) := R_D_mux(8 downto 0); ELSE DataOutR_zd(8 downto 0) := (OTHERS => 'Z'); END IF; END IF; IF OEL = '0' OR OEL = 'L' THEN DOL_zd <= DataOutL_zd; ELSE DOL_zd <= (others => 'Z'); END IF; IF OER = '0' OR OER = 'L' THEN DOR_zd <= DataOutR_zd; ELSE DOR_zd <= (others => 'Z'); END IF; -------------------------------------------------------------------- -- File Read Section -------------------------------------------------------------------- -- memory preload format -- @address -- dddddd -> address -- dddddd -> address+1 -- ddd is 9bit byte ( 0 - 1FF ) IF (mem_file_name /= "none")AND NOW=0 ns THEN ind := 0; WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '#' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 to 6)); ELSE IF h(buf(1 to 3)) < 16#200# THEN MemDatA(ind) := h(buf(1 to 3)); END IF; IF h(buf(4 to 6)) < 16#200# THEN MemDatB(ind) := h(buf(4 to 6)); END IF; ind := ind + 1; END IF; END LOOP; END IF; ----------------------------------------------------------------------- --Collision Path Delay ----------------------------------------------------------------------- VitalPathDelay01( OutSignal => COLNegL, OutSignalName => "COL#L", OutTemp => ColL_zd, Mode => VitalTransport, GlitchData => ColL_GlitchData, Paths => ( 0 => (InputChangeTime => ClockL'LAST_EVENT, PathDelay => tpd_CLKL_COLNegL, PathCondition => TRUE) ) ); VitalPathDelay01( OutSignal => INTNegL, OutSignalName => "INT#L", OutTemp => Linterrupt, Mode => VitalTransport, GlitchData => IntL_GlitchData, Paths => ( 0 => (InputChangeTime => ClockL'LAST_EVENT, PathDelay => tpd_CLKL_IntNegL, PathCondition => Linterrupt='1'), 1 => (InputChangeTime => ClockR'LAST_EVENT, PathDelay => tpd_CLKL_IntNegL, PathCondition => Linterrupt='0') ) ); VitalPathDelay01( OutSignal => COLNegR, OutSignalName => "COL#R", OutTemp => ColR_zd, Mode => VitalTransport, GlitchData => ColR_GlitchData, Paths => ( 0 => (InputChangeTime => ClockR'LAST_EVENT, PathDelay => tpd_CLKL_COLNegL, PathCondition => TRUE) ) ); VitalPathDelay01( OutSignal => INTNegR, OutSignalName => "INT#L", OutTemp => Rinterrupt, Mode => VitalTransport, GlitchData => IntR_GlitchData, Paths => ( 0 => (InputChangeTime => ClockR'LAST_EVENT, PathDelay => tpd_CLKL_IntNegL, PathCondition => Rinterrupt='1'), 1 => (InputChangeTime => ClockL'LAST_EVENT, PathDelay => tpd_CLKL_IntNegL, PathCondition => Rinterrupt='0') ) ); END PROCESS BothPort; --------------------------------------------------------------------------- -- Path Delay Section for LeftPOrt signal --------------------------------------------------------------------------- Left_PathDelay_Gen : FOR i IN DOL_zd'RANGE GENERATE PROCESS(DOL_zd(i))--, OEL ) VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DataOutL(i), OutSignalName => "DataOutL", OutTemp => DOL_zd(i), GlitchData => D_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => true, Paths => ( 0 => (InputChangeTime => ClockL'LAST_EVENT, PathDelay => tpd_CLKL_IO0L, PathCondition => PLNegL='1' ), 1 => (InputChangeTime => ClockL'LAST_EVENT, PathDelay => tpd_CLKR_IO0R, PathCondition => PLNegL='0' ), 2 => (InputChangeTime => OEL'LAST_EVENT, PathDelay => tpd_OENegL_IO0L, PathCondition => true) ) ); END PROCESS; END GENERATE Left_PathDelay_Gen; --------------------------------------------------------------------------- -- Path Delay Section for Right Port signal --------------------------------------------------------------------------- Right_PathDelay_Gen : FOR i IN DOR_zd'RANGE GENERATE PROCESS(DOR_zd(i))--, OER ) VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DataOutR(i), OutSignalName => "DataOutR", OutTemp => DOR_zd(i), GlitchData => D_GlitchData, IgnoreDefaultDelay => TRUE, Mode => VitalTransport, RejectFastPath => true, Paths => ( 0 => (InputChangeTime => ClockR'LAST_EVENT, PathDelay => tpd_CLKL_IO0L, PathCondition => PLNegR='1' ), 1 => (InputChangeTime => ClockR'LAST_EVENT, PathDelay => tpd_CLKR_IO0R, PathCondition => PLNegR='0' ), 2 => (InputChangeTime => OER'LAST_EVENT, PathDelay => tpd_OENegL_IO0L, PathCondition => true) ) ); END PROCESS; END GENERATE Right_PathDelay_Gen; END BLOCK Behavior; END vhdl_behavioral;