-------------------------------------------------------------------------------- -- File Name: idt709079.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 00 Oct 24 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: IDT709079 -- -- Description: Sync Pipelined Dual-Port SRAM 32K x 8 -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt709079 IS GENERIC ( -- tipd delays: interconnect path delays tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_CE1R : VitalDelayType01 := VitalZeroDelay01; tipd_CE1L : VitalDelayType01 := VitalZeroDelay01; tipd_PIPER : VitalDelayType01 := VitalZeroDelay01; tipd_CLKR : VitalDelayType01 := VitalZeroDelay01; tipd_CLKL : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTRSTLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR10 : VitalDelayType01 := VitalZeroDelay01; tipd_AR11 : VitalDelayType01 := VitalZeroDelay01; tipd_AR12 : VitalDelayType01 := VitalZeroDelay01; tipd_AR13 : VitalDelayType01 := VitalZeroDelay01; tipd_AR14 : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL10 : VitalDelayType01 := VitalZeroDelay01; tipd_AL11 : VitalDelayType01 := VitalZeroDelay01; tipd_AL12 : VitalDelayType01 := VitalZeroDelay01; tipd_AL13 : VitalDelayType01 := VitalZeroDelay01; tipd_AL14 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tOE, tOLZ, tOHZ tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; -- tCD1, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_0 : VitalDelayType01Z := UnitDelay01Z; -- tCD2, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tCWDD tpd_CLKL_IOR0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tLC1 tpw_CLKR_PIPER_EQ_0_negedge : VitalDelayType := UnitDelay; -- tHC1 tpw_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tLC2 tpw_CLKR_PIPER_EQ_1_negedge : VitalDelayType := UnitDelay; -- tHC2 tpw_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq -- tCYC1 tperiod_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tCYC2 tperiod_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tSA tsetup_AL0_CLKL : VitalDelayType := UnitDelay; -- tSC tsetup_CE1L_CLKL : VitalDelayType := UnitDelay; -- tSW tsetup_RWL_CLKL : VitalDelayType := UnitDelay; -- tSD tsetup_IOL0_CLKL : VitalDelayType := UnitDelay; -- tSAD tsetup_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tSCN tsetup_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tSRST tsetup_CNTRSTLNeg_CLKL : VitalDelayType := UnitDelay; -- tCCS tsetup_CLKR_CLKL : VitalDelayType := UnitDelay; -- thold values: hold times -- tHA thold_AL0_CLKL : VitalDelayType := UnitDelay; -- tHC thold_CE1L_CLKL : VitalDelayType := UnitDelay; -- tHW thold_RWL_CLKL : VitalDelayType := UnitDelay; -- tHD thold_IOL0_CLKL : VitalDelayType := UnitDelay; -- tHAD thold_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tHCN thold_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tHRST thold_CNTRSTLNeg_CLKL : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( RWR : IN std_ulogic := 'U'; RWL : IN std_ulogic := 'U'; CE1R : IN std_ulogic := 'U'; CE1L : IN std_ulogic := 'U'; PIPER : IN std_ulogic := 'U'; CLKR : IN std_ulogic := 'U'; CLKL : IN std_ulogic := 'U'; CNTENRNeg : IN std_ulogic := 'U'; CNTENLNeg : IN std_ulogic := 'U'; CNTRSTRNeg : IN std_ulogic := 'U'; CNTRSTLNeg : IN std_ulogic := 'U'; ADSRNeg : IN std_ulogic := 'U'; ADSLNeg : IN std_ulogic := 'U'; CE0RNeg : IN std_ulogic := 'U'; CE0LNeg : IN std_ulogic := 'U'; OERNeg : IN std_ulogic := 'U'; OELNeg : IN std_ulogic := 'U'; IOR7 : INOUT std_ulogic := 'U'; IOR6 : INOUT std_ulogic := 'U'; IOR5 : INOUT std_ulogic := 'U'; IOR4 : INOUT std_ulogic := 'U'; IOR3 : INOUT std_ulogic := 'U'; IOR2 : INOUT std_ulogic := 'U'; IOR1 : INOUT std_ulogic := 'U'; IOR0 : INOUT std_ulogic := 'U'; IOL7 : INOUT std_ulogic := 'U'; IOL6 : INOUT std_ulogic := 'U'; IOL5 : INOUT std_ulogic := 'U'; IOL4 : INOUT std_ulogic := 'U'; IOL3 : INOUT std_ulogic := 'U'; IOL2 : INOUT std_ulogic := 'U'; IOL1 : INOUT std_ulogic := 'U'; IOL0 : INOUT std_ulogic := 'U'; AR0 : IN std_ulogic := 'U'; AR1 : IN std_ulogic := 'U'; AR2 : IN std_ulogic := 'U'; AR3 : IN std_ulogic := 'U'; AR4 : IN std_ulogic := 'U'; AR5 : IN std_ulogic := 'U'; AR6 : IN std_ulogic := 'U'; AR7 : IN std_ulogic := 'U'; AR8 : IN std_ulogic := 'U'; AR9 : IN std_ulogic := 'U'; AR10 : IN std_ulogic := 'U'; AR11 : IN std_ulogic := 'U'; AR12 : IN std_ulogic := 'U'; AR13 : IN std_ulogic := 'U'; AR14 : IN std_ulogic := 'U'; AL0 : IN std_ulogic := 'U'; AL1 : IN std_ulogic := 'U'; AL2 : IN std_ulogic := 'U'; AL3 : IN std_ulogic := 'U'; AL4 : IN std_ulogic := 'U'; AL5 : IN std_ulogic := 'U'; AL6 : IN std_ulogic := 'U'; AL7 : IN std_ulogic := 'U'; AL8 : IN std_ulogic := 'U'; AL9 : IN std_ulogic := 'U'; AL10 : IN std_ulogic := 'U'; AL11 : IN std_ulogic := 'U'; AL12 : IN std_ulogic := 'U'; AL13 : IN std_ulogic := 'U'; AL14 : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt709079 : ENTITY IS TRUE; END idt709079; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt709079 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "IDT709079"; CONSTANT MaxData : NATURAL := 255; CONSTANT TotalLOC : NATURAL := 32767; CONSTANT HiAbit : NATURAL := 14; CONSTANT HiDbit : NATURAL := 7; CONSTANT DataWidth : NATURAL := 8; SIGNAL RWR_ipd : std_ulogic := 'U'; SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL CE1R_ipd : std_ulogic := 'U'; SIGNAL CE1L_ipd : std_ulogic := 'U'; SIGNAL PIPER_ipd : std_ulogic := 'U'; SIGNAL CLKR_ipd : std_ulogic := 'U'; SIGNAL CLKL_ipd : std_ulogic := 'U'; SIGNAL CNTENRNeg_ipd : std_ulogic := 'U'; SIGNAL CNTENLNeg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTRNeg_ipd : std_ulogic := 'U'; SIGNAL CNTRSTLNeg_ipd : std_ulogic := 'U'; SIGNAL ADSRNeg_ipd : std_ulogic := 'U'; SIGNAL ADSLNeg_ipd : std_ulogic := 'U'; SIGNAL CE0RNeg_ipd : std_ulogic := 'U'; SIGNAL CE0LNeg_ipd : std_ulogic := 'U'; SIGNAL OERNeg_ipd : std_ulogic := 'U'; SIGNAL OELNeg_ipd : std_ulogic := 'U'; SIGNAL IOR7_ipd : std_ulogic := 'U'; SIGNAL IOR6_ipd : std_ulogic := 'U'; SIGNAL IOR5_ipd : std_ulogic := 'U'; SIGNAL IOR4_ipd : std_ulogic := 'U'; SIGNAL IOR3_ipd : std_ulogic := 'U'; SIGNAL IOR2_ipd : std_ulogic := 'U'; SIGNAL IOR1_ipd : std_ulogic := 'U'; SIGNAL IOR0_ipd : std_ulogic := 'U'; SIGNAL IOL7_ipd : std_ulogic := 'U'; SIGNAL IOL6_ipd : std_ulogic := 'U'; SIGNAL IOL5_ipd : std_ulogic := 'U'; SIGNAL IOL4_ipd : std_ulogic := 'U'; SIGNAL IOL3_ipd : std_ulogic := 'U'; SIGNAL IOL2_ipd : std_ulogic := 'U'; SIGNAL IOL1_ipd : std_ulogic := 'U'; SIGNAL IOL0_ipd : std_ulogic := 'U'; SIGNAL AR0_ipd : std_ulogic := 'U'; SIGNAL AR1_ipd : std_ulogic := 'U'; SIGNAL AR2_ipd : std_ulogic := 'U'; SIGNAL AR3_ipd : std_ulogic := 'U'; SIGNAL AR4_ipd : std_ulogic := 'U'; SIGNAL AR5_ipd : std_ulogic := 'U'; SIGNAL AR6_ipd : std_ulogic := 'U'; SIGNAL AR7_ipd : std_ulogic := 'U'; SIGNAL AR8_ipd : std_ulogic := 'U'; SIGNAL AR9_ipd : std_ulogic := 'U'; SIGNAL AR10_ipd : std_ulogic := 'U'; SIGNAL AR11_ipd : std_ulogic := 'U'; SIGNAL AR12_ipd : std_ulogic := 'U'; SIGNAL AR13_ipd : std_ulogic := 'U'; SIGNAL AR14_ipd : std_ulogic := 'U'; SIGNAL AL0_ipd : std_ulogic := 'U'; SIGNAL AL1_ipd : std_ulogic := 'U'; SIGNAL AL2_ipd : std_ulogic := 'U'; SIGNAL AL3_ipd : std_ulogic := 'U'; SIGNAL AL4_ipd : std_ulogic := 'U'; SIGNAL AL5_ipd : std_ulogic := 'U'; SIGNAL AL6_ipd : std_ulogic := 'U'; SIGNAL AL7_ipd : std_ulogic := 'U'; SIGNAL AL8_ipd : std_ulogic := 'U'; SIGNAL AL9_ipd : std_ulogic := 'U'; SIGNAL AL10_ipd : std_ulogic := 'U'; SIGNAL AL11_ipd : std_ulogic := 'U'; SIGNAL AL12_ipd : std_ulogic := 'U'; SIGNAL AL13_ipd : std_ulogic := 'U'; SIGNAL AL14_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR); w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL); w_3 : VitalWireDelay (CE1R_ipd, CE1R, tipd_CE1R); w_4 : VitalWireDelay (CE1L_ipd, CE1L, tipd_CE1L); w_5 : VitalWireDelay (PIPER_ipd, PIPER, tipd_PIPER); w_6 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR); w_7 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL); w_8 : VitalWireDelay (CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg); w_9 : VitalWireDelay (CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg); w_10 : VitalWireDelay (CNTRSTRNeg_ipd, CNTRSTRNeg, tipd_CNTRSTRNeg); w_11 : VitalWireDelay (CNTRSTLNeg_ipd, CNTRSTLNeg, tipd_CNTRSTLNeg); w_12 : VitalWireDelay (ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg); w_13 : VitalWireDelay (ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg); w_14 : VitalWireDelay (CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg); w_15 : VitalWireDelay (CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg); w_16 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg); w_17 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg); w_20 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0); w_21 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1); w_22 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2); w_23 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3); w_24 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4); w_25 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5); w_26 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6); w_27 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7); w_28 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8); w_29 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9); w_30 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10); w_31 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11); w_32 : VitalWireDelay (AR12_ipd, AR12, tipd_AR12); w_33 : VitalWireDelay (AR13_ipd, AR13, tipd_AR13); w_34 : VitalWireDelay (AR14_ipd, AR14, tipd_AR14); w_37 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0); w_38 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1); w_39 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2); w_40 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3); w_41 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4); w_42 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5); w_43 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6); w_44 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7); w_45 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8); w_46 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9); w_47 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10); w_48 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11); w_49 : VitalWireDelay (AL12_ipd, AL12, tipd_AL12); w_50 : VitalWireDelay (AL13_ipd, AL13, tipd_AL13); w_51 : VitalWireDelay (AL14_ipd, AL14, tipd_AL14); w_53 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7); w_54 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6); w_55 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5); w_56 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4); w_57 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3); w_58 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2); w_59 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1); w_60 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0); w_61 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7); w_62 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6); w_63 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5); w_64 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4); w_65 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3); w_66 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2); w_67 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1); w_68 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ALIn : IN std_logic_vector(HiAbit downto 0); ARIn : IN std_logic_vector(HiAbit downto 0); IOLIn : IN std_logic_vector(HiDbit downto 0); IORIn : IN std_logic_vector(HiDbit downto 0); IOLOut : OUT std_logic_vector(HiDbit downto 0); IOROut : OUT std_logic_vector(HiDbit downto 0); RWLIn : IN std_ulogic := 'U'; RWRIn : IN std_ulogic := 'U'; OELNegIn : IN std_ulogic := 'U'; OERNegIn : IN std_ulogic := 'U'; CE0LNegIn : IN std_ulogic := 'U'; CE0RNegIn : IN std_ulogic := 'U'; CE1LIn : IN std_ulogic := 'U'; CE1RIn : IN std_ulogic := 'U'; CLKLIn : IN std_ulogic := 'U'; CLKRIn : IN std_ulogic := 'U'; CNTRSTLNegIn : IN std_ulogic := 'U'; CNTRSTRNegIn : IN std_ulogic := 'U'; CNTENRNegIn : IN std_ulogic := 'U'; CNTENLNegIn : IN std_ulogic := 'U'; ADSRNegIn : IN std_ulogic := 'U'; ADSLNegIn : IN std_ulogic := 'U'; PIPERIn : IN std_ulogic := '1' ); PORT MAP ( ALIn(0) => AL0_ipd, ALIn(1) => AL1_ipd, ALIn(2) => AL2_ipd, ALIn(3) => AL3_ipd, ALIn(4) => AL4_ipd, ALIn(5) => AL5_ipd, ALIn(6) => AL6_ipd, ALIn(7) => AL7_ipd, ALIn(8) => AL8_ipd, ALIn(9) => AL9_ipd, ALIn(10) => AL10_ipd, ALIn(11) => AL11_ipd, ALIn(12) => AL12_ipd, ALIn(13) => AL13_ipd, ALIn(14) => AL14_ipd, ARIn(0) => AR0_ipd, ARIn(1) => AR1_ipd, ARIn(2) => AR2_ipd, ARIn(3) => AR3_ipd, ARIn(4) => AR4_ipd, ARIn(5) => AR5_ipd, ARIn(6) => AR6_ipd, ARIn(7) => AR7_ipd, ARIn(8) => AR8_ipd, ARIn(9) => AR9_ipd, ARIn(10) => AR10_ipd, ARIn(11) => AR11_ipd, ARIn(12) => AR12_ipd, ARIn(13) => AR13_ipd, ARIn(14) => AR14_ipd, IOLIn(0) => IOL0_ipd, IOLIn(1) => IOL1_ipd, IOLIn(2) => IOL2_ipd, IOLIn(3) => IOL3_ipd, IOLIn(4) => IOL4_ipd, IOLIn(5) => IOL5_ipd, IOLIn(6) => IOL6_ipd, IOLIn(7) => IOL7_ipd, IORIn(0) => IOR0_ipd, IORIn(1) => IOR1_ipd, IORIn(2) => IOR2_ipd, IORIn(3) => IOR3_ipd, IORIn(4) => IOR4_ipd, IORIn(5) => IOR5_ipd, IORIn(6) => IOR6_ipd, IORIn(7) => IOR7_ipd, IOLOut(0) => IOL0, IOLOut(1) => IOL1, IOLOut(2) => IOL2, IOLOut(3) => IOL3, IOLOut(4) => IOL4, IOLOut(5) => IOL5, IOLOut(6) => IOL6, IOLOut(7) => IOL7, IOROut(0) => IOR0, IOROut(1) => IOR1, IOROut(2) => IOR2, IOROut(3) => IOR3, IOROut(4) => IOR4, IOROut(5) => IOR5, IOROut(6) => IOR6, IOROut(7) => IOR7, RWLIn => RWL_ipd, RWRIn => RWR_ipd, OELNegIn => OELNeg_ipd, OERNegIn => OERNeg_ipd, CE0LNegIn => CE0LNeg_ipd, CE0RNegIn => CE0RNeg_ipd, CE1LIn => CE1L_ipd, CE1RIn => CE1R_ipd, CLKLIn => CLKL_ipd, CLKRIn => CLKR_ipd, CNTRSTLNegIn => CNTRSTLNeg_ipd, CNTRSTRNegIn => CNTRSTRNeg_ipd, CNTENRNegIn => CNTENRNeg_ipd, CNTENLNegIn => CNTENLNeg_ipd, ADSRNegIn => ADSRNeg_ipd, ADSLNegIn => ADSLNeg_ipd, PIPERIn => PIPER_ipd ); SIGNAL IOL_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL Addr_Match : boolean; BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CE0LNegIn, CE0RNegIn, ALIn, ARIn, IOLIn, IORIn, CE1LIn, CE1RIn, CLKLIn, CLKRIn, CNTRSTLNegIn, CNTRSTRNegIn, CNTENRNegIn, CNTENLNegIn, ADSRNegIn, ADSLNegIn, PIPERIn) -- Timing Check Variables VARIABLE Tviol_ALIn_CLKLIn : X01 := '0'; VARIABLE TD_ALIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_ARIn_CLKRIn : X01 := '0'; VARIABLE TD_ARIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CE0LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_CE0LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CE0RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_CE0RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CE1LIn_CLKLIn : X01 := '0'; VARIABLE TD_CE1LIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CE1RIn_CLKRIn : X01 := '0'; VARIABLE TD_CE1RIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_RWLIn_CLKLIn : X01 := '0'; VARIABLE TD_RWLIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_RWRIn_CLKRIn : X01 := '0'; VARIABLE TD_RWRIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_IOLIn_CLKLIn : X01 := '0'; VARIABLE TD_IOLIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_IORIn_CLKRIn : X01 := '0'; VARIABLE TD_IORIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_ADSLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_ADSLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_ADSRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_ADSRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CNTENLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_CNTENLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CNTENRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_CNTENRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CNTRSTLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_CNTRSTLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CNTRSTRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_CNTRSTRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CLKRIn_CLKLIn : X01 := '0'; VARIABLE TD_CLKRIn_CLKLIn : VitalTimingDataType; VARIABLE Pviol_CLKLIn : X01 := '0'; VARIABLE TD_CLKLIn : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKRIn : X01 := '0'; VARIABLE TD_CLKRIn : VitalPeriodDataType := VitalPeriodDataInit; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER RANGE -2 TO MaxData; VARIABLE DataLDrive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataRDrive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataLtmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataRtmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataTempL : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR : INTEGER RANGE -2 TO MaxData := -2; VARIABLE LocationL : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LocationR : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE MemData : MemStore; VARIABLE LatencyL : BOOLEAN; VARIABLE LatencyR : BOOLEAN; -- Output Glitch Detection Variables -- No Weak Values Variables VARIABLE CE0LNeg_nwv : UX01 := 'U'; VARIABLE CE0RNeg_nwv : UX01 := 'U'; VARIABLE CE1L_nwv : UX01 := 'U'; VARIABLE CE1R_nwv : UX01 := 'U'; VARIABLE RWR_nwv : UX01 := 'U'; VARIABLE RWL_nwv : UX01 := 'U'; VARIABLE ADSLNeg_nwv : UX01 := 'U'; VARIABLE ADSRNeg_nwv : UX01 := 'U'; VARIABLE PIPER_nwv : UX01 := 'U'; VARIABLE OELNeg_nwv : UX01 := 'U'; VARIABLE OERNeg_nwv : UX01 := 'U'; VARIABLE CNTRSTLNeg_nwv : UX01 := 'U'; VARIABLE CNTRSTRNeg_nwv : UX01 := 'U'; VARIABLE CNTENLNeg_nwv : UX01 := 'U'; VARIABLE CNTENRNeg_nwv : UX01 := 'U'; BEGIN CE0LNeg_nwv := To_UX01 (s => CE0LNegIn); CE0RNeg_nwv := To_UX01 (s => CE0RNegIn); CE1L_nwv := To_UX01 (s => CE1LIn); CE1R_nwv := To_UX01 (s => CE1RIn); RWL_nwv := To_UX01 (s => RWLIn); RWR_nwv := To_UX01 (s => RWRIn); ADSLNeg_nwv := To_UX01 (s => ADSLNegIn); ADSRNeg_nwv := To_UX01 (s => ADSRNegIn); PIPER_nwv := To_UX01 (s => PIPERIn); OELNeg_nwv := To_UX01 (s => OELNegIn); OERNeg_nwv := To_UX01 (s => OERNegIn); CNTRSTLNeg_nwv := To_UX01 (s => CNTRSTLNegIn); CNTRSTRNeg_nwv := To_UX01 (s => CNTRSTRNegIn); CNTENLNeg_nwv := To_UX01 (s => CNTENLNegIn); CNTENRNeg_nwv := To_UX01 (s => CNTENRNegIn); -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE0LNegIn, TestSignalName => "CE0LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE0RNegIn, TestSignalName => "CE0RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE1LIn, TestSignalName => "CE1L", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1LIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1LIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE1RIn, TestSignalName => "CE1R", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1RIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1RIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => RWLIn, TestSignalName => "RWL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWLIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWLIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => RWRIn, TestSignalName => "RWR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWRIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWRIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOLIn, TestSignalName => "IOL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOLIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOLIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IORIn, TestSignalName => "IOR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1' AND RWR_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IORIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IORIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => ADSLNegIn, TestSignalName => "ADSLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => ADSRNegIn, TestSignalName => "ADSRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSRNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CNTENLNegIn, TestSignalName => "CNTENLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CNTENLNeg_CLKL, SetupLow => tsetup_CNTENLNeg_CLKL, HoldHigh => thold_CNTENLNeg_CLKL, HoldLow => thold_CNTENLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTENLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CNTENRNegIn, TestSignalName => "CNTENRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CNTENLNeg_CLKL, SetupLow => tsetup_CNTENLNeg_CLKL, HoldHigh => thold_CNTENLNeg_CLKL, HoldLow => thold_CNTENLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTENRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENRNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CNTRSTLNegIn, TestSignalName => "CNTRSTLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CNTRSTLNeg_CLKL, SetupLow => tsetup_CNTRSTLNeg_CLKL, HoldHigh => thold_CNTRSTLNeg_CLKL, HoldLow => thold_CNTRSTLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CNTRSTRNegIn, TestSignalName => "CNTRSTRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CNTRSTLNeg_CLKL, SetupLow => tsetup_CNTRSTLNeg_CLKL, HoldHigh => thold_CNTRSTLNeg_CLKL, HoldLow => thold_CNTRSTLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTRSTRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTRSTRNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CLKLIn, TestSignalName => "CLKL", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CLKR_CLKL, CheckEnabled => (RWLIn = '0' AND ALIn = ARIn AND PIPERIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CLKRIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CLKRIn_CLKLIn ); VitalPeriodPulseCheck ( TestSignal => CLKLIn, TestSignalName => "CLKL", Period => tperiod_CLKR_PIPER_EQ_1_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_1_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_1_posedge, PeriodData => TD_CLKLIn, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE, Violation => Pviol_CLKLIn ); VitalPeriodPulseCheck ( TestSignal => CLKRIn, TestSignalName => "CLKR", Period => tperiod_CLKR_PIPER_EQ_1_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_1_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_1_posedge, PeriodData => TD_CLKRIn, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPER_nwv = '1'), Violation => Pviol_CLKRIn ); VitalPeriodPulseCheck ( TestSignal => CLKRIn, TestSignalName => "CLKR", Period => tperiod_CLKR_PIPER_EQ_0_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_0_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_0_posedge, PeriodData => TD_CLKRIn, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPER_nwv = '0'), Violation => Pviol_CLKRIn ); Violation := Tviol_ALIn_CLKLIn OR Tviol_ARIn_CLKRIn OR Tviol_CE0LNegIn_CLKLIn OR Tviol_CE0RNegIn_CLKRIn OR Tviol_CE1LIn_CLKLIn OR Tviol_CE1RIn_CLKRIn OR Tviol_RWLIn_CLKLIn OR Tviol_RWRIn_CLKRIn OR Tviol_IOLIn_CLKLIn OR Tviol_IORIn_CLKRIn OR Tviol_ADSLNegIn_CLKLIn OR Tviol_ADSRNegIn_CLKRIn OR Tviol_CNTENLNegIn_CLKLIn OR Tviol_CNTENRNegIn_CLKRIn OR Tviol_CNTRSTLNegIn_CLKLIn OR Tviol_CNTRSTRNegIn_CLKRIn OR Pviol_CLKLIn OR Pviol_CLKRIn; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- IF rising_edge(CLKLIn) THEN IF RWL_nwv = '1' THEN -- read pipeline IF DataTempL >= 0 THEN DataLTmp := To_slv(DataTempL, DataWidth); ELSIF DataTempL = -2 THEN DataLTmp := (OTHERS => 'U'); ELSE DataLTmp := (OTHERS => 'X'); END IF; IF LatencyL THEN DataLTmp := (OTHERS => 'Z'); END IF; LatencyL := false; END IF; IF CE0LNeg_nwv = '0' AND CE1L_nwv = '1' THEN IF CNTRSTLNeg_nwv = '0' THEN -- reset addr LocationL := 0; ELSIF ADSLNeg_nwv = '0' THEN -- load addr LocationL := To_Nat(ALIn); ELSIF CNTENLNeg_nwv = '0' THEN IF LocationL < TotalLOC THEN -- inc addr LocationL := LocationL + 1; ELSE LocationL := 0; END IF; END IF; IF RWL_nwv = '1' THEN -- read DataTempL := MemData(LocationL); ELSE -- write DataLTmp := (OTHERS => 'Z'); LatencyL := true; IF Violation = '0' THEN MemData(LocationL) := To_Nat(IOLIn); ELSE MemData(LocationL) := -1; WrtDataL := -1; END IF; END IF; END IF; END IF; IF rising_edge(CLKRIn) THEN IF Tviol_CLKRIn_CLKLin = 'X' THEN Addr_Match <= true; ELSE Addr_Match <= false; END IF; IF RWR_nwv = '1' AND PIPERIn = '1' THEN -- read pipeline IF DataTempR >= 0 THEN DataRtmp := To_slv(DataTempR, DataWidth); ELSIF DataTempR = -2 THEN DataRtmp := (OTHERS => 'U'); ELSE DataRtmp := (OTHERS => 'X'); END IF; IF LatencyR THEN DataRtmp := (OTHERS => 'Z'); END IF; LatencyR := false; END IF; IF CE0RNeg_nwv = '0' AND CE1R_nwv = '1' THEN IF CNTRSTRNeg_nwv = '0' THEN -- reset addr LocationR := 0; ELSIF ADSRNeg_nwv = '0' THEN -- load addr LocationR := To_Nat(ARIn); ELSIF CNTENRNeg_nwv = '0' THEN IF LocationR < TotalLOC THEN -- inc addr LocationR := LocationR + 1; ELSE LocationR := 0; END IF; END IF; IF RWR_nwv = '1' THEN -- read DataTempR := MemData(LocationR); IF PIPERIn = '0' THEN IF DataTempR >= 0 THEN DataRtmp := To_slv(DataTempR, DataWidth); ELSIF DataTempR = -2 THEN DataRtmp := (OTHERS => 'U'); ELSE DataRtmp := (OTHERS => 'X'); END IF; END IF; ELSE -- write DataRtmp := (OTHERS => 'Z'); LatencyR := true; IF Violation = '0' THEN MemData(LocationR) := To_Nat(IORIn); ELSE MemData(LocationR) := -1; WrtDataR := -1; END IF; END IF; END IF; END IF; IF (OELNeg_nwv = '1') THEN DataLDrive := (OTHERS => 'Z'); ELSE DataLDrive := DataLTmp; END IF; IF (OERNeg_nwv = '1') THEN DataRDrive := (OTHERS => 'Z'); ELSE DataRDrive := DataRTmp; END IF; IOL_zd <= DataLDrive; IOR_zd <= DataRDrive; END PROCESS; ------------------------------------------------------------------------ -- Path Delay Processes generated as a function of data width ------------------------------------------------------------------------ DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOut_Delay : PROCESS (IOR_zd(i), IOL_zd(i)) VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => IOLOut(i), OutSignalName => "IOL", OutTemp => IOL_zd(i), Mode => OnEvent, GlitchData => IOL_GlitchData(i), Paths => ( 0 => (InputChangeTime => OELNegIn'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => TRUE), 1 => (InputChangeTime => CLKLIn'LAST_EVENT, PathDelay => tpd_CLKR_IOR0_PIPER_EQ_1, PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IOROut(i), OutSignalName => "IOR", OutTemp => IOR_zd(i), Mode => OnEvent, GlitchData => IOR_GlitchData(i), Paths => ( 0 => (InputChangeTime => OERNegIn'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => TRUE), 1 => (InputChangeTime => CLKRIn'LAST_EVENT, PathDelay => tpd_CLKR_IOR0_PIPER_EQ_1, PathCondition => (PIPERIn = '1')), 2 => (InputChangeTime => CLKRIn'LAST_EVENT, PathDelay => tpd_CLKR_IOR0_PIPER_EQ_0, PathCondition => (PIPERIn = '0' AND not Addr_Match)), 3 => (InputChangeTime => CLKLIn'LAST_EVENT, PathDelay => tpd_CLKL_IOR0, PathCondition => Addr_Match) ) ); END PROCESS; END GENERATE; END BLOCK; END vhdl_behavioral;