-------------------------------------------------------------------------------- -- File Name: idt703599.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2001 Integrated Device Technology; http://www.idt.com/ -- Developed & supported by Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no -- warranty with respect to the information contained herein. IDT DISCLAIMS -- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE -- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN -- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN -- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, -- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR -- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make -- changes without notice to any product herein to improve reliability, -- function, or design. IDT does not convey any license under patent rights -- or any other intellectual property rights, including those of third parties. -- IDT is not obligated to provide maintenance or support for the licensed VHDL -- model. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 01 Mar 22 Initial release -- V1.1 R. Munden 01 Nov 10 Corrected address cntr w/o enable -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: IDT703599 -- -- Description: Sync Pipelined Dual-Port SRAM 128K x 36 -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY idt703599 IS GENERIC ( -- tipd delays: interconnect path delays tipd_OPTR : VitalDelayType01 := VitalZeroDelay01; tipd_OPTL : VitalDelayType01 := VitalZeroDelay01; tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_CE1R : VitalDelayType01 := VitalZeroDelay01; tipd_CE1L : VitalDelayType01 := VitalZeroDelay01; tipd_PIPER : VitalDelayType01 := VitalZeroDelay01; tipd_PIPEL : VitalDelayType01 := VitalZeroDelay01; tipd_CLKR : VitalDelayType01 := VitalZeroDelay01; tipd_CLKL : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CNTENLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_REPEATLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE3RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE2RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE1RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE0RNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE3LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE2LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE1LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BE0LNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IOR35 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL35 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL34 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL33 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL32 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL31 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL30 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL29 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL28 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL27 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL26 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL25 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL24 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL23 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL22 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL21 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL20 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL19 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL18 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL17 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL16 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL15 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL14 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL13 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL12 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL11 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL10 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL9 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL8 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR10 : VitalDelayType01 := VitalZeroDelay01; tipd_AR11 : VitalDelayType01 := VitalZeroDelay01; tipd_AR12 : VitalDelayType01 := VitalZeroDelay01; tipd_AR13 : VitalDelayType01 := VitalZeroDelay01; tipd_AR14 : VitalDelayType01 := VitalZeroDelay01; tipd_AR15 : VitalDelayType01 := VitalZeroDelay01; tipd_AR16 : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL10 : VitalDelayType01 := VitalZeroDelay01; tipd_AL11 : VitalDelayType01 := VitalZeroDelay01; tipd_AL12 : VitalDelayType01 := VitalZeroDelay01; tipd_AL13 : VitalDelayType01 := VitalZeroDelay01; tipd_AL14 : VitalDelayType01 := VitalZeroDelay01; tipd_AL15 : VitalDelayType01 := VitalZeroDelay01; tipd_AL16 : VitalDelayType01 := VitalZeroDelay01; tipd_TDI : VitalDelayType01 := VitalZeroDelay01; tipd_TCK : VitalDelayType01 := VitalZeroDelay01; tipd_TMS : VitalDelayType01 := VitalZeroDelay01; tipd_TRSTNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tOE, tOLZ, tOHZ tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; -- tCD1, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_0 : VitalDelayType01Z := UnitDelay01Z; -- tCD2, tCKHZ, tCKLZ tpd_CLKR_IOR0_PIPER_EQ_1 : VitalDelayType01Z := UnitDelay01Z; -- tJCD tpd_TCK_TDO : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tLC1 tpw_CLKR_PIPER_EQ_0_negedge : VitalDelayType := UnitDelay; -- tHC1 tpw_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tLC2 tpw_CLKR_PIPER_EQ_1_negedge : VitalDelayType := UnitDelay; -- tHC2 tpw_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tJCL tpw_TCK_negedge : VitalDelayType := UnitDelay; -- tJRST tpw_TRSTNeg_negedge : VitalDelayType := UnitDelay; -- tperiod_min: minimum clock period = 1/max freq -- tCYC1 tperiod_CLKR_PIPER_EQ_0_posedge : VitalDelayType := UnitDelay; -- tCYC2 tperiod_CLKR_PIPER_EQ_1_posedge : VitalDelayType := UnitDelay; -- tJCYC tperiod_TCK_negedge : VitalDelayType := UnitDelay; -- trecovery values: release times -- tJRSR trecovery_TRSTNeg_TCK : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tSA tsetup_AL0_CLKL : VitalDelayType := UnitDelay; -- tSC tsetup_CE1L_CLKL : VitalDelayType := UnitDelay; -- tSW tsetup_RWL_CLKL : VitalDelayType := UnitDelay; -- tSD tsetup_IOL0_CLKL : VitalDelayType := UnitDelay; -- tSAD tsetup_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tSCN tsetup_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tSRST tsetup_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; -- tJS tsetup_TDI_TCK : VitalDelayType := UnitDelay; -- thold values: hold times -- tHA thold_AL0_CLKL : VitalDelayType := UnitDelay; -- tHC thold_CE1L_CLKL : VitalDelayType := UnitDelay; -- tHW thold_RWL_CLKL : VitalDelayType := UnitDelay; -- tHD thold_IOL0_CLKL : VitalDelayType := UnitDelay; -- tHAD thold_ADSLNeg_CLKL : VitalDelayType := UnitDelay; -- tHCN thold_CNTENLNeg_CLKL : VitalDelayType := UnitDelay; -- tHRST thold_REPEATLNeg_CLKL : VitalDelayType := UnitDelay; -- tJH thold_TDI_TCK : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( OPTR : IN std_ulogic := 'U'; OPTL : IN std_ulogic := 'U'; RWR : IN std_ulogic := 'U'; RWL : IN std_ulogic := 'U'; CE1R : IN std_ulogic := 'U'; CE1L : IN std_ulogic := 'U'; PIPER : IN std_ulogic := 'H'; PIPEL : IN std_ulogic := 'H'; CLKR : IN std_ulogic := 'U'; CLKL : IN std_ulogic := 'U'; CNTENRNeg : IN std_ulogic := 'U'; CNTENLNeg : IN std_ulogic := 'U'; REPEATRNeg : IN std_ulogic := 'U'; REPEATLNeg : IN std_ulogic := 'U'; ADSRNeg : IN std_ulogic := 'U'; ADSLNeg : IN std_ulogic := 'U'; CE0RNeg : IN std_ulogic := 'U'; CE0LNeg : IN std_ulogic := 'U'; OERNeg : IN std_ulogic := 'U'; OELNeg : IN std_ulogic := 'U'; BE3RNeg : IN std_ulogic := 'U'; BE2RNeg : IN std_ulogic := 'U'; BE1RNeg : IN std_ulogic := 'U'; BE0RNeg : IN std_ulogic := 'U'; BE3LNeg : IN std_ulogic := 'U'; BE2LNeg : IN std_ulogic := 'U'; BE1LNeg : IN std_ulogic := 'U'; BE0LNeg : IN std_ulogic := 'U'; IOR35 : INOUT std_ulogic := 'U'; IOR34 : INOUT std_ulogic := 'U'; IOR33 : INOUT std_ulogic := 'U'; IOR32 : INOUT std_ulogic := 'U'; IOR31 : INOUT std_ulogic := 'U'; IOR30 : INOUT std_ulogic := 'U'; IOR29 : INOUT std_ulogic := 'U'; IOR28 : INOUT std_ulogic := 'U'; IOR27 : INOUT std_ulogic := 'U'; IOR26 : INOUT std_ulogic := 'U'; IOR25 : INOUT std_ulogic := 'U'; IOR24 : INOUT std_ulogic := 'U'; IOR23 : INOUT std_ulogic := 'U'; IOR22 : INOUT std_ulogic := 'U'; IOR21 : INOUT std_ulogic := 'U'; IOR20 : INOUT std_ulogic := 'U'; IOR19 : INOUT std_ulogic := 'U'; IOR18 : INOUT std_ulogic := 'U'; IOR17 : INOUT std_ulogic := 'U'; IOR16 : INOUT std_ulogic := 'U'; IOR15 : INOUT std_ulogic := 'U'; IOR14 : INOUT std_ulogic := 'U'; IOR13 : INOUT std_ulogic := 'U'; IOR12 : INOUT std_ulogic := 'U'; IOR11 : INOUT std_ulogic := 'U'; IOR10 : INOUT std_ulogic := 'U'; IOR9 : INOUT std_ulogic := 'U'; IOR8 : INOUT std_ulogic := 'U'; IOR7 : INOUT std_ulogic := 'U'; IOR6 : INOUT std_ulogic := 'U'; IOR5 : INOUT std_ulogic := 'U'; IOR4 : INOUT std_ulogic := 'U'; IOR3 : INOUT std_ulogic := 'U'; IOR2 : INOUT std_ulogic := 'U'; IOR1 : INOUT std_ulogic := 'U'; IOR0 : INOUT std_ulogic := 'U'; IOL35 : INOUT std_ulogic := 'U'; IOL34 : INOUT std_ulogic := 'U'; IOL33 : INOUT std_ulogic := 'U'; IOL32 : INOUT std_ulogic := 'U'; IOL31 : INOUT std_ulogic := 'U'; IOL30 : INOUT std_ulogic := 'U'; IOL29 : INOUT std_ulogic := 'U'; IOL28 : INOUT std_ulogic := 'U'; IOL27 : INOUT std_ulogic := 'U'; IOL26 : INOUT std_ulogic := 'U'; IOL25 : INOUT std_ulogic := 'U'; IOL24 : INOUT std_ulogic := 'U'; IOL23 : INOUT std_ulogic := 'U'; IOL22 : INOUT std_ulogic := 'U'; IOL21 : INOUT std_ulogic := 'U'; IOL20 : INOUT std_ulogic := 'U'; IOL19 : INOUT std_ulogic := 'U'; IOL18 : INOUT std_ulogic := 'U'; IOL17 : INOUT std_ulogic := 'U'; IOL16 : INOUT std_ulogic := 'U'; IOL15 : INOUT std_ulogic := 'U'; IOL14 : INOUT std_ulogic := 'U'; IOL13 : INOUT std_ulogic := 'U'; IOL12 : INOUT std_ulogic := 'U'; IOL11 : INOUT std_ulogic := 'U'; IOL10 : INOUT std_ulogic := 'U'; IOL9 : INOUT std_ulogic := 'U'; IOL8 : INOUT std_ulogic := 'U'; IOL7 : INOUT std_ulogic := 'U'; IOL6 : INOUT std_ulogic := 'U'; IOL5 : INOUT std_ulogic := 'U'; IOL4 : INOUT std_ulogic := 'U'; IOL3 : INOUT std_ulogic := 'U'; IOL2 : INOUT std_ulogic := 'U'; IOL1 : INOUT std_ulogic := 'U'; IOL0 : INOUT std_ulogic := 'U'; AR0 : IN std_ulogic := 'U'; AR1 : IN std_ulogic := 'U'; AR2 : IN std_ulogic := 'U'; AR3 : IN std_ulogic := 'U'; AR4 : IN std_ulogic := 'U'; AR5 : IN std_ulogic := 'U'; AR6 : IN std_ulogic := 'U'; AR7 : IN std_ulogic := 'U'; AR8 : IN std_ulogic := 'U'; AR9 : IN std_ulogic := 'U'; AR10 : IN std_ulogic := 'U'; AR11 : IN std_ulogic := 'U'; AR12 : IN std_ulogic := 'U'; AR13 : IN std_ulogic := 'U'; AR14 : IN std_ulogic := 'U'; AR15 : IN std_ulogic := 'U'; AR16 : IN std_ulogic := 'U'; AL0 : IN std_ulogic := 'U'; AL1 : IN std_ulogic := 'U'; AL2 : IN std_ulogic := 'U'; AL3 : IN std_ulogic := 'U'; AL4 : IN std_ulogic := 'U'; AL5 : IN std_ulogic := 'U'; AL6 : IN std_ulogic := 'U'; AL7 : IN std_ulogic := 'U'; AL8 : IN std_ulogic := 'U'; AL9 : IN std_ulogic := 'U'; AL10 : IN std_ulogic := 'U'; AL11 : IN std_ulogic := 'U'; AL12 : IN std_ulogic := 'U'; AL13 : IN std_ulogic := 'U'; AL14 : IN std_ulogic := 'U'; AL15 : IN std_ulogic := 'U'; AL16 : IN std_ulogic := 'U'; TDI : IN std_ulogic := 'U'; TCK : IN std_ulogic := 'U'; TMS : IN std_ulogic := 'U'; TRSTNeg : IN std_ulogic := 'U'; TDO : OUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt703599 : ENTITY IS TRUE; END idt703599; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of idt703599 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "IDT703599"; CONSTANT MaxData : NATURAL := 511; CONSTANT TotalLOC : NATURAL := 131071; CONSTANT HiAbit : NATURAL := 16; CONSTANT HiDbit : NATURAL := 8; CONSTANT DataWidth : NATURAL := 9; CONSTANT bsr_size : NATURAL := 142; CONSTANT jtagID : std_logic_vector(31 downto 0) := "00000000001100010010000001100111"; SIGNAL OPTR_ipd : std_ulogic := 'U'; SIGNAL OPTL_ipd : std_ulogic := 'U'; SIGNAL RWR_ipd : std_ulogic := 'U'; SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL CE1R_ipd : std_ulogic := 'U'; SIGNAL CE1L_ipd : std_ulogic := 'U'; SIGNAL PIPER_ipd : std_ulogic := 'U'; SIGNAL PIPEL_ipd : std_ulogic := 'U'; SIGNAL CLKR_ipd : std_ulogic := 'U'; SIGNAL CLKL_ipd : std_ulogic := 'U'; SIGNAL CNTENRNeg_ipd : std_ulogic := 'U'; SIGNAL CNTENLNeg_ipd : std_ulogic := 'U'; SIGNAL REPEATRNeg_ipd : std_ulogic := 'U'; SIGNAL REPEATLNeg_ipd : std_ulogic := 'U'; SIGNAL ADSRNeg_ipd : std_ulogic := 'U'; SIGNAL ADSLNeg_ipd : std_ulogic := 'U'; SIGNAL CE0RNeg_ipd : std_ulogic := 'U'; SIGNAL CE0LNeg_ipd : std_ulogic := 'U'; SIGNAL OERNeg_ipd : std_ulogic := 'U'; SIGNAL OELNeg_ipd : std_ulogic := 'U'; SIGNAL BE3RNeg_ipd : std_ulogic := 'U'; SIGNAL BE2RNeg_ipd : std_ulogic := 'U'; SIGNAL BE1RNeg_ipd : std_ulogic := 'U'; SIGNAL BE0RNeg_ipd : std_ulogic := 'U'; SIGNAL BE3LNeg_ipd : std_ulogic := 'U'; SIGNAL BE2LNeg_ipd : std_ulogic := 'U'; SIGNAL BE1LNeg_ipd : std_ulogic := 'U'; SIGNAL BE0LNeg_ipd : std_ulogic := 'U'; SIGNAL IOR35_ipd : std_ulogic := 'U'; SIGNAL IOR34_ipd : std_ulogic := 'U'; SIGNAL IOR33_ipd : std_ulogic := 'U'; SIGNAL IOR32_ipd : std_ulogic := 'U'; SIGNAL IOR31_ipd : std_ulogic := 'U'; SIGNAL IOR30_ipd : std_ulogic := 'U'; SIGNAL IOR29_ipd : std_ulogic := 'U'; SIGNAL IOR28_ipd : std_ulogic := 'U'; SIGNAL IOR27_ipd : std_ulogic := 'U'; SIGNAL IOR26_ipd : std_ulogic := 'U'; SIGNAL IOR25_ipd : std_ulogic := 'U'; SIGNAL IOR24_ipd : std_ulogic := 'U'; SIGNAL IOR23_ipd : std_ulogic := 'U'; SIGNAL IOR22_ipd : std_ulogic := 'U'; SIGNAL IOR21_ipd : std_ulogic := 'U'; SIGNAL IOR20_ipd : std_ulogic := 'U'; SIGNAL IOR19_ipd : std_ulogic := 'U'; SIGNAL IOR18_ipd : std_ulogic := 'U'; SIGNAL IOR17_ipd : std_ulogic := 'U'; SIGNAL IOR16_ipd : std_ulogic := 'U'; SIGNAL IOR15_ipd : std_ulogic := 'U'; SIGNAL IOR14_ipd : std_ulogic := 'U'; SIGNAL IOR13_ipd : std_ulogic := 'U'; SIGNAL IOR12_ipd : std_ulogic := 'U'; SIGNAL IOR11_ipd : std_ulogic := 'U'; SIGNAL IOR10_ipd : std_ulogic := 'U'; SIGNAL IOR9_ipd : std_ulogic := 'U'; SIGNAL IOR8_ipd : std_ulogic := 'U'; SIGNAL IOR7_ipd : std_ulogic := 'U'; SIGNAL IOR6_ipd : std_ulogic := 'U'; SIGNAL IOR5_ipd : std_ulogic := 'U'; SIGNAL IOR4_ipd : std_ulogic := 'U'; SIGNAL IOR3_ipd : std_ulogic := 'U'; SIGNAL IOR2_ipd : std_ulogic := 'U'; SIGNAL IOR1_ipd : std_ulogic := 'U'; SIGNAL IOR0_ipd : std_ulogic := 'U'; SIGNAL IOL35_ipd : std_ulogic := 'U'; SIGNAL IOL34_ipd : std_ulogic := 'U'; SIGNAL IOL33_ipd : std_ulogic := 'U'; SIGNAL IOL32_ipd : std_ulogic := 'U'; SIGNAL IOL31_ipd : std_ulogic := 'U'; SIGNAL IOL30_ipd : std_ulogic := 'U'; SIGNAL IOL29_ipd : std_ulogic := 'U'; SIGNAL IOL28_ipd : std_ulogic := 'U'; SIGNAL IOL27_ipd : std_ulogic := 'U'; SIGNAL IOL26_ipd : std_ulogic := 'U'; SIGNAL IOL25_ipd : std_ulogic := 'U'; SIGNAL IOL24_ipd : std_ulogic := 'U'; SIGNAL IOL23_ipd : std_ulogic := 'U'; SIGNAL IOL22_ipd : std_ulogic := 'U'; SIGNAL IOL21_ipd : std_ulogic := 'U'; SIGNAL IOL20_ipd : std_ulogic := 'U'; SIGNAL IOL19_ipd : std_ulogic := 'U'; SIGNAL IOL18_ipd : std_ulogic := 'U'; SIGNAL IOL17_ipd : std_ulogic := 'U'; SIGNAL IOL16_ipd : std_ulogic := 'U'; SIGNAL IOL15_ipd : std_ulogic := 'U'; SIGNAL IOL14_ipd : std_ulogic := 'U'; SIGNAL IOL13_ipd : std_ulogic := 'U'; SIGNAL IOL12_ipd : std_ulogic := 'U'; SIGNAL IOL11_ipd : std_ulogic := 'U'; SIGNAL IOL10_ipd : std_ulogic := 'U'; SIGNAL IOL9_ipd : std_ulogic := 'U'; SIGNAL IOL8_ipd : std_ulogic := 'U'; SIGNAL IOL7_ipd : std_ulogic := 'U'; SIGNAL IOL6_ipd : std_ulogic := 'U'; SIGNAL IOL5_ipd : std_ulogic := 'U'; SIGNAL IOL4_ipd : std_ulogic := 'U'; SIGNAL IOL3_ipd : std_ulogic := 'U'; SIGNAL IOL2_ipd : std_ulogic := 'U'; SIGNAL IOL1_ipd : std_ulogic := 'U'; SIGNAL IOL0_ipd : std_ulogic := 'U'; SIGNAL AR0_ipd : std_ulogic := 'U'; SIGNAL AR1_ipd : std_ulogic := 'U'; SIGNAL AR2_ipd : std_ulogic := 'U'; SIGNAL AR3_ipd : std_ulogic := 'U'; SIGNAL AR4_ipd : std_ulogic := 'U'; SIGNAL AR5_ipd : std_ulogic := 'U'; SIGNAL AR6_ipd : std_ulogic := 'U'; SIGNAL AR7_ipd : std_ulogic := 'U'; SIGNAL AR8_ipd : std_ulogic := 'U'; SIGNAL AR9_ipd : std_ulogic := 'U'; SIGNAL AR10_ipd : std_ulogic := 'U'; SIGNAL AR11_ipd : std_ulogic := 'U'; SIGNAL AR12_ipd : std_ulogic := 'U'; SIGNAL AR13_ipd : std_ulogic := 'U'; SIGNAL AR14_ipd : std_ulogic := 'U'; SIGNAL AR15_ipd : std_ulogic := 'U'; SIGNAL AR16_ipd : std_ulogic := 'U'; SIGNAL AL0_ipd : std_ulogic := 'U'; SIGNAL AL1_ipd : std_ulogic := 'U'; SIGNAL AL2_ipd : std_ulogic := 'U'; SIGNAL AL3_ipd : std_ulogic := 'U'; SIGNAL AL4_ipd : std_ulogic := 'U'; SIGNAL AL5_ipd : std_ulogic := 'U'; SIGNAL AL6_ipd : std_ulogic := 'U'; SIGNAL AL7_ipd : std_ulogic := 'U'; SIGNAL AL8_ipd : std_ulogic := 'U'; SIGNAL AL9_ipd : std_ulogic := 'U'; SIGNAL AL10_ipd : std_ulogic := 'U'; SIGNAL AL11_ipd : std_ulogic := 'U'; SIGNAL AL12_ipd : std_ulogic := 'U'; SIGNAL AL13_ipd : std_ulogic := 'U'; SIGNAL AL14_ipd : std_ulogic := 'U'; SIGNAL AL15_ipd : std_ulogic := 'U'; SIGNAL AL16_ipd : std_ulogic := 'U'; SIGNAL TDI_ipd : std_ulogic := 'U'; SIGNAL TCK_ipd : std_ulogic := 'U'; SIGNAL TMS_ipd : std_ulogic := 'U'; SIGNAL TRSTNeg_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR); w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL); w_3 : VitalWireDelay (CE1R_ipd, CE1R, tipd_CE1R); w_4 : VitalWireDelay (CE1L_ipd, CE1L, tipd_CE1L); w_5 : VitalWireDelay (PIPER_ipd, PIPER, tipd_PIPER); w_6 : VitalWireDelay (PIPEL_ipd, PIPEL, tipd_PIPEL); w_7 : VitalWireDelay (CLKR_ipd, CLKR, tipd_CLKR); w_8 : VitalWireDelay (CLKL_ipd, CLKL, tipd_CLKL); w_9 : VitalWireDelay (CNTENRNeg_ipd, CNTENRNeg, tipd_CNTENRNeg); w_10 : VitalWireDelay (CNTENLNeg_ipd, CNTENLNeg, tipd_CNTENLNeg); w_11 : VitalWireDelay (REPEATRNeg_ipd, REPEATRNeg, tipd_REPEATRNeg); w_12 : VitalWireDelay (REPEATLNeg_ipd, REPEATLNeg, tipd_REPEATLNeg); w_13 : VitalWireDelay (ADSRNeg_ipd, ADSRNeg, tipd_ADSRNeg); w_14 : VitalWireDelay (ADSLNeg_ipd, ADSLNeg, tipd_ADSLNeg); w_15 : VitalWireDelay (CE0RNeg_ipd, CE0RNeg, tipd_CE0RNeg); w_16 : VitalWireDelay (CE0LNeg_ipd, CE0LNeg, tipd_CE0LNeg); w_17 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg); w_18 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg); w_19a : VitalWireDelay (BE3RNeg_ipd, BE3RNeg, tipd_BE3RNeg); w_19b : VitalWireDelay (BE2RNeg_ipd, BE2RNeg, tipd_BE2RNeg); w_19 : VitalWireDelay (BE1RNeg_ipd, BE1RNeg, tipd_BE1RNeg); w_20 : VitalWireDelay (BE0RNeg_ipd, BE0RNeg, tipd_BE0RNeg); w_21a : VitalWireDelay (BE3LNeg_ipd, BE3LNeg, tipd_BE3LNeg); w_21b : VitalWireDelay (BE2LNeg_ipd, BE2LNeg, tipd_BE2LNeg); w_21 : VitalWireDelay (BE1LNeg_ipd, BE1LNeg, tipd_BE1LNeg); w_22 : VitalWireDelay (BE0LNeg_ipd, BE0LNeg, tipd_BE0LNeg); w_23 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0); w_24 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1); w_25 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2); w_26 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3); w_27 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4); w_28 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5); w_29 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6); w_30 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7); w_31 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8); w_32 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9); w_33 : VitalWireDelay (AR10_ipd, AR10, tipd_AR10); w_34 : VitalWireDelay (AR11_ipd, AR11, tipd_AR11); w_35 : VitalWireDelay (AR12_ipd, AR12, tipd_AR12); w_36 : VitalWireDelay (AR13_ipd, AR13, tipd_AR13); w_37 : VitalWireDelay (AR14_ipd, AR14, tipd_AR14); w_38 : VitalWireDelay (AR15_ipd, AR15, tipd_AR15); w_39 : VitalWireDelay (AR16_ipd, AR16, tipd_AR16); w_41 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0); w_42 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1); w_43 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2); w_44 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3); w_45 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4); w_46 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5); w_47 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6); w_48 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7); w_49 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8); w_50 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9); w_51 : VitalWireDelay (AL10_ipd, AL10, tipd_AL10); w_52 : VitalWireDelay (AL11_ipd, AL11, tipd_AL11); w_53 : VitalWireDelay (AL12_ipd, AL12, tipd_AL12); w_54 : VitalWireDelay (AL13_ipd, AL13, tipd_AL13); w_55 : VitalWireDelay (AL14_ipd, AL14, tipd_AL14); w_56 : VitalWireDelay (AL15_ipd, AL15, tipd_AL15); w_57 : VitalWireDelay (AL16_ipd, AL16, tipd_AL16); w_58 : VitalWireDelay (IOR35_ipd, IOR35, tipd_IOR35); w_59 : VitalWireDelay (IOR34_ipd, IOR34, tipd_IOR34); w_60 : VitalWireDelay (IOR33_ipd, IOR33, tipd_IOR33); w_61 : VitalWireDelay (IOR32_ipd, IOR32, tipd_IOR32); w_62 : VitalWireDelay (IOR31_ipd, IOR31, tipd_IOR31); w_63 : VitalWireDelay (IOR30_ipd, IOR30, tipd_IOR30); w_64 : VitalWireDelay (IOR29_ipd, IOR29, tipd_IOR29); w_65 : VitalWireDelay (IOR28_ipd, IOR28, tipd_IOR28); w_66 : VitalWireDelay (IOR27_ipd, IOR27, tipd_IOR27); w_67 : VitalWireDelay (IOR26_ipd, IOR26, tipd_IOR26); w_68 : VitalWireDelay (IOR25_ipd, IOR25, tipd_IOR25); w_69 : VitalWireDelay (IOR24_ipd, IOR24, tipd_IOR24); w_70 : VitalWireDelay (IOR23_ipd, IOR23, tipd_IOR23); w_71 : VitalWireDelay (IOR22_ipd, IOR22, tipd_IOR22); w_72 : VitalWireDelay (IOR21_ipd, IOR21, tipd_IOR21); w_73 : VitalWireDelay (IOR20_ipd, IOR20, tipd_IOR20); w_74 : VitalWireDelay (IOR19_ipd, IOR19, tipd_IOR19); w_75 : VitalWireDelay (IOR18_ipd, IOR18, tipd_IOR18); w_76 : VitalWireDelay (IOR17_ipd, IOR17, tipd_IOR17); w_77 : VitalWireDelay (IOR16_ipd, IOR16, tipd_IOR16); w_78 : VitalWireDelay (IOR15_ipd, IOR15, tipd_IOR15); w_79 : VitalWireDelay (IOR14_ipd, IOR14, tipd_IOR14); w_80 : VitalWireDelay (IOR13_ipd, IOR13, tipd_IOR13); w_81 : VitalWireDelay (IOR12_ipd, IOR12, tipd_IOR12); w_82 : VitalWireDelay (IOR11_ipd, IOR11, tipd_IOR11); w_83 : VitalWireDelay (IOR10_ipd, IOR10, tipd_IOR10); w_84 : VitalWireDelay (IOR9_ipd, IOR9, tipd_IOR9); w_85 : VitalWireDelay (IOR8_ipd, IOR8, tipd_IOR8); w_86 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7); w_87 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6); w_88 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5); w_89 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4); w_90 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3); w_91 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2); w_92 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1); w_93 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0); w_94 : VitalWireDelay (IOL35_ipd, IOL35, tipd_IOL35); w_95 : VitalWireDelay (IOL34_ipd, IOL34, tipd_IOL34); w_96 : VitalWireDelay (IOL33_ipd, IOL33, tipd_IOL33); w_97 : VitalWireDelay (IOL32_ipd, IOL32, tipd_IOL32); w_98 : VitalWireDelay (IOL31_ipd, IOL31, tipd_IOL31); w_99 : VitalWireDelay (IOL30_ipd, IOL30, tipd_IOL30); w_101 : VitalWireDelay (IOL29_ipd, IOL29, tipd_IOL29); w_102 : VitalWireDelay (IOL28_ipd, IOL28, tipd_IOL28); w_103 : VitalWireDelay (IOL27_ipd, IOL27, tipd_IOL27); w_104 : VitalWireDelay (IOL26_ipd, IOL26, tipd_IOL26); w_105 : VitalWireDelay (IOL25_ipd, IOL25, tipd_IOL25); w_106 : VitalWireDelay (IOL24_ipd, IOL24, tipd_IOL24); w_107 : VitalWireDelay (IOL23_ipd, IOL23, tipd_IOL23); w_108 : VitalWireDelay (IOL22_ipd, IOL22, tipd_IOL22); w_109 : VitalWireDelay (IOL21_ipd, IOL21, tipd_IOL21); w_110 : VitalWireDelay (IOL20_ipd, IOL20, tipd_IOL20); w_111 : VitalWireDelay (IOL19_ipd, IOL19, tipd_IOL19); w_112 : VitalWireDelay (IOL18_ipd, IOL18, tipd_IOL18); w_113 : VitalWireDelay (IOL17_ipd, IOL17, tipd_IOL17); w_114 : VitalWireDelay (IOL16_ipd, IOL16, tipd_IOL16); w_115 : VitalWireDelay (IOL15_ipd, IOL15, tipd_IOL15); w_116 : VitalWireDelay (IOL14_ipd, IOL14, tipd_IOL14); w_117 : VitalWireDelay (IOL13_ipd, IOL13, tipd_IOL13); w_118 : VitalWireDelay (IOL12_ipd, IOL12, tipd_IOL12); w_119 : VitalWireDelay (IOL11_ipd, IOL11, tipd_IOL11); w_120 : VitalWireDelay (IOL10_ipd, IOL10, tipd_IOL10); w_121 : VitalWireDelay (IOL9_ipd, IOL9, tipd_IOL9); w_122 : VitalWireDelay (IOL8_ipd, IOL8, tipd_IOL8); w_123 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7); w_124 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6); w_125 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5); w_126 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4); w_127 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3); w_128 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2); w_129 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1); w_130 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0); w_131 : VitalWireDelay (TDI_ipd, TDI, tipd_TDI); w_132 : VitalWireDelay (TCK_ipd, TCK, tipd_TCK); w_133 : VitalWireDelay (TMS_ipd, TMS, tipd_TMS); w_134 : VitalWireDelay (TRSTNeg_ipd, TRSTNeg, tipd_TRSTNeg); w_135 : VitalWireDelay (OPTR_ipd, OPTR, tipd_OPTR); w_136 : VitalWireDelay (OPTL_ipd, OPTL, tipd_OPTL); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ALIn : IN std_logic_vector(HiAbit downto 0); ARIn : IN std_logic_vector(HiAbit downto 0); IOL3In : IN std_logic_vector(HiDbit downto 0); IOR3In : IN std_logic_vector(HiDbit downto 0); IOL2In : IN std_logic_vector(HiDbit downto 0); IOR2In : IN std_logic_vector(HiDbit downto 0); IOL1In : IN std_logic_vector(HiDbit downto 0); IOR1In : IN std_logic_vector(HiDbit downto 0); IOL0In : IN std_logic_vector(HiDbit downto 0); IOR0In : IN std_logic_vector(HiDbit downto 0); IOL3Out : OUT std_logic_vector(HiDbit downto 0); IOR3Out : OUT std_logic_vector(HiDbit downto 0); IOL2Out : OUT std_logic_vector(HiDbit downto 0); IOR2Out : OUT std_logic_vector(HiDbit downto 0); IOL1Out : OUT std_logic_vector(HiDbit downto 0); IOR1Out : OUT std_logic_vector(HiDbit downto 0); IOL0Out : OUT std_logic_vector(HiDbit downto 0); IOR0Out : OUT std_logic_vector(HiDbit downto 0); OPTRIn : IN std_ulogic := 'U'; OPTLIn : IN std_ulogic := 'U'; RWLIn : IN std_ulogic := 'U'; RWRIn : IN std_ulogic := 'U'; OELNegIn : IN std_ulogic := 'U'; OERNegIn : IN std_ulogic := 'U'; BE3LNegIn : IN std_ulogic := 'U'; BE2LNegIn : IN std_ulogic := 'U'; BE1LNegIn : IN std_ulogic := 'U'; BE0LNegIn : IN std_ulogic := 'U'; BE3RNegIn : IN std_ulogic := 'U'; BE2RNegIn : IN std_ulogic := 'U'; BE1RNegIn : IN std_ulogic := 'U'; BE0RNegIn : IN std_ulogic := 'U'; CE0LNegIn : IN std_ulogic := 'U'; CE0RNegIn : IN std_ulogic := 'U'; CE1LIn : IN std_ulogic := 'U'; CE1RIn : IN std_ulogic := 'U'; CLKLIn : IN std_ulogic := 'U'; CLKRIn : IN std_ulogic := 'U'; REPEATLNegIn : IN std_ulogic := 'U'; REPEATRNegIn : IN std_ulogic := 'U'; CNTENRNegIn : IN std_ulogic := 'U'; CNTENLNegIn : IN std_ulogic := 'U'; ADSRNegIn : IN std_ulogic := 'U'; ADSLNegIn : IN std_ulogic := 'U'; PIPERIn : IN std_ulogic := '1'; PIPELIn : IN std_ulogic := '1'; TDIIn : IN std_ulogic := '1'; TCKIn : IN std_ulogic := '1'; TMSIn : IN std_ulogic := '1'; TRSTNegIn : IN std_ulogic := '1' ); PORT MAP ( ALIn(0) => AL0_ipd, ALIn(1) => AL1_ipd, ALIn(2) => AL2_ipd, ALIn(3) => AL3_ipd, ALIn(4) => AL4_ipd, ALIn(5) => AL5_ipd, ALIn(6) => AL6_ipd, ALIn(7) => AL7_ipd, ALIn(8) => AL8_ipd, ALIn(9) => AL9_ipd, ALIn(10) => AL10_ipd, ALIn(11) => AL11_ipd, ALIn(12) => AL12_ipd, ALIn(13) => AL13_ipd, ALIn(14) => AL14_ipd, ALIn(15) => AL15_ipd, ALIn(16) => AL16_ipd, ARIn(0) => AR0_ipd, ARIn(1) => AR1_ipd, ARIn(2) => AR2_ipd, ARIn(3) => AR3_ipd, ARIn(4) => AR4_ipd, ARIn(5) => AR5_ipd, ARIn(6) => AR6_ipd, ARIn(7) => AR7_ipd, ARIn(8) => AR8_ipd, ARIn(9) => AR9_ipd, ARIn(10) => AR10_ipd, ARIn(11) => AR11_ipd, ARIn(12) => AR12_ipd, ARIn(13) => AR13_ipd, ARIn(14) => AR14_ipd, ARIn(15) => AR15_ipd, ARIn(16) => AR16_ipd, IOL0In(0) => IOL0_ipd, IOL0In(1) => IOL1_ipd, IOL0In(2) => IOL2_ipd, IOL0In(3) => IOL3_ipd, IOL0In(4) => IOL4_ipd, IOL0In(5) => IOL5_ipd, IOL0In(6) => IOL6_ipd, IOL0In(7) => IOL7_ipd, IOL0In(8) => IOL8_ipd, IOL1In(0) => IOL9_ipd, IOL1In(1) => IOL10_ipd, IOL1In(2) => IOL11_ipd, IOL1In(3) => IOL12_ipd, IOL1In(4) => IOL13_ipd, IOL1In(5) => IOL14_ipd, IOL1In(6) => IOL15_ipd, IOL1In(7) => IOL16_ipd, IOL1In(8) => IOL17_ipd, IOL2In(0) => IOL18_ipd, IOL2In(1) => IOL19_ipd, IOL2In(2) => IOL20_ipd, IOL2In(3) => IOL21_ipd, IOL2In(4) => IOL22_ipd, IOL2In(5) => IOL23_ipd, IOL2In(6) => IOL24_ipd, IOL2In(7) => IOL25_ipd, IOL2In(8) => IOL26_ipd, IOL3In(0) => IOL27_ipd, IOL3In(1) => IOL28_ipd, IOL3In(2) => IOL29_ipd, IOL3In(3) => IOL30_ipd, IOL3In(4) => IOL31_ipd, IOL3In(5) => IOL32_ipd, IOL3In(6) => IOL33_ipd, IOL3In(7) => IOL34_ipd, IOL3In(8) => IOL35_ipd, IOR0In(0) => IOR0_ipd, IOR0In(1) => IOR1_ipd, IOR0In(2) => IOR2_ipd, IOR0In(3) => IOR3_ipd, IOR0In(4) => IOR4_ipd, IOR0In(5) => IOR5_ipd, IOR0In(6) => IOR6_ipd, IOR0In(7) => IOR7_ipd, IOR0In(8) => IOR8_ipd, IOR1In(0) => IOR9_ipd, IOR1In(1) => IOR10_ipd, IOR1In(2) => IOR11_ipd, IOR1In(3) => IOR12_ipd, IOR1In(4) => IOR13_ipd, IOR1In(5) => IOR14_ipd, IOR1In(6) => IOR15_ipd, IOR1In(7) => IOR16_ipd, IOR1In(8) => IOR17_ipd, IOR2In(0) => IOR18_ipd, IOR2In(1) => IOR19_ipd, IOR2In(2) => IOR20_ipd, IOR2In(3) => IOR21_ipd, IOR2In(4) => IOR22_ipd, IOR2In(5) => IOR23_ipd, IOR2In(6) => IOR24_ipd, IOR2In(7) => IOR25_ipd, IOR2In(8) => IOR26_ipd, IOR3In(0) => IOR27_ipd, IOR3In(1) => IOR28_ipd, IOR3In(2) => IOR29_ipd, IOR3In(3) => IOR30_ipd, IOR3In(4) => IOR31_ipd, IOR3In(5) => IOR32_ipd, IOR3In(6) => IOR33_ipd, IOR3In(7) => IOR34_ipd, IOR3In(8) => IOR35_ipd, IOL0Out(0) => IOL0, IOL0Out(1) => IOL1, IOL0Out(2) => IOL2, IOL0Out(3) => IOL3, IOL0Out(4) => IOL4, IOL0Out(5) => IOL5, IOL0Out(6) => IOL6, IOL0Out(7) => IOL7, IOL0Out(8) => IOL8, IOL1Out(0) => IOL9, IOL1Out(1) => IOL10, IOL1Out(2) => IOL11, IOL1Out(3) => IOL12, IOL1Out(4) => IOL13, IOL1Out(5) => IOL14, IOL1Out(6) => IOL15, IOL1Out(7) => IOL16, IOL1Out(8) => IOL17, IOL2Out(0) => IOL18, IOL2Out(1) => IOL19, IOL2Out(2) => IOL20, IOL2Out(3) => IOL21, IOL2Out(4) => IOL22, IOL2Out(5) => IOL23, IOL2Out(6) => IOL24, IOL2Out(7) => IOL25, IOL2Out(8) => IOL26, IOL3Out(0) => IOL27, IOL3Out(1) => IOL28, IOL3Out(2) => IOL29, IOL3Out(3) => IOL30, IOL3Out(4) => IOL31, IOL3Out(5) => IOL32, IOL3Out(6) => IOL33, IOL3Out(7) => IOL34, IOL3Out(8) => IOL35, IOR0Out(0) => IOR0, IOR0Out(1) => IOR1, IOR0Out(2) => IOR2, IOR0Out(3) => IOR3, IOR0Out(4) => IOR4, IOR0Out(5) => IOR5, IOR0Out(6) => IOR6, IOR0Out(7) => IOR7, IOR0Out(8) => IOR8, IOR1Out(0) => IOR9, IOR1Out(1) => IOR10, IOR1Out(2) => IOR11, IOR1Out(3) => IOR12, IOR1Out(4) => IOR13, IOR1Out(5) => IOR14, IOR1Out(6) => IOR15, IOR1Out(7) => IOR16, IOR1Out(8) => IOR17, IOR2Out(0) => IOR18, IOR2Out(1) => IOR19, IOR2Out(2) => IOR20, IOR2Out(3) => IOR21, IOR2Out(4) => IOR22, IOR2Out(5) => IOR23, IOR2Out(6) => IOR24, IOR2Out(7) => IOR25, IOR2Out(8) => IOR26, IOR3Out(0) => IOR27, IOR3Out(1) => IOR28, IOR3Out(2) => IOR29, IOR3Out(3) => IOR30, IOR3Out(4) => IOR31, IOR3Out(5) => IOR32, IOR3Out(6) => IOR33, IOR3Out(7) => IOR34, IOR3Out(8) => IOR35, OPTRIn => OPTR_ipd, OPTLIn => OPTL_ipd, RWLIn => RWL_ipd, RWRIn => RWR_ipd, OELNegIn => OELNeg_ipd, OERNegIn => OERNeg_ipd, BE3RNegIn => BE3RNeg_ipd, BE2RNegIn => BE2RNeg_ipd, BE1RNegIn => BE1RNeg_ipd, BE0RNegIn => BE0RNeg_ipd, BE3LNegIn => BE3LNeg_ipd, BE2LNegIn => BE2LNeg_ipd, BE1LNegIn => BE1LNeg_ipd, BE0LNegIn => BE0LNeg_ipd, CE0LNegIn => CE0LNeg_ipd, CE0RNegIn => CE0RNeg_ipd, CE1LIn => CE1L_ipd, CE1RIn => CE1R_ipd, CLKLIn => CLKL_ipd, CLKRIn => CLKR_ipd, REPEATLNegIn => REPEATLNeg_ipd, REPEATRNegIn => REPEATRNeg_ipd, CNTENRNegIn => CNTENRNeg_ipd, CNTENLNegIn => CNTENLNeg_ipd, ADSRNegIn => ADSRNeg_ipd, ADSLNegIn => ADSLNeg_ipd, PIPELIn => to_UX01(PIPEL_ipd), PIPERIn => to_UX01(PIPER_ipd), TDIIn => to_UX01(TDI_ipd), TCKIn => to_UX01(TCK_ipd), TMSIn => to_UX01(TMS_ipd), TRSTNegIn => to_UX01(TRSTNeg_ipd) ); SIGNAL IOL3_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOL2_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOL1_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOL0_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR3_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR2_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR1_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR0_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL BSR_READ : boolean := false; SIGNAL Tri_Outs : boolean := false; SIGNAL EXTST : boolean := false; SIGNAL bsr : std_logic_vector(bsr_size - 1 downto 0) := (OTHERS => '0'); BEGIN ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CE0LNegIn, CE0RNegIn, ALIn, ARIn, IOL0In, IOR0In, CE1LIn, CE1RIn, CLKLIn, CLKRIn, REPEATLNegIn, REPEATRNegIn, CNTENRNegIn, CNTENLNegIn, ADSRNegIn, ADSLNegIn, PIPERIn, PIPELIn, IOL1In, IOR1In, BE1RNegIn, BE1LNegIn, BE0RNegIn, BE0LNegIn, IOL2In, IOR2In, IOL3In, IOR3In, BE2RNegIn, BE2LNegIn, BE3RNegIn, BE3LNegIn, BSR_READ, Tri_Outs) -- Timing Check Variables VARIABLE Tviol_ALIn_CLKLIn : X01 := '0'; VARIABLE TD_ALIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_ARIn_CLKRIn : X01 := '0'; VARIABLE TD_ARIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CE0LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_CE0LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CE0RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_CE0RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CE1LIn_CLKLIn : X01 := '0'; VARIABLE TD_CE1LIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CE1RIn_CLKRIn : X01 := '0'; VARIABLE TD_CE1RIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_RWLIn_CLKLIn : X01 := '0'; VARIABLE TD_RWLIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_RWRIn_CLKRIn : X01 := '0'; VARIABLE TD_RWRIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_IOL3In_CLKLIn : X01 := '0'; VARIABLE TD_IOL3In_CLKLIn : VitalTimingDataType; VARIABLE Tviol_IOL2In_CLKLIn : X01 := '0'; VARIABLE TD_IOL2In_CLKLIn : VitalTimingDataType; VARIABLE Tviol_IOL1In_CLKLIn : X01 := '0'; VARIABLE TD_IOL1In_CLKLIn : VitalTimingDataType; VARIABLE Tviol_IOL0In_CLKLIn : X01 := '0'; VARIABLE TD_IOL0In_CLKLIn : VitalTimingDataType; VARIABLE Tviol_IOR3In_CLKRIn : X01 := '0'; VARIABLE TD_IOR3In_CLKRIn : VitalTimingDataType; VARIABLE Tviol_IOR2In_CLKRIn : X01 := '0'; VARIABLE TD_IOR2In_CLKRIn : VitalTimingDataType; VARIABLE Tviol_IOR1In_CLKRIn : X01 := '0'; VARIABLE TD_IOR1In_CLKRIn : VitalTimingDataType; VARIABLE Tviol_IOR0In_CLKRIn : X01 := '0'; VARIABLE TD_IOR0In_CLKRIn : VitalTimingDataType; VARIABLE Tviol_BE3RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_BE3RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_BE2RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_BE2RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_BE1RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_BE1RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_BE0RNegIn_CLKRIn : X01 := '0'; VARIABLE TD_BE0RNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_BE3LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_BE3LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_BE2LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_BE2LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_BE1LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_BE1LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_BE0LNegIn_CLKLIn : X01 := '0'; VARIABLE TD_BE0LNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_ADSLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_ADSLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_ADSRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_ADSRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_CNTENLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_CNTENLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_CNTENRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_CNTENRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Tviol_REPEATLNegIn_CLKLIn : X01 := '0'; VARIABLE TD_REPEATLNegIn_CLKLIn : VitalTimingDataType; VARIABLE Tviol_REPEATRNegIn_CLKRIn : X01 := '0'; VARIABLE TD_REPEATRNegIn_CLKRIn : VitalTimingDataType; VARIABLE Pviol_CLKLIn0 : X01 := '0'; VARIABLE TD_CLKLIn0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKRIn0 : X01 := '0'; VARIABLE TD_CLKRIn0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKLIn1 : X01 := '0'; VARIABLE TD_CLKLIn1 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CLKRIn1 : X01 := '0'; VARIABLE TD_CLKRIn1 : VitalPeriodDataType := VitalPeriodDataInit; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER RANGE -2 TO MaxData; VARIABLE DataL3Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL2Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL1Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL0Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR3Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR2Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR1Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR0Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGL3Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGL2Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGL1Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGL0Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGR3Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGR2Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGR1Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE JTAGR0Drive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL3tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL2tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL1tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataL0tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR3tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR2tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR1tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataR0tmp : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'Z'); VARIABLE DataTempL3 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempL2 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempL1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempL0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR3 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR2 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL3 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL2 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataL0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR3 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR2 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR1 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE WrtDataR0 : INTEGER RANGE -2 TO MaxData := -2; VARIABLE LocationL : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LocationR : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LastLocL : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE LastLocR : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE MemData3 : MemStore; VARIABLE MemData2 : MemStore; VARIABLE MemData1 : MemStore; VARIABLE MemData0 : MemStore; VARIABLE LatencyL : BOOLEAN; VARIABLE LatencyR : BOOLEAN; -- No Weak Values Variables VARIABLE CE0LNeg_nwv : UX01 := 'U'; VARIABLE CE0RNeg_nwv : UX01 := 'U'; VARIABLE CE1L_nwv : UX01 := 'U'; VARIABLE CE1R_nwv : UX01 := 'U'; VARIABLE CE0LNeg_reg : UX01 := 'U'; VARIABLE CE0RNeg_reg : UX01 := 'U'; VARIABLE CE1L_reg : UX01 := 'U'; VARIABLE CE1R_reg : UX01 := 'U'; VARIABLE RWR_nwv : UX01 := 'U'; VARIABLE RWL_nwv : UX01 := 'U'; VARIABLE ADSLNeg_nwv : UX01 := 'U'; VARIABLE ADSRNeg_nwv : UX01 := 'U'; VARIABLE OELNeg_nwv : UX01 := 'U'; VARIABLE OERNeg_nwv : UX01 := 'U'; VARIABLE BE3LNeg_nwv : UX01 := 'U'; VARIABLE BE2LNeg_nwv : UX01 := 'U'; VARIABLE BE1LNeg_nwv : UX01 := 'U'; VARIABLE BE0LNeg_nwv : UX01 := 'U'; VARIABLE BE3RNeg_nwv : UX01 := 'U'; VARIABLE BE2RNeg_nwv : UX01 := 'U'; VARIABLE BE1RNeg_nwv : UX01 := 'U'; VARIABLE BE0RNeg_nwv : UX01 := 'U'; VARIABLE BE3LNeg_reg : UX01 := 'U'; VARIABLE BE2LNeg_reg : UX01 := 'U'; VARIABLE BE1LNeg_reg : UX01 := 'U'; VARIABLE BE0LNeg_reg : UX01 := 'U'; VARIABLE BE3RNeg_reg : UX01 := 'U'; VARIABLE BE2RNeg_reg : UX01 := 'U'; VARIABLE BE1RNeg_reg : UX01 := 'U'; VARIABLE BE0RNeg_reg : UX01 := 'U'; VARIABLE REPEATLNeg_nwv : UX01 := 'U'; VARIABLE REPEATRNeg_nwv : UX01 := 'U'; VARIABLE CNTENLNeg_nwv : UX01 := 'U'; VARIABLE CNTENRNeg_nwv : UX01 := 'U'; BEGIN CE0LNeg_nwv := To_UX01 (s => CE0LNegIn); CE0RNeg_nwv := To_UX01 (s => CE0RNegIn); CE1L_nwv := To_UX01 (s => CE1LIn); CE1R_nwv := To_UX01 (s => CE1RIn); RWL_nwv := To_UX01 (s => RWLIn); RWR_nwv := To_UX01 (s => RWRIn); ADSLNeg_nwv := To_UX01 (s => ADSLNegIn); ADSRNeg_nwv := To_UX01 (s => ADSRNegIn); OELNeg_nwv := To_UX01 (s => OELNegIn); OERNeg_nwv := To_UX01 (s => OERNegIn); BE3LNeg_nwv := To_UX01 (s => BE3LNegIn); BE2LNeg_nwv := To_UX01 (s => BE2LNegIn); BE1LNeg_nwv := To_UX01 (s => BE1LNegIn); BE0LNeg_nwv := To_UX01 (s => BE0LNegIn); BE3RNeg_nwv := To_UX01 (s => BE3RNegIn); BE2RNeg_nwv := To_UX01 (s => BE2RNegIn); BE1RNeg_nwv := To_UX01 (s => BE1RNegIn); BE0RNeg_nwv := To_UX01 (s => BE0RNegIn); REPEATLNeg_nwv := To_UX01 (s => REPEATLNegIn); REPEATRNeg_nwv := To_UX01 (s => REPEATRNegIn); CNTENLNeg_nwv := To_UX01 (s => CNTENLNegIn); CNTENRNeg_nwv := To_UX01 (s => CNTENRNegIn); -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_AL0_CLKL, SetupLow => tsetup_AL0_CLKL, HoldHigh => thold_AL0_CLKL, HoldLow => thold_AL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE0LNegIn, TestSignalName => "CE0LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE0RNegIn, TestSignalName => "CE0RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE0RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE0RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CE1LIn, TestSignalName => "CE1L", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1LIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1LIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CE1RIn, TestSignalName => "CE1R", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CE1L_CLKL, SetupLow => tsetup_CE1L_CLKL, HoldHigh => thold_CE1L_CLKL, HoldLow => thold_CE1L_CLKL, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE1RIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE1RIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => RWLIn, TestSignalName => "RWL", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWLIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWLIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => RWRIn, TestSignalName => "RWR", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_RWL_CLKL, SetupLow => tsetup_RWL_CLKL, HoldHigh => thold_RWL_CLKL, HoldLow => thold_RWL_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RWRIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RWRIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOL3In, TestSignalName => "IOL3", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE3LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL3In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL3In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOL2In, TestSignalName => "IOL2", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE2LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL2In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL2In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOL1In, TestSignalName => "IOL1", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE1LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL1In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL1In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOL0In, TestSignalName => "IOL0", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1' AND RWL_nwv = '0' AND BE0LNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOL0In_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOL0In_CLKLIn ); VitalSetupHoldCheck ( TestSignal => IOR3In, TestSignalName => "IOR3", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1' AND RWR_nwv = '0' AND BE3RNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOR3In_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR3In_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOR2In, TestSignalName => "IOR2", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1' AND RWR_nwv = '0' AND BE2RNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOR2In_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR2In_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOR1In, TestSignalName => "IOR1", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1' AND RWR_nwv = '0' AND BE1RNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOR1In_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR1In_CLKRIn ); VitalSetupHoldCheck ( TestSignal => IOR0In, TestSignalName => "IOR0", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_IOL0_CLKL, SetupLow => tsetup_IOL0_CLKL, HoldHigh => thold_IOL0_CLKL, HoldLow => thold_IOL0_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1' AND RWR_nwv = '0' AND BE0RNeg_nwv = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOR0In_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOR0In_CLKRIn ); VitalSetupHoldCheck ( TestSignal => BE3LNegIn, TestSignalName => "BE3LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE3LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE3LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => BE2LNegIn, TestSignalName => "BE2LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE2LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE2LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => BE1LNegIn, TestSignalName => "BE1LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE1LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE1LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => BE0LNegIn, TestSignalName => "BE0LNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE0LNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE0LNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => BE3RNegIn, TestSignalName => "BE3RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE3RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE3RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => BE2RNegIn, TestSignalName => "BE2RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE2RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE2RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => BE1RNegIn, TestSignalName => "BE1RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE1RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE1RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => BE0RNegIn, TestSignalName => "BE0RNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BE0RNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BE0RNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => ADSLNegIn, TestSignalName => "ADSLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => ADSRNegIn, TestSignalName => "ADSRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_ADSLNeg_CLKL, SetupLow => tsetup_ADSLNeg_CLKL, HoldHigh => thold_ADSLNeg_CLKL, HoldLow => thold_ADSLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSRNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => CNTENLNegIn, TestSignalName => "CNTENLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_CNTENLNeg_CLKL, SetupLow => tsetup_CNTENLNeg_CLKL, HoldHigh => thold_CNTENLNeg_CLKL, HoldLow => thold_CNTENLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTENLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => CNTENRNegIn, TestSignalName => "CNTENRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_CNTENLNeg_CLKL, SetupLow => tsetup_CNTENLNeg_CLKL, HoldHigh => thold_CNTENLNeg_CLKL, HoldLow => thold_CNTENLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CNTENRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CNTENRNegIn_CLKRIn ); VitalSetupHoldCheck ( TestSignal => REPEATLNegIn, TestSignalName => "REPEATLNeg", RefSignal => CLKLIn, RefSignalName => "CLKL", SetupHigh => tsetup_REPEATLNeg_CLKL, SetupLow => tsetup_REPEATLNeg_CLKL, HoldHigh => thold_REPEATLNeg_CLKL, HoldLow => thold_REPEATLNeg_CLKL, CheckEnabled => (CE0LNeg_nwv ='0' AND CE1L_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_REPEATLNegIn_CLKLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_REPEATLNegIn_CLKLIn ); VitalSetupHoldCheck ( TestSignal => REPEATRNegIn, TestSignalName => "REPEATRNeg", RefSignal => CLKRIn, RefSignalName => "CLKR", SetupHigh => tsetup_REPEATLNeg_CLKL, SetupLow => tsetup_REPEATLNeg_CLKL, HoldHigh => thold_REPEATLNeg_CLKL, HoldLow => thold_REPEATLNeg_CLKL, CheckEnabled => (CE0RNeg_nwv ='0' AND CE1R_nwv = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_REPEATRNegIn_CLKRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_REPEATRNegIn_CLKRIn ); VitalPeriodPulseCheck ( TestSignal => CLKLIn, TestSignalName => "CLKL", Period => tperiod_CLKR_PIPER_EQ_1_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_1_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_1_posedge, PeriodData => TD_CLKLIn1, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPELIn = '0'), Violation => Pviol_CLKLIn1 ); VitalPeriodPulseCheck ( TestSignal => CLKRIn, TestSignalName => "CLKR", Period => tperiod_CLKR_PIPER_EQ_1_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_1_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_1_posedge, PeriodData => TD_CLKRIn1, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPERIn = '1'), Violation => Pviol_CLKRIn1 ); VitalPeriodPulseCheck ( TestSignal => CLKLIn, TestSignalName => "CLKL", Period => tperiod_CLKR_PIPER_EQ_0_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_0_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_0_posedge, PeriodData => TD_CLKLIn0, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPELIn = '0'), Violation => Pviol_CLKLIn0 ); VitalPeriodPulseCheck ( TestSignal => CLKRIn, TestSignalName => "CLKR", Period => tperiod_CLKR_PIPER_EQ_0_posedge, PulseWidthLow => tpw_CLKR_PIPER_EQ_0_negedge, PulseWidthHigh => tpw_CLKR_PIPER_EQ_0_posedge, PeriodData => TD_CLKRIn0, XOn => XOn, MsgOn => MsgOn, HeaderMsg => InstancePath & PartID, CheckEnabled => (PIPERIn = '0'), Violation => Pviol_CLKRIn0 ); Violation := Tviol_ALIn_CLKLIn OR Tviol_ARIn_CLKRIn OR Tviol_CE0LNegIn_CLKLIn OR Tviol_CE0RNegIn_CLKRIn OR Tviol_CE1LIn_CLKLIn OR Tviol_CE1RIn_CLKRIn OR Tviol_RWLIn_CLKLIn OR Tviol_RWRIn_CLKRIn OR Tviol_IOL3In_CLKLIn OR Tviol_IOR3In_CLKRIn OR Tviol_IOL2In_CLKLIn OR Tviol_IOR2In_CLKRIn OR Tviol_IOL1In_CLKLIn OR Tviol_IOR1In_CLKRIn OR Tviol_IOL0In_CLKLIn OR Tviol_IOR0In_CLKRIn OR Tviol_BE3LNegIn_CLKLIn OR Tviol_BE3RNegIn_CLKRIn OR Tviol_BE2LNegIn_CLKLIn OR Tviol_BE2RNegIn_CLKRIn OR Tviol_BE1LNegIn_CLKLIn OR Tviol_BE1RNegIn_CLKRIn OR Tviol_BE0LNegIn_CLKLIn OR Tviol_BE0RNegIn_CLKRIn OR Tviol_ADSLNegIn_CLKLIn OR Tviol_ADSRNegIn_CLKRIn OR Tviol_CNTENLNegIn_CLKLIn OR Tviol_CNTENRNegIn_CLKRIn OR Tviol_REPEATLNegIn_CLKLIn OR Tviol_REPEATRNegIn_CLKRIn OR Pviol_CLKLIn0 OR Pviol_CLKRIn0 OR Pviol_CLKLIn1 OR Pviol_CLKRIn1; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- IF rising_edge(CLKLIn) THEN IF RWL_nwv = '1' AND PIPELIn = '1' THEN -- read pipeline IF BE0LNeg_reg = '0' AND CE0LNeg_reg = '0' AND CE1L_reg = '1' THEN IF DataTempL0 >= 0 THEN DataL0Tmp := To_slv(DataTempL0, DataWidth); ELSIF DataTempL0 = -2 THEN DataL0Tmp := (OTHERS => 'U'); ELSE DataL0Tmp := (OTHERS => 'X'); END IF; IF LatencyL THEN DataL0Tmp := (OTHERS => 'Z'); END IF; ELSE DataL0tmp := (OTHERS => 'Z'); END IF; IF BE1LNeg_reg = '0' AND CE0LNeg_reg = '0' AND CE1L_reg = '1' THEN IF DataTempL1 >= 0 THEN DataL1Tmp := To_slv(DataTempL1, DataWidth); ELSIF DataTempL1 = -2 THEN DataL1Tmp := (OTHERS => 'U'); ELSE DataL1Tmp := (OTHERS => 'X'); END IF; IF LatencyL THEN DataL1Tmp := (OTHERS => 'Z'); END IF; ELSE DataL1tmp := (OTHERS => 'Z'); END IF; IF BE2LNeg_reg = '0' AND CE0LNeg_reg = '0' AND CE1L_reg = '1' THEN IF DataTempL2 >= 0 THEN DataL2Tmp := To_slv(DataTempL2, DataWidth); ELSIF DataTempL2 = -2 THEN DataL2Tmp := (OTHERS => 'U'); ELSE DataL2Tmp := (OTHERS => 'X'); END IF; IF LatencyL THEN DataL2Tmp := (OTHERS => 'Z'); END IF; ELSE DataL2tmp := (OTHERS => 'Z'); END IF; IF BE3LNeg_reg = '0' AND CE0LNeg_reg = '0' AND CE1L_reg = '1' THEN IF DataTempL3 >= 0 THEN DataL3Tmp := To_slv(DataTempL3, DataWidth); ELSIF DataTempL3 = -2 THEN DataL3Tmp := (OTHERS => 'U'); ELSE DataL3Tmp := (OTHERS => 'X'); END IF; IF LatencyL THEN DataL3Tmp := (OTHERS => 'Z'); END IF; ELSE DataL3tmp := (OTHERS => 'Z'); END IF; LatencyL := false; END IF; IF PIPELIn = '1' THEN -- register enables BE0LNeg_reg := BE0LNeg_nwv; BE1LNeg_reg := BE1LNeg_nwv; BE2LNeg_reg := BE2LNeg_nwv; BE3LNeg_reg := BE3LNeg_nwv; CE0LNeg_reg := CE0LNeg_nwv; CE1L_reg := CE1L_nwv; END IF; IF REPEATLNeg_nwv = '0' THEN -- reset addr LocationL := LastLocL; ELSIF ADSLNeg_nwv = '0' THEN -- load addr LocationL := To_Nat(ALIn); LastLocL := LocationL; ELSIF CNTENLNeg_nwv = '0' THEN IF LocationL < TotalLOC THEN -- inc addr LocationL := LocationL + 1; ELSE LocationL := 0; END IF; END IF; IF CE0LNeg_nwv = '0' AND CE1L_nwv = '1' THEN IF RWL_nwv = '1' THEN -- read IF BE0LNeg_nwv = '0' THEN DataTempL0 := MemData0(LocationL); IF PIPELIn = '0' THEN IF DataTempL0 >= 0 THEN DataL0tmp := To_slv(DataTempL0, DataWidth); ELSIF DataTempL0 = -2 THEN DataL0tmp := (OTHERS => 'U'); ELSE DataL0tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataL0tmp := (OTHERS => 'Z'); END IF; IF BE1LNeg_nwv = '0' THEN DataTempL1 := MemData1(LocationL); IF PIPELIn = '0' THEN IF DataTempL1 >= 0 THEN DataL1tmp := To_slv(DataTempL1, DataWidth); ELSIF DataTempL1 = -2 THEN DataL1tmp := (OTHERS => 'U'); ELSE DataL1tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataL1tmp := (OTHERS => 'Z'); END IF; IF BE2LNeg_nwv = '0' THEN DataTempL2 := MemData2(LocationL); IF PIPELIn = '0' THEN IF DataTempL2 >= 0 THEN DataL2tmp := To_slv(DataTempL2, DataWidth); ELSIF DataTempL2 = -2 THEN DataL2tmp := (OTHERS => 'U'); ELSE DataL2tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataL2tmp := (OTHERS => 'Z'); END IF; IF BE3LNeg_nwv = '0' THEN DataTempL3 := MemData3(LocationL); IF PIPELIn = '0' THEN IF DataTempL3 >= 0 THEN DataL3tmp := To_slv(DataTempL3, DataWidth); ELSIF DataTempL3 = -2 THEN DataL3tmp := (OTHERS => 'U'); ELSE DataL3tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataL3tmp := (OTHERS => 'Z'); END IF; ELSE -- write DataL0tmp := (OTHERS => 'Z'); DataL1tmp := (OTHERS => 'Z'); DataL2tmp := (OTHERS => 'Z'); DataL3tmp := (OTHERS => 'Z'); IF BE0LNeg_nwv = '0' THEN LatencyL := true; IF Violation = '0' THEN MemData0(LocationL) := To_Nat(IOL0In); ELSE MemData1(LocationL) := -1; WrtDataL1 := -1; END IF; END IF; IF BE1LNeg_nwv = '0' THEN LatencyL := true; IF Violation = '0' THEN MemData1(LocationL) := To_Nat(IOL1In); ELSE MemData1(LocationL) := -1; WrtDataL1 := -1; END IF; END IF; IF BE2LNeg_nwv = '0' THEN LatencyL := true; IF Violation = '0' THEN MemData2(LocationL) := To_Nat(IOL2In); ELSE MemData2(LocationL) := -1; WrtDataL2 := -1; END IF; END IF; IF BE3LNeg_nwv = '0' THEN LatencyL := true; IF Violation = '0' THEN MemData3(LocationL) := To_Nat(IOL3In); ELSE MemData3(LocationL) := -1; WrtDataL3 := -1; END IF; END IF; END IF; ELSIF PIPELIn = '0' THEN DataL0tmp := (OTHERS => 'Z'); DataL1tmp := (OTHERS => 'Z'); DataL2tmp := (OTHERS => 'Z'); DataL3tmp := (OTHERS => 'Z'); END IF; END IF; IF rising_edge(CLKRIn) THEN IF RWR_nwv = '1' AND PIPERIn = '1' THEN -- read pipeline IF BE0RNeg_reg = '0' AND CE0RNeg_reg = '0' AND CE1R_reg = '1' THEN IF DataTempR0 >= 0 THEN DataR0tmp := To_slv(DataTempR0, DataWidth); ELSIF DataTempR0 = -2 THEN DataR0tmp := (OTHERS => 'U'); ELSE DataR0tmp := (OTHERS => 'X'); END IF; IF LatencyR THEN DataR0tmp := (OTHERS => 'Z'); END IF; ELSE DataR0tmp := (OTHERS => 'Z'); END IF; IF BE1RNeg_reg = '0' AND CE0RNeg_reg = '0' AND CE1R_reg = '1' THEN IF DataTempR1 >= 0 THEN DataR1tmp := To_slv(DataTempR1, DataWidth); ELSIF DataTempR1 = -2 THEN DataR1tmp := (OTHERS => 'U'); ELSE DataR1tmp := (OTHERS => 'X'); END IF; IF LatencyR THEN DataR1tmp := (OTHERS => 'Z'); END IF; ELSE DataR1tmp := (OTHERS => 'Z'); END IF; IF BE2RNeg_reg = '0' AND CE0RNeg_reg = '0' AND CE1R_reg = '1' THEN IF DataTempR2 >= 0 THEN DataR2tmp := To_slv(DataTempR2, DataWidth); ELSIF DataTempR2 = -2 THEN DataR2tmp := (OTHERS => 'U'); ELSE DataR2tmp := (OTHERS => 'X'); END IF; IF LatencyR THEN DataR2tmp := (OTHERS => 'Z'); END IF; ELSE DataR2tmp := (OTHERS => 'Z'); END IF; IF BE3RNeg_reg = '0' AND CE0RNeg_reg = '0' AND CE1R_reg = '1' THEN IF DataTempR3 >= 0 THEN DataR3tmp := To_slv(DataTempR3, DataWidth); ELSIF DataTempR3 = -2 THEN DataR3tmp := (OTHERS => 'U'); ELSE DataR3tmp := (OTHERS => 'X'); END IF; IF LatencyR THEN DataR3tmp := (OTHERS => 'Z'); END IF; ELSE DataR3tmp := (OTHERS => 'Z'); END IF; LatencyR := false; END IF; IF PIPERIn = '1' THEN -- register enables BE0RNeg_reg := BE0RNeg_nwv; BE1RNeg_reg := BE1RNeg_nwv; BE2RNeg_reg := BE2RNeg_nwv; BE3RNeg_reg := BE3RNeg_nwv; CE0RNeg_reg := CE0RNeg_nwv; CE1R_reg := CE1R_nwv; END IF; IF REPEATRNeg_nwv = '0' THEN -- reset addr LocationR := LastLocR; ELSIF ADSRNeg_nwv = '0' THEN -- load addr LocationR := To_Nat(ARIn); LastLocR := LocationR; ELSIF CNTENRNeg_nwv = '0' THEN IF LocationR < TotalLOC THEN -- inc addr LocationR := LocationR + 1; ELSE LocationR := 0; END IF; END IF; IF CE0RNeg_nwv = '0' AND CE1R_nwv = '1' THEN IF RWR_nwv = '1' THEN -- read IF BE0RNeg_nwv = '0' THEN DataTempR0 := MemData0(LocationR); IF PIPERIn = '0' THEN IF DataTempR0 >= 0 THEN DataR0tmp := To_slv(DataTempR0, DataWidth); ELSIF DataTempR0 = -2 THEN DataR0tmp := (OTHERS => 'U'); ELSE DataR0tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataR0tmp := (OTHERS => 'Z'); END IF; IF BE1RNeg_nwv = '0' THEN DataTempR1 := MemData1(LocationR); IF PIPERIn = '0' THEN IF DataTempR1 >= 0 THEN DataR1tmp := To_slv(DataTempR1, DataWidth); ELSIF DataTempR1 = -2 THEN DataR1tmp := (OTHERS => 'U'); ELSE DataR1tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataR1tmp := (OTHERS => 'Z'); END IF; IF BE2RNeg_nwv = '0' THEN DataTempR2 := MemData2(LocationR); IF PIPERIn = '0' THEN IF DataTempR2 >= 0 THEN DataR2tmp := To_slv(DataTempR2, DataWidth); ELSIF DataTempR2 = -2 THEN DataR2tmp := (OTHERS => 'U'); ELSE DataR2tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataR2tmp := (OTHERS => 'Z'); END IF; IF BE3RNeg_nwv = '0' THEN DataTempR3 := MemData3(LocationR); IF PIPERIn = '0' THEN IF DataTempR3 >= 0 THEN DataR3tmp := To_slv(DataTempR3, DataWidth); ELSIF DataTempR3 = -2 THEN DataR3tmp := (OTHERS => 'U'); ELSE DataR3tmp := (OTHERS => 'X'); END IF; END IF; ELSE DataR3tmp := (OTHERS => 'Z'); END IF; ELSE -- write DataR0tmp := (OTHERS => 'Z'); DataR1tmp := (OTHERS => 'Z'); DataR2tmp := (OTHERS => 'Z'); DataR3tmp := (OTHERS => 'Z'); IF BE0RNeg_nwv = '0' THEN LatencyR := true; IF Violation = '0' THEN MemData0(LocationR) := To_Nat(IOR0In); ELSE MemData1(LocationR) := -1; WrtDataR1 := -1; END IF; END IF; IF BE1RNeg_nwv = '0' THEN LatencyR := true; IF Violation = '0' THEN MemData1(LocationR) := To_Nat(IOR1In); ELSE MemData1(LocationR) := -1; WrtDataR1 := -1; END IF; END IF; IF BE2RNeg_nwv = '0' THEN LatencyR := true; IF Violation = '0' THEN MemData2(LocationR) := To_Nat(IOR2In); ELSE MemData2(LocationR) := -1; WrtDataR2 := -1; END IF; END IF; IF BE3RNeg_nwv = '0' THEN LatencyR := true; IF Violation = '0' THEN MemData3(LocationR) := To_Nat(IOR3In); ELSE MemData3(LocationR) := -1; WrtDataR3 := -1; END IF; END IF; END IF; ELSIF PIPERIn = '0' THEN DataR0tmp := (OTHERS => 'Z'); DataR1tmp := (OTHERS => 'Z'); DataR2tmp := (OTHERS => 'Z'); DataR3tmp := (OTHERS => 'Z'); END IF; END IF; IF BSR_READ THEN IF bsr(49) = '1' THEN JTAGL0Drive(0) := bsr(31); JTAGL0Drive(1) := bsr(33); JTAGL0Drive(2) := bsr(35); JTAGL0Drive(3) := bsr(37); JTAGL0Drive(4) := bsr(39); JTAGL0Drive(5) := bsr(41); JTAGL0Drive(6) := bsr(43); JTAGL0Drive(7) := bsr(45); JTAGL0Drive(8) := bsr(47); ELSE JTAGL0Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(50) = '1' THEN JTAGL1Drive(0) := bsr(54); JTAGL1Drive(1) := bsr(56); JTAGL1Drive(2) := bsr(58); JTAGL1Drive(3) := bsr(60); JTAGL1Drive(4) := bsr(62); JTAGL1Drive(5) := bsr(64); JTAGL1Drive(6) := bsr(66); JTAGL1Drive(7) := bsr(68); JTAGL1Drive(8) := bsr(70); ELSE JTAGL1Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(51) = '1' THEN JTAGR0Drive(0) := bsr(32); JTAGR0Drive(1) := bsr(34); JTAGR0Drive(2) := bsr(36); JTAGR0Drive(3) := bsr(38); JTAGR0Drive(4) := bsr(40); JTAGR0Drive(5) := bsr(42); JTAGR0Drive(6) := bsr(44); JTAGR0Drive(7) := bsr(46); JTAGR0Drive(8) := bsr(48); ELSE JTAGR0Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(52) = '1' THEN JTAGR1Drive(0) := bsr(53); JTAGR1Drive(1) := bsr(55); JTAGR1Drive(2) := bsr(57); JTAGR1Drive(3) := bsr(59); JTAGR1Drive(4) := bsr(61); JTAGR1Drive(5) := bsr(63); JTAGR1Drive(6) := bsr(65); JTAGR1Drive(7) := bsr(67); JTAGR1Drive(8) := bsr(69); ELSE JTAGR1Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(120) = '1' THEN JTAGR2Drive(0) := bsr(103); JTAGR2Drive(1) := bsr(105); JTAGR2Drive(2) := bsr(107); JTAGR2Drive(3) := bsr(109); JTAGR2Drive(4) := bsr(111); JTAGR2Drive(5) := bsr(113); JTAGR2Drive(6) := bsr(115); JTAGR2Drive(7) := bsr(117); JTAGR2Drive(8) := bsr(119); ELSE JTAGR2Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(121) = '1' THEN JTAGR3Drive(0) := bsr(124); JTAGR3Drive(1) := bsr(126); JTAGR3Drive(2) := bsr(128); JTAGR3Drive(3) := bsr(130); JTAGR3Drive(4) := bsr(132); JTAGR3Drive(5) := bsr(134); JTAGR3Drive(6) := bsr(136); JTAGR3Drive(7) := bsr(138); JTAGR3Drive(8) := bsr(140); ELSE JTAGR3Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(122) = '1' THEN JTAGL2Drive(0) := bsr(102); JTAGL2Drive(1) := bsr(104); JTAGL2Drive(2) := bsr(106); JTAGL2Drive(3) := bsr(108); JTAGL2Drive(4) := bsr(110); JTAGL2Drive(5) := bsr(112); JTAGL2Drive(6) := bsr(114); JTAGL2Drive(7) := bsr(116); JTAGL2Drive(8) := bsr(118); ELSE JTAGL2Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; IF bsr(123) = '1' THEN JTAGL3Drive(0) := bsr(125); JTAGL3Drive(1) := bsr(127); JTAGL3Drive(2) := bsr(129); JTAGL3Drive(3) := bsr(131); JTAGL3Drive(4) := bsr(133); JTAGL3Drive(5) := bsr(135); JTAGL3Drive(6) := bsr(137); JTAGL3Drive(7) := bsr(139); JTAGL3Drive(8) := bsr(141); ELSE JTAGL3Drive(8 DOWNTO 0) := (OTHERS => 'Z'); END IF; END IF; IF Tri_Outs THEN IOL0_zd <= (OTHERS => 'Z'); IOL1_zd <= (OTHERS => 'Z'); IOL2_zd <= (OTHERS => 'Z'); IOL3_zd <= (OTHERS => 'Z'); IOR0_zd <= (OTHERS => 'Z'); IOR1_zd <= (OTHERS => 'Z'); IOR2_zd <= (OTHERS => 'Z'); IOR3_zd <= (OTHERS => 'Z'); ELSIF EXTST THEN IOL0_zd <= JTAGL0Drive; IOL1_zd <= JTAGL1Drive; IOL2_zd <= JTAGL2Drive; IOL3_zd <= JTAGL3Drive; IOR0_zd <= JTAGR0Drive; IOR1_zd <= JTAGR1Drive; IOR2_zd <= JTAGR2Drive; IOR3_zd <= JTAGR3Drive; ELSE IF (OELNeg_nwv = '1') THEN DataL0Drive := (OTHERS => 'Z'); DataL1Drive := (OTHERS => 'Z'); DataL2Drive := (OTHERS => 'Z'); DataL3Drive := (OTHERS => 'Z'); ELSE DataL0Drive := DataL0Tmp; DataL1Drive := DataL1Tmp; DataL2Drive := DataL2Tmp; DataL3Drive := DataL3Tmp; END IF; IF (OERNeg_nwv = '1') THEN DataR0Drive := (OTHERS => 'Z'); DataR1Drive := (OTHERS => 'Z'); DataR2Drive := (OTHERS => 'Z'); DataR3Drive := (OTHERS => 'Z'); ELSE DataR0Drive := DataR0Tmp; DataR1Drive := DataR1Tmp; DataR2Drive := DataR2Tmp; DataR3Drive := DataR3Tmp; END IF; IOL0_zd <= DataL0Drive; IOL1_zd <= DataL1Drive; IOL2_zd <= DataL2Drive; IOL3_zd <= DataL3Drive; IOR0_zd <= DataR0Drive; IOR1_zd <= DataR1Drive; IOR2_zd <= DataR2Drive; IOR3_zd <= DataR3Drive; END IF; END PROCESS Memory; ---------------------------------------------------------------------------- -- JTAG Behavior Process ---------------------------------------------------------------------------- VitalJTAGBehavior : PROCESS (TCKIn, TDIIn, TMSIn, TRSTNegIn) CONSTANT ir_size : natural := 4; -- Type definitions TYPE instruction_type IS (idcode, extest, bypass, highz, sample_preload); TYPE tap_state_type IS (Test_Logic_Reset, Run_Test_Idle, Select_DR_Scan, Capture_DR, Shift_DR, Exit1_DR, Pause_DR, Exit2_DR, Update_DR, Select_IR_Scan, Capture_IR, Shift_IR, Exit1_IR, Pause_IR, Exit2_IR, Update_IR ); -- Registers VARIABLE TAP_state : tap_state_type; VARIABLE prev_state : tap_state_type; VARIABLE instruction : instruction_type; VARIABLE decode : boolean := false; VARIABLE wrt2bsr : boolean := false; VARIABLE IDreg : std_logic_vector(31 downto 0) := jtagID; VARIABLE ir : std_logic_vector(ir_size - 1 downto 0); VARIABLE bstmp : std_logic_vector(bsr_size - 1 downto 0); VARIABLE bpr : X01; -- Timing Check Variables VARIABLE Tviol_TDI_TCK : X01 := '0'; VARIABLE TD_TDI_TCK : VitalTimingDataType; VARIABLE Tviol_TMS_TCK : X01 := '0'; VARIABLE TD_TMS_TCK : VitalTimingDataType; VARIABLE Rviol_TRSTNeg_TCK : X01 := '0'; VARIABLE TD_TRSTNeg_TCK : VitalTimingDataType; VARIABLE Pviol_TCK : X01 := '0'; VARIABLE PD_TCK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_TRST : X01 := '0'; VARIABLE PD_TRST : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE TDO_zd : std_ulogic; -- No Weak Values Variables VARIABLE TDI_nwv : UX01 := 'U'; VARIABLE TMS_nwv : UX01 := 'U'; VARIABLE TRSTNeg_nwv : UX01 := 'U'; -- Output Glitch Detection Variables VARIABLE TDO_GlitchData : VitalGlitchDataType; BEGIN TDI_nwv := To_UX01 (s => TDIIn); TMS_nwv := To_UX01 (s => TMSIn); TRSTNeg_nwv := To_UX01 (s => TRSTNegIn); ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => TMSIn, TestSignalName => "TMS", RefSignal => TCKIn, RefSignalName => "TCK", SetupHigh => tsetup_TDI_TCK, SetupLow => tsetup_TDI_TCK, HoldHigh => thold_TDI_TCK, HoldLow => thold_TDI_TCK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/partID", TimingData => TD_TMS_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TMS_TCK ); VitalSetupHoldCheck ( TestSignal => TDIIn, TestSignalName => "TDI", RefSignal => TCKIn, RefSignalName => "TCK", SetupHigh => tsetup_TDI_TCK, SetupLow => tsetup_TDI_TCK, HoldHigh => thold_TDI_TCK, HoldLow => thold_TDI_TCK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/partID", TimingData => TD_TDI_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_TDI_TCK ); VitalRecoveryRemovalCheck ( TestSignal => TRSTNegIn, TestSignalName => "TRSTNeg", RefSignal => TCKIn, RefSignalName => "TCKIn", Recovery => trecovery_TRSTNeg_TCK, ActiveLow => TRUE, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/partID", TimingData => TD_TRSTNeg_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Rviol_TRSTNeg_TCK ); VitalPeriodPulseCheck ( TestSignal => TCKIn, TestSignalName => "TCK", Period => tperiod_TCK_negedge, PulseWidthHigh => tpw_TCK_negedge, PulseWidthLow => tpw_TCK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/partID", PeriodData => PD_TCK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_TCK ); VitalPeriodPulseCheck ( TestSignal => TRSTNegIn, TestSignalName => "TRSTNeg", PulseWidthLow => tpw_TRSTNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/partID", PeriodData => PD_TRST, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_TRST ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_TDI_TCK OR Pviol_TCK OR Tviol_TMS_TCK OR Rviol_TRSTNeg_TCK OR Pviol_TRST; IF TRSTNeg_nwv = '0' THEN TAP_state := Test_Logic_Reset; prev_state := Test_Logic_Reset; instruction := idcode; IDreg := jtagID; Tri_Outs <= false; BSR_READ <= false; EXTST <= false; ELSIF falling_edge(TCKIn) THEN IF TAP_state = Test_Logic_Reset AND prev_state /= Test_Logic_Reset THEN instruction := idcode; EXTST <= false; Tri_Outs <= false; ELSIF TAP_state = Select_DR_Scan THEN BSR_READ <= false; ELSIF TAP_state = Shift_DR THEN CASE instruction IS WHEN idcode => TDO_zd := IDreg(0); WHEN bypass => TDO_zd := bpr; WHEN extest => TDO_zd := bsr(0); WHEN sample_preload => TDO_zd := bsr(0); WHEN others => null; END CASE; ELSIF TAP_state = Exit1_DR THEN TDO_zd := 'Z'; ELSIF TAP_state = Update_DR THEN CASE instruction IS WHEN extest => BSR_READ <= true; WHEN sample_preload => null; WHEN others => null; END CASE; ELSIF TAP_state = Shift_IR THEN TDO_zd := ir(0); ELSIF TAP_state = Exit1_IR THEN TDO_zd := 'Z'; END IF; ELSIF rising_edge(TCKIn) THEN CASE TAP_state IS WHEN Test_Logic_Reset => IF TMS_nwv = '0' THEN TAP_state := Run_Test_Idle; END IF; WHEN Run_Test_Idle => IF TMS_nwv = '1' THEN TAP_state := Select_DR_Scan; END IF; WHEN Select_DR_Scan => IF TMS_nwv = '0' THEN TAP_state := Capture_DR; ELSIF TMS_nwv = '1' THEN TAP_state := Select_IR_Scan; END IF; prev_state := Select_DR_Scan; WHEN Capture_DR => IF instruction = sample_preload OR instruction = extest THEN wrt2bsr := true; ELSIF instruction = idcode THEN IDreg := jtagID; END IF; IF TMS_nwv = '0' THEN TAP_state := Shift_DR; bpr := '0'; ELSIF TMS_nwv = '1' THEN TAP_state := Exit1_DR; END IF; WHEN Shift_DR => IF instruction = bypass OR instruction = highz THEN bpr := TDI_nwv; ELSIF instruction = idcode THEN FOR i IN 1 TO 31 LOOP IDreg(i - 1) := IDreg(i); END LOOP; IDreg(31) := TDI_nwv; ELSIF instruction = sample_preload OR instruction = extest THEN FOR i IN 1 TO bsr_size - 1 LOOP bsr(i - 1) <= bsr(i); END LOOP; bsr(bsr_size - 1) <= TDI_nwv; END IF; IF TMS_nwv = '1' THEN TAP_state := Exit1_DR; END IF; WHEN Exit1_DR => IF TMS_nwv = '0' THEN TAP_state := Pause_DR; ELSIF TMS_nwv = '1' THEN TAP_state := Update_DR; END IF; BSR_READ <= false; WHEN Pause_DR => IF TMS_nwv = '1' THEN TAP_state := Exit2_DR;