------------------------------------------------------------------------------ -- File Name: hyb18t1g160af_120.vhd ------------------------------------------------------------------------------ -- Developed by HDL-Design House, www.hdl-dh.com -- Copyright (C) 2006 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Stojanovic 06 Feb 21 Initial release -- ------------------------------------------------------------------------------ -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: hyb18t1g160af_120 -- -- Description: 1-Gbit DDR2 SDRAM ------------------------------------------------------------------------------ -- NOTES : -- -- Simulator resolution : 1 ps ------------------------------------------------------------------------------ LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; ------------------------------------------------------------------------------ -- ENTITY DECLARATION ------------------------------------------------------------------------------ ENTITY hyb18t1g160af_120 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CK : VitalDelayType01 := VitalZeroDelay01; tipd_CKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CKE : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BA0 : VitalDelayType01 := VitalZeroDelay01; tipd_BA1 : VitalDelayType01 := VitalZeroDelay01; tipd_BA2 : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ9 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ10 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ11 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ13 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ14 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ15 : VitalDelayType01 := VitalZeroDelay01; tipd_UDQS : VitalDelayType01 := VitalZeroDelay01; tipd_UDQSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDQS : VitalDelayType01 := VitalZeroDelay01; tipd_LDQSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_UDM : VitalDelayType01 := VitalZeroDelay01; tipd_LDM : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CK_DQ0 : VitalDelayType01Z := UnitDelay01Z; -- tAC, tHZ tpd_CK_UDQS : VitalDelayType01Z := UnitDelay01Z; -- tDQSCK -- tperiod values tperiod_CK : VitalDelayType := UnitDelay; -- tCK -- tsetup values: setup times tsetup_DQ0_UDQSNeg : VitalDelayType := UnitDelay; -- tDS tsetup_DQ0_UDQS : VitalDelayType := UnitDelay; -- tDS1 tsetup_A0_CK : VitalDelayType := UnitDelay; -- tIS -- thold values: hold times thold_DQ0_UDQSNeg : VitalDelayType := UnitDelay; -- tDH thold_DQ0_UDQS : VitalDelayType := UnitDelay; -- tDH1 thold_A0_CK : VitalDelayType := UnitDelay; -- tIH -- tdevice values: values for internal delays tdevice_RAS : VitalDelayType := UnitDelay; -- extract tdevice_RC : VitalDelayType := UnitDelay; -- extract tdevice_RCD : VitalDelayType := 15 ns; tdevice_RP : VitalDelayType := 15 ns; tdevice_REFI : VitalDelayType := 7.8 us; tdevice_RFC : VitalDelayType := 127.5 ns; tdevice_RRD : VitalDelayType := 10 ns; tdevice_RTP : VitalDelayType := 7.5 ns; tdevice_WR : VitalDelayType := 15 ns; tdevice_WTR : VitalDelayType := UnitDelay; -- extract tdevice_XSNR : VitalDelayType := 137.5 ns; -- tpowerup : power up time before initialization -- dataheet say 200 us tpowerup : TIME := 200 us; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING := "hyb18t1g160af_120.mem"; UserPreload : BOOLEAN := TRUE; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( CK : IN std_ulogic := 'U'; -- clock signal CKNeg : IN std_ulogic := 'U'; -- complementary CK CKE : IN std_ulogic := 'U'; -- clock enable RASNeg : IN std_ulogic := 'U'; -- row address strobe CASNeg : IN std_ulogic := 'U'; -- column address strobe WENeg : IN std_ulogic := 'U'; -- write enable CSNeg : IN std_ulogic := 'U'; -- chip select BA0 : IN std_ulogic := 'U'; -------------------- BA1 : IN std_ulogic := 'U'; -- bank address bus BA2 : IN std_ulogic := 'U'; -------------------- A0 : IN std_ulogic := 'U'; -------------------- A1 : IN std_ulogic := 'U'; -- A2 : IN std_ulogic := 'U'; -- A3 : IN std_ulogic := 'U'; -- A4 : IN std_ulogic := 'U'; -- A5 : IN std_ulogic := 'U'; -- address signal bus A6 : IN std_ulogic := 'U'; -- A7 : IN std_ulogic := 'U'; -- x16 : A0 - A12 A8 : IN std_ulogic := 'U'; -- A9 : IN std_ulogic := 'U'; -- A10 : IN std_ulogic := 'U'; -- A10/autoprecharge A11 : IN std_ulogic := 'U'; -- A12 : IN std_ulogic := 'U'; -------------------- DQ0 : INOUT std_ulogic := 'Z'; -------------------- DQ1 : INOUT std_ulogic := 'Z'; -- DQ2 : INOUT std_ulogic := 'Z'; -- DQ3 : INOUT std_ulogic := 'Z'; -- DQ4 : INOUT std_ulogic := 'Z'; -- DQ5 : INOUT std_ulogic := 'Z'; -- DQ6 : INOUT std_ulogic := 'Z'; -- data signal bus DQ7 : INOUT std_ulogic := 'Z'; -- DQ8 : INOUT std_ulogic := 'Z'; -- DQ9 : INOUT std_ulogic := 'Z'; -- x16 : D0 - D15 DQ10 : INOUT std_ulogic := 'Z'; -- DQ11 : INOUT std_ulogic := 'Z'; -- DQ12 : INOUT std_ulogic := 'Z'; -- DQ13 : INOUT std_ulogic := 'Z'; -- DQ14 : INOUT std_ulogic := 'Z'; -- DQ15 : INOUT std_ulogic := 'Z'; -------------------- -- Data Strobe x16 UDQS : INOUT std_ulogic := 'Z'; -- data strobe (upper) UDQSNeg : INOUT std_ulogic := 'Z'; -- complementary UDQS LDQS : INOUT std_ulogic := 'Z'; -- data strobe (lower) LDQSNeg : INOUT std_ulogic := 'Z'; -- complementary LDQS -- Data Mask x16 UDM : IN std_ulogic := 'U'; -- data mask (upper) LDM : IN std_ulogic := 'U' -- data mask (lower) ); ATTRIBUTE VITAL_LEVEL0 of hyb18t1g160af_120 : ENTITY IS TRUE; END hyb18t1g160af_120; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION - DYNAMIC MEMORY ALLOCATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_dynamic_memory_allocation of hyb18t1g160af_120 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral_dynamic_memory_allocation : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "hyb18t1g160af_120"; CONSTANT HiBankBit : INTEGER := 2; CONSTANT HiAddrBit : INTEGER := 12; CONSTANT HiRowBit : INTEGER := 12; CONSTANT HiColBit : INTEGER := 9; CONSTANT HiDataBit : INTEGER := 15; CONSTANT MaxBank : INTEGER := 8; CONSTANT MaxRow : INTEGER := 8192; CONSTANT MaXColumn : INTEGER := 1024; CONSTANT MaxData : INTEGER := 65535; CONSTANT NoneBank : INTEGER := 8; -- Simulation without .sdf SIGNAL t_CK : TIME := 5 ns; SIGNAL PoweredUp : BOOLEAN := FALSE; SIGNAL tsetup_UDQS_CK : TIME; -- tDSS (0.2*t_CK) SIGNAL thold_UDQS_CK : TIME; -- tDSH (0.2*t_CK) SIGNAL tpwCKEnegedge : TIME; SIGNAL tpwDQ0posedge : TIME; SIGNAL tpwDQSposedge : TIME; SIGNAL tpwA0posedge : TIME; SIGNAL tpwCKposedge : TIME; -- tCH SIGNAL tpwCKnegedge : TIME; -- tCL SIGNAL tdevice_MRD : TIME; --2* tCK SIGNAL tdevic_RPRE : TIME; -- (1.1*tCK) SIGNAL tdevic_RPST : TIME; -- (0.6*tCK) SIGNAL tdevic_WPRE : TIME; -- (0.35 * tCK) SIGNAL tdevic_WPST : TIME; -- (0.35 * tCK) SIGNAL tdevice_XARD : TIME; -- 2*tCK; SIGNAL tdevice_XARDS : TIME; -- (6-AL)*tCK; SIGNAL tdevice_XP : TIME; --2*tCK; SIGNAL tdevice_XSRD : TIME; -- 200*tCK; -- interconnect path delay signals SIGNAL CK_ipd : std_ulogic := 'U'; SIGNAL CKNeg_ipd : std_ulogic := 'U'; SIGNAL CKE_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL BA0_ipd : std_ulogic := 'U'; SIGNAL BA1_ipd : std_ulogic := 'U'; SIGNAL BA2_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'Z'; SIGNAL DQ1_ipd : std_ulogic := 'Z'; SIGNAL DQ2_ipd : std_ulogic := 'Z'; SIGNAL DQ3_ipd : std_ulogic := 'Z'; SIGNAL DQ4_ipd : std_ulogic := 'Z'; SIGNAL DQ5_ipd : std_ulogic := 'Z'; SIGNAL DQ6_ipd : std_ulogic := 'Z'; SIGNAL DQ7_ipd : std_ulogic := 'Z'; SIGNAL DQ8_ipd : std_ulogic := 'Z'; SIGNAL DQ9_ipd : std_ulogic := 'Z'; SIGNAL DQ10_ipd : std_ulogic := 'Z'; SIGNAL DQ11_ipd : std_ulogic := 'Z'; SIGNAL DQ12_ipd : std_ulogic := 'Z'; SIGNAL DQ13_ipd : std_ulogic := 'Z'; SIGNAL DQ14_ipd : std_ulogic := 'Z'; SIGNAL DQ15_ipd : std_ulogic := 'Z'; SIGNAL UDQS_ipd : std_ulogic := 'U'; SIGNAL UDQSNeg_ipd : std_ulogic := 'U'; SIGNAL LDQS_ipd : std_ulogic := 'U'; SIGNAL LDQSNeg_ipd : std_ulogic := 'U'; SIGNAL UDM_ipd : std_ulogic := 'U'; SIGNAL LDM_ipd : std_ulogic := 'U'; -- non weak values SIGNAL CK_nwv : UX01 := 'U'; SIGNAL CKNeg_nwv : UX01 := 'U'; SIGNAL CKE_nwv : UX01 := 'U'; SIGNAL RASNeg_nwv : UX01 := 'U'; SIGNAL CASNeg_nwv : UX01 := 'U'; SIGNAL WENeg_nwv : UX01 := 'U'; SIGNAL CSNeg_nwv : UX01 := 'U'; SIGNAL BA0_nwv : UX01 := 'U'; SIGNAL BA1_nwv : UX01 := 'U'; SIGNAL BA2_nwv : UX01 := 'U'; SIGNAL A0_nwv : UX01 := 'U'; SIGNAL A1_nwv : UX01 := 'U'; SIGNAL A2_nwv : UX01 := 'U'; SIGNAL A3_nwv : UX01 := 'U'; SIGNAL A4_nwv : UX01 := 'U'; SIGNAL A5_nwv : UX01 := 'U'; SIGNAL A6_nwv : UX01 := 'U'; SIGNAL A7_nwv : UX01 := 'U'; SIGNAL A8_nwv : UX01 := 'U'; SIGNAL A9_nwv : UX01 := 'U'; SIGNAL A10_nwv : UX01 := 'U'; SIGNAL A11_nwv : UX01 := 'U'; SIGNAL A12_nwv : UX01 := 'U'; SIGNAL DQ0_nwv : UX01 := 'U'; SIGNAL DQ1_nwv : UX01 := 'U'; SIGNAL DQ2_nwv : UX01 := 'U'; SIGNAL DQ3_nwv : UX01 := 'U'; SIGNAL DQ4_nwv : UX01 := 'U'; SIGNAL DQ5_nwv : UX01 := 'U'; SIGNAL DQ6_nwv : UX01 := 'U'; SIGNAL DQ7_nwv : UX01 := 'U'; SIGNAL DQ8_nwv : UX01 := 'U'; SIGNAL DQ9_nwv : UX01 := 'U'; SIGNAL DQ10_nwv : UX01 := 'U'; SIGNAL DQ11_nwv : UX01 := 'U'; SIGNAL DQ12_nwv : UX01 := 'U'; SIGNAL DQ13_nwv : UX01 := 'U'; SIGNAL DQ14_nwv : UX01 := 'U'; SIGNAL DQ15_nwv : UX01 := 'U'; SIGNAL UDQS_nwv : UX01 := 'U'; SIGNAL UDQSNeg_nwv : UX01 := 'U'; SIGNAL LDQS_nwv : UX01 := 'U'; SIGNAL LDQSNeg_nwv : UX01 := 'U'; SIGNAL UDM_nwv : UX01 := 'U'; SIGNAL LDM_nwv : UX01 := 'U'; SIGNAL CKEInPrev : std_ulogic := '0'; SIGNAL CKEInnew : std_ulogic := '0'; SIGNAL command_changed : bit := '0'; SIGNAL new_rw : std_ulogic := '0'; SIGNAL rc_in : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rc_out : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rcd_in : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rcd_out : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL ras_in : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL ras_out : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rp_in : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rp_out : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rtp_in : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL rtp_out : std_ulogic_vector(7 downto 0) := (others => '0'); SIGNAL refi_in : std_ulogic := '0'; SIGNAL refi_out : std_ulogic := '0'; SIGNAL rfc_in : std_ulogic := '0'; SIGNAL rfc_out : std_ulogic := '0'; SIGNAL rrd_in : std_ulogic := '0'; SIGNAL rrd_out : std_ulogic := '0'; SIGNAL wr_in : std_ulogic := '0'; SIGNAL wr_out : std_ulogic := '0'; SIGNAL wtr_in : std_ulogic := '0'; SIGNAL wtr_out : std_ulogic := '0'; SIGNAL xsnr_in : std_ulogic := '0'; SIGNAL xsnr_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- -- Artificial VITAL primitives to incorporate internal delays --Bank A Row to Bank A Precharge TRAS0 : VitalBuf (ras_out(0) , ras_in(0) , (tdevice_RAS, tdevice_RAS)); TRAS1 : VitalBuf (ras_out(1) , ras_in(1) , (tdevice_RAS, tdevice_RAS)); TRAS2 : VitalBuf (ras_out(2) , ras_in(2) , (tdevice_RAS, tdevice_RAS)); TRAS3 : VitalBuf (ras_out(3) , ras_in(3) , (tdevice_RAS, tdevice_RAS)); TRAS4 : VitalBuf (ras_out(4) , ras_in(4) , (tdevice_RAS, tdevice_RAS)); TRAS5 : VitalBuf (ras_out(5) , ras_in(5) , (tdevice_RAS, tdevice_RAS)); TRAS6 : VitalBuf (ras_out(6) , ras_in(6) , (tdevice_RAS, tdevice_RAS)); TRAS7 : VitalBuf (ras_out(7) , ras_in(7) , (tdevice_RAS, tdevice_RAS)); --Bank A Row to Bank A next Row delay TRC0 : VitalBuf (rc_out(0) , rc_in(0) , (tdevice_RC, tdevice_RC)); TRC1 : VitalBuf (rc_out(1) , rc_in(1) , (tdevice_RC, tdevice_RC)); TRC2 : VitalBuf (rc_out(2) , rc_in(2) , (tdevice_RC, tdevice_RC)); TRC3 : VitalBuf (rc_out(3) , rc_in(3) , (tdevice_RC, tdevice_RC)); TRC4 : VitalBuf (rc_out(4) , rc_in(4) , (tdevice_RC, tdevice_RC)); TRC5 : VitalBuf (rc_out(5) , rc_in(5) , (tdevice_RC, tdevice_RC)); TRC6 : VitalBuf (rc_out(6) , rc_in(6) , (tdevice_RC, tdevice_RC)); TRC7 : VitalBuf (rc_out(7) , rc_in(7) , (tdevice_RC, tdevice_RC)); --Bank A Row to Bank A Column delay TRCD0 : VitalBuf (rcd_out(0) , rcd_in(0) , (tdevice_RCD, tdevice_RCD)); TRCD1 : VitalBuf (rcd_out(1) , rcd_in(1) , (tdevice_RCD, tdevice_RCD)); TRCD2 : VitalBuf (rcd_out(2) , rcd_in(2) , (tdevice_RCD, tdevice_RCD)); TRCD3 : VitalBuf (rcd_out(3) , rcd_in(3) , (tdevice_RCD, tdevice_RCD)); TRCD4 : VitalBuf (rcd_out(4) , rcd_in(4) , (tdevice_RCD, tdevice_RCD)); TRCD5 : VitalBuf (rcd_out(5) , rcd_in(5) , (tdevice_RCD, tdevice_RCD)); TRCD6 : VitalBuf (rcd_out(6) , rcd_in(6) , (tdevice_RCD, tdevice_RCD)); TRCD7 : VitalBuf (rcd_out(7) , rcd_in(7) , (tdevice_RCD, tdevice_RCD)); --Row precharge time (Precharge to Activate the same row) TRP0 : VitalBuf (rp_out(0) , rp_in(0) , (tdevice_RP, tdevice_RP)); TRP1 : VitalBuf (rp_out(1) , rp_in(1) , (tdevice_RP, tdevice_RP)); TRP2 : VitalBuf (rp_out(2) , rp_in(2) , (tdevice_RP, tdevice_RP)); TRP3 : VitalBuf (rp_out(3) , rp_in(3) , (tdevice_RP, tdevice_RP)); TRP4 : VitalBuf (rp_out(4) , rp_in(4) , (tdevice_RP, tdevice_RP)); TRP5 : VitalBuf (rp_out(5) , rp_in(5) , (tdevice_RP, tdevice_RP)); TRP6 : VitalBuf (rp_out(6) , rp_in(6) , (tdevice_RP, tdevice_RP)); TRP7 : VitalBuf (rp_out(7) , rp_in(7) , (tdevice_RP, tdevice_RP)); --Internal read to precharge delay TRTP0 : VitalBuf (rtp_out(0) , rtp_in(0) , (tdevice_RTP, tdevice_RTP)); TRTP1 : VitalBuf (rtp_out(1) , rtp_in(1) , (tdevice_RTP, tdevice_RTP)); TRTP2 : VitalBuf (rtp_out(2) , rtp_in(2) , (tdevice_RTP, tdevice_RTP)); TRTP3 : VitalBuf (rtp_out(3) , rtp_in(3) , (tdevice_RTP, tdevice_RTP)); TRTP4 : VitalBuf (rtp_out(4) , rtp_in(4) , (tdevice_RTP, tdevice_RTP)); TRTP5 : VitalBuf (rtp_out(5) , rtp_in(5) , (tdevice_RTP, tdevice_RTP)); TRTP6 : VitalBuf (rtp_out(6) , rtp_in(6) , (tdevice_RTP, tdevice_RTP)); TRTP7 : VitalBuf (rtp_out(7) , rtp_in(7) , (tdevice_RTP, tdevice_RTP)); --Periodic refresh interval TREFI : VitalBuf (refi_out , refi_in , (VitalZeroDelay, tdevice_REFI)); --Auto Refresh to another Auto Refresh or Activate command TRFC : VitalBuf (rfc_out , rfc_in , (VitalZeroDelay, tdevice_RFC)); --Active Bank A to Active Bank B delay TRRD : VitalBuf (rrd_out , rrd_in , (VitalZeroDelay, tdevice_RRD)); --Write recovery for write without Auto-Precharge TWR : VitalBuf (wr_out , wr_in , (VitalZeroDelay, tdevice_WR)); --Internal write to read command delay TWTR : VitalBuf (wtr_out , wtr_in , (VitalZeroDelay, tdevice_WTR)); --Exit Self-Refresh to non-read command TXSNR : VitalBuf (xsnr_out , xsnr_in , (VitalZeroDelay, tdevice_XSNR)); -------------------------------------------------------------------------- -- Wire Delays -------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (CK_ipd,CK,tipd_CK); w_02 : VitalWireDelay (CKNeg_ipd,CKNeg,tipd_CKNeg); w_03 : VitalWireDelay (CKE_ipd,CKE,tipd_CKE); w_04 : VitalWireDelay (RASNeg_ipd,RASNeg,tipd_RASNeg); w_05 : VitalWireDelay (CASNeg_ipd,CASNeg,tipd_CASNeg); w_06 : VitalWireDelay (WENeg_ipd,WENeg,tipd_WENeg); w_07 : VitalWireDelay (CSNeg_ipd,CSNeg,tipd_CSNeg); w_08 : VitalWireDelay (BA0_ipd,BA0,tipd_BA0); w_09 : VitalWireDelay (BA1_ipd,BA1,tipd_BA1); w_10 : VitalWireDelay (BA2_ipd,BA2,tipd_BA2); w_11 : VitalWireDelay (A0_ipd,A0,tipd_A0); w_12 : VitalWireDelay (A1_ipd,A1,tipd_A1); w_13 : VitalWireDelay (A2_ipd,A2,tipd_A2); w_14 : VitalWireDelay (A3_ipd,A3,tipd_A3); w_15 : VitalWireDelay (A4_ipd,A4,tipd_A4); w_16 : VitalWireDelay (A5_ipd,A5,tipd_A5); w_17 : VitalWireDelay (A6_ipd,A6,tipd_A6); w_18 : VitalWireDelay (A7_ipd,A7,tipd_A7); w_19 : VitalWireDelay (A8_ipd,A8,tipd_A8); w_20 : VitalWireDelay (A9_ipd,A9,tipd_A9); w_21 : VitalWireDelay (A10_ipd,A10,tipd_A10); w_22 : VitalWireDelay (A11_ipd,A11,tipd_A11); w_23 : VitalWireDelay (A12_ipd,A12,tipd_A12); w_24 : VitalWireDelay (DQ0_ipd,DQ0,tipd_DQ0); w_25 : VitalWireDelay (DQ1_ipd,DQ1,tipd_DQ1); w_26 : VitalWireDelay (DQ2_ipd,DQ2,tipd_DQ2); w_27 : VitalWireDelay (DQ3_ipd,DQ3,tipd_DQ3); w_28 : VitalWireDelay (DQ4_ipd,DQ4,tipd_DQ4); w_29 : VitalWireDelay (DQ5_ipd,DQ5,tipd_DQ5); w_30 : VitalWireDelay (DQ6_ipd,DQ6,tipd_DQ6); w_31 : VitalWireDelay (DQ7_ipd,DQ7,tipd_DQ7); w_32 : VitalWireDelay (DQ8_ipd,DQ8,tipd_DQ8); w_33 : VitalWireDelay (DQ9_ipd,DQ9,tipd_DQ9); w_34 : VitalWireDelay (DQ10_ipd,DQ10,tipd_DQ10); w_35 : VitalWireDelay (DQ11_ipd,DQ11,tipd_DQ11); w_36 : VitalWireDelay (DQ12_ipd,DQ12,tipd_DQ12); w_37 : VitalWireDelay (DQ13_ipd,DQ13,tipd_DQ13); w_38 : VitalWireDelay (DQ14_ipd,DQ14,tipd_DQ14); w_39 : VitalWireDelay (DQ15_ipd,DQ15,tipd_DQ15); w_40 : VitalWireDelay (UDQS_ipd,UDQS,tipd_UDQS); w_41 : VitalWireDelay (UDQSNeg_ipd,UDQSNeg,tipd_UDQSNeg); w_42 : VitalWireDelay (LDQS_ipd,LDQS,tipd_LDQS); w_43 : VitalWireDelay (LDQSNeg_ipd,LDQSNeg,tipd_LDQSNeg); w_44 : VitalWireDelay (UDM_ipd,UDM,tipd_UDM); w_45 : VitalWireDelay (LDM_ipd,LDM,tipd_LDM); END BLOCK WireDelay; -- non weak values CK_nwv <= To_UX01(s => CK_ipd); CKNeg_nwv <= To_UX01(s => CKNeg_ipd); CKE_nwv <= To_UX01(s => CKE_ipd); RASNeg_nwv <= To_UX01(s => RASNeg_ipd); CASNeg_nwv <= To_UX01(s => CASNeg_ipd); WENeg_nwv <= To_UX01(s => WENeg_ipd); CSNeg_nwv <= To_UX01(s => CSNeg_ipd); BA0_nwv <= To_UX01(s => BA0_ipd); BA1_nwv <= To_UX01(s => BA1_ipd); BA2_nwv <= To_UX01(s => BA2_ipd); A0_nwv <= To_UX01(s => A0_ipd); A1_nwv <= To_UX01(s => A1_ipd); A2_nwv <= To_UX01(s => A2_ipd); A3_nwv <= To_UX01(s => A3_ipd); A4_nwv <= To_UX01(s => A4_ipd); A5_nwv <= To_UX01(s => A5_ipd); A6_nwv <= To_UX01(s => A6_ipd); A7_nwv <= To_UX01(s => A7_ipd); A8_nwv <= To_UX01(s => A8_ipd); A9_nwv <= To_UX01(s => A9_ipd); A10_nwv <= To_UX01(s => A10_ipd); A11_nwv <= To_UX01(s => A11_ipd); A12_nwv <= To_UX01(s => A12_ipd); DQ0_nwv <= To_UX01(s => DQ0_ipd); DQ1_nwv <= To_UX01(s => DQ1_ipd); DQ2_nwv <= To_UX01(s => DQ2_ipd); DQ3_nwv <= To_UX01(s => DQ3_ipd); DQ4_nwv <= To_UX01(s => DQ4_ipd); DQ5_nwv <= To_UX01(s => DQ5_ipd); DQ6_nwv <= To_UX01(s => DQ6_ipd); DQ7_nwv <= To_UX01(s => DQ7_ipd); DQ8_nwv <= To_UX01(s => DQ8_ipd); DQ9_nwv <= To_UX01(s => DQ9_ipd); DQ10_nwv <= To_UX01(s => DQ10_ipd); DQ11_nwv <= To_UX01(s => DQ11_ipd); DQ12_nwv <= To_UX01(s => DQ12_ipd); DQ13_nwv <= To_UX01(s => DQ13_ipd); DQ14_nwv <= To_UX01(s => DQ14_ipd); DQ15_nwv <= To_UX01(s => DQ15_ipd); UDQS_nwv <= To_UX01(s => UDQS_ipd); UDQSNeg_nwv <= To_UX01(s => UDQSNeg_ipd); LDQS_nwv <= To_UX01(s => LDQS_ipd); LDQSNeg_nwv <= To_UX01(s => LDQSNeg_ipd); UDM_nwv <= To_UX01(s => UDM_ipd); LDM_nwv <= To_UX01(s => LDM_ipd); ---------------------------------------------------------------------------- -- Main behavior Block ---------------------------------------------------------------------------- VitalBehavior: BLOCK PORT ( CKIn : IN std_ulogic := 'U'; CKNegIn : IN std_ulogic := 'U'; CKEIn : IN std_ulogic := 'U'; WENegIn : IN std_ulogic := 'U'; RASNegIn : IN std_ulogic := 'U'; CSNegIn : IN std_ulogic := 'U'; CASNegIn : IN std_ulogic := 'U'; BAIn : IN std_logic_vector(HiBankBit downto 0); AddressIn : IN std_logic_vector(HiAddrBit downto 0); DataIn : IN std_logic_vector(HiDataBit downto 0); DataOut : OUT std_logic_vector(HiDataBit downto 0) := (others => 'Z'); UDQSIn : IN std_logic ; UDQSNegIn : IN std_logic ; UDQSOut : OUT std_logic := 'Z'; UDQSNegOut : OUT std_logic := 'Z'; LDQSIn : IN std_logic := 'Z'; LDQSNegIn : IN std_logic := 'Z'; LDQSOut : OUT std_logic := 'Z'; LDQSNegOut : OUT std_logic := 'Z'; UDMIn : IN std_ulogic := 'U'; LDMIn : IN std_ulogic := 'U' ); PORT MAP ( CKIn => CK_nwv, CKNegIn => CKNeg_nwv, CKEIn => CKE_nwv, WENegIn => WENeg_nwv, RASNegIn => RASNeg_nwv, CSNegIn => CSNeg_nwv, CASNegIn => CASNeg_nwv, BAIn(0) => BA0_nwv, BAIn(1) => BA1_nwv, BAIn(2) => BA2_nwv, AddressIn(0) => A0_nwv, AddressIn(1) => A1_nwv, AddressIn(2) => A2_nwv, AddressIn(3) => A3_nwv, AddressIn(4) => A4_nwv, AddressIn(5) => A5_nwv, AddressIn(6) => A6_nwv, AddressIn(7) => A7_nwv, AddressIn(8) => A8_nwv, AddressIn(9) => A9_nwv, AddressIn(10) => A10_nwv, AddressIn(11) => A11_nwv, AddressIn(12) => A12_nwv, DataIn(0) => DQ0_ipd,--_nwv, DataIn(1) => DQ1_ipd,--_nwv, DataIn(2) => DQ2_ipd,--_nwv, DataIn(3) => DQ3_ipd,--_nwv, DataIn(4) => DQ4_ipd,--_nwv, DataIn(5) => DQ5_ipd,--_nwv, DataIn(6) => DQ6_ipd,--_nwv, DataIn(7) => DQ7_ipd,--_nwv, DataIn(8) => DQ8_ipd,--_nwv, DataIn(9) => DQ9_ipd,--_nwv, DataIn(10) => DQ10_ipd,--_nwv, DataIn(11) => DQ11_ipd,--_nwv, DataIn(12) => DQ12_ipd,--_nwv, DataIn(13) => DQ13_ipd,--_nwv, DataIn(14) => DQ14_ipd,--_nwv, DataIn(15) => DQ15_ipd,--_nwv, DataOut(0) => DQ0, DataOut(1) => DQ1, DataOut(2) => DQ2, DataOut(3) => DQ3, DataOut(4) => DQ4, DataOut(5) => DQ5, DataOut(6) => DQ6, DataOut(7) => DQ7, DataOut(8) => DQ8, DataOut(9) => DQ9, DataOut(10) => DQ10, DataOut(11) => DQ11, DataOut(12) => DQ12, DataOut(13) => DQ13, DataOut(14) => DQ14, DataOut(15) => DQ15, UDQSIn => UDQS_nwv, UDQSNegIn=> UDQSNeg_ipd, LDQSIn => LDQS_nwv, LDQSNegIn=> LDQSNeg_nwv, UDQSOut => UDQS, UDQSNegOut => UDQSNeg, LDQSOut => LDQS, LDQSNegOut => LDQSNeg, UDMIn => UDM_nwv, LDMIn => LDM_nwv ); -- Type definition for commands TYPE command_type is (nop, deselect, mrs, autoref, bankact, presingle, preall, write, writeapre, read, readapre, selfrefentry, pwrdwnentry, selfrefpwrdwnexit ); -- Type definition for state machine TYPE state_type IS (init_state, idle_state, mrs_set_state, self_refresh_state, auto_refresh_state, pwrdown_precharge_state, pwrdown_active_state, activating_state, bank_active_state, write_state, write_auto_precharge_state, read_state, read_auto_precharge_state, precharge_state ); TYPE statebanktype IS array (MaxBank-1 downto 0) of state_type; TYPE rowbanktype IS array (MaxBank-1 downto 0) of INTEGER RANGE 0 to MaxRow-1; TYPE burst_addr_seq_type IS (sequential, interleaved); TYPE power_down_mode_type IS (standard,lowpower); TYPE bool_array_type IS ARRAY (0 TO MaxBank-1) OF BOOLEAN; TYPE columnarraytype IS ARRAY (0 TO 7) OF INTEGER RANGE 0 TO MaxColumn - 1; TYPE burst_sequence_type IS ARRAY (0 TO 7) OF INTEGER RANGE 0 TO 15; TYPE sequence_4 IS ARRAY (0 TO 3) OF burst_sequence_type; TYPE sequence_8 IS ARRAY (0 TO 7) OF burst_sequence_type; SHARED VARIABLE burst_sequence : burst_sequence_type:=(0&0&0&0&0&0&0&0); SHARED VARIABLE burst_index : INTEGER := 0; SHARED VARIABLE burst_offset : INTEGER := 0; CONSTANT sa_4 : sequence_4 := ((4&5&6&7&0&0&0&0), (4&5&6&3&0&0&0&0), (4&5&2&3&0&0&0&0), (4&1&2&3&0&0&0&0)); CONSTANT ia_4 : sequence_4 := ((4&5&6&7&0&0&0&0), (4&3&6&5&0&0&0&0), (4&5&2&3&0&0&0&0), (4&3&2&1&0&0&0&0)); CONSTANT sa_8 : sequence_8 := ((8&9&10&11&12&13&14&15), (8&9&10&7&12&13&14&11), (8&9&6&7&12&13&10&11), (8&5&6&7&12&9&10&11), (8&9&10&11&4&5&6&7), (8&9&10&7&4&5&6&3), (8&9&6&7&4&5&2&3), (8&5&6&7&4&1&2&3)); CONSTANT ia_8 : sequence_8 := ((8&9&10&11&12&13&14&15), (8&7&10&9&12&11&14&13), (8&9&6&7&12&13&10&11), (8&7&6&5&12&11&10&9), (8&9&10&11&4&5&6&7), (8&7&10&9&4&3&6&5), (8&9&6&7&4&5&2&3), (8&7&6&5&4&3&2&1)); SHARED VARIABLE columnFIFObuffer : columnarraytype; SHARED VARIABLE in_index : INTEGER RANGE 0 TO 7 := 0; SHARED VARIABLE out_index : INTEGER RANGE 0 TO 7 := 0; -- commands SIGNAL command : command_type; -- states SIGNAL current_state : statebanktype := init_state & init_state & init_state & init_state & init_state & init_state & init_state & init_state; SIGNAL next_state : statebanktype := init_state & init_state & init_state & init_state & init_state & init_state & init_state & init_state; SHARED VARIABLE current_row : rowbanktype; SHARED VARIABLE current_column : INTEGER range 0 to MaxColumn-1; SHARED VARIABLE current_bank : INTEGER range 0 to MaxBank; -- MRS : -- Burst length SHARED VARIABLE BL : INTEGER RANGE 0 TO 8;-- burst_length -- Burst type SHARED VARIABLE BT : burst_addr_seq_type; -- CAS latency SHARED VARIABLE CL : INTEGER RANGE 0 TO 7;-- number of CKIn cycles -- Test mode SHARED VARIABLE TM : std_logic; -- Dll reset SHARED VARIABLE DLLreset : std_logic; -- write recovery (for write with auto precharge) SHARED VARIABLE WR : INTEGER RANGE 0 TO 7; -- number of CKIn cycles -- power down mode SHARED VARIABLE PD : power_down_mode_type; -- EMRS(1) : -- Dll enable SHARED VARIABLE DLLenable : std_logic; -- Odd-chip driver impedance control SHARED VARIABLE DIC : std_logic; -- additive latency SHARED VARIABLE AL : INTEGER RANGE 0 TO 4;-- number of CKIn cycles -- disables DQSNeg signal (0-differential , 1-single) SHARED VARIABLE DQSNegDis : BOOLEAN; -- disables output (1-outputs HiZ, 0-regular outputs) SHARED VARIABLE QoffHIz : std_logic; -- EMRS(2) : future use -- EMRS(3) : future use SHARED VARIABLE RL :INTEGER RANGE 0 TO 10 := 0;-- number of CKIn SHARED VARIABLE WL :INTEGER RANGE 0 TO 9 := 0;-- number of CKIn SHARED VARIABLE DataOut_temp : std_logic_vector(HiDataBit downto 0) := (others => 'Z'); -- Functionality result (zero delay) variables SIGNAL DataOut_zd : std_logic_vector(HiDataBit downto 0) := (others => 'Z'); SIGNAL UDQSOut_zd : std_logic := 'Z'; SIGNAL UDQSNegOut_zd : std_logic := 'Z'; SIGNAL LDQSOut_zd : std_logic := 'Z'; SIGNAL LDQSNegOut_zd : std_logic := 'Z'; SIGNAL command_update : std_logic := '0'; SIGNAL mrs_finished : bool_array_type; SIGNAL aref_finished : bool_array_type; SIGNAL write_finished : bool_array_type; SIGNAL read_finished : bool_array_type; SIGNAL wap_finished : bool_array_type; SIGNAL rap_finished : bool_array_type; SIGNAL prech_finished : bool_array_type; SIGNAL read_dqs_enabled_0 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_0 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_1 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_1 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_2 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_2 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_3 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_3 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_4 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_4 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_5 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_5 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_6 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_6 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_dqs_enabled_7 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL read_data_enabled_7 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_0 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_1 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_2 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_3 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_4 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_5 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_6 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL write_data_enabled_7 : std_logic_vector(MaxBank-1 downto 0) := "00000000"; SIGNAL w_burst_n_interrupted_0: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_1: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_2: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_3: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_4: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_5: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_0: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_1: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_2: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_3: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_4: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL r_burst_n_interrupted_5: std_logic_vector(MaxBank-1 downto 0) := "11111111"; SIGNAL w_burst_n_interrupted_g : std_logic := '1'; SIGNAL r_burst_n_interrupted_g : std_logic := '1'; SIGNAL read_dqs_enabled_g : std_logic := '0'; SIGNAL read_data_enabled_g : std_logic := '0'; SIGNAL write_data_enabled_g : std_logic := '0'; SHARED VARIABLE read_finished_interrupted : std_logic := '0'; -- --------------------------------------------------------------------- -- DYNAMIC MEMORY ALLOCATION VARIABLES & PROCEDURES -- --------------------------------------------------------------------- -- --------------------------------------------------------------------- -- Data types required to implement link list structure -- --------------------------------------------------------------------- TYPE mem_data_t; TYPE mem_data_pointer_t IS ACCESS mem_data_t; TYPE mem_data_t IS RECORD key_address : INTEGER; val_data : INTEGER; successor : mem_data_pointer_t; END RECORD; -- --------------------------------------------------------------------- -- Array of linked lists. -- Support memory region partitioning for faster access. -- --------------------------------------------------------------------- TYPE mem_data_pointer_array_t IS ARRAY(NATURAL RANGE <>) OF mem_data_pointer_t; -- --------------------------------------------------------------------- -- Create linked listed -- --------------------------------------------------------------------- PROCEDURE create_list( key_address : IN INTEGER; val_data : IN INTEGER; root : INOUT mem_data_pointer_t) IS BEGIN root := NEW mem_data_t; root.successor := NULL; root.key_address := key_address; root.val_data := val_data; END PROCEDURE create_list; -- -------------------------------------------------------------------- -- Iterate through linked listed comapring key values -- Stop when key value greater or equal -- -------------------------------------------------------------------- PROCEDURE position_list( key_address : IN INTEGER; root : INOUT mem_data_pointer_t; found : INOUT mem_data_pointer_t; prev : INOUT mem_data_pointer_t) IS BEGIN found := root; prev := NULL; WHILE ((found /= NULL) AND (found.key_address < key_address)) LOOP prev := found; found := found.successor; END LOOP; END PROCEDURE position_list; -- ------------------------------------------------------------------- -- Add new element to a linked list -- ------------------------------------------------------------------- PROCEDURE insert_list( key_address : IN INTEGER; val_data : IN INTEGER; root : INOUT mem_data_pointer_t) IS VARIABLE new_element : mem_data_pointer_t; VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; BEGIN position_list(key_address, root, found, prev); -- Insert at list tail IF (found = NULL) THEN prev.successor := NEW mem_data_t; prev.successor.key_address := key_address; prev.successor.val_data := val_data; prev.successor.successor := NULL; ELSE -- Element exists, update memory data value IF (found.key_address = key_address) THEN found.val_data := val_data; ELSE -- No element found, allocate and link new_element := NEW mem_data_t; new_element.key_address := key_address; new_element.val_data := val_data; new_element.successor := found; -- Possible root position IF (prev /= NULL) THEN prev.successor := new_element; ELSE root := new_element; END IF; END IF; END IF; END PROCEDURE insert_list; -- -------------------------------------------------------------------- -- Memory READ operation performed above dynamically allocated space -- -------------------------------------------------------------------- PROCEDURE read_mem( linked_list : INOUT mem_data_pointer_t; data : INOUT INTEGER; address : IN INTEGER) IS VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; VARIABLE m_data : INTEGER RANGE -2 TO MaxData; BEGIN IF (linked_list = NULL) THEN -- Not allocated, not written, initial value m_data := -2; ELSE position_list(address, linked_list, found, prev); IF (found /= NULL) THEN IF found.key_address = address THEN -- Allocated, val_data stored m_data := found.val_data; ELSE -- Not allocated, not written, initial value m_data := -2; END IF; ELSE -- Not allocated, not written, initial value m_data := -2; END IF; END IF; data := m_data; END PROCEDURE read_mem; -- ------------------------------------------------------------------ -- Memory WRITE operation performed above dynamically allocated space -- ------------------------------------------------------------------ PROCEDURE write_mem( linked_list : INOUT mem_data_pointer_t; address : IN INTEGER; data : IN INTEGER) IS BEGIN -- Handle possible root value update IF (linked_list /= NULL) THEN insert_list(address, data, linked_list); ELSE create_list(address, data, linked_list); END IF; END PROCEDURE write_mem; ------------------------------------------------------------------- -- Handle dynamic memory allocation ------------------------------------------------------------------- -- Partition dynamically allocated space for performance CONSTANT list_num : INTEGER := MaxBank-1; -- 8 list, 1 for each bank CONSTANT list_size : INTEGER := 16#20000#; -- Access dynamically allocated space SHARED VARIABLE linked_list : mem_data_pointer_array_t(0 TO list_num); SHARED VARIABLE list_id_v : NATURAL; SHARED VARIABLE mem_address : INTEGER RANGE 0 TO MaxRow*MaxColumn; SHARED VARIABLE mem_data : INTEGER RANGE -2 TO MaxData; -- Asure proper initialization PROCEDURE initialize_list IS VARIABLE I : INTEGER; BEGIN FOR I IN 0 TO list_num LOOP linked_list(I) := NULL; END LOOP; END PROCEDURE initialize_list; BEGIN read_dqs_enabled_g <= read_dqs_enabled_0(0) OR read_dqs_enabled_0(1) OR read_dqs_enabled_0(2) OR read_dqs_enabled_0(3) OR read_dqs_enabled_0(4) OR read_dqs_enabled_0(5) OR read_dqs_enabled_0(6) OR read_dqs_enabled_0(7) OR read_dqs_enabled_1(0) OR read_dqs_enabled_1(1) OR read_dqs_enabled_1(2) OR read_dqs_enabled_1(3) OR read_dqs_enabled_1(4) OR read_dqs_enabled_1(5) OR read_dqs_enabled_1(6) OR read_dqs_enabled_1(7) OR read_dqs_enabled_2(0) OR read_dqs_enabled_2(1) OR read_dqs_enabled_2(2) OR read_dqs_enabled_2(3) OR read_dqs_enabled_2(4) OR read_dqs_enabled_2(5) OR read_dqs_enabled_2(6) OR read_dqs_enabled_2(7) OR read_dqs_enabled_3(0) OR read_dqs_enabled_3(1) OR read_dqs_enabled_3(2) OR read_dqs_enabled_3(3) OR read_dqs_enabled_3(4) OR read_dqs_enabled_3(5) OR read_dqs_enabled_3(6) OR read_dqs_enabled_3(7) OR read_dqs_enabled_4(0) OR read_dqs_enabled_4(1) OR read_dqs_enabled_4(2) OR read_dqs_enabled_4(3) OR read_dqs_enabled_4(4) OR read_dqs_enabled_4(5) OR read_dqs_enabled_4(6) OR read_dqs_enabled_4(7) OR read_dqs_enabled_5(0) OR read_dqs_enabled_5(1) OR read_dqs_enabled_5(2) OR read_dqs_enabled_5(3) OR read_dqs_enabled_5(4) OR read_dqs_enabled_5(5) OR read_dqs_enabled_5(6) OR read_dqs_enabled_5(7) OR read_dqs_enabled_6(0) OR read_dqs_enabled_6(1) OR read_dqs_enabled_6(2) OR read_dqs_enabled_6(3) OR read_dqs_enabled_6(4) OR read_dqs_enabled_6(5) OR read_dqs_enabled_6(6) OR read_dqs_enabled_6(7) OR read_dqs_enabled_7(0) OR read_dqs_enabled_7(1) OR read_dqs_enabled_7(2) OR read_dqs_enabled_7(3) OR read_dqs_enabled_7(4) OR read_dqs_enabled_7(5) OR read_dqs_enabled_7(6) OR read_dqs_enabled_7(7); read_data_enabled_g <=(read_data_enabled_0(0) OR read_data_enabled_0(1) OR read_data_enabled_0(2) OR read_data_enabled_0(3) OR read_data_enabled_0(4) OR read_data_enabled_0(5) OR read_data_enabled_0(6) OR read_data_enabled_0(7) OR read_data_enabled_1(0) OR read_data_enabled_1(1) OR read_data_enabled_1(2) OR read_data_enabled_1(3) OR read_data_enabled_1(4) OR read_data_enabled_1(5) OR read_data_enabled_1(6) OR read_data_enabled_1(7) OR read_data_enabled_2(0) OR read_data_enabled_2(1) OR read_data_enabled_2(2) OR read_data_enabled_2(3) OR read_data_enabled_2(4) OR read_data_enabled_2(5) OR read_data_enabled_2(6) OR read_data_enabled_2(7) OR read_data_enabled_3(0) OR read_data_enabled_3(1) OR read_data_enabled_3(2) OR read_data_enabled_3(3) OR read_data_enabled_3(4) OR read_data_enabled_3(5) OR read_data_enabled_3(6) OR read_data_enabled_3(7) OR read_data_enabled_4(0) OR read_data_enabled_4(1) OR read_data_enabled_4(2) OR read_data_enabled_4(3) OR read_data_enabled_4(4) OR read_data_enabled_4(5) OR read_data_enabled_4(6) OR read_data_enabled_4(7) OR read_data_enabled_5(0) OR read_data_enabled_5(1) OR read_data_enabled_5(2) OR read_data_enabled_5(3) OR read_data_enabled_5(4) OR read_data_enabled_5(5) OR read_data_enabled_5(6) OR read_data_enabled_5(7) OR read_data_enabled_6(0) OR read_data_enabled_6(1) OR read_data_enabled_6(2) OR read_data_enabled_6(3) OR read_data_enabled_6(4) OR read_data_enabled_6(5) OR read_data_enabled_6(6) OR read_data_enabled_6(7) OR read_data_enabled_7(0) OR read_data_enabled_7(1) OR read_data_enabled_7(2) OR read_data_enabled_7(3) OR read_data_enabled_7(4) OR read_data_enabled_7(5) OR read_data_enabled_7(6) OR read_data_enabled_7(7)) AND r_burst_n_interrupted_g; write_data_enabled_g <=(write_data_enabled_0(0) OR write_data_enabled_0(1) OR write_data_enabled_0(2) OR write_data_enabled_0(3) OR write_data_enabled_0(4) OR write_data_enabled_0(5) OR write_data_enabled_0(6) OR write_data_enabled_0(7) OR write_data_enabled_1(0) OR write_data_enabled_1(1) OR write_data_enabled_1(2) OR write_data_enabled_1(3) OR write_data_enabled_1(4) OR write_data_enabled_1(5) OR write_data_enabled_1(6) OR write_data_enabled_1(7) OR write_data_enabled_2(0) OR write_data_enabled_2(1) OR write_data_enabled_2(2) OR write_data_enabled_2(3) OR write_data_enabled_2(4) OR write_data_enabled_2(5) OR write_data_enabled_2(6) OR write_data_enabled_2(7) OR write_data_enabled_3(0) OR write_data_enabled_3(1) OR write_data_enabled_3(2) OR write_data_enabled_3(3) OR write_data_enabled_3(4) OR write_data_enabled_3(5) OR write_data_enabled_3(6) OR write_data_enabled_3(7) OR write_data_enabled_4(0) OR write_data_enabled_4(1) OR write_data_enabled_4(2) OR write_data_enabled_4(3) OR write_data_enabled_4(4) OR write_data_enabled_4(5) OR write_data_enabled_4(6) OR write_data_enabled_4(7) OR write_data_enabled_5(0) OR write_data_enabled_5(1) OR write_data_enabled_5(2) OR write_data_enabled_5(3) OR write_data_enabled_5(4) OR write_data_enabled_5(5) OR write_data_enabled_5(6) OR write_data_enabled_5(7) OR write_data_enabled_6(0) OR write_data_enabled_6(1) OR write_data_enabled_6(2) OR write_data_enabled_6(3) OR write_data_enabled_6(4) OR write_data_enabled_6(5) OR write_data_enabled_6(6) OR write_data_enabled_6(7) OR write_data_enabled_7(0) OR write_data_enabled_7(1) OR write_data_enabled_7(2) OR write_data_enabled_7(3) OR write_data_enabled_7(4) OR write_data_enabled_7(5) OR write_data_enabled_7(6) OR write_data_enabled_7(7))AND w_burst_n_interrupted_g; r_burst_n_interrupted_g <= r_burst_n_interrupted_0(0) AND r_burst_n_interrupted_0(1) AND r_burst_n_interrupted_0(2) AND r_burst_n_interrupted_0(3) AND r_burst_n_interrupted_0(4) AND r_burst_n_interrupted_0(5) AND r_burst_n_interrupted_0(6) AND r_burst_n_interrupted_0(7) AND r_burst_n_interrupted_1(0) AND r_burst_n_interrupted_1(1) AND r_burst_n_interrupted_1(2) AND r_burst_n_interrupted_1(3) AND r_burst_n_interrupted_1(4) AND r_burst_n_interrupted_1(5) AND r_burst_n_interrupted_1(6) AND r_burst_n_interrupted_1(7) AND r_burst_n_interrupted_2(0) AND r_burst_n_interrupted_2(1) AND r_burst_n_interrupted_2(2) AND r_burst_n_interrupted_2(3) AND r_burst_n_interrupted_2(4) AND r_burst_n_interrupted_2(5) AND r_burst_n_interrupted_2(6) AND r_burst_n_interrupted_2(7) AND r_burst_n_interrupted_3(0) AND r_burst_n_interrupted_3(1) AND r_burst_n_interrupted_3(2) AND r_burst_n_interrupted_3(3) AND r_burst_n_interrupted_3(4) AND r_burst_n_interrupted_3(5) AND r_burst_n_interrupted_3(6) AND r_burst_n_interrupted_3(7) AND r_burst_n_interrupted_4(0) AND r_burst_n_interrupted_4(1) AND r_burst_n_interrupted_4(2) AND r_burst_n_interrupted_4(3) AND r_burst_n_interrupted_4(4) AND r_burst_n_interrupted_4(5) AND r_burst_n_interrupted_4(6) AND r_burst_n_interrupted_4(7) AND r_burst_n_interrupted_5(0) AND r_burst_n_interrupted_5(1) AND r_burst_n_interrupted_5(2) AND r_burst_n_interrupted_5(3) AND r_burst_n_interrupted_5(4) AND r_burst_n_interrupted_5(5) AND r_burst_n_interrupted_5(6) AND r_burst_n_interrupted_5(7); w_burst_n_interrupted_g <= w_burst_n_interrupted_0(0) AND w_burst_n_interrupted_0(1) AND w_burst_n_interrupted_0(2) AND w_burst_n_interrupted_0(3) AND w_burst_n_interrupted_0(4) AND w_burst_n_interrupted_0(5) AND w_burst_n_interrupted_0(6) AND w_burst_n_interrupted_0(7) AND w_burst_n_interrupted_1(0) AND w_burst_n_interrupted_1(1) AND w_burst_n_interrupted_1(2) AND w_burst_n_interrupted_1(3) AND w_burst_n_interrupted_1(4) AND w_burst_n_interrupted_1(5) AND w_burst_n_interrupted_1(6) AND w_burst_n_interrupted_1(7) AND w_burst_n_interrupted_2(0) AND w_burst_n_interrupted_2(1) AND w_burst_n_interrupted_2(2) AND w_burst_n_interrupted_2(3) AND w_burst_n_interrupted_2(4) AND w_burst_n_interrupted_2(5) AND w_burst_n_interrupted_2(6) AND w_burst_n_interrupted_2(7) AND w_burst_n_interrupted_3(0) AND w_burst_n_interrupted_3(1) AND w_burst_n_interrupted_3(2) AND w_burst_n_interrupted_3(3) AND w_burst_n_interrupted_3(4) AND w_burst_n_interrupted_3(5) AND w_burst_n_interrupted_3(6) AND w_burst_n_interrupted_3(7) AND w_burst_n_interrupted_4(0) AND w_burst_n_interrupted_4(1) AND w_burst_n_interrupted_4(2) AND w_burst_n_interrupted_4(3) AND w_burst_n_interrupted_4(4) AND w_burst_n_interrupted_4(5) AND w_burst_n_interrupted_4(6) AND w_burst_n_interrupted_4(7) AND w_burst_n_interrupted_5(0) AND w_burst_n_interrupted_5(1) AND w_burst_n_interrupted_5(2) AND w_burst_n_interrupted_5(3) AND w_burst_n_interrupted_5(4) AND w_burst_n_interrupted_5(5) AND w_burst_n_interrupted_5(6) AND w_burst_n_interrupted_5(7); tsetup_UDQS_CK <= 0.2 * t_CK; -- tDSS thold_UDQS_CK <= 0.2 * t_CK; -- tDSH tpwCKEnegedge <= 3 * t_CK; -- tCKE tpwDQ0posedge <= 0.35 * t_CK; -- tDIPW (DQ and DM) tpwDQSposedge <= 0.35 * t_CK; -- tDQSL,H tpwA0posedge <= 0.6 * t_CK; -- tIPW tpwCKposedge <= 0.45 * t_CK; tpwCKnegedge <= 0.45 * t_CK; tdevice_MRD <= 2 * t_CK; --Mode register set cycle time tdevic_RPRE <= 1.1 * t_CK; tdevic_RPST <= 0.6 * t_CK; tdevic_WPRE <= 0.35 * t_CK; tdevic_WPST <= 0.35 * t_CK; tdevice_XARD <= 2* t_CK; tdevice_XARDS <= (6-AL) * t_CK; tdevice_XP <= 2 * t_CK; tdevice_XSRD <= 200 * t_CK; -- by default data outputs are 'Z', might get over-written by _zd 's -- of the passes below DataOut <= (OTHERS => 'Z'); --------------------------------------------------------------- -- Process section --------------------------------------------------------------- --------------------------------------------------------------------------- -- VITAL Timing Checks Procedures --------------------------------------------------------------------------- VITALTimingCheck: PROCESS (DataIn, AddressIn, CKIn, CKEIn, CSNegIn, CASNegIn,RASNegIn, WENegIn, UDQSIn, UDMIn) -- Timing check variables VARIABLE TD_DQ0_DQS_diff : VitalTimingDataType; VARIABLE Tviol_DQ0_DQS_diff : X01 := '0'; VARIABLE TD_DQ0_DQS_single : VitalTimingDataType; VARIABLE Tviol_DQ0_DQS_single : X01 := '0'; VARIABLE TD_DM_DQS_diff : VitalTimingDataType; VARIABLE Tviol_DM_DQS_diff : X01 := '0'; VARIABLE TD_DM_DQS_single : VitalTimingDataType; VARIABLE Tviol_DM_DQS_single : X01 := '0'; VARIABLE TD_Address_CK : VitalTimingDataType; VARIABLE Tviol_Address_CK : X01 := '0'; VARIABLE TD_CSNeg_CK : VitalTimingDataType; VARIABLE Tviol_CSNeg_CK : X01 := '0'; VARIABLE TD_RASNeg_CK : VitalTimingDataType; VARIABLE Tviol_RASNeg_CK : X01 := '0'; VARIABLE TD_CASNeg_CK : VitalTimingDataType; VARIABLE Tviol_CASNeg_CK : X01 := '0'; VARIABLE TD_WENeg_CK : VitalTimingDataType; VARIABLE Tviol_WENeg_CK : X01 := '0'; VARIABLE TD_DQS_CK : VitalTimingDataType; VARIABLE Tviol_DQS_CK : X01 := '0'; VARIABLE PD_CK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK : X01 := '0'; VARIABLE PD_DQ : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ : X01 := '0'; VARIABLE PD_DM : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM : X01 := '0'; VARIABLE PD_DQS : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS : X01 := '0'; VARIABLE PD_A0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A0 : X01 := '0'; VARIABLE PD_CS : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CS : X01 := '0'; VARIABLE PD_CAS : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CAS : X01 := '0'; VARIABLE PD_RAS : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RAS : X01 := '0'; VARIABLE PD_WE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WE : X01 := '0'; VARIABLE PD_CKE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CKE : X01 := '0'; VARIABLE Violation : X01 := '0'; BEGIN IF (TimingChecksOn) THEN ------------------------------------------------------------------- -- Timing Check Section ------------------------------------------------------------------- VitalSetupHoldCheck( TestSignal => DataIn, TestSignalName => "DQ", RefSignal => UDQSNeg, RefSignalName => "DQSNeg", SetupHigh => tsetup_DQ0_UDQSNeg, SetupLow => tsetup_DQ0_UDQSNeg, HoldHigh => thold_DQ0_UDQSNeg, HoldLow => thold_DQ0_UDQSNeg, CheckEnabled => DQSNegDis = FALSE AND write_data_enabled_g = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS_diff, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_DQS_diff); VitalSetupHoldCheck( TestSignal => DataIn, TestSignalName => "DQ", RefSignal => UDQSNegIn, RefSignalName => "DQSNeg", SetupHigh => tsetup_DQ0_UDQSNeg, SetupLow => tsetup_DQ0_UDQSNeg, HoldHigh => thold_DQ0_UDQSNeg, HoldLow => thold_DQ0_UDQSNeg, CheckEnabled => DQSNegDis = FALSE AND write_data_enabled_g = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS_diff, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_DQS_diff); VitalSetupHoldCheck( TestSignal => DataIn, TestSignalName => "DQ", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQS, SetupLow => tsetup_DQ0_UDQS, HoldHigh => thold_DQ0_UDQS, HoldLow => thold_DQ0_UDQS, CheckEnabled => DQSNegDis = TRUE AND write_data_enabled_g = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS_single, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_DQS_single); VitalSetupHoldCheck ( TestSignal => DataIn, TestSignalName => "DQ", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQS, SetupLow => tsetup_DQ0_UDQS, HoldHigh => thold_DQ0_UDQS, HoldLow => thold_DQ0_UDQS, CheckEnabled => DQSNegDis = TRUE AND write_data_enabled_g = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS_single, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQ0_DQS_single); VitalSetupHoldCheck ( TestSignal => UDMIn, TestSignalName => "DM", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQSNeg, SetupLow => tsetup_DQ0_UDQSNeg, HoldHigh => thold_DQ0_UDQSNeg, HoldLow => thold_DQ0_UDQSNeg, CheckEnabled => DQSNegDis = FALSE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM_DQS_diff, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DM_DQS_diff); VitalSetupHoldCheck ( TestSignal => UDMIn, TestSignalName => "DM", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQSNeg, SetupLow => tsetup_DQ0_UDQSNeg, HoldHigh => thold_DQ0_UDQSNeg, HoldLow => thold_DQ0_UDQSNeg, CheckEnabled => DQSNegDis = FALSE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM_DQS_diff, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DM_DQS_diff); VitalSetupHoldCheck ( TestSignal => UDMIn, TestSignalName => "DM", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQS, SetupLow => tsetup_DQ0_UDQS, HoldHigh => thold_DQ0_UDQS, HoldLow => thold_DQ0_UDQS, CheckEnabled => DQSNegDis = TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM_DQS_single, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DM_DQS_single); VitalSetupHoldCheck ( TestSignal => UDMIn, TestSignalName => "DM", RefSignal => UDQSIn, RefSignalName => "DQS", SetupHigh => tsetup_DQ0_UDQS, SetupLow => tsetup_DQ0_UDQS, HoldHigh => thold_DQ0_UDQS, HoldLow => thold_DQ0_UDQS, CheckEnabled => DQSNegDis = TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM_DQS_single, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DM_DQS_single); VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CKIn, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_Address_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_Address_CK ); VitalSetupHoldCheck ( TestSignal => CSNegIn, TestSignalName => "CSNeg", RefSignal => CKIn, RefSignalName => "CKIn", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CSNeg_CK ); VitalSetupHoldCheck ( TestSignal => RASNegIn, TestSignalName => "RASNeg", RefSignal => CKIn, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RASNeg_CK ); VitalSetupHoldCheck ( TestSignal => CASNegIn, TestSignalName => "CASNeg", RefSignal => CKIn, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CASNeg_CK ); VitalSetupHoldCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", RefSignal => CKIn, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENeg_CK ); VitalSetupHoldCheck ( TestSignal => UDQSIn, TestSignalName => "DQS", RefSignal => CKIn, RefSignalName => "CK", SetupLow => tsetup_UDQS_CK, HoldLow => thold_UDQS_CK, CheckEnabled => write_data_enabled_g = '1', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DQS_CK ); VitalPeriodPulseCheck( TestSignal => CKIn, TestSignalName => "CK", Period => t_CK, PulseWidthLow => tpwCKposedge, PulseWidthHigh => tpwCKnegedge, PeriodData => PD_CK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CK, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => DataIn(0), TestSignalName => "DQ", PulseWidthLow => tpwDQ0posedge, PulseWidthHigh => tpwDQ0posedge, PeriodData => PD_DQ, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_DQ, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => UDMIn, TestSignalName => "DM", PulseWidthLow => tpwDQ0posedge, PulseWidthHigh => tpwDQ0posedge, PeriodData => PD_DM, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_DM, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => UDQSIn, TestSignalName => "DQS", PulseWidthLow => tpwDQSposedge, PulseWidthHigh => tpwDQSposedge, PeriodData => PD_DQS, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_DQS, HeaderMsg => InstancePath & PartID, CheckEnabled => write_data_enabled_g = '1' ); VitalPeriodPulseCheck ( TestSignal => AddressIn(0), TestSignalName => "Address", PulseWidthLow => tpwA0posedge, PulseWidthHigh => tpwA0posedge, PeriodData => PD_A0, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_A0, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => CSNegIn, TestSignalName => "CSNeg", PulseWidthLow => tpwA0posedge, PulseWidthHigh => tpwA0posedge, PeriodData => PD_CS, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CS, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => CASNegIn, TestSignalName => "CASNeg", PulseWidthLow => tpwA0posedge, PulseWidthHigh => tpwA0posedge, PeriodData => PD_CAS, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CAS, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => RASNegIn, TestSignalName => "RASNeg", PulseWidthLow => tpwA0posedge, PulseWidthHigh => tpwA0posedge, PeriodData => PD_RAS, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RAS, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", PulseWidthLow => tpwA0posedge, PulseWidthHigh => tpwA0posedge, PeriodData => PD_WE, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WE, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => CKEIn, TestSignalName => "CKE", PulseWidthLow => tpwCKEnegedge, PulseWidthHigh => tpwCKEnegedge, PeriodData => PD_CKE, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CKE, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE); Violation := Tviol_DQ0_DQS_diff OR Tviol_DQ0_DQS_single OR Tviol_DM_DQS_diff OR Tviol_DM_DQS_single OR Tviol_Address_CK OR Tviol_CSNeg_CK OR Tviol_RASNeg_CK OR Tviol_CASNeg_CK OR Tviol_WENeg_CK OR Tviol_DQS_CK OR Pviol_CK OR Pviol_DQ OR Pviol_DM OR Pviol_A0 OR Pviol_CS OR Pviol_CAS OR Pviol_RAS OR Pviol_WE OR Pviol_CKE; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY WARNING; END IF; END PROCESS VITALTimingCheck; ----------------------------------------------------------------------- -- Functionality Section ----------------------------------------------------------------------- ----------------------------------------------------------------------- -- Info process ----------------------------------------------------------------------- InfoProcess : PROCESS BEGIN REPORT ""; REPORT "DYNAMIC MEMORY ALLOCATION"; REPORT ""; WAIT; END PROCESS InfoProcess; ----------------------------------------------------------------------- -- Process that reads actual clock frequency ----------------------------------------------------------------------- CK_period_read : PROCESS (CKIn) VARIABLE tprev : TIME := 0 ns; VARIABLE tnow : TIME := 0 ns; BEGIN tprev := tnow; tnow := Now; t_CK <= 2 *(tnow - tprev); END PROCESS CK_period_read; ----------------------------------------------------------------------- -- Process that stores information of previous CKEIn value on CKEIn change ----------------------------------------------------------------------- CKEInPrevAssign : PROCESS (CKEIn, CKIn) BEGIN CKEInPrev <= CKEInnew; CKEInnew <= CKEIn; END PROCESS CKEInPrevAssign; ---------------------------------------------------------------------------- -- Sequential process for FSM state transition ---------------------------------------------------------------------------- State_transition_Gen : FOR i IN MaxBank-1 DOWNTO 0 GENERATE StateTransition : PROCESS(next_state(i)) BEGIN current_state(i) <= next_state(i); END PROCESS StateTransition; END GENERATE State_transition_Gen; ---------------------------------------------------------------------------- -- Command decode process : - reads control signals and generates commands ---------------------------------------------------------------------------- CommandDecode : PROCESS (CKIn) VARIABLE entered_pwr_down : BOOLEAN := FALSE; BEGIN -- commands entered on each CKIn rising edge IF (rising_edge(CKIn)) THEN -- command_changed is used in FSM sensitivity list -- Read new command every CKIn or CKNegIn rise IF (command_update = '1') THEN command_update <= '0'; ELSE command_update <= '1'; END IF; IF (CKEInPrev = '1' OR PoweredUp = FALSE) THEN IF (CKEInNew = '1') THEN -- deselect IF (CSNegIn = '1') THEN command <= deselect; -- nop ELSIF((CSNegIn='0') AND (RASNegIn='1') AND (CASNegIn='1') AND (WENegIn = '1')) THEN command <= nop; -- (extended) mode register set ELSIF ((CSNegIn='0') AND (RASNegIn='0') AND (CASNegIn='0') AND (WENegIn = '0')) THEN command <= mrs; -- + BA[2:0], A[12:0] loaded -- auto refresh ELSIF ((CSNegIn='0') AND (RASNegIn='0') AND (CASNegIn='0') AND (WENegIn = '1')) THEN command <= autoref; -- bank activate ELSIF ((CSNegIn='0') AND (RASNegIn='0') AND (CASNegIn='1') AND (WENegIn = '1')) THEN command <= bankact; -- precharge single bank -- precharge all banks ELSIF ((CSNegIn='0') AND (RASNegIn='0') AND (CASNegIn='1') AND (WENegIn = '0')) THEN IF AddressIn(10) = '0' THEN command <= presingle; ELSE command <= preall; END IF; -- write -- write with auto precharge ELSIF ((CSNegIn='0') AND (RASNegIn='1') AND (CASNegIn='0') AND (WENegIn = '0')) THEN IF AddressIn(10) = '0' THEN command <= write; ELSE command <= writeapre; END IF; -- read -- read with auto precharge ELSIF ((CSNegIn='0') AND (RASNegIn='1') AND (CASNegIn='0') AND (WENegIn = '1')) THEN IF AddressIn(10) = '0' THEN command <= read; ELSE command <= readapre; END IF; END IF; ELSE --( CKEInNew = '0') -- self refresh entry IF ((CSNegIn='0') AND (RASNegIn='0') AND (CASNegIn='0') AND (WENegIn = '1')) THEN command <= selfrefentry; -- CKE : H -> L (entry) END IF; -- power down entry IF ( (CSNegIn = '1') OR ((CSNegIn='0') AND (RASNegIn='1') AND (CASNegIn='1') AND (WENegIn = '1')) ) THEN command <= pwrdwnentry; -- CKE : H -> L (entry) entered_pwr_down := TRUE; END IF; END IF; ELSIF (CKEInPrev = '0' AND CKEInNew = '1') THEN -- self refresh exit -- power down exit IF ( (CSNegIn = '1') OR ((CSNegIn = '0') AND (RASNegIn = '1') AND (CASNegIn = '1') AND (WENegIn = '1')) ) THEN command <= selfrefpwrdwnexit; -- CKE : L -> H (exit) entered_pwr_down := FALSE; END IF; ELSE -- (CKEInPrev = '0' AND CKEInNew = '0') IF (entered_pwr_down = TRUE) THEN command <= nop; END IF; END IF; -- CKEInPrev = '1' END IF; -- rising_edge(CKIn) END PROCESS CommandDecode; --------------------------------------------------------------------------- -- State Generation Process -- combinational process for next state generation --------------------------------------------------------------------------- StateGen : PROCESS(command_update) VARIABLE all_banks_precharged : BOOLEAN; VARIABLE enable_precharge_all : BOOLEAN; VARIABLE init_counter : INTEGER := 0; VARIABLE timing_ok : std_logic := '1'; BEGIN -- Initialization sequence IF (PoweredUp = FALSE) THEN -- 'Power Up - Initialization' STATE MACHINE IF (current_state(0) = init_state) THEN IF ((command = nop) OR (command = deselect)) THEN init_counter := 1; ELSIF ((command = preall) AND (init_counter = 1)) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= precharge_state; END LOOP; init_counter := 2; ELSE ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " during initialization!" SEVERITY WARNING; END IF; ELSIF (current_state(0) = mrs_set_state) THEN -- automatic transition of all banks to idle_state after finish IF (mrs_finished(0) = TRUE) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= idle_state; END LOOP; IF (init_counter >= 11) THEN PoweredUp <= TRUE; END IF; END IF; ELSIF (current_state(0) = idle_state) THEN IF (command = mrs) THEN init_counter := init_counter +1; FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= mrs_set_state; END LOOP; END IF; IF ((command = preall) AND (init_counter >= 6)) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= precharge_state; END LOOP; init_counter := 7; END IF; IF ((command = autoref) AND (init_counter >= 7 )) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= auto_refresh_state; END LOOP; init_counter := 8; END IF; ELSIF (current_state(0) = precharge_state) THEN -- automatic transition of all banks to idle_state after finish IF (prech_finished(0) = TRUE) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= idle_state; END LOOP; END IF; ELSE -- auto_refresh_state : -- automatic transition of all banks to idle_state after finish IF (aref_finished(0) = TRUE) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= idle_state; END LOOP; END IF; END IF; ELSE -- PoweredUp = TRUE -- 'Powered Up' STATE MACHINE -- current bank (0..7) IF ((command = presingle) OR (command = bankact) OR (command = write) OR (command = writeapre) OR (command = read) OR (command = readapre)) THEN current_bank := To_Nat (BAIn(2 downto 0)); ELSIF ((command /= nop) AND (command /= deselect)) THEN current_bank := NoneBank; -- none bank selected END IF; -- current row (0..8191) IF (command = bankact) THEN current_row(current_bank) := To_Nat (AddressIn(12 downto 0)); END IF; -- current column (0..1023) IF ((command = write) OR (command = writeapre) OR (command = read) OR (command = readapre)) THEN columnFIFObuffer(in_index) := To_Nat (AddressIn(9 downto 0)); IF (in_index) = 7 THEN in_index := 0; ELSE in_index := in_index + 1; END IF; END IF; enable_precharge_all := FALSE; IF (command = preall) THEN FOR i IN 0 TO MaxBank-1 LOOP IF ((current_state(i) = bank_active_state) OR (current_state(i) = write_state) OR (current_state(i) = read_state)) THEN enable_precharge_all := TRUE; END IF; END LOOP; END IF; all_banks_precharged := TRUE; FOR i IN 0 TO MaxBank-1 LOOP IF (current_state(i) /= idle_state) THEN all_banks_precharged := FALSE; END IF; END LOOP; --PROTOCOL CHECKING timing_ok := '1'; IF (command = presingle) THEN IF (ras_out(current_bank) /= ras_in(current_bank)) THEN ASSERT FALSE REPORT InstancePath & partID & ": Precharge cannot be executed due to" & " tRAS time is not met!" SEVERITY WARNING; timing_ok := '0'; END IF; ELSIF (command = bankact) THEN IF (rp_out(current_bank) /= rp_in(current_bank)) THEN ASSERT FALSE REPORT InstancePath & partID & ": Bank Activation cannot be executed due to" & " tRP time is not met!" SEVERITY WARNING; timing_ok := '0'; END IF; ELSIF ((command = write) OR (command = writeapre) OR (command = read) OR (command = readapre)) THEN IF (rcd_out(current_bank) /= rcd_in(current_bank)) THEN ASSERT FALSE REPORT InstancePath & partID & ": Memory access (read or write) cannot be" & " executed due to tRCD time is not met!" SEVERITY WARNING; timing_ok := '0'; END IF; END IF; -- STATE MACHINE : IF (timing_ok = '1') THEN -- STATE MACHINE : -- bank_act , write , read -> precharge (all) IF (enable_precharge_all = TRUE) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= precharge_state; END LOOP; END IF; -- idle -> mrs, self_refresh, auto_refresh, pwrdwn_precharge IF (all_banks_precharged = TRUE) THEN IF (command = mrs) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= mrs_set_state; END LOOP; END IF; IF (command = autoref) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= auto_refresh_state; END LOOP; END IF; IF (command = selfrefentry) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= self_refresh_state; END LOOP; END IF; IF (command = pwrdwnentry) THEN FOR i IN 0 TO MaxBank-1 LOOP next_state(i) <= pwrdown_precharge_state; END LOOP; END IF; ELSE IF ((command = mrs) OR (command = autoref) OR ((current_state(0) /= self_refresh_state) AND (command = selfrefentry))) THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " All banks must be precharged!" SEVERITY WARNING; END IF; END IF; FOR i IN 0 TO MaxBank-1 LOOP CASE current_state(i) IS -- mrs -> idle WHEN mrs_set_state => IF (mrs_finished(0) = TRUE) THEN next_state(i) <= idle_state; END IF; -- pwrdown_active -> bank_active WHEN pwrdown_active_state => IF (command = selfrefpwrdwnexit) THEN next_state(i) <= bank_active_state; END IF; -- pwrdwn_precharge -> idle WHEN pwrdown_precharge_state => IF (command = selfrefpwrdwnexit) THEN next_state(i) <= idle_state; END IF; -- bank_active -> pwrdown_active WHEN bank_active_state => IF (command = pwrdwnentry) THEN next_state(i) <= pwrdown_active_state; END IF; -- precharge -> idle WHEN precharge_state => IF (prech_finished(i) = TRUE) THEN -- automatic transition to idle_state after finish next_state(i) <= idle_state; END IF; -- write -> bank_active WHEN write_state => IF (write_finished(i)) THEN -- automatic transition to bank_active_state after finish next_state(i) <= bank_active_state; END IF; -- read -> bank_active WHEN read_state => IF (read_finished(i)) THEN -- automatic transition to bank_active_state after finish next_state(i) <= bank_active_state; END IF; -- write_auto_precharge -> idle WHEN write_auto_precharge_state => IF (wap_finished(i)) THEN -- automatic transition to idle_state after finish next_state(i) <= idle_state; END IF; -- read_auto_precharge -> idle WHEN read_auto_precharge_state => IF (rap_finished(i)) THEN -- automatic transition to idle_state after finish next_state(i) <= idle_state; END IF; -- self_refresh -> idle WHEN self_refresh_state => IF (command = selfrefpwrdwnexit) THEN next_state(i) <= idle_state; END IF; WHEN auto_refresh_state => -- auto_refresh -> pwrdown_precharge , idle IF (command = pwrdwnentry) THEN next_state(i) <= pwrdown_precharge_state; ELSIF (aref_finished(0) = TRUE) THEN next_state(i) <= idle_state; END IF; WHEN activating_state => IF (command = pwrdwnentry) THEN next_state(i) <= pwrdown_active_state; ELSE next_state(i) <= bank_active_state; END IF; WHEN OTHERS => NULL; END CASE; END LOOP; IF (current_bank /= NoneBank) THEN CASE current_state(current_bank) IS -- idle -> activating -> bank_active_state WHEN idle_state => IF (command = bankact) THEN -- automatic transition to bank_active_state t_CK from -- entering activating_state next_state(current_bank) <= activating_state; ELSIF (command /= nop) AND (command /= deselect) THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " expecting bank activating command" SEVERITY WARNING; END IF; -- bank_active -> write , write_auto_precharge -- read , read_auto_precharge, precharge WHEN bank_active_state => IF (command = write) THEN next_state(current_bank) <= write_state; ELSIF (command = writeapre) THEN next_state(current_bank) <= write_auto_precharge_state; ELSIF (command = read) THEN next_state(current_bank) <= read_state; ELSIF (command = readapre) THEN next_state(current_bank) <= read_auto_precharge_state; ELSIF (command = presingle) THEN next_state(current_bank) <= precharge_state; ELSIF (command /= nop) AND (command /= deselect) THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " Bank is already ACTIVE" SEVERITY WARNING; END IF; -- write -> write_auto_precharge, read, read_auto_precharge, -- precharge, bank_active WHEN write_state => IF (command = write) THEN new_rw <= NOT new_rw; ELSIF (command = writeapre) THEN next_state(current_bank) <= write_auto_precharge_state; ELSIF (command = read) THEN next_state(current_bank) <= read_state; ELSIF (command = readapre) THEN next_state(current_bank) <= read_auto_precharge_state; ELSIF (command = presingle) THEN next_state(current_bank) <= precharge_state; END IF; -- read -> read_auto_precharge, write, write_auto_precharge, -- precharge, bank_active WHEN read_state => IF (command = read) THEN new_rw <= NOT new_rw; ELSIF (command = readapre) THEN next_state(current_bank) <= read_auto_precharge_state; ELSIF (command = write) THEN next_state(current_bank) <= write_state; ELSIF (command = writeapre) THEN next_state(current_bank) <= write_auto_precharge_state; ELSIF (command = presingle) THEN next_state(current_bank) <= precharge_state; END IF; WHEN OTHERS => NULL; END CASE; END IF; END IF; -- (timing_ok = '1') END IF; --(PoweredUp /= TRUE) END PROCESS StateGen; --------------------------------------------------------------------------- --FSM Output generation and general funcionality --------------------------------------------------------------------------- Functional_Gen : FOR i IN MaxBank-1 DOWNTO 0 GENERATE Functional : PROCESS(current_state(i), new_rw) VARIABLE idle_entry : TIME := 0 ns; VARIABLE mrs_set_entry : TIME := 0 ns; VARIABLE self_refresh_entry : TIME := 0 ns; VARIABLE auto_refresh_entry : TIME := 0 ns; VARIABLE pwrdown_precharge_entry : TIME := 0 ns; VARIABLE pwrdown_active_entry : TIME := 0 ns; VARIABLE activating_entry : TIME := 0 ns; VARIABLE bank_active_entry : TIME := 0 ns; VARIABLE write_entry : TIME := 0 ns; VARIABLE write_auto_precharge_entry : TIME := 0 ns; VARIABLE read_entry : TIME := 0 ns; VARIABLE read_auto_precharge_entry : TIME := 0 ns; VARIABLE precharge_entry : TIME := 0 ns; VARIABLE j : INTEGER RANGE 0 TO 7 := 0; VARIABLE k : INTEGER RANGE 0 TO 7 := 0; VARIABLE m : INTEGER RANGE 0 TO 5 := 0; VARIABLE n : INTEGER RANGE 0 TO 5 := 0; BEGIN CASE current_state(i) IS WHEN idle_state => idle_entry := Now; WHEN mrs_set_state => IF (i=0) THEN mrs_set_entry := Now; mrs_finished(i) <= FALSE, TRUE after tdevice_MRD, FALSE after tdevice_MRD + t_CK; CASE BAIn IS --MRS WHEN "000" => CASE AddressIn(2 downto 0) IS WHEN "010" => BL := 4; WHEN "011" => BL := 8; WHEN OTHERS => BL := 0; ASSERT FALSE REPORT InstancePath & partID & ": Illegal : Address[2..0]" & " BL cannot be adjusted" SEVERITY WARNING; END CASE; CASE AddressIn(3) IS WHEN '0' => BT := sequential; WHEN OTHERS => -- WHEN '1' BT := interleaved; END CASE; CASE AddressIn(6 downto 4) IS WHEN "010" => CL := 2; WHEN "011" => CL := 3; WHEN "100" => CL := 4; WHEN "101" => CL := 5; WHEN "110" => CL := 6; WHEN OTHERS => CL := 1; ASSERT FALSE REPORT InstancePath & partID & ": Illegal : Address[6..4]" & " CL cannot be adjusted" SEVERITY WARNING; END CASE; RL := AL + CL; WL := RL -1; TM := AddressIn(7); DLLreset := AddressIn(8); CASE AddressIn(11 downto 9) IS WHEN "001" => WR := 2; WHEN "010" => WR := 3; WHEN "011" => WR := 4; WHEN "100" => WR := 5; WHEN "101" => WR := 6; WHEN OTHERS => WR := 1; ASSERT FALSE REPORT InstancePath & partID & ": Illegal : Address[11..9]" & " WR cannot be adjusted" SEVERITY WARNING; END CASE; CASE AddressIn(12) IS WHEN '0' => PD := standard; WHEN OTHERS => -- WHEN '1' PD := lowpower; END CASE; -- EMRS(1) WHEN "001" => DLLenable := AddressIn(0); DIC := AddressIn(1); CASE AddressIn(5 downto 3) IS WHEN "000" => AL := 0; WHEN "001" => AL := 1; WHEN "010" => AL := 2; WHEN "011" => AL := 3; WHEN "100" => AL := 4; WHEN OTHERS => AL := 0; ASSERT FALSE REPORT InstancePath & partID & ": Illegal : Address[5..3]" & " AL cannot be adjusted" SEVERITY WARNING; END CASE; RL := AL + CL; WL := RL -1; IF (AddressIn(10) = '1') THEN DQSNegDis := TRUE; ELSE DQSNegDis := FALSE; END IF; QoffHIz := AddressIn(12); -- EMRS(2) WHEN "010" => IF (AddressIn(12 downto 8)&AddressIn(6 downto 0) /= "000000000000") THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " EMRS(2) cannot be adjusted" SEVERITY ERROR; END IF; -- EMRS(3) WHEN "011" => IF (AddressIn /= "0000000000000") THEN ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " EMRS(3) cannot be adjusted" SEVERITY ERROR; END IF; WHEN OTHERS => --BAIn[2] is '1' ASSERT FALSE REPORT InstancePath & partID & ": Illegal command" & " BA[2] = '1' is NOT allowed !" SEVERITY ERROR; END CASE; -- BAIn END IF; -- (i = 0) WHEN self_refresh_state => IF (i = 0) THEN self_refresh_entry := Now; END IF; WHEN auto_refresh_state => IF (i = 0) THEN auto_refresh_entry := Now; aref_finished(i) <= FALSE, TRUE AFTER tdevice_RFC, FALSE AFTER tdevice_RFC + t_CK; END IF; WHEN pwrdown_precharge_state => IF (i = 0) THEN pwrdown_precharge_entry := Now; END IF; WHEN pwrdown_active_state => pwrdown_active_entry := Now; WHEN activating_state => activating_entry := Now; ras_in(i) <= NOT ras_in(i); rc_in(i) <= NOT rc_in(i); rcd_in(i) <= NOT rcd_in(i); WHEN bank_active_state => bank_active_entry := Now; WHEN write_state | write_auto_precharge_state => IF ((BL = 8) AND ((Now - write_entry) = 2* t_CK)) THEN IF (m = 0) THEN w_burst_n_interrupted_0(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; ELSIF (m = 1) THEN w_burst_n_interrupted_1(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; ELSIF (m = 2) THEN w_burst_n_interrupted_2(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; ELSIF (m = 3) THEN w_burst_n_interrupted_3(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; ELSIF (m = 4) THEN w_burst_n_interrupted_4(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; ELSE w_burst_n_interrupted_5(i) <= '0' AFTER WL*t_CK - t_CK/4 - t_CK/128, '1' AFTER WL*t_CK - t_CK/4 + t_CK/64; END IF; IF (m = 5) THEN m := 0; ELSE m := m + 1; END IF; END IF; IF (current_state(i) = write_state) THEN write_entry := Now; write_finished(i)<=FALSE, TRUE AFTER (WL+(BL/2))*t_CK+tdevice_WR+t_CK/8; ELSE -- extra tWR time needed to precharge command -- extra tWR+tRP time needed to bank activate command write_auto_precharge_entry := Now; wap_finished(i) <= FALSE, TRUE AFTER (WL+(BL/2)+WR)*t_CK; END IF; IF (k = 0) THEN write_data_enabled_0(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 1) THEN write_data_enabled_1(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 2) THEN write_data_enabled_2(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 3) THEN write_data_enabled_3(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 4) THEN write_data_enabled_4(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 5) THEN write_data_enabled_5(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSIF (k = 6) THEN write_data_enabled_6(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; ELSE write_data_enabled_7(i) <= '1' AFTER (WL)*t_CK - t_CK/4 + t_CK/128, '0' AFTER (WL+(BL/2))*t_CK - t_CK/4 - t_CK/128; END IF; IF (k = 7) THEN k := 0; ELSE k := k + 1; END IF; WHEN read_state | read_auto_precharge_state => IF ((BL = 8) AND ((Now - read_entry) = 2*t_CK)) THEN IF (n = 0) THEN r_burst_n_interrupted_0(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; ELSIF (n = 1) THEN r_burst_n_interrupted_1(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; ELSIF (n = 2) THEN r_burst_n_interrupted_2(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; ELSIF (n = 3) THEN r_burst_n_interrupted_3(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; ELSIF (n = 4) THEN r_burst_n_interrupted_4(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; ELSE r_burst_n_interrupted_5(i) <= '0' AFTER RL*t_CK - 3*t_CK/8, '1' AFTER RL*t_CK - t_CK/8; END IF; IF (n = 5) THEN n := 0; ELSE n := n + 1; END IF; END IF; read_entry := Now; IF (current_state(i) = read_state) THEN rtp_in(i) <= NOT rtp_in(i); read_finished(i) <= FALSE, TRUE AFTER (RL+(BL/2))*t_CK + t_CK/8; ELSE rap_finished(i) <= FALSE, TRUE AFTER (RL-1+BL/4)*t_CK + tdevice_RP + tdevice_RTP; END IF; IF (j = 0) THEN read_dqs_enabled_0(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_0(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 1) THEN read_dqs_enabled_1(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_1(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 2) THEN read_dqs_enabled_2(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_2(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 3) THEN read_dqs_enabled_3(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_3(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 4) THEN read_dqs_enabled_4(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_4(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 5) THEN read_dqs_enabled_5(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_data_enabled_5(i) <= '1' AFTER (RL)*t_CK, '0' AFTER (RL + (BL/2))*t_CK - t_CK/2 + t_CK/8; ELSIF (j = 6) THEN read_dqs_enabled_6(i) <= '1' AFTER (RL-1)*t_CK, '0' AFTER (RL)*t_CK; read_da