-------------------------------------------------------------------------------- -- File Name: hm5113805f.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 S.Janevski 07 Aug 24 Initial release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: HM5113805F -- -- Description: 128M (16 Mword x 8) EDO DRAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY hm5113805f IS GENERIC ( -- tipd delays: interconnect path delays tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_IO0 : VitalDelayType01 := VitalZeroDelay01; tipd_IO1 : VitalDelayType01 := VitalZeroDelay01; tipd_IO2 : VitalDelayType01 := VitalZeroDelay01; tipd_IO3 : VitalDelayType01 := VitalZeroDelay01; tipd_IO4 : VitalDelayType01 := VitalZeroDelay01; tipd_IO5 : VitalDelayType01 := VitalZeroDelay01; tipd_IO6 : VitalDelayType01 := VitalZeroDelay01; tipd_IO7 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CASNeg_IO0_neg_edge : VitalDelayType01Z := UnitDelay01Z; -- tCAC tpd_CASNeg_IO0_pos_edge : VitalDelayType01Z := UnitDelay01Z; -- tCPA tpd_OENeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tOEA tpd_RASNeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tRAC tpd_A0_IO0 : VitalDelayType01 := UnitDelay01; -- tAA tpd_WENeg_IO0 : VitalDelayType01Z := UnitDelay01Z; -- tWEZ -- tsetup values tsetup_A0_RASNeg : VitalDelayType := UnitDelay; -- tRAL tsetup_A0_CASNeg : VitalDelayType := UnitDelay; -- tCAL tsetup_CASNeg_WENeg : VitalDelayType := UnitDelay; -- tCWD tsetup_A0_WENeg : VitalDelayType := UnitDelay; -- tAWD tsetup_IO0_WENeg : VitalDelayType := UnitDelay; -- tDS tsetup_IO0_CASNeg : VitalDelayType := UnitDelay; -- tDS tsetup_RASNeg_CASNeg_read_noedge_posedge : VitalDelayType := UnitDelay; -- tCSH tsetup_RASNeg_CASNeg_read1_noedge_negedge : VitalDelayType := UnitDelay; -- tRCD tsetup_CASNeg_RASNeg_cas_before2_noedge_negedge : VitalDelayType := UnitDelay; --tCSR -- thold values thold_A0_RASNeg : VitalDelayType := UnitDelay; -- tRAH thold_A0_CASNeg : VitalDelayType := UnitDelay; -- tCAH thold_RASNeg_WENeg : VitalDelayType := UnitDelay; -- tRWL thold_CASNeg_WENeg : VitalDelayType := UnitDelay; -- tCWL thold_WENeg_CASNeg : VitalDelayType := UnitDelay; -- tWCH thold_WENeg_RASNeg : VitalDelayType := UnitDelay; -- tWRH thold_OENeg_WENeg : VitalDelayType := UnitDelay; -- tOEH thold_CASNeg_OENeg : VitalDelayType := UnitDelay; --tCOL thold_OENeg_CASNeg : VitalDelayType := UnitDelay; -- tCOP thold_IO0_WENeg : VitalDelayType := UnitDelay; -- tDH thold_IO0_CASNeg : VitalDelayType := UnitDelay; -- tDH thold_RASNeg_CASNeg_read_noedge_negedge : VitalDelayType := UnitDelay; -- tRSH thold_CASNeg_RASNeg_cas_before1_noedge_posedge : VitalDelayType := UnitDelay; --tRPC thold_CASNeg_RASNeg_cas_before2_noedge_negedge : VitalDelayType := UnitDelay; -- tCHR thold_RASNeg_CASNeg_cas_before1_noedge_posedge : VitalDelayType := UnitDelay; -- tCRP thold_RASNeg_CASNeg_page_rd_noedge_posedge : VitalDelayType := UnitDelay; -- tCPRH thold_WENeg_CASNeg_page_rd_noedge_posedge : VitalDelayType := UnitDelay; -- tRCHC thold_WENeg_CASNeg_page_rd_mod_noedge_posedge : VitalDelayType := UnitDelay; -- tCPW -- tpw values tpw_CASNeg_negedge : VitalDelayType := UnitDelay; -- tCAS tpw_RASNeg_negedge : VitalDelayType := UnitDelay; -- tRAS tpw_CASNeg_posedge : VitalDelayType := UnitDelay; -- tCP tpw_RASNeg_posedge : VitalDelayType := UnitDelay; -- tRP tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tWP, tWPE tpw_OENeg_posedge : VitalDelayType := UnitDelay; -- tOEP -- tperiod values tperiod_CASNeg_page_rd : VitalDelayType := UnitDelay; -- tHCP tperiod_CASNeg_page_rd_mod_wr : VitalDelayType := UnitDelay; -- tHPRWC tperiod_RASNeg : VitalDelayType := UnitDelay; -- tRC -- tdevice values: values for internal delays tdevice_tRASMAX : VitalDelayType := 10000 ns; -- TRASMAX tdevice_tRASPMAX : VitalDelayType := 100000 ns; -- TRASPMAX tdevice_tCASMAX : VitalDelayType := 10000 ns; -- TCASMAX tdevice_tRWC : VitalDelayType := 140 ns; -- TRWC tdevice_tRAD : VitalDelayType := 12 ns; -- TRAD tdevice_tRADMAX : VitalDelayType := 30 ns; -- TRADMAX tdevice_tRCDMAX : VitalDelayType := 45 ns; -- TRCDMAX tdevice_tRCHR : VitalDelayType := 60 ns; -- tRCHR tdevice_tRWD : VitalDelayType := 79 ns; -- tRWD tdevice_tOED : VitalDelayType := 15 ns; -- tCDD,tRDD,tWED,tOED -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- memory file to be loaded mem_file_name : string := "none"; UserPreload : boolean := FALSE; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( CASNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; A0 : IN std_ulogic := 'U'; A1 : IN std_ulogic := 'U'; A2 : IN std_ulogic := 'U'; A3 : IN std_ulogic := 'U'; A4 : IN std_ulogic := 'U'; A5 : IN std_ulogic := 'U'; A6 : IN std_ulogic := 'U'; A7 : IN std_ulogic := 'U'; A8 : IN std_ulogic := 'U'; A9 : IN std_ulogic := 'U'; A10 : IN std_ulogic := 'U'; A11 : IN std_ulogic := 'U'; IO0 : INOUT std_ulogic := 'U'; IO1 : INOUT std_ulogic := 'U'; IO2 : INOUT std_ulogic := 'U'; IO3 : INOUT std_ulogic := 'U'; IO4 : INOUT std_ulogic := 'U'; IO5 : INOUT std_ulogic := 'U'; IO6 : INOUT std_ulogic := 'U'; IO7 : INOUT std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 OF hm5113805f : ENTITY IS TRUE; END hm5113805f; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF hm5113805f IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT PartID : string := "hm5113805f"; CONSTANT MaxData : natural := 16#FF#; CONSTANT MemSize : natural := 16#FFFFFF#; CONSTANT RowSize : natural := 16#FFF#; CONSTANT ColSize : natural := 16#FFF#; -- ipd SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL IO0_ipd : std_ulogic := 'U'; SIGNAL IO1_ipd : std_ulogic := 'U'; SIGNAL IO2_ipd : std_ulogic := 'U'; SIGNAL IO3_ipd : std_ulogic := 'U'; SIGNAL IO4_ipd : std_ulogic := 'U'; SIGNAL IO5_ipd : std_ulogic := 'U'; SIGNAL IO6_ipd : std_ulogic := 'U'; SIGNAL IO7_ipd : std_ulogic := 'U'; -- nwv SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL OENeg_nwv : std_ulogic := 'U'; SIGNAL A0_nwv : std_ulogic := 'U'; SIGNAL A1_nwv : std_ulogic := 'U'; SIGNAL A2_nwv : std_ulogic := 'U'; SIGNAL A3_nwv : std_ulogic := 'U'; SIGNAL A4_nwv : std_ulogic := 'U'; SIGNAL A5_nwv : std_ulogic := 'U'; SIGNAL A6_nwv : std_ulogic := 'U'; SIGNAL A7_nwv : std_ulogic := 'U'; SIGNAL A8_nwv : std_ulogic := 'U'; SIGNAL A9_nwv : std_ulogic := 'U'; SIGNAL A10_nwv : std_ulogic := 'U'; SIGNAL A11_nwv : std_ulogic := 'U'; SIGNAL IO0_nwv : std_ulogic := 'U'; SIGNAL IO1_nwv : std_ulogic := 'U'; SIGNAL IO2_nwv : std_ulogic := 'U'; SIGNAL IO3_nwv : std_ulogic := 'U'; SIGNAL IO4_nwv : std_ulogic := 'U'; SIGNAL IO5_nwv : std_ulogic := 'U'; SIGNAL IO6_nwv : std_ulogic := 'U'; SIGNAL IO7_nwv : std_ulogic := 'U'; --- internal delays SIGNAL tRCHR_tmp_in : std_ulogic := '0'; SIGNAL tRCHR_tmp_out : std_ulogic := '0'; SIGNAL tRWD_tmp_in : std_ulogic := '0'; SIGNAL tRWD_tmp_out : std_ulogic := '0'; SIGNAL TRASMAX_tmp_out : std_ulogic := '0'; SIGNAL TRASMAX_tmp_in : std_ulogic := '0'; SIGNAL TRASPMAX_tmp_out : std_ulogic := '0'; SIGNAL TRASPMAX_tmp_in : std_ulogic := '0'; SIGNAL TCASMAX_tmp_out : std_ulogic := '0'; SIGNAL TCASMAX_tmp_in : std_ulogic := '0'; SIGNAL TRWC_tmp_out : std_ulogic := '0'; SIGNAL TRWC_tmp_in : std_ulogic := '0'; SIGNAL TRAD_tmp_out : std_ulogic := '0'; SIGNAL TRAD_tmp_in : std_ulogic := '0'; SIGNAL TOED_tmp_out : std_ulogic := '0'; SIGNAL TOED_tmp_in : std_ulogic := '0'; SIGNAL TRADMAX_tmp_out : std_ulogic := '0'; SIGNAL TRADMAX_tmp_in : std_ulogic := '0'; SIGNAL TRCDMAX_tmp_out : std_ulogic := '0'; SIGNAL TRCDMAX_tmp_in : std_ulogic := '0'; SIGNAL TRASMAX_out : std_ulogic := '0'; SIGNAL TRASMAX_in : std_ulogic := '0'; SIGNAL TRASPMAX_out : std_ulogic := '0'; SIGNAL TRASPMAX_in : std_ulogic := '0'; SIGNAL TCASMAX_out : std_ulogic := '0'; SIGNAL TCASMAX_in : std_ulogic := '0'; SIGNAL TRAD_out : std_ulogic := '0'; SIGNAL TRAD_in : std_ulogic := '0'; SIGNAL TRADMAX_out : std_ulogic := '0'; SIGNAL TRADMAX_in : std_ulogic := '0'; SIGNAL TRCDMAX_out : std_ulogic := '0'; SIGNAL TRCDMAX_in : std_ulogic := '0'; SIGNAL tRCHR_in : std_ulogic := '0'; SIGNAL tRCHR_out : std_ulogic := '0'; SIGNAL tOED_in : std_ulogic := '0'; SIGNAL tOED_out : std_ulogic := '0'; SIGNAL tRWD_in : std_ulogic := '0'; SIGNAL tRWD_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- TRASMAX : VitalBuf(tRASMAX_tmp_out, tRASMAX_tmp_in, (tdevice_tRASMAX, UnitDelay)); TRASPMAX : VitalBuf(tRASPMAX_tmp_out, tRASPMAX_tmp_in, (tdevice_tRASPMAX, UnitDelay)); TCASMAX : VitalBuf(tCASMAX_tmp_out, tCASMAX_tmp_in, (tdevice_tCASMAX, UnitDelay)); TRWC : VitalBuf(tRWC_tmp_out, tRWC_tmp_in,(tdevice_tRWC, UnitDelay)); TRAD : VitalBuf(tRAD_tmp_out, tRAD_tmp_in, (tdevice_tRAD, UnitDelay)); TRADMAX : VitalBuf(tRADMAX_tmp_out, tRADMAX_tmp_in, (tdevice_tRADMAX, UnitDelay)); TRCDMAX : VitalBuf(tRCDMAX_tmp_out, tRCDMAX_tmp_in, (tdevice_tRCDMAX, UnitDelay)); TRCHR : VitalBuf(tRCHR_tmp_out, tRCHR_tmp_in, (tdevice_tRCHR, UnitDelay)); TRWD : VitalBuf(tRWD_tmp_out, tRWD_tmp_in, (tdevice_tRWD, UnitDelay)); TOED : VitalBuf(tOED_tmp_out, tOED_tmp_in, (tdevice_tOED, UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg); w_02 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg); w_03 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_04 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_05 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_06 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_07 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_08 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_09 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_10 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_11 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_12 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_13 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_14 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_15 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_16 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_17 : VitalWireDelay (IO0_ipd, IO0, tipd_IO0); w_18 : VitalWireDelay (IO1_ipd, IO1, tipd_IO1); w_19 : VitalWireDelay (IO2_ipd, IO2, tipd_IO2); w_20 : VitalWireDelay (IO3_ipd, IO3, tipd_IO3); w_21 : VitalWireDelay (IO4_ipd, IO4, tipd_IO4); w_22 : VitalWireDelay (IO5_ipd, IO5, tipd_IO5); w_23 : VitalWireDelay (IO6_ipd, IO6, tipd_IO6); w_24 : VitalWireDelay (IO7_ipd, IO7, tipd_IO7); END BLOCK; CASNeg_nwv <= To_UX01(CASNeg_ipd); RASNeg_nwv <= To_UX01(RASNeg_ipd); WENeg_nwv <= To_UX01(WENeg_ipd); OENeg_nwv <= To_UX01(OENeg_ipd); A0_nwv <= To_UX01(A0_ipd); A1_nwv <= To_UX01(A1_ipd); A2_nwv <= To_UX01(A2_ipd); A3_nwv <= To_UX01(A3_ipd); A4_nwv <= To_UX01(A4_ipd); A5_nwv <= To_UX01(A5_ipd); A6_nwv <= To_UX01(A6_ipd); A7_nwv <= To_UX01(A7_ipd); A8_nwv <= To_UX01(A8_ipd); A9_nwv <= To_UX01(A9_ipd); A10_nwv <= To_UX01(A10_ipd); A11_nwv <= To_UX01(A11_ipd); IO0_nwv <= To_UX01(IO0_ipd); IO1_nwv <= To_UX01(IO1_ipd); IO2_nwv <= To_UX01(IO2_ipd); IO3_nwv <= To_UX01(IO3_ipd); IO4_nwv <= To_UX01(IO4_ipd); IO5_nwv <= To_UX01(IO5_ipd); IO6_nwv <= To_UX01(IO6_ipd); IO7_nwv <= To_UX01(IO7_ipd); ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( CASNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; AIn : IN std_logic_vector(11 DOWNTO 0) := (OTHERS => 'U'); DIn : IN std_logic_vector(7 DOWNTO 0) := (OTHERS => 'U'); DOut : OUT std_ulogic_vector(7 DOWNTO 0) := (OTHERS => 'Z') ); PORT MAP ( CASNeg => CASNeg_nwv, RASNeg => RASNeg_nwv, WENeg => WENeg_nwv, OENeg => OENeg_nwv, AIn(0) => A0_nwv, AIn(1) => A1_nwv, AIn(2) => A2_nwv, AIn(3) => A3_nwv, AIn(4) => A4_nwv, AIn(5) => A5_nwv, AIn(6) => A6_nwv, AIn(7) => A7_nwv, AIn(8) => A8_nwv, AIn(9) => A9_nwv, AIn(10) => A10_nwv, AIn(11) => A11_nwv, DIn(0) => IO0_nwv, DIn(1) => IO1_nwv, DIn(2) => IO2_nwv, DIn(3) => IO3_nwv, DIn(4) => IO4_nwv, DIn(5) => IO5_nwv, DIn(6) => IO6_nwv, DIn(7) => IO7_nwv, DOut(0) => IO0, DOut(1) => IO1, DOut(2) => IO2, DOut(3) => IO3, DOut(4) => IO4, DOut(5) => IO5, DOut(6) => IO6, DOut(7) => IO7 ); --memory definition TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData; SHARED VARIABLE Mem : MemStore; -- states during initialization TYPE State_type IS (init0, init1, init2, init3, init4, init5, init6, init7, init8); SIGNAL curr_init_state : State_type := init0; SIGNAL next_init_state : State_type := init0; -- powerup SIGNAL PoweredUp : std_logic := '0'; -- initialization SIGNAL Initialized : std_logic := '0'; --zero delay signals SIGNAL DOut_zd : std_logic_vector(7 downto 0):=(OTHERS=>'Z'); SIGNAL DOut_Pass : std_logic_vector(7 downto 0):=(OTHERS=>'Z'); SIGNAL D_tmp : NATURAL RANGE 0 TO MaxData; SIGNAL Mem_address : NATURAL RANGE 0 TO MemSize; --Command Register SIGNAL write : std_logic := '0'; SIGNAL read : std_logic := '0'; SIGNAL Init_change : std_logic := '0'; -- has value '1' for 1 ns when CAS# is high SIGNAL CAS_posedge : std_logic := '0'; SIGNAL RAS_posedge : std_logic := '0'; SHARED VARIABLE CAS_low : BOOLEAN; SHARED VARIABLE from_neg_en : BOOLEAN; SHARED VARIABLE page_mode : BOOLEAN; SHARED VARIABLE oe : BOOLEAN; SHARED VARIABLE trwc_time : time := 0 ns; SHARED VARIABLE read_mod_wr : BOOLEAN; SHARED VARIABLE Mem_addr : NATURAL RANGE 0 TO MemSize; SHARED VARIABLE read_entered : BOOLEAN; -- set to TRUE when early write cycle SHARED VARIABLE twcs_count : BOOLEAN; SHARED VARIABLE end_cycle : BOOLEAN; -- Access time variables SHARED VARIABLE OPENLATCH : BOOLEAN; SHARED VARIABLE FROMCAS : BOOLEAN; SHARED VARIABLE FROMOE : BOOLEAN; SHARED VARIABLE FROMRAS : BOOLEAN; SHARED VARIABLE FROMWE : BOOLEAN; -- timing check violation SIGNAL Viol : X01 := '0'; BEGIN ---------------------------------------------------------------------------- --Power Up time 200 us; --------------------------------------------------------------------------- PoweredUp <= '1' AFTER 200 us; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehaviour: PROCESS(DIn, RASNeg, CASNeg, WENeg, OEneg, AIn) -- Timing Check Variables VARIABLE Tviol_IO0_WENeg : X01 := '0'; VARIABLE TD_IO0_WENeg : VitalTimingDataType; VARIABLE Tviol_IO0_CASNeg : X01 := '0'; VARIABLE TD_IO0_CASNeg : VitalTimingDataType; VARIABLE Tviol_A0_CASNeg_s : X01 := '0'; VARIABLE TD_A0_CASNeg_s : VitalTimingDataType; VARIABLE Tviol_A0_CASNeg_h : X01 := '0'; VARIABLE TD_A0_CASNeg_h : VitalTimingDataType; VARIABLE Tviol_A0_RASNeg_s : X01 := '0'; VARIABLE TD_A0_RASNeg_s : VitalTimingDataType; VARIABLE Tviol_A0_RASNeg_h : X01 := '0'; VARIABLE TD_A0_RASNeg_h : VitalTimingDataType; VARIABLE Tviol_A0_WENeg : X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_OENeg_WENeg : X01 := '0'; VARIABLE TD_OENeg_WENeg : VitalTimingDataType; VARIABLE Tviol_OENeg_CASNeg : X01 := '0'; VARIABLE TD_OENeg_CASNeg : VitalTimingDataType; VARIABLE Tviol_CASNeg_OENeg : X01 := '0'; VARIABLE TD_CASNeg_OENeg : VitalTimingDataType; VARIABLE Tviol_CASNeg_WENeg : X01 := '0'; VARIABLE TD_CASNeg_WENeg : VitalTimingDataType; VARIABLE Tviol_CASNeg_WENeg_1 : X01 := '0'; VARIABLE TD_CASNeg_WENeg_1 : VitalTimingDataType; VARIABLE Tviol_RASNeg_CASNeg : X01 := '0'; VARIABLE TD_RASNeg_CASNeg : VitalTimingDataType; VARIABLE Tviol_RASNeg_CASNeg_1 : X01 := '0'; VARIABLE TD_RASNeg_CASNeg_1 : VitalTimingDataType; VARIABLE Tviol_RASNeg_CASNeg_2 : X01 := '0'; VARIABLE TD_RASNeg_CASNeg_2 : VitalTimingDataType; VARIABLE Tviol_RASNeg_CASNeg_3 : X01 := '0'; VARIABLE TD_RASNeg_CASNeg_3 : VitalTimingDataType; VARIABLE Tviol_CASNeg_RASNeg : X01 := '0'; VARIABLE TD_CASNeg_RASNeg : VitalTimingDataType; VARIABLE Tviol_CASNeg_RASNeg_1 : X01 := '0'; VARIABLE TD_CASNeg_RASNeg_1 : VitalTimingDataType; VARIABLE Tviol_CASNeg_RASNeg_2 : X01 := '0'; VARIABLE TD_CASNeg_RASNeg_2 : VitalTimingDataType; VARIABLE Tviol_WENeg_CASNeg : X01 := '0'; VARIABLE TD_WENeg_CASNeg : VitalTimingDataType; VARIABLE Tviol_WENeg_CASNeg_1 : X01 := '0'; VARIABLE TD_WENeg_CASNeg_1 : VitalTimingDataType; VARIABLE Tviol_WENeg_CASNeg_2 : X01 := '0'; VARIABLE TD_WENeg_CASNeg_2 : VitalTimingDataType; VARIABLE Tviol_WENeg_RASNeg : X01 := '0'; VARIABLE TD_WENeg_RASNeg : VitalTimingDataType; VARIABLE Tviol_RASNeg_WENeg : X01 := '0'; VARIABLE TD_RASNeg_WENeg : VitalTimingDataType; VARIABLE Pviol_RASNeg : X01 := '0'; VARIABLE PD_RASNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg : X01 := '0'; VARIABLE PD_CASNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg_rd : X01 := '0'; VARIABLE PD_CASNeg_rd : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg_rd_mod_wr : X01 := '0'; VARIABLE PD_CASNeg_rd_mod_wr : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_OENeg : X01 := '0'; VARIABLE PD_OENeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between DIn and WENeg VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => WENeg, RefSignalName => "WENeg", SetupHigh => tsetup_IO0_WENeg, SetupLow => tsetup_IO0_WENeg, HoldHigh => thold_IO0_WENeg, HoldLow => thold_IO0_WENeg, CheckEnabled => CASNeg = '0' AND OENeg = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IO0_WENeg, Violation => Tviol_IO0_WENeg ); -- Setup/Hold Check between DIn and CASNeg VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "DIn", RefSignal => CASNeg, RefSignalName => "CASNeg", SetupHigh => tsetup_IO0_CASNeg, SetupLow => tsetup_IO0_CASNeg, HoldHigh => thold_IO0_CASNeg, HoldLow => thold_IO0_CASNeg, CheckEnabled => WENeg = '0' AND OENeg = '1', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_IO0_CASNeg, Violation => Tviol_IO0_CASNeg ); -- Setup/Hold Check between RASNeg and CASNeg VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CASNeg, RefSignalName => "CASNeg", SetupLow => tsetup_RASNeg_CASNeg_read_noedge_posedge, --tcsh CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CASNeg, Violation => Tviol_RASNeg_CASNeg ); -- Setup/Hold Check between RASNeg and CASNeg VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CASNeg, RefSignalName => "CASNeg", SetupLow => tsetup_RASNeg_CASNeg_read1_noedge_negedge,-- trcd HoldLow => thold_RASNeg_CASNeg_read_noedge_negedge, -- trsh CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CASNeg_1, Violation => Tviol_RASNeg_CASNeg_1 ); -- Setup/Hold Check between CASNeg and RASNeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => RASNeg, RefSignalName => "RASNeg", -- trpc HoldHigh => thold_CASNeg_RASNeg_cas_before1_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_RASNeg, Violation => Tviol_CASNeg_RASNeg ); -- Setup/Hold Check between CASNeg and RASNeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => RASNeg, RefSignalName => "RASNeg", -- tcsr SetupLow => tsetup_CASNeg_RASNeg_cas_before2_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_RASNeg_1, Violation => Tviol_CASNeg_RASNeg_1 ); -- Setup/Hold Check between CASNeg and RASNeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => RASNeg, RefSignalName => "RASNeg", -- tchr HoldLow => thold_CASNeg_RASNeg_cas_before2_noedge_negedge, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_RASNeg_2, Violation => Tviol_CASNeg_RASNeg_2 ); -- Setup/Hold Check between RASNeg and CASNeg VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CASNeg, RefSignalName => "CASNeg", -- tcrp HoldHigh => thold_RASNeg_CASNeg_cas_before1_noedge_posedge, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CASNeg_2, Violation => Tviol_RASNeg_CASNeg_2 ); -- Setup/Hold Check between RASNeg and CASNeg VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CASNeg, RefSignalName => "CASNeg", HoldLow => thold_RASNeg_CASNeg_page_rd_noedge_posedge, -- tcprh CheckEnabled => page_mode = TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CASNeg_3, Violation => Tviol_RASNeg_CASNeg_3 ); -- Setup/Hold Check between WENeg and RASNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => RASNeg, RefSignalName => "RASNeg", HoldHigh => thold_WENeg_RASNeg, -- twrh CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_RASNeg, Violation => Tviol_WENeg_RASNeg ); -- Setup/Hold Check between WENeg and CASNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CASNeg, RefSignalName => "CASNeg", HoldHigh => thold_WENeg_CASNeg_page_rd_noedge_posedge, -- trchc CheckEnabled => page_mode = TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CASNeg, Violation => Tviol_WENeg_CASNeg ); -- Setup/Hold Check between WENeg and CASNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CASNeg, RefSignalName => "CASNeg", -- tcpw HoldHigh => thold_WENeg_CASNeg_page_rd_mod_noedge_posedge, CheckEnabled => read_mod_wr = TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CASNeg_1, Violation => Tviol_WENeg_CASNeg_1 ); -- Setup/Hold Check between AIn and CASNeg VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => CASNeg, RefSignalName => "CASNeg", SetupHigh => tsetup_A0_CASNeg, SetupLow => tsetup_A0_CASNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CASNeg_s, Violation => Tviol_A0_CASNeg_s ); -- Setup/Hold Check between AIn and CASNeg VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => CASNeg, RefSignalName => "CASNeg", HoldHigh => thold_A0_CASNeg, HoldLow => thold_A0_CASNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CASNeg_h, Violation => Tviol_A0_CASNeg_h ); -- Setup/Hold Check between AIn and RASNeg VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => RASNeg, RefSignalName => "RASNeg", SetupHigh => tsetup_A0_RASNeg, SetupLow => tsetup_A0_RASNeg, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_RASNeg_s, Violation => Tviol_A0_RASNeg_s ); -- Setup/Hold Check between AIn and RASNeg VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => RASNeg, RefSignalName => "RASNeg", HoldHigh => thold_A0_RASNeg, HoldLow => thold_A0_RASNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_RASNeg_h, Violation => Tviol_A0_RASNeg_h ); -- Setup/Hold Check between CASNeg and WENeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_CASNeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_WENeg, Violation => Tviol_CASNeg_WENeg ); -- Setup/Hold Check between OENeg and WENeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldHigh => thold_OENeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_WENeg, Violation => Tviol_OENeg_WENeg ); -- Setup/Hold Check between CASNeg and OENeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => OENeg, RefSignalName => "OENeg", HoldLow => thold_CASNeg_OENeg, -- tcol CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_OENeg, Violation => Tviol_CASNeg_OENeg ); -- Setup/Hold Check between OENeg and CASNeg VitalSetupHoldCheck ( TestSignal => OENeg, TestSignalName => "OENeg", RefSignal => CASNeg, RefSignalName => "CASNeg", HoldHigh => thold_OENeg_CASNeg, --tcop CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_OENeg_CASNeg, Violation => Tviol_OENeg_CASNeg ); -- Setup/Hold Check between AIn and WENeg VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => WENeg, RefSignalName => "WENeg", SetupLow => tsetup_A0_WENeg, SetupHigh => tsetup_A0_WENeg, CheckEnabled => CASNeg = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, Violation => Tviol_A0_WENeg ); -- Setup/Hold Check between RASNeg and WENeg VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldLow => thold_RASNeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_WENeg, Violation => Tviol_RASNeg_WENeg ); -- Setup/Hold Check between CASNeg and WENeg VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => WENeg, RefSignalName => "WENeg", HoldLow => thold_CASNeg_WENeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_WENeg_1, Violation => Tviol_CASNeg_WENeg_1 ); -- Setup/Hold Check between WENeg and CASNeg VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CASNeg, RefSignalName => "CASNeg", HoldLow => thold_WENeg_CASNeg, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CASNeg_2, Violation => Tviol_WENeg_CASNeg_2 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_RASNeg_negedge, PulseWidthHigh => tpw_RASNeg_posedge, Period => tperiod_RASNeg, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg, Violation => Pviol_RASNeg ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_CASNeg_negedge, PulseWidthHigh => tpw_CASNeg_posedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg, Violation => Pviol_CASNeg ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", Period => tperiod_CASNeg_page_rd, -- thpc CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg_rd, Violation => Pviol_CASNeg_rd ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", Period => tperiod_CASNeg_page_rd_mod_wr, -- thprwc CheckEnabled => read_mod_wr = TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg_rd_mod_wr, Violation => Pviol_CASNeg_rd_mod_wr ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_WENeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg, Violation => Pviol_WENeg ); -- PulseWidth Check for OENeg VitalPeriodPulseCheck ( TestSignal => OENeg, TestSignalName => "OENeg", PulseWidthHigh => tpw_OENeg_posedge, CheckEnabled => page_mode = TRUE, HeaderMsg => InstancePath & PartID, PeriodData => PD_OENeg, Violation => Pviol_OENeg ); Violation := Tviol_IO0_WENeg OR Tviol_IO0_CASNeg OR Tviol_A0_CASNeg_s OR Tviol_A0_CASNeg_h OR Tviol_A0_RASNeg_s OR Tviol_A0_RASNeg_h OR Tviol_A0_WENeg OR Tviol_OENeg_WENeg OR Tviol_OENeg_CASNeg OR Tviol_CASNeg_OENeg OR Tviol_CASNeg_WENeg OR Tviol_CASNeg_WENeg_1 OR Tviol_RASNeg_CASNeg OR Tviol_RASNeg_CASNeg_1 OR Tviol_RASNeg_CASNeg_2 OR Tviol_RASNeg_CASNeg_3 OR Tviol_CASNeg_RASNeg OR Tviol_CASNeg_RASNeg_1 OR Tviol_CASNeg_RASNeg_2 OR Tviol_WENeg_CASNeg OR Tviol_WENeg_CASNeg_1 OR Tviol_WENeg_CASNeg_2 OR Tviol_WENeg_RASNeg OR Tviol_RASNeg_WENeg OR Pviol_RASNeg OR Pviol_CASNeg OR Pviol_CASNeg_rd OR Pviol_CASNeg_rd_mod_wr OR Pviol_OENeg OR Pviol_WENeg; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY warning; END IF; END PROCESS VITALBehaviour; ref_decode : PROCESS(CASNeg, RASNeg) VARIABLE RAS_ONLY_REF : BOOLEAN; VARIABLE CAS_BEFORE_RAS_REF : BOOLEAN; BEGIN IF falling_edge(RASNeg) AND CASNeg = '1' THEN RAS_ONLY_REF := TRUE; ELSIF rising_edge(RASNeg) AND CASNeg = '1' AND RAS_ONLY_REF THEN RAS_ONLY_REF := FALSE; Init_change <= '1', '0' AFTER 1 ns; ELSIF falling_edge(RASNeg) AND CASNeg = '0' AND WENeg = '1' THEN CAS_BEFORE_RAS_REF := TRUE; ELSIF rising_edge(RASNeg) AND CAS_BEFORE_RAS_REF THEN CAS_BEFORE_RAS_REF := FALSE; Init_change <= '1', '0' AFTER 1 ns; END IF; END PROCESS ref_decode; StateGen : PROCESS(Init_change) BEGIN CASE curr_init_state IS WHEN init0 => IF (PoweredUp = '1') AND (Init_change = '1') THEN next_init_state <= init1; ELSE next_init_state <= init0; END IF; WHEN init1 => IF Init_change = '1' THEN next_init_state <= init2; ELSE next_init_state <= init1; END IF; WHEN init2 => IF Init_change = '1' THEN next_init_state <= init3; ELSE next_init_state <= init2; END IF; WHEN init3 => IF Init_change = '1' THEN next_init_state <= init4; ELSE next_init_state <= init3; END IF; WHEN init4 => IF Init_change = '1' THEN next_init_state <= init5; ELSE next_init_state <= init4; END IF; WHEN init5 => IF Init_change = '1' THEN next_init_state <= init6; ELSE next_init_state <= init5; END IF; WHEN init6 => IF Init_change = '1' THEN next_init_state <= init7; ELSE next_init_state <= init6; END IF; WHEN init7 => IF Init_change = '1' THEN next_init_state <= init8; ELSE next_init_state <= init7; END IF; WHEN init8 => NULL; END CASE; END PROCESS StateGen; StateTransition : PROCESS(next_init_state) BEGIN IF PoweredUp = '1' THEN curr_init_state <= next_init_state; ELSE curr_init_state <= init0; END IF; END PROCESS StateTransition; Functionality : PROCESS(curr_init_state) BEGIN CASE curr_init_state IS WHEN init0 => NULL; WHEN init1 => NULL; WHEN init2 => NULL; WHEN init3 => NULL; WHEN init4 => NULL; WHEN init5 => NULL; WHEN init6 => NULL; WHEN init7 => NULL; WHEN init8 => Initialized <= '1'; END CASE; END PROCESS Functionality; -- check if early or delayed write cycle PROCESS (CASNeg, WENeg) BEGIN IF RASNeg = '0' AND falling_edge(CASNeg) AND WENeg = '1' THEN twcs_count := FALSE; ELSIF RASNeg = '0' AND ((falling_edge(WENeg) AND CASNeg = '1') OR (falling_edge(CASNeg) AND falling_edge(WENeg))) THEN twcs_count := TRUE; END IF; END PROCESS; write_dc: PROCESS (WENeg, CASNeg, OENeg, RASNeg) BEGIN IF Initialized = '1' THEN IF (WENeg = '0') AND (CASNeg = '0') AND (RASNeg = '0') AND ((OENeg = '1' AND NOT twcs_count) OR twcs_count) THEN write <= '1'; ELSE write <= '0'; END IF; IF (WENeg = '1') AND (CASNeg = '0' AND RASNeg = '0') AND (OENeg = '0') THEN read <= '1'; ELSE read <= '0'; END IF; ELSE read <= '0'; write <= '0'; END IF; END PROCESS write_dc; --------------------------------------------------------------------------- --Latch address on falling edge of RAS# and CAS# --Latches data on falling edge of WE# or CAS# what ever comes later --------------------------------------------------------------------------- BusCycleDecode : PROCESS(AIn, Din, write, WENeg, CASNeg, RASNeg, OENeg) VARIABLE Row : NATURAL RANGE 0 TO RowSize; VARIABLE Column : NATURAL RANGE 0 TO ColSize; BEGIN IF Initialized = '1' THEN IF (falling_edge(RASNeg) AND CASNeg= '1') THEN Row := to_nat(AIn(11 downto 0)); ELSIF (falling_edge(CASNeg) AND RASNeg = '0') THEN Column := to_nat(AIn(11 downto 0)); Mem_addr := Row*(RowSize+1) + Column; Mem_address <= Mem_addr; ELSIF rising_edge(write) THEN Mem(Mem_addr) := to_nat(Din); D_tmp <= to_nat(Din); END IF; END IF; END PROCESS BusCycleDecode; page_read_modify_write : PROCESS(CASNeg, RASNeg,RAS_posedge, WENeg, OENeg) VARIABLE cnt : NATURAL :=0; VARIABLE read_wr_possible : BOOLEAN; BEGIN IF falling_edge(RASNeg) or rising_edge(RAS_posedge) THEN read_wr_possible := FALSE; read_entered := FALSE; page_mode := FALSE; cnt := 0; END IF; IF falling_edge(CASNeg) AND RASNeg = '0' THEN read_wr_possible := TRUE; read_entered := FALSE; read_mod_wr := FALSE; cnt := cnt + 1; ELSIF rising_edge(CASNeg) THEN read_wr_possible := FALSE; END IF; IF rising_edge(OENeg) AND CASNeg = '0' AND read_wr_possible THEN read_entered := TRUE; ELSIF falling_edge(WENeg) AND CASNeg = '0' AND read_entered THEN read_mod_wr := TRUE; ELSIF falling_edge(CASNeg) AND (RASNeg = '0' AND cnt > 1) THEN page_mode := TRUE; END IF; END PROCESS page_read_modify_write; read_proc : PROCESS(CASNeg, RASNeg, OENeg, WENeg, read) BEGIN oe:= rising_edge(read) OR (read = '1'); IF oe THEN IF Mem(Mem_addr) = -1 THEN DOut_zd <= (OTHERS=>'X'); ELSE DOut_zd <= to_slv(Mem(Mem_addr),8); END IF; END IF; IF OENeg = '1' OR WENeg = '0' OR (RASNeg = '1' AND CASNeg = '1') THEN DOut_zd <= (OTHERS=>'Z'); END IF; IF (RASNeg = '1' AND CASNeg = '1') THEN end_cycle := TRUE; ELSE end_cycle := FALSE; END IF; END PROCESS read_proc; -- generate signal CAS_posedge and variable CAS_low to provide -- tCAP time passed when reading gen_CAS_posedge : PROCESS(CASNeg) BEGIN IF CASNeg = '0' THEN CAS_low := TRUE; ELSE CAS_low := FALSE; END IF; IF CASNeg = '1' THEN CAS_posedge <= NOT CAS_posedge; ELSE CAS_posedge <= CAS_posedge; END IF; END PROCESS gen_CAS_posedge; gen_RAS_posedge : PROCESS(RASNeg) BEGIN IF RASNeg = '1' THEN RAS_posedge <= '0', '1' AFTER 1 ns; ELSE RAS_posedge <= '0'; END IF; END PROCESS gen_RAS_posedge; -- checker for tCDD, tRDD, tOED, tWED Check_delay_to_Din : PROCESS(CASNeg, RASNeg, OENeg, WENeg, Din, tOED_out) BEGIN IF (rising_edge(OENeg) OR rising_edge(CASNeg) OR rising_edge(RASNeg) OR falling_edge(WENeg)) AND Din(0) /= '0' AND Din(0) /= '1' THEN tOED_in <= '1'; ELSIF tOED_in = '1' AND tOED_out = '0' AND (Din(0) = '0' OR Din(0) = '1') THEN ASSERT FALSE REPORT "During 15 ns Din should be Hi-Z" SEVERITY warning; END IF; IF falling_edge(tOED_out) THEN tOED_in <= '0'; END IF; END PROCESS Check_delay_to_Din; PROCESS(tOED_in) BEGIN IF rising_edge(tOED_in) THEN tOED_out <= '1' AFTER tdevice_tOED, '0' AFTER tdevice_tOED + 1 ns; END IF; END PROCESS; -- checker for tRWD and tRCHR Checker : PROCESS(RASNeg, WENeg) BEGIN IF falling_edge(RASNeg) THEN tRWD_in <= '1', '0' AFTER 1 ns; tRCHR_in <= '1','0' AFTER 1 ns; END IF; IF falling_edge(WENeg) THEN ASSERT NOT read_entered OR tRWD_out = '1' OR CASNeg = '1' REPORT "Not elapsed tRWD time from RASNeg to WENeg " & "during read modify write cycle" SEVERITY WARNING; ASSERT NOT read_entered OR tRCHR_out = '1' OR CASNeg = '0' REPORT "Not elapsed tRCHR time from RASNeg to WENeg" SEVERITY WARNING; END IF; END PROCESS Checker; -- checker for tRASMAX TRASMAX_proc : PROCESS(RASNeg) BEGIN IF RASNeg = '0' THEN TRASMAX_in <= '1', '0' AFTER 1 ns; END IF; IF (RASNeg = '1') AND (NOT page_mode) AND (TRASMAX_out = '1') THEN ASSERT FALSE REPORT "Pulse width low of RAS# is longer than tRAS max value" SEVERITY warning; END IF; END PROCESS TRASMAX_proc; -- checker for tRASPMAX TRASPMAX_proc : PROCESS(RASNeg) BEGIN IF RASNeg = '0' THEN TRASPMAX_in <= '1', '0' AFTER 1 ns; END IF; IF (RASNeg = '1') AND page_mode AND (TRASPMAX_out = '1') THEN ASSERT FALSE REPORT "Pulse width low of RAS# is longer than tRASP max value" SEVERITY warning; END IF; END PROCESS TRASPMAX_proc; -- checker for tCASMAX TCASMAX_proc : PROCESS(CASNeg) BEGIN IF CASNeg = '0' THEN TCASMAX_in <= '1', '0' AFTER 1 ns; END IF; IF (CASNeg = '1') AND (NOT page_mode) AND (TCASMAX_out = '1') THEN ASSERT FALSE REPORT "Pulse width low of CAS# is longer than tCAS max value" SEVERITY warning; END IF; END PROCESS TCASMAX_proc; -- checker for tRAD, tRADMAX TRAD_proc : PROCESS(RASNeg, AIn) BEGIN IF falling_edge(RASNeg) AND CASNeg = '1' THEN tRAD_in <= '1', '0' AFTER 1 ns; tRADMAX_in <= '1', '0' AFTER 1 ns; END IF; IF AIn'event AND RASNeg = '0' THEN ASSERT tRAD_out = '1' REPORT "AIn changed before tRAD elapsed" SEVERITY warning; ASSERT tRADMAX_out = '0' REPORT "AIn didn't change before tRADMAX elapsed" SEVERITY warning; END IF; END PROCESS TRAD_proc; -- checker for tRCDMAX TRCD_proc : PROCESS(RASNeg, CASNeg) BEGIN IF falling_edge(RASNeg) AND CASNeg = '1' THEN tRCDMAX_in <= '1', '0' AFTER 1 ns; END IF; IF falling_edge(CASNeg) AND RASNeg = '0' THEN ASSERT tRCDMAX_out = '0' REPORT "CAS# didn't assert low before tRCDMAX elapsed" SEVERITY warning; END IF; END PROCESS TRCD_proc; -- checker for tRWC TRWC_proc : PROCESS(RASNeg) BEGIN IF RASNeg = '0' THEN IF (NOW - trwc_time) < tdevice_tRWC AND read_mod_wr THEN ASSERT FALSE REPORT "Period of RAS is less than tRWC" SEVERITY warning; END IF; trwc_time := NOW; read_mod_wr := FALSE; END IF; END PROCESS TRWC_proc; PROCESS(TRAD_in) BEGIN IF rising_edge(TRAD_in) THEN TRAD_out <= '0', '1' AFTER tdevice_tRAD + 1 ns; END IF; END PROCESS; PROCESS(TRADMAX_in, CASNeg) BEGIN IF rising_edge(TRADMAX_in) THEN TRADMAX_out <= '0', '1' AFTER tdevice_tRADMAX + 1 ns; ELSIF rising_edge(CASNeg) THEN TRADMAX_out <= '0'; END IF; END PROCESS; PROCESS(TRCDMAX_in, CASNeg) BEGIN IF rising_edge(TRCDMAX_in) THEN TRCDMAX_out <= '0', '1' AFTER tdevice_tRCDMAX + 1 ns; ELSIF rising_edge(CASNeg) THEN TRCDMAX_out <= '0'; END IF; END PROCESS; PROCESS(TRASMAX_in) BEGIN IF rising_edge(TRASMAX_in) THEN TRASMAX_out <= '0', '1' AFTER tdevice_tRASMAX + 1 ns; END IF; END PROCESS; PROCESS(TRASPMAX_in) BEGIN IF rising_edge(TRASPMAX_in) THEN TRASPMAX_out <= '0', '1' AFTER tdevice_tRASPMAX + 1 ns; END IF; END PROCESS; PROCESS(TCASMAX_in) BEGIN IF rising_edge(TCASMAX_in) THEN TCASMAX_out <= '0', '1' AFTER tdevice_tCASMAX + 1 ns; END IF; END PROCESS; PROCESS(tRWD_in) BEGIN IF rising_edge(tRWD_in) THEN tRWD_out <= '0', '1' AFTER tdevice_tRWD + 1 ns; END IF; END PROCESS; PROCESS(tRCHR_in) BEGIN IF rising_edge(tRCHR_in) THEN tRCHR_out <= '0', '1' AFTER tdevice_tRCHR + 1 ns; END IF; END PROCESS; DOutPassThrough : PROCESS(DOut_zd) VARIABLE ValidData : std_logic_vector(7 downto 0); VARIABLE CASDQ_negt : TIME; VARIABLE CASDQ_post : TIME; VARIABLE CASDQ_t : TIME; VARIABLE RASDQ_t : TIME; VARIABLE OEDQ_t : TIME; VARIABLE WEDQ_t : TIME; VARIABLE ADDRDQ_t : TIME; VARIABLE after_ADDR : BOOLEAN; VARIABLE after_RAS : BOOLEAN; VARIABLE time_tmp : TIME; BEGIN IF DOut_zd(0) /= 'Z' THEN OPENLATCH := TRUE; CASDQ_negt := -CASNeg'LAST_EVENT + tpd_CASNeg_IO0_neg_edge(trz0); CASDQ_post := -CAS_posedge'LAST_EVENT + tpd_CASNeg_IO0_pos_edge(trz0); RASDQ_t := -RASNeg'LAST_EVENT + tpd_RASNeg_IO0(trz0); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_IO0(trz0); ADDRDQ_t := -AIn'LAST_EVENT + tpd_A0_IO0(tr01); IF CAS_low THEN IF (CASDQ_negt >= CASDQ_post) AND (CASDQ_negt > 0 ns) THEN CASDQ_t := CASDQ_negt; from_neg_en := TRUE; ELSIF (CASDQ_post >= CASDQ_negt) AND (CASDQ_post > 0 ns) THEN CASDQ_t := CASDQ_post; from_neg_en := FALSE; END IF; ELSE from_neg_en := FALSE; END IF; FROMCAS := (CASDQ_t > OEDQ_t) AND (CASDQ_t > 0 ns); FROMOE := (OEDQ_t >= CASDQ_t) AND (OEDQ_t > 0 ns); ValidData := "XXXXXXXX"; IF (ADDRDQ_t > 0 ns AND ADDRDQ_t > RASDQ_t) THEN after_ADDR := TRUE; after_RAS := FALSE; ELSIF (RASDQ_t > 0 ns AND RASDQ_t > ADDRDQ_t) THEN after_ADDR := FALSE; after_RAS := TRUE; ELSE after_ADDR := FALSE; after_RAS := FALSE; END IF; IF (after_ADDR AND (((ADDRDQ_t > CASDQ_t) AND FROMCAS) OR ((ADDRDQ_t > OEDQ_t) AND FROMOE))) THEN DOut_Pass <= ValidData, DOut_zd AFTER ADDRDQ_t; ELSIF ((RASDQ_t > CASDQ_t) AND FROMCAS) OR ((RASDQ_t > OEDQ_t) AND FROMOE) THEN FROMRAS := TRUE; FROMOE := FALSE; FROMCAS := FALSE; DOut_Pass <= DOut_zd; ELSE DOut_Pass <= DOut_zd; END IF; ELSE CASDQ_t := -CASNeg'LAST_EVENT + tpd_CASNeg_IO0_neg_edge(tr0z); RASDQ_t := -RASNeg'LAST_EVENT + tpd_RASNeg_IO0(tr0z); OEDQ_t := -OENeg'LAST_EVENT + tpd_OENeg_IO0(tr0z); WEDQ_t := -WENeg'LAST_EVENT + tpd_WENeg_IO0(tr0z); FROMRAS := ((RASDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR ( RASDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (RASDQ_t > 0 ns) AND ((RASDQ_t <= OEDQ_t AND OEDQ_t >= 0 ns) OR (RASDQ_t > OEDQ_t AND OEDQ_t < 0 ns)) AND ((RASDQ_t <= CASDQ_t AND CASDQ_t >= 0 ns) OR (RASDQ_t > CASDQ_t AND CASDQ_t < 0 ns)) AND end_cycle; FROMOE := ((OEDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR ( OEDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (OEDQ_t > 0 ns) AND ((OEDQ_t <= RASDQ_t AND RASDQ_t >= 0 ns) OR (OEDQ_t > RASDQ_t AND RASDQ_t < 0 ns)) AND ((OEDQ_t <= CASDQ_t AND CASDQ_t >= 0 ns) OR (OEDQ_t > CASDQ_t AND CASDQ_t < 0 ns)); FROMCAS :=((CASDQ_t <= WEDQ_t AND WEDQ_t >= 0 ns) OR ( CASDQ_t > WEDQ_t AND WEDQ_t < 0 ns)) AND (CASDQ_t > 0 ns) AND ((CASDQ_t <= OEDQ_t AND OEDQ_t >= 0 ns) OR (CASDQ_t > OEDQ_t AND OEDQ_t < 0 ns)) AND ((CASDQ_t <= RASDQ_t AND RASDQ_t >= 0 ns) OR (CASDQ_t > RASDQ_t AND RASDQ_t < 0 ns)) AND end_cycle; DOut_Pass <= DOut_zd; OPENLATCH := FALSE; END IF; END PROCESS DOutPassThrough; --------------------------------------------------------------------------- -- Path Delay Section --------------------------------------------------------------------------- D_Out_PathDelay_Gen : FOR i IN 0 TO 7 GENERATE PROCESS(DOut_Pass(i)) VARIABLE D0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DOut(i), OutSignalName => "DOut", OutTemp => DOut_Pass(i), GlitchData => D0_GlitchData, Mode => VitalTransport, Paths => ( 0 => (InputChangeTime => CASNeg'LAST_EVENT, PathDelay => tpd_CASNeg_IO0_neg_edge, PathCondition => (NOT OPENLATCH AND FROMCAS) OR (OPENLATCH AND FROMCAS AND from_neg_en)), 1 => (InputChangeTime => CAS_posedge'LAST_EVENT, PathDelay => tpd_CASNeg_IO0_pos_edge, PathCondition => (OPENLATCH AND FROMCAS AND (NOT from_neg_en) AND (CAS_low))), 2 => (InputChangeTime => RASNeg'LAST_EVENT, PathDelay => tpd_RASNeg_IO0, PathCondition => (NOT OPENLATCH AND FROMRAS) OR (OPENLATCH AND FROMRAS)), 3 => (InputChangeTime => OENeg'LAST_EVENT, PathDelay => tpd_OENeg_IO0, PathCondition => (NOT OPENLATCH AND FROMOE) OR (OPENLATCH AND FROMOE)), 4 => (InputChangeTime => AIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_A0_IO0), PathCondition => (NOT FROMOE) AND (NOT FROMCAS) AND (NOT FROMRAS)), 5 => (InputChangeTime => WENeg'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_WENeg_IO0), PathCondition => (NOT FROMOE) AND (NOT FROMCAS) AND (NOT FROMRAS) AND NOT OPENLATCH) ) ); END PROCESS; END GENERATE D_Out_PathDelay_Gen; default: PROCESS -- Text file input variables FILE mem_file : text IS mem_file_name; VARIABLE ind : natural := 0; VARIABLE buf : line; BEGIN -- Preload Control ------------------------------------------------------------------------ -- File Read Section ------------------------------------------------------------------------ ------------------------------------------------------------------------ ----- hm5113805f memory preload file format ---------------------------- ------------------------------------------------------------------------ -- / - comment -- @aaaaaaa - stands for address within memory, -- 24 LSBits determine address within bank, -- other bits determine bank address, -- bytes within bank are written row by row -- dd -
is byte to be written at address aaaaaaa++ -- (aaaaaaa is incremented at every load), -- only first 1-8 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------ IF UserPreload AND (mem_file_name /= "none" ) THEN ind := 0; Mem := (OTHERS => -2); WHILE (NOT ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 TO 7)); --address ELSE IF ind < (MemSize+1) THEN Mem(ind MOD (MemSize+1)) := h(buf(1 TO 2)); ind := ind + 1; ELSE REPORT "Memory address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS default; END BLOCK behavior; END vhdl_behavioral;