-------------------------------------------------------------------------------- -- File Name: edj5304ba.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2006-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 M.Novkovic 06 Nov 20 Initial release -- V1.1 M.Novkovic 06 Dec 21 Dinamic memory -- allocation added -- V1.2 S.Janevski 07 June 19 Correction of state -- transitions with warnings; -- Implemented warnings for -- time delays; -- Additive latency is fixed; -- Start address of write -- burst is corrected; -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: EDJ5304BA -- -- Description: 512 Mb (16 M Words x 4 bits x 8 banks) DDR3 SDRAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY edj5304ba IS GENERIC ( -- tipd delays: interconnect path delays tipd_ODT : VitalDelayType01 := VitalZeroDelay01; tipd_CK : VitalDelayType01 := VitalZeroDelay01; tipd_CKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CKE : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_BA0 : VitalDelayType01 := VitalZeroDelay01; tipd_BA1 : VitalDelayType01 := VitalZeroDelay01; tipd_BA2 : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQS : VitalDelayType01 := VitalZeroDelay01; tipd_DQSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_DM : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CK_DQ0 : VitalDelayType01Z := UnitDelay01Z; -- tHZ(max) tpd_CK_DQ1 : VitalDelayType := UnitDelay; -- tHZ(min) tpd_CK_DQS : VitalDelayType01Z := UnitDelay01Z; -- tDQSCK(max) -- tsetup values tsetup_DQ0_DQS : VitalDelayType := UnitDelay; -- tDS tsetup_A0_CK : VitalDelayType := UnitDelay; -- tIS tsetup_DQS_CK_CL5_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL6_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL7_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL8_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL9_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL10_negedge_posedge: VitalDelayType := UnitDelay; -- tDSS tsetup_CKE_RESETNeg : VitalDelayType := UnitDelay; tsetup_CK_DQS : VitalDelayType := UnitDelay; -- tWLS -- thold values thold_DQ0_DQS : VitalDelayType := UnitDelay; -- tDH thold_A0_CK : VitalDelayType := UnitDelay; -- tIH thold_DQS_CK_CL5_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL6_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL7_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL8_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL9_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL10_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_CKE_RESETNeg : VitalDelayType := UnitDelay; thold_CK_DQS : VitalDelayType := UnitDelay; -- tWLH -- tpw values tpw_CK_CL5_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL5_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL6_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL6_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL7_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL7_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL8_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL8_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL9_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL9_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL10_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL10_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_A0_CL5 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL6 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL7 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL8 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL9 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL10 : VitalDelayType := UnitDelay; -- tIPW tpw_DQ0_CL5 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL6 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL7 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL8 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL9 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL10 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQS_normCL5_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL5_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL6_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL6_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL7_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL7_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL8_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL8_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL9_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL9_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL10_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL10_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_postCL5_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL6_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL7_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL8_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL9_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL10_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_CKE_SelfRefresh_negedge : VitalDelayType := UnitDelay; -- tCKESR -- 200 us from diagram on page 58. tpw_RESETNeg_PoweredUp_eq_0_negedge : VitalDelayType := UnitDelay; -- 100 ns from diagram on page 58. tpw_RESETNeg_PoweredUp_eq_1_negedge : VitalDelayType := UnitDelay; -- tperiod values tperiod_CK_CL5 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL6 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL7 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL8 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL9 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL10 : VitalDelayType := UnitDelay; -- tCKAVG(min) -- tskew values tskew_CK_DQS_CL5_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL6_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL7_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL8_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL9_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL10_posedge_posedge: VitalDelayType := UnitDelay; -- tDQSS -- tdevice values: values for internal delays tdevice_tRC : VitalDelayType := 49.5 ns; -- tRC- tdevice_tRRD : VitalDelayType := 6 ns; -- tRRD- tdevice_tRCD : VitalDelayType := 13.5 ns; -- tRCD- tdevice_tFAW : VitalDelayType := 30 ns; -- tFAW- tdevice_tRASMIN : VitalDelayType := 36 ns; -- tRAS(min)- tdevice_tRASMAX : VitalDelayType := 70.2 us; -- tRAS(max)- tdevice_tRTP : VitalDelayType := 7.5 ns; -- tRTP- tdevice_tWR : VitalDelayType := 15 ns; -- tWR- tdevice_tWTR : VitalDelayType := 7.5 ns; -- tWTR- tdevice_tRP : VitalDelayType := 13.5 ns; -- tRP- tdevice_tRFCMIN : VitalDelayType := 90 ns; -- tRFC(min)- tdevice_tREFPer : VitalDelayType := 7.8 us; -- refresh period tdevice_tCKAVGMAX : VitalDelayType := 3.333 ns; -- tCKAVG(max)- tdevice_tMRD : VitalDelayType := 6 ns; -- tMRD - tdevice_tMOD : VitalDelayType := 22.5 ns; -- tMOD - tdevice_tXPR : VitalDelayType := 7.5 ns; -- tXPR - tdevice_tZQINIT : VitalDelayType := 384 ns; -- tZQINIT tdevice_tZQOPER : VitalDelayType := 768 ns; -- tZQOPER tdevice_tZQCS : VitalDelayType := 96 ns; -- tZQCS tdevice_tCKSRX : VitalDelayType := 7.5 ns; -- tCKSRX tdevice_tCKSRE : VitalDelayType := 7.5 ns; -- tCKSRE tdevice_tCKESR : VitalDelayType := 6 ns; -- tCKESR tdevice_tWLDQSEN : VitalDelayType := 37.5 ns; -- tWLDQSEN tdevice_tWLMRD : VitalDelayType := 60 ns; -- tWLMRD tdevice_tWLOMAX : VitalDelayType := 10 ns; -- tWLO(MAX) tdevice_tWLOEMAX : VitalDelayType := 2 ns; -- tWLOE(MAX) -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- memory file to be loaded mem_file_name : string := "none"; UserPreload : boolean := FALSE; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( ODT : IN std_ulogic := 'U'; CK : IN std_ulogic := 'U'; CKNeg : IN std_ulogic := 'U'; CKE : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; CASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; BA0 : IN std_ulogic := 'U'; BA1 : IN std_ulogic := 'U'; BA2 : IN std_ulogic := 'U'; A0 : IN std_ulogic := 'U'; A1 : IN std_ulogic := 'U'; A2 : IN std_ulogic := 'U'; A3 : IN std_ulogic := 'U'; A4 : IN std_ulogic := 'U'; A5 : IN std_ulogic := 'U'; A6 : IN std_ulogic := 'U'; A7 : IN std_ulogic := 'U'; A8 : IN std_ulogic := 'U'; A9 : IN std_ulogic := 'U'; A10 : IN std_ulogic := 'U'; A11 : IN std_ulogic := 'U'; A12 : IN std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DM : IN std_ulogic := 'U'; DQS : INOUT std_ulogic := 'U'; DQSNeg : INOUT std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 OF edj5304ba : ENTITY IS TRUE; END edj5304ba; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_static_memory_allocation OF edj5304ba IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral_static_memory_allocation : ARCHITECTURE IS TRUE; CONSTANT PartID : string := "EDJ5304BA"; CONSTANT BankNum : natural := 7; CONSTANT MaxData : natural := 16#F#; CONSTANT MemSize : natural := 16#FFFFFF#; CONSTANT RowNum : natural := 16#1FFF#; CONSTANT ColNum : natural := 16#7FF#; -- ipd SIGNAL ODT_ipd : std_ulogic := 'U'; SIGNAL CK_ipd : std_ulogic := 'U'; SIGNAL CKNeg_ipd : std_ulogic := 'U'; SIGNAL CKE_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL DM_ipd : std_ulogic := 'U'; SIGNAL BA0_ipd : std_ulogic := 'U'; SIGNAL BA1_ipd : std_ulogic := 'U'; SIGNAL BA2_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQS_ipd : std_ulogic := 'U'; SIGNAL DQSNeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; -- nwv SIGNAL ODT_nwv : std_ulogic := 'U'; SIGNAL CK_nwv : std_ulogic := 'U'; SIGNAL CKNeg_nwv : std_ulogic := 'U'; SIGNAL CKE_nwv : std_ulogic := 'U'; SIGNAL CSNeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL BA0_nwv : std_ulogic := 'U'; SIGNAL BA1_nwv : std_ulogic := 'U'; SIGNAL BA2_nwv : std_ulogic := 'U'; SIGNAL A0_nwv : std_ulogic := 'U'; SIGNAL A1_nwv : std_ulogic := 'U'; SIGNAL A2_nwv : std_ulogic := 'U'; SIGNAL A3_nwv : std_ulogic := 'U'; SIGNAL A4_nwv : std_ulogic := 'U'; SIGNAL A5_nwv : std_ulogic := 'U'; SIGNAL A6_nwv : std_ulogic := 'U'; SIGNAL A7_nwv : std_ulogic := 'U'; SIGNAL A8_nwv : std_ulogic := 'U'; SIGNAL A9_nwv : std_ulogic := 'U'; SIGNAL A10_nwv : std_ulogic := 'U'; SIGNAL A11_nwv : std_ulogic := 'U'; SIGNAL A12_nwv : std_ulogic := 'U'; SIGNAL DQ0_nwv : std_ulogic := 'U'; SIGNAL DQ1_nwv : std_ulogic := 'U'; SIGNAL DQ2_nwv : std_ulogic := 'U'; SIGNAL DQ3_nwv : std_ulogic := 'U'; SIGNAL DM_nwv : std_ulogic := 'U'; SIGNAL DQS_nwv : std_ulogic := 'U'; SIGNAL DQSNeg_nwv : std_ulogic := 'U'; SIGNAL RESETNeg_nwv : std_ulogic := 'U'; --- internal delays SIGNAL tRC_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRC_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRRD_in : std_ulogic := '1'; SIGNAL tRRD_out : std_ulogic := '1'; SIGNAL tRCD_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRCD_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_in : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_out : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMIN_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMIN_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMAX_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMAX_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRTP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRTP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRFCMIN_in : std_ulogic := '0'; SIGNAL tRFCMIN_out : std_ulogic := '0'; SIGNAL tXS_in : std_ulogic := '0'; SIGNAL tXS_out : std_ulogic := '0'; SIGNAL tREFPer_in : std_ulogic := '0'; SIGNAL tREFPer_out : std_ulogic := '0'; SIGNAL tCKAVGMAX_in : std_ulogic := '0'; SIGNAL tCKAVGMAX_out : std_ulogic := '0'; SIGNAL tWPSTMAX_in : std_ulogic := '0'; SIGNAL tWPSTMAX_out : std_ulogic := '0'; SIGNAL tCKSRX_in : std_ulogic := '0'; SIGNAL tCKSRX_out : std_ulogic := '0'; SIGNAL tCKSRE_in : std_ulogic := '0'; SIGNAL tCKSRE_out : std_ulogic := '0'; SIGNAL tWLODTEN_in : std_ulogic := '0'; SIGNAL tWLODTEN_out : std_ulogic := '0'; SIGNAL tWLDQSEN_in : std_ulogic := '0'; SIGNAL tWLDQSEN_out : std_ulogic := '0'; SIGNAL tWLMRD_in : std_ulogic := '0'; SIGNAL tWLMRD_out : std_ulogic := '0'; SIGNAL tWLOMAX_in : std_ulogic := '0'; SIGNAL tWLOMAX_out : std_ulogic := '0'; SIGNAL tWLOEMAX_in : std_ulogic := '0'; SIGNAL tWLOEMAX_out : std_ulogic := '0'; SIGNAL tODTLOFF_in : std_ulogic := '0'; SIGNAL tODTLOFF_out : std_ulogic := '0'; SIGNAL tMRD_in : std_ulogic := '0'; SIGNAL tMRD_out : std_ulogic := '0'; SIGNAL tMOD_in : std_ulogic := '0'; SIGNAL tMOD_out : std_ulogic := '0'; SIGNAL tMOD_in_tmp : std_ulogic := '0'; SIGNAL tMOD_out_tmp : std_ulogic := '0'; SIGNAL tXPR_in : std_ulogic := '0'; SIGNAL tXPR_out : std_ulogic := '0'; SIGNAL tZQINIT_in : std_ulogic := '0'; SIGNAL tZQINIT_out : std_ulogic := '0'; SIGNAL tZQOPER_in : std_ulogic := '0'; SIGNAL tZQOPER_out : std_ulogic := '0'; SIGNAL tZQCS_in : std_ulogic := '0'; SIGNAL tZQCS_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- TRC : VitalBuf(tRC_out(0), tRC_in(0), (tdevice_tRC - 1 ns, UnitDelay)); TRC1 : VitalBuf(tRC_out(1), tRC_in(1), (tdevice_tRC - 1 ns, UnitDelay)); TRC2 : VitalBuf(tRC_out(2), tRC_in(2), (tdevice_tRC - 1 ns, UnitDelay)); TRC3 : VitalBuf(tRC_out(3), tRC_in(3), (tdevice_tRC - 1 ns, UnitDelay)); TRC4 : VitalBuf(tRC_out(4), tRC_in(4), (tdevice_tRC - 1 ns, UnitDelay)); TRC5 : VitalBuf(tRC_out(5), tRC_in(5), (tdevice_tRC - 1 ns, UnitDelay)); TRC6 : VitalBuf(tRC_out(6), tRC_in(6), (tdevice_tRC - 1 ns, UnitDelay)); TRC7 : VitalBuf(tRC_out(7), tRC_in(7), (tdevice_tRC - 1 ns, UnitDelay)); TRRD : VitalBuf(tRRD_out, tRRD_in, (tdevice_tRRD - 1 ns, UnitDelay)); TRCD : VitalBuf(tRCD_out(0), tRCD_in(0), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD1 : VitalBuf(tRCD_out(1), tRCD_in(1), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD2 : VitalBuf(tRCD_out(2), tRCD_in(2), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD3 : VitalBuf(tRCD_out(3), tRCD_in(3), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD4 : VitalBuf(tRCD_out(4), tRCD_in(4), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD5 : VitalBuf(tRCD_out(5), tRCD_in(5), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD6 : VitalBuf(tRCD_out(6), tRCD_in(6), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD7 : VitalBuf(tRCD_out(7), tRCD_in(7), (tdevice_tRCD - 1 ns, UnitDelay)); TFAW : VitalBuf(tFAW_out(0), tFAW_in(0), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW1 : VitalBuf(tFAW_out(1), tFAW_in(1), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW2 : VitalBuf(tFAW_out(2), tFAW_in(2), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW3 : VitalBuf(tFAW_out(3), tFAW_in(3), (tdevice_tFAW - 2 ns, UnitDelay)); TRASMIN : VitalBuf(tRASMIN_out(0), tRASMIN_in(0), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN1 : VitalBuf(tRASMIN_out(1), tRASMIN_in(1), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN2 : VitalBuf(tRASMIN_out(2), tRASMIN_in(2), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN3 : VitalBuf(tRASMIN_out(3), tRASMIN_in(3), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN4 : VitalBuf(tRASMIN_out(4), tRASMIN_in(4), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN5 : VitalBuf(tRASMIN_out(5), tRASMIN_in(5), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN6 : VitalBuf(tRASMIN_out(6), tRASMIN_in(6), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN7 : VitalBuf(tRASMIN_out(7), tRASMIN_in(7), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMAX : VitalBuf(tRASMAX_out(0), tRASMAX_in(0), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX1 : VitalBuf(tRASMAX_out(1), tRASMAX_in(1), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX2 : VitalBuf(tRASMAX_out(2), tRASMAX_in(2), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX3 : VitalBuf(tRASMAX_out(3), tRASMAX_in(3), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX4 : VitalBuf(tRASMAX_out(4), tRASMAX_in(4), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX5 : VitalBuf(tRASMAX_out(5), tRASMAX_in(5), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX6 : VitalBuf(tRASMAX_out(6), tRASMAX_in(6), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX7 : VitalBuf(tRASMAX_out(7), tRASMAX_in(7), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRTP : VitalBuf(tRTP_out(0), tRTP_in(0), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP1 : VitalBuf(tRTP_out(1), tRTP_in(1), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP2 : VitalBuf(tRTP_out(2), tRTP_in(2), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP3 : VitalBuf(tRTP_out(3), tRTP_in(3), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP4 : VitalBuf(tRTP_out(4), tRTP_in(4), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP5 : VitalBuf(tRTP_out(5), tRTP_in(5), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP6 : VitalBuf(tRTP_out(6), tRTP_in(6), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP7 : VitalBuf(tRTP_out(7), tRTP_in(7), (tdevice_tRTP - 1 ns, UnitDelay)); TWR : VitalBuf(tWR_out(0), tWR_in(0), (tdevice_tWR - 1 ns, UnitDelay)); TWR1 : VitalBuf(tWR_out(1), tWR_in(1), (tdevice_tWR - 1 ns, UnitDelay)); TWR2 : VitalBuf(tWR_out(2), tWR_in(2), (tdevice_tWR - 1 ns, UnitDelay)); TWR3 : VitalBuf(tWR_out(3), tWR_in(3), (tdevice_tWR - 1 ns, UnitDelay)); TWR4 : VitalBuf(tWR_out(4), tWR_in(4), (tdevice_tWR - 1 ns, UnitDelay)); TWR5 : VitalBuf(tWR_out(5), tWR_in(5), (tdevice_tWR - 1 ns, UnitDelay)); TWR6 : VitalBuf(tWR_out(6), tWR_in(6), (tdevice_tWR - 1 ns, UnitDelay)); TWR7 : VitalBuf(tWR_out(7), tWR_in(7), (tdevice_tWR - 1 ns, UnitDelay)); TWTR : VitalBuf(tWTR_out(0), tWTR_in(0), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR1 : VitalBuf(tWTR_out(1), tWTR_in(1), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR2 : VitalBuf(tWTR_out(2), tWTR_in(2), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR3 : VitalBuf(tWTR_out(3), tWTR_in(3), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR4 : VitalBuf(tWTR_out(4), tWTR_in(4), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR5 : VitalBuf(tWTR_out(5), tWTR_in(5), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR6 : VitalBuf(tWTR_out(6), tWTR_in(6), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR7 : VitalBuf(tWTR_out(7), tWTR_in(7), (tdevice_tWTR - 1 ns, UnitDelay)); TRP : VitalBuf(tRP_out(0), tRP_in(0), (tdevice_tRP - 1 ns, UnitDelay)); TRP1 : VitalBuf(tRP_out(1), tRP_in(1), (tdevice_tRP - 1 ns, UnitDelay)); TRP2 : VitalBuf(tRP_out(2), tRP_in(2), (tdevice_tRP - 1 ns, UnitDelay)); TRP3 : VitalBuf(tRP_out(3), tRP_in(3), (tdevice_tRP - 1 ns, UnitDelay)); TRP4 : VitalBuf(tRP_out(4), tRP_in(4), (tdevice_tRP - 1 ns, UnitDelay)); TRP5 : VitalBuf(tRP_out(5), tRP_in(5), (tdevice_tRP - 1 ns, UnitDelay)); TRP6 : VitalBuf(tRP_out(6), tRP_in(6), (tdevice_tRP - 1 ns, UnitDelay)); TRP7 : VitalBuf(tRP_out(7), tRP_in(7), (tdevice_tRP - 1 ns, UnitDelay)); TCKESR : VitalBuf(tCKESR_out(0), tCKESR_in(0), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR1 : VitalBuf(tCKESR_out(1), tCKESR_in(1), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR2 : VitalBuf(tCKESR_out(2), tCKESR_in(2), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR3 : VitalBuf(tCKESR_out(3), tCKESR_in(3), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR4 : VitalBuf(tCKESR_out(4), tCKESR_in(4), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR5 : VitalBuf(tCKESR_out(5), tCKESR_in(5), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR6 : VitalBuf(tCKESR_out(6), tCKESR_in(6), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR7 : VitalBuf(tCKESR_out(7), tCKESR_in(7), (tdevice_tCKESR - 1 ns, UnitDelay)); TRFCMIN : VitalBuf(tRFCMIN_out, tRFCMIN_in, (tdevice_tRFCMIN - 1 ns, UnitDelay)); TXS : VitalBuf(tXS_out, tXS_in, (tdevice_tRFCMIN + 9 ns, UnitDelay)); TREFPER : VitalBuf(tREFPer_out, tREFPer_in, (tdevice_tREFPer - 1 ns, UnitDelay)); TCKAVGMAX: VitalBuf(tCKAVGMAX_out, tCKAVGMAX_in, (tdevice_tCKAVGMAX - 1 ns, UnitDelay)); TMRD: VitalBuf(tMRD_out, tMRD_in, (tdevice_tMRD - 1 ns, UnitDelay)); TMOD: VitalBuf(tMOD_out, tMOD_in, (tdevice_tMOD - 1 ns, UnitDelay)); TXPR: VitalBuf(tXPR_out, tXPR_in, (tdevice_tXPR - 1 ns, UnitDelay)); TZQINIT: VitalBuf(tZQINIT_out, tZQINIT_in, (tdevice_tZQINIT - 1 ns, UnitDelay)); TZQOPER: VitalBuf(tZQOPER_out, tZQOPER_in, (tdevice_tZQOPER - 1 ns, UnitDelay)); TZQCS: VitalBuf(tZQCS_out, tZQCS_in, (tdevice_tZQCS - 1 ns, UnitDelay)); TCKSRX : VitalBuf(tCKSRX_out, tCKSRX_in, (tdevice_tCKSRX - 1 ns, UnitDelay)); TCKSRE : VitalBuf(tCKSRE_out, tCKSRE_in, (tdevice_tCKSRE - 1 ns, UnitDelay)); TWLODTEN : VitalBuf(tWLODTEN_out, tWLODTEN_in, (tdevice_tMOD -1 ns, UnitDelay)); TWLDQSEN : VitalBuf(tWLDQSEN_out, tWLDQSEN_in,(tdevice_tWLDQSEN - 1 ns, UnitDelay)); TWLMRD : VitalBuf(tWLMRD_out, tWLMRD_in, (tdevice_tWLMRD - 1 ns, UnitDelay)); TWLOMAX : VitalBuf(tWLOMAX_out, tWLOMAX_in, (tdevice_tWLOMAX - 1 ns, UnitDelay)); TWLOEMAX : VitalBuf(tWLOEMAX_out, tWLOEMAX_in, (tdevice_tWLOEMAX - 1 ns, UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (ODT_ipd, ODT, tipd_ODT); w_02 : VitalWireDelay (CK_ipd, CK, tipd_CK); w_03 : VitalWireDelay (CKNeg_ipd, CKNeg, tipd_CKNeg); w_04 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE); w_05 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg); w_06 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg); w_07 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg); w_08 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_09 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0); w_10 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1); w_11 : VitalWireDelay (BA2_ipd, BA2, tipd_BA2); w_12 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_13 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_14 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_15 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_18 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_19 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_20 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_21 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_22 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_23 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_24 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_25 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_26 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_27 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_28 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_29 : VitalWireDelay (DQS_ipd, DQS, tipd_DQS); w_30 : VitalWireDelay (DQSNeg_ipd, DQSNeg, tipd_DQSNeg); w_31 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_32 : VitalWireDelay (DM_ipd, DM, tipd_DM); END BLOCK; ODT_nwv <= To_UX01(ODT_ipd); CK_nwv <= To_UX01(CK_ipd); CKNeg_nwv <= To_UX01(CKNeg_ipd); CKE_nwv <= To_UX01(CKE_ipd); CSNeg_nwv <= To_UX01(CSNeg_ipd); RASNeg_nwv <= To_UX01(RASNeg_ipd); CASNeg_nwv <= To_UX01(CASNeg_ipd); WENeg_nwv <= To_UX01(WENeg_ipd); DM_nwv <= To_UX01(DM_ipd); BA0_nwv <= To_UX01(BA0_ipd); BA1_nwv <= To_UX01(BA1_ipd); BA2_nwv <= To_UX01(BA2_ipd); A0_nwv <= To_UX01(A0_ipd); A1_nwv <= To_UX01(A1_ipd); A2_nwv <= To_UX01(A2_ipd); A3_nwv <= To_UX01(A3_ipd); A4_nwv <= To_UX01(A4_ipd); A5_nwv <= To_UX01(A5_ipd); A6_nwv <= To_UX01(A6_ipd); A7_nwv <= To_UX01(A7_ipd); A8_nwv <= To_UX01(A8_ipd); A9_nwv <= To_UX01(A9_ipd); A10_nwv <= To_UX01(A10_ipd); A11_nwv <= To_UX01(A11_ipd); A12_nwv <= To_UX01(A12_ipd); DQ0_nwv <= To_UX01(DQ0_ipd); DQ1_nwv <= To_UX01(DQ1_ipd); DQ2_nwv <= To_UX01(DQ2_ipd); DQ3_nwv <= To_UX01(DQ3_ipd); DQS_nwv <= To_UX01(DQS_ipd); DQSNeg_nwv <= To_UX01(DQSNeg_ipd); RESETNeg_nwv <= To_UX01(RESETNeg_ipd); ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ODT : IN std_ulogic := 'U'; CK : IN std_ulogic := 'U'; CKNeg : IN std_ulogic := 'U'; CKE : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; CASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; DM : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; BAIn : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => 'U'); AIn : IN std_logic_vector(12 DOWNTO 0) := (OTHERS => 'U'); DQIn : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => 'U'); DQOut : OUT std_ulogic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); DQSIn : IN std_ulogic := 'U'; DQSOut : OUT std_ulogic := 'Z'; DQSNegIn : IN std_ulogic := 'U'; DQSNegOut : OUT std_ulogic := 'Z' ); PORT MAP ( ODT => ODT_nwv, CK => CK_nwv, CKNeg => CKNeg_nwv, CKE => CKE_nwv, CSNeg => CSNeg_nwv, RASNeg => RASNeg_nwv, CASNeg => CASNeg_nwv, WENeg => WENeg_nwv, DM => DM_nwv, BAIn(0) => BA0_nwv, BAIn(1) => BA1_nwv, BAIn(2) => BA2_nwv, AIn(0) => A0_nwv, AIn(1) => A1_nwv, AIn(2) => A2_nwv, AIn(3) => A3_nwv, AIn(4) => A4_nwv, AIn(5) => A5_nwv, AIn(6) => A6_nwv, AIn(7) => A7_nwv, AIn(8) => A8_nwv, AIn(9) => A9_nwv, AIn(10) => A10_nwv, AIn(11) => A11_nwv, AIn(12) => A12_nwv, DQIn(0) => DQ0_nwv, DQIn(1) => DQ1_nwv, DQIn(2) => DQ2_nwv, DQIn(3) => DQ3_nwv, DQOut(0) => DQ0, DQOut(1) => DQ1, DQOut(2) => DQ2, DQOut(3) => DQ3, RESETNeg => RESETNeg_nwv, DQSIn => DQS_nwv, DQSOut => DQS, DQSNegIn => DQSNeg_nwv, DQSNegOut => DQSNeg ); --zero delay signals SIGNAL DQOut_zd : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL DQSOut_zd : std_logic := 'Z'; SIGNAL DQSNegOut_zd : std_logic := 'Z'; SIGNAL DOut_Pass : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); --differential inputs SIGNAL CKDiff : std_logic := 'Z'; SIGNAL DQSDiff : std_logic := 'Z'; --DLL implementation SIGNAL CKPeriod : time := 3 ns; SIGNAL CKInt : std_ulogic := '0'; SIGNAL CKtemp : std_ulogic := '1'; SIGNAL CKHalfPer : time := 0 ns; SIGNAL CKDLLDelay: time := 0 ns; SIGNAL CK_stable : boolean := FALSE; SIGNAL PoweredUp : boolean := FALSE; SIGNAL In_d : boolean := FALSE; --delay before first MRS command tXPR SIGNAL In_d1 : boolean := FALSE; --mode register set comand cycle time --during initialization SIGNAL In_d2 : boolean := FALSE; -- delay during initial ZQ calibration SIGNAL In_d3 : boolean := FALSE; -- delay during reset ZQ calibration SIGNAL In_d4 : boolean := FALSE; -- delay during ZQ calibration SIGNAL Init_delay : boolean := FALSE;--command during initialization SIGNAL Init_delay1 : boolean := FALSE;--command during initialization SIGNAL Init_delay2 : boolean := FALSE;--command during initialization SIGNAL Init_delay3 : boolean := FALSE;--command during reset ZQ --calibration SIGNAL Init_delay4 : boolean := FALSE;--command during ZQ calibration SIGNAL Initialized : boolean := FALSE;--initialization completed SIGNAL DLL_delay : std_logic := '0'; --delay between DLL SIGNAL DLL_delay_elapsed : boolean := TRUE;--reset and read command SIGNAL In_data : std_ulogic := '0';--start of write operation SIGNAL preamble_gen : std_logic := 'Z';--preamble before read operation SIGNAL Out_data : std_logic := 'Z';--start of read operation SIGNAL fly_flag : std_logic := '0'; --Determine weather read or write -- command is BL4 or BL8 on the fly SIGNAL DQ_driven : boolean;-- DQ driven during Write Leveling procedure -- timing check violation SIGNAL Viol : X01 := '0'; SIGNAL CK_COUNT : natural := 0; --burst sequences TYPE sequence IS ARRAY (0 TO 7) OF integer RANGE -7 TO 7; TYPE seqtab IS ARRAY (0 TO 7) OF sequence; CONSTANT seq0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT seq1 : sequence := (0, 1, 2,-1, 4, 5, 6, 3); CONSTANT seq2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT seq3 : sequence := (0,-3,-2,-1, 4, 1, 2, 3); CONSTANT seq4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT seq5 : sequence := (0, 1, 2,-1,-4,-3,-2,-5); CONSTANT seq6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT seq7 : sequence := (0,-3,-2,-1,-4,-7,-6,-5); CONSTANT seq : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5, seq6, seq7); CONSTANT inl0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT inl1 : sequence := (0,-1, 2, 1, 4, 3, 6, 5); CONSTANT inl2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT inl3 : sequence := (0,-1,-2,-3, 4, 3, 2, 1); CONSTANT inl4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT inl5 : sequence := (0,-1, 2, 1,-4,-5,-2,-3); CONSTANT inl6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT inl7 : sequence := (0,-1,-2,-3,-4,-5,-6,-7); CONSTANT inl : seqtab := (inl0, inl1, inl2, inl3, inl4, inl5, inl6, inl7); --memory definition TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData; TYPE MemBlock IS ARRAY (0 TO BankNum) OF MemStore; SHARED VARIABLE Mem : MemBlock; --mode registers SHARED VARIABLE MR0 : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0'); SHARED VARIABLE MR1 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR2 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR3 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active --commands during tFAW --bank, row and column of scheduled read or write operation SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE current_row : natural RANGE 0 TO RowNum; SHARED VARIABLE current_column : natural RANGE 0 TO ColNum; --bank, row and column of read operation that starts SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE read_row : natural RANGE 0 TO RowNum; SHARED VARIABLE read_column : natural RANGE 0 TO ColNum; -- WRITE LEVELING PROCEDURE SIGNAL WL_on : boolean := FALSE;--Write Leveling enabled SHARED VARIABLE ODTLOFF : boolean := FALSE; TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean; TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type; --all scheduled reads within all banks SHARED VARIABLE read_sch : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); --reads that should be preceeded by preamble SHARED VARIABLE preamble : write_sch_bank_type := (OTHERS => (OTHERS => TRUE)); TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic; TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type; --wait_read triggers process that counts remaining cycles to the --beggining of scheduled read when aditive latency has elapsed, and --read_delay keeps information of number of remaining cycles SIGNAL wait_read : wait_read_bank_type; SHARED VARIABLE read_delay : natural RANGE 0 TO 10; --needed for check if all rows were refreshed during refresh period SIGNAL Ref_per_start : std_ulogic := '0'; SIGNAL Ref_per_expired : std_ulogic := '0'; SHARED VARIABLE CK_rise : time := 0 ns; SHARED VARIABLE CK_period : time := 0 ns; TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating, active, reading, readingAP, writting, writtingAP, precharging, prechall,ZQ_calib); TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type; SHARED VARIABLE Curr_bank_state : Bank_state_array_type; SHARED VARIABLE Next_bank_state : Bank_state_array_type; SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered SIGNAL SelfRefresh : boolean := FALSE;--self refresh active --Partial self refresh active SIGNAL PartialSelfRefresh : boolean := FALSE; SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be --turned off SIGNAL Pre_PD : boolean := FALSE;--precharge power down active SIGNAL Act_PD : boolean := FALSE;--active power down active SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress, SIGNAL ReadStart : boolean := FALSE; --no pd entry SIGNAL Reset : boolean := FALSE;--reset function active SIGNAL RST : std_logic := '1'; SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be --turned off SIGNAL SimulationEnd : boolean := FALSE; SHARED VARIABLE mrs_cnt : natural; SIGNAL mrs_active : std_logic := '0'; SIGNAL preamble_check : boolean := FALSE; SIGNAL postamble_check : boolean := FALSE; FUNCTION bool_to_nat(tm : boolean) RETURN natural IS VARIABLE Temp : natural; BEGIN Temp := 0; IF tm THEN Temp := 1; END IF; RETURN Temp; END bool_to_nat; BEGIN RST <= RESETNeg AFTER 100 ns; CK_DLL: PROCESS(CKDiff) VARIABLE Previous : time := 0 ns; VARIABLE TmpPer : time := 0 ns; BEGIN IF rising_edge(CKDiff) THEN TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN CKPeriod <= TmpPer; END IF; Previous := NOW; CKHalfPer <= CKPeriod / 2; CKDLLDelay <= CKPeriod + tpd_CK_DQ1; END IF; END PROCESS CK_DLL; CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL BEGIN CKtemp <= NOT CKtemp AFTER CKHalfPer; END PROCESS CK_temp; CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay; Clock_init: PROCESS(CK) BEGIN IF rising_edge(CK) AND NOT PoweredUp THEN CK_COUNT <= CK_COUNT + 1; END IF; END PROCESS Clock_init; Power_up: PROCESS(CK_stable,CK_COUNT) BEGIN IF CK_stable AND (CK_COUNT >= 5) AND NOT PoweredUp THEN PoweredUp <= TRUE; END IF; END PROCESS Power_up; Init_d: PROCESS(In_d) BEGIN IF In_d THEN Init_delay <= TRUE AFTER tdevice_tXPR; ELSE Init_delay <= FALSE; END IF; END PROCESS Init_d; Init_d1: PROCESS(In_d1) BEGIN IF In_d1 THEN Init_delay1 <= TRUE AFTER tdevice_tMRD; ELSE Init_delay1 <= FALSE; END IF; END PROCESS Init_d1; Init_d2: PROCESS(In_d2) BEGIN IF In_d2 THEN Init_delay2 <= TRUE AFTER tdevice_tZQINIT; ELSE Init_delay2 <= FALSE; END IF; END PROCESS Init_d2; Init_d3: PROCESS(In_d3) BEGIN IF In_d3 THEN Init_delay3 <= TRUE AFTER tdevice_tZQOPER; ELSE Init_delay3 <= FALSE; END IF; END PROCESS Init_d3; Init_d4: PROCESS(In_d4) BEGIN IF In_d4 THEN Init_delay4 <= TRUE AFTER tdevice_tZQCS; ELSE Init_delay4 <= FALSE; END IF; END PROCESS Init_d4; PROCESS (tMOD_in_tmp) BEGIN IF rising_edge(tMOD_in_tmp) THEN tMOD_out_tmp <= '0', '1' AFTER tdevice_tMOD; END IF; END PROCESS; DLLdelay: PROCESS(DLL_delay, CKDiff) VARIABLE cnt : natural; BEGIN IF rising_edge(DLL_delay) THEN cnt := 0; DLL_delay_elapsed <= FALSE; ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN cnt := cnt + 1; IF cnt = 511 THEN DLL_delay_elapsed <= TRUE; END IF; END IF; END PROCESS DLLdelay; ---------------------------------------------------------------------------- -- Vital Behavior Process ---------------------------------------------------------------------------- VITALBehaviour: PROCESS(CKDiff, DQSDiff, DQSIn, DQIn, DM, ODT, CKE, CSNeg, RASNeg, CASNeg, WENeg, BAIn, AIn, RESETNeg) -- Timing Check Variables VARIABLE Tviol_DQ0_DQS : X01 := '0'; VARIABLE TD_DQ0_DQS : VitalTimingDataType; VARIABLE Tviol_DQ0_DQS1 : X01 := '0'; VARIABLE TD_DQ0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS : X01 := '0'; VARIABLE TD_DQ1_DQS : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS1 : X01 := '0'; VARIABLE TD_DQ1_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM0_DQS : X01 := '0'; VARIABLE TD_DM0_DQS : VitalTimingDataType; VARIABLE Tviol_DM0_DQS1 : X01 := '0'; VARIABLE TD_DM0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM1_DQS : X01 := '0'; VARIABLE TD_DM1_DQS : VitalTimingDataType; VARIABLE Tviol_DM1_DQS1 : X01 := '0'; VARIABLE TD_DM1_DQS1 : VitalTimingDataType; VARIABLE Tviol_ODT_CK : X01 := '0'; VARIABLE TD_ODT_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK : X01 := '0'; VARIABLE TD_CKE_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK_RESET : X01 := '0'; VARIABLE TD_CKE_CK_RESET : VitalTimingDataType; VARIABLE Tviol_CSNeg_CK : X01 := '0'; VARIABLE TD_CSNeg_CK : VitalTimingDataType; VARIABLE Tviol_RASNeg_CK : X01 := '0'; VARIABLE TD_RASNeg_CK : VitalTimingDataType; VARIABLE Tviol_CASNeg_CK : X01 := '0'; VARIABLE TD_CASNeg_CK : VitalTimingDataType; VARIABLE Tviol_WENeg_CK : X01 := '0'; VARIABLE TD_WENeg_CK : VitalTimingDataType; VARIABLE Tviol_BA0_CK : X01 := '0'; VARIABLE TD_BA0_CK : VitalTimingDataType; VARIABLE Tviol_A0_CK : X01 := '0'; VARIABLE TD_A0_CK : VitalTimingDataType; VARIABLE Tviol_DQS_CK5 : X01 := '0'; VARIABLE TD_DQS_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS_CK6 : X01 := '0'; VARIABLE TD_DQS_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS_CK7 : X01 := '0'; VARIABLE TD_DQS_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS_CK8 : X01 := '0'; VARIABLE TD_DQS_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS_CK9 : X01 := '0'; VARIABLE TD_DQS_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS_CK10 : X01 := '0'; VARIABLE TD_DQS_CK10 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK5 : X01 := '0'; VARIABLE TD_DQS1_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK6 : X01 := '0'; VARIABLE TD_DQS1_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK7 : X01 := '0'; VARIABLE TD_DQS1_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK8 : X01 := '0'; VARIABLE TD_DQS1_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK9 : X01 := '0'; VARIABLE TD_DQS1_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK10 : X01 := '0'; VARIABLE TD_DQS1_CK10 : VitalTimingDataType; VARIABLE Tviol_CKE_RESETNeg : X01 := '0'; VARIABLE TD_CKE_RESETNeg : VitalTimingDataType; VARIABLE Tviol_CK_DQSDiff : X01 := '0'; VARIABLE TD_CK_DQSDiff : VitalTimingDataType; VARIABLE Tviol_CK_DQSIn : X01 := '0'; VARIABLE TD_CK_DQSIn : VitalTimingDataType; VARIABLE Pviol_A05 : X01 := '0'; VARIABLE PD_A05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A06 : X01 := '0'; VARIABLE PD_A06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A07 : X01 := '0'; VARIABLE PD_A07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A08 : X01 := '0'; VARIABLE PD_A08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A09 : X01 := '0'; VARIABLE PD_A09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A010 : X01 := '0'; VARIABLE PD_A010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT5 : X01 := '0'; VARIABLE PD_ODT5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT6 : X01 := '0'; VARIABLE PD_ODT6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT7 : X01 := '0'; VARIABLE PD_ODT7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT8 : X01 := '0'; VARIABLE PD_ODT8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT9 : X01 := '0'; VARIABLE PD_ODT9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT10 : X01 := '0'; VARIABLE PD_ODT10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg5 : X01 := '0'; VARIABLE PD_CSNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg6 : X01 := '0'; VARIABLE PD_CSNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg7 : X01 := '0'; VARIABLE PD_CSNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg8 : X01 := '0'; VARIABLE PD_CSNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg9 : X01 := '0'; VARIABLE PD_CSNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg10 : X01 := '0'; VARIABLE PD_CSNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg5 : X01 := '0'; VARIABLE PD_RASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg6 : X01 := '0'; VARIABLE PD_RASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg7 : X01 := '0'; VARIABLE PD_RASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg8 : X01 := '0'; VARIABLE PD_RASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg9 : X01 := '0'; VARIABLE PD_RASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg10 : X01 := '0'; VARIABLE PD_RASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg5 : X01 := '0'; VARIABLE PD_CASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg6 : X01 := '0'; VARIABLE PD_CASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg7 : X01 := '0'; VARIABLE PD_CASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg8 : X01 := '0'; VARIABLE PD_CASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg9 : X01 := '0'; VARIABLE PD_CASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg10 : X01 := '0'; VARIABLE PD_CASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg5 : X01 := '0'; VARIABLE PD_WENeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg6 : X01 := '0'; VARIABLE PD_WENeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg7 : X01 := '0'; VARIABLE PD_WENeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg8 : X01 := '0'; VARIABLE PD_WENeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg9 : X01 := '0'; VARIABLE PD_WENeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg10 : X01 := '0'; VARIABLE PD_WENeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ05 : X01 := '0'; VARIABLE PD_DQ05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ06 : X01 := '0'; VARIABLE PD_DQ06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ07 : X01 := '0'; VARIABLE PD_DQ07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ08 : X01 := '0'; VARIABLE PD_DQ08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ09 : X01 := '0'; VARIABLE PD_DQ09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ010 : X01 := '0'; VARIABLE PD_DQ010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM5 : X01 := '0'; VARIABLE PD_DM5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM6 : X01 := '0'; VARIABLE PD_DM6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM7 : X01 := '0'; VARIABLE PD_DM7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM8 : X01 := '0'; VARIABLE PD_DM8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM9 : X01 := '0'; VARIABLE PD_DM9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM10 : X01 := '0'; VARIABLE PD_DM10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS15 : X01 := '0'; VARIABLE PD_DQS15 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS16 : X01 := '0'; VARIABLE PD_DQS16 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS17 : X01 := '0'; VARIABLE PD_DQS17 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS18 : X01 := '0'; VARIABLE PD_DQS18 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS19 : X01 := '0'; VARIABLE PD_DQS19 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS110 : X01 := '0'; VARIABLE PD_DQS110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS115 : X01 := '0'; VARIABLE PD_DQS115 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS116 : X01 := '0'; VARIABLE PD_DQS116 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS117 : X01 := '0'; VARIABLE PD_DQS117 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS118 : X01 := '0'; VARIABLE PD_DQS118 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS119 : X01 := '0'; VARIABLE PD_DQS119 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS1110 : X01 := '0'; VARIABLE PD_DQS1110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS35 : X01 := '0'; VARIABLE PD_DQS35 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS36 : X01 := '0'; VARIABLE PD_DQS36 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS37 : X01 := '0'; VARIABLE PD_DQS37 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS38 : X01 := '0'; VARIABLE PD_DQS38 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS39 : X01 := '0'; VARIABLE PD_DQS39 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS310 : X01 := '0'; VARIABLE PD_DQS310 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS315 : X01 := '0'; VARIABLE PD_DQS315 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS316 : X01 := '0'; VARIABLE PD_DQS316 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS317 : X01 := '0'; VARIABLE PD_DQS317 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS318 : X01 := '0'; VARIABLE PD_DQS318 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS319 : X01 := '0'; VARIABLE PD_DQS319 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS3110 : X01 := '0'; VARIABLE PD_DQS3110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CKE : X01 := '0'; VARIABLE PD_CKE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg_PoweredUp : X01 := '0'; VARIABLE PD_RESETNeg_PoweredUp : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK5 : X01 := '0'; VARIABLE PD_CK5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK6 : X01 := '0'; VARIABLE PD_CK6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK7 : X01 := '0'; VARIABLE PD_CK7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK8 : X01 := '0'; VARIABLE PD_CK8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK9 : X01 := '0'; VARIABLE PD_CK9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK10 : X01 := '0'; VARIABLE PD_CK10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS, Violation => Tviol_DQ0_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS1, Violation => Tviol_DQ0_DQS1 ); -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS, Violation => Tviol_DQ1_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS1, Violation => Tviol_DQ1_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS, Violation => Tviol_DM0_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS1, Violation => Tviol_DM0_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS, Violation => Tviol_DM1_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS1, Violation => Tviol_DM1_DQS1 ); -- Setup/Hold Check between ODT and CKDiff VitalSetupHoldCheck ( TestSignal => ODT, TestSignalName => "ODT", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ODT_CK, Violation => Tviol_ODT_CK ); -- Setup/Hold Check between CKE and CKDiff VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK, Violation => Tviol_CKE_CK ); -- Setup/Hold Check between CKE and CK VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CK, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => Reset_enter_cycle AND CK_COUNT = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK_RESET, Violation => Tviol_CKE_CK_RESET ); -- Setup/Hold Check between CSNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_CK, Violation => Tviol_CSNeg_CK ); -- Setup/Hold Check between RASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CK, Violation => Tviol_RASNeg_CK ); -- Setup/Hold Check between CASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_CK, Violation => Tviol_CASNeg_CK ); -- Setup/Hold Check between WENeg and CKDiff VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CK, Violation => Tviol_WENeg_CK ); -- Setup/Hold Check between BAIn and CKDiff VitalSetupHoldCheck ( TestSignal => BAIn, TestSignalName => "BAIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BA0_CK, Violation => Tviol_BA0_CK ); -- Setup/Hold Check between AIn and CKDiff VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CK, Violation => Tviol_A0_CK ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK5, Violation => Tviol_DQS_CK5 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK6, Violation => Tviol_DQS_CK6 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK7, Violation => Tviol_DQS_CK7 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK8, Violation => Tviol_DQS_CK8 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK9, Violation => Tviol_DQS_CK9 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK10, Violation => Tviol_DQS_CK10 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK5, Violation => Tviol_DQS1_CK5 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK6, Violation => Tviol_DQS1_CK6 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK7, Violation => Tviol_DQS1_CK7 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK8, Violation => Tviol_DQS1_CK8 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK9, Violation => Tviol_DQS1_CK9 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK10, Violation => Tviol_DQS1_CK10 ); -- Setup Check between CKE and RESETNeg VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKEIn", RefSignal => RESETNeg, RefSignalName => "RESETNeg", SetupLow => tsetup_CKE_RESETNeg, HoldLow => thold_CKE_RESETNeg, CheckEnabled => Reset_enter_cycle, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_RESETNeg, Violation => Tviol_CKE_RESETNeg ); -- Setup Check between CK and DQSIn VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSIn, Violation => Tviol_CK_DQSIn ); -- Setup Check between CK and DQSDiff VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSDiff, Violation => Tviol_CK_DQSDiff ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_A05, Violation => Pviol_A05 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_A06, Violation => Pviol_A06 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_A07, Violation => Pviol_A07 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_A08, Violation => Pviol_A08 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_A09, Violation => Pviol_A09 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_A010, Violation => Pviol_A010 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT5, Violation => Pviol_ODT5 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT6, Violation => Pviol_ODT6 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT7, Violation => Pviol_ODT7 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT8, Violation => Pviol_ODT8 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT9, Violation => Pviol_ODT9 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT10, Violation => Pviol_ODT10 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg5, Violation => Pviol_CSNeg5 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg6, Violation => Pviol_CSNeg6 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg7, Violation => Pviol_CSNeg7 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg8, Violation => Pviol_CSNeg8 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg9, Violation => Pviol_CSNeg9 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg10, Violation => Pviol_CSNeg10 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg5, Violation => Pviol_RASNeg5 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg6, Violation => Pviol_RASNeg6 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg7, Violation => Pviol_RASNeg7 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg8, Violation => Pviol_RASNeg8 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg9, Violation => Pviol_RASNeg9 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg10, Violation => Pviol_RASNeg10 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg5, Violation => Pviol_CASNeg5 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg6, Violation => Pviol_CASNeg6 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg7, Violation => Pviol_CASNeg7 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg8, Violation => Pviol_CASNeg8 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg9, Violation => Pviol_CASNeg9 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg10, Violation => Pviol_CASNeg10 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg5, Violation => Pviol_WENeg5 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg6, Violation => Pviol_WENeg6 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg7, Violation => Pviol_WENeg7 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg8, Violation => Pviol_WENeg8 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg9, Violation => Pviol_WENeg9 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg10, Violation => Pviol_WENeg10 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ05, Violation => Pviol_DQ05 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ06, Violation => Pviol_DQ06 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ07, Violation => Pviol_DQ07 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ08, Violation => Pviol_DQ08 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ09, Violation => Pviol_DQ09 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ010, Violation => Pviol_DQ010 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM5, Violation => Pviol_DM5 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM6, Violation => Pviol_DM6 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM7, Violation => Pviol_DM7 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM8, Violation => Pviol_DM8 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM9, Violation => Pviol_DM9 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM10, Violation => Pviol_DM10 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS15, Violation => Pviol_DQS15 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS16, Violation => Pviol_DQS16 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS17, Violation => Pviol_DQS17 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS18, Violation => Pviol_DQS18 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS19, Violation => Pviol_DQS19 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS110, Violation => Pviol_DQS110 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS115, Violation => Pviol_DQS115 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS116, Violation => Pviol_DQS116 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS117, Violation => Pviol_DQS117 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS118, Violation => Pviol_DQS118 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS119, Violation => Pviol_DQS119 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS1110, Violation => Pviol_DQS1110 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS35, Violation => Pviol_DQS35 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS36, Violation => Pviol_DQS36 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS37, Violation => Pviol_DQS37 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS38, Violation => Pviol_DQS38 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS39, Violation => Pviol_DQS39 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS310, Violation => Pviol_DQS310 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS315, Violation => Pviol_DQS315 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS316, Violation => Pviol_DQS316 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS317, Violation => Pviol_DQS317 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS318, Violation => Pviol_DQS318 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS319, Violation => Pviol_DQS319 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS3110, Violation => Pviol_DQS3110 ); -- PulseWidth Check for CKE VitalPeriodPulseCheck ( TestSignal => CKE, TestSignalName => "CKE", PulseWidthLow => tpw_CKE_SelfRefresh_negedge, CheckEnabled => SelfRefresh, HeaderMsg => InstancePath & PartID, PeriodData => PD_CKE, Violation => Pviol_CKE ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_0_negedge, CheckEnabled => NOT PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg_PoweredUp, Violation => Pviol_RESETNeg_PoweredUp ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_1_negedge, CheckEnabled => PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL5, PulseWidthLow => tpw_CK_CL5_negedge, PulseWidthHigh => tpw_CK_CL5_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK5, Violation => Pviol_CK5 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL6, PulseWidthLow => tpw_CK_CL6_negedge, PulseWidthHigh => tpw_CK_CL6_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK6, Violation => Pviol_CK6 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL7, PulseWidthLow => tpw_CK_CL7_negedge, PulseWidthHigh => tpw_CK_CL7_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK7, Violation => Pviol_CK7 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL8, PulseWidthLow => tpw_CK_CL8_negedge, PulseWidthHigh => tpw_CK_CL8_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK8, Violation => Pviol_CK8 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL9, PulseWidthLow => tpw_CK_CL9_negedge, PulseWidthHigh => tpw_CK_CL9_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK9, Violation => Pviol_CK9 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL10, PulseWidthLow => tpw_CK_CL10_negedge, PulseWidthHigh => tpw_CK_CL10_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK10, Violation => Pviol_CK10 ); Violation := Tviol_DQ0_DQS OR Tviol_DQ0_DQS1 OR Tviol_DQ1_DQS OR Tviol_DQ1_DQS1 OR Tviol_DM0_DQS OR Tviol_DM0_DQS1 OR Tviol_DM1_DQS OR Tviol_DM1_DQS1 OR Tviol_ODT_CK OR Tviol_CKE_CK OR Tviol_CKE_CK_RESET OR Tviol_CSNeg_CK OR Tviol_RASNeg_CK OR Tviol_CASNeg_CK OR Tviol_WENeg_CK OR Tviol_BA0_CK OR Tviol_A0_CK OR Tviol_DQS_CK5 OR Tviol_DQS_CK6 OR Tviol_DQS_CK7 OR Tviol_DQS_CK8 OR Tviol_DQS_CK9 OR Tviol_DQS_CK10 OR Tviol_DQS1_CK5 OR Tviol_DQS1_CK6 OR Tviol_DQS1_CK7 OR Tviol_DQS1_CK8 OR Tviol_DQS1_CK9 OR Tviol_DQS1_CK10 OR Tviol_CKE_RESETNeg OR Tviol_CK_DQSIn OR Tviol_CK_DQSDiff OR Pviol_A05 OR Pviol_A06 OR Pviol_A07 OR Pviol_A08 OR Pviol_A09 OR Pviol_A010 OR Pviol_ODT5 OR Pviol_ODT6 OR Pviol_ODT7 OR Pviol_ODT8 OR Pviol_ODT9 OR Pviol_ODT10 OR Pviol_CSNeg5 OR Pviol_CSNeg6 OR Pviol_CSNeg7 OR Pviol_CSNeg8 OR Pviol_CSNeg9 OR Pviol_CSNeg10 OR Pviol_RASNeg5 OR Pviol_RASNeg6 OR Pviol_RASNeg7 OR Pviol_RASNeg8 OR Pviol_RASNeg9 OR Pviol_RASNeg10 OR Pviol_CASNeg5 OR Pviol_CASNeg6 OR Pviol_CASNeg7 OR Pviol_CASNeg8 OR Pviol_CASNeg9 OR Pviol_CASNeg10 OR Pviol_WENeg5 OR Pviol_WENeg6 OR Pviol_WENeg7 OR Pviol_WENeg8 OR Pviol_WENeg9 OR Pviol_WENeg10 OR Pviol_DQ05 OR Pviol_DQ06 OR Pviol_DQ07 OR Pviol_DQ08 OR Pviol_DQ09 OR Pviol_DQ010 OR Pviol_DM5 OR Pviol_DM6 OR Pviol_DM7 OR Pviol_DM8 OR Pviol_DM9 OR Pviol_DM10 OR Pviol_DQS15 OR Pviol_DQS16 OR Pviol_DQS17 OR Pviol_DQS18 OR Pviol_DQS19 OR Pviol_DQS110 OR Pviol_DQS115 OR Pviol_DQS116 OR Pviol_DQS117 OR Pviol_DQS118 OR Pviol_DQS119 OR Pviol_DQS1110 OR Pviol_DQS35 OR Pviol_DQS36 OR Pviol_DQS37 OR Pviol_DQS38 OR Pviol_DQS39 OR Pviol_DQS310 OR Pviol_DQS315 OR Pviol_DQS316 OR Pviol_DQS317 OR Pviol_DQS318 OR Pviol_DQS319 OR Pviol_DQS3110 OR Pviol_CKE OR Pviol_RESETNeg_PoweredUp OR Pviol_RESETNeg OR Pviol_CK5 OR Pviol_CK6 OR Pviol_CK7 OR Pviol_CK8 OR Pviol_CK9 OR Pviol_CK10; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY warning; END IF; END PROCESS VITALBehaviour; DiffRecCK: PROCESS(CK, CKNeg) VARIABLE CKDiff_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 1); VARIABLE CK_GlitchData : VitalGlitchDataType; BEGIN VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (CK, CKNeg), Result => CKDiff_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CKDiff, OutSignalName => "CKDiff", OutTemp => CKDiff_zd, GlitchData => CK_GlitchData, Paths => ( 0 => (InputChangeTime => CK'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS DiffRecCK; DiffRecDQS: PROCESS(DQSIn, DQSNegIn) VARIABLE DQSDiff_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 1); VARIABLE DQS_GlitchData : VitalGlitchDataType; BEGIN VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (DQSIn, DQSNegIn), Result => DQSDiff_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => DQSDiff, OutSignalName => "DQSDiff", OutTemp => DQSDiff_zd, GlitchData => DQS_GlitchData, Paths => ( 0 => (InputChangeTime => DQSIn'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS DiffRecDQS; Functionality: PROCESS(CKDiff, CKE, tRFCMIN_out, ODT, tXS_out, SimulationEnd, SelfRefresh, SR_exit,tCKESR_out, tREFPer_out,Init_delay2, Init_delay3,AIn,tMRD_out, tWLDQSEN_out,tWLODTEN_out,RESETNeg,RST,tRC_out,tRRD_out) VARIABLE TimModTemp : string(1 TO 20) := (OTHERS => 'X');--extended TM --latencies of scheduled read and write operations TYPE Lat_type IS ARRAY (0 TO 10) OF natural RANGE 0 TO 10; TYPE Lat_bank_type IS ARRAY (0 TO BankNum) OF Lat_type; VARIABLE AL : Lat_bank_type; VARIABLE CL : Lat_bank_type; VARIABLE WL : Lat_bank_type; VARIABLE AL_tmp : natural; VARIABLE CL_tmp : natural; VARIABLE WL_tmp : natural; VARIABLE RL_tmp : natural; VARIABLE rd_pd_cnt : natural; VARIABLE prechall_viol : boolean;--command other than NOP or DESL issued --tRPA after precharge all VARIABLE idle : boolean;--all banks idle state TYPE row_type IS ARRAY (0 TO BankNum) OF integer RANGE 0 TO RowNum; VARIABLE active_row : row_type;--activated rows --starting columns of scheduled read or write operations TYPE col_type IS ARRAY (0 TO 10) OF natural RANGE 0 TO ColNum; TYPE col_bank_type IS ARRAY (0 TO BankNum) OF col_type; VARIABLE start_column : col_bank_type; --needed when multiple reads or writes scheduled in same bank VARIABLE free_slot : natural RANGE 0 TO 10; --all scheduled writes within all banks VARIABLE write_sch : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); --elapsed aditive latencies of scheduled reads VARIABLE AL_elapsed : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); TYPE last_write_type IS ARRAY (0 TO BankNum) OF boolean; --needed for verification of durations measured since end of write burst VARIABLE last_write : last_write_type := (OTHERS => FALSE); --programmed write latency elapsed since end of write burst VARIABLE WR_elapsed : last_write_type := (OTHERS => TRUE); --2 cycles elapsed since end of write burst VARIABLE WTR_elapsed : last_write_type := (OTHERS => TRUE); --AL + BL/2 elapsed since read command VARIABLE RTP_elapsed : last_write_type := (OTHERS => TRUE); TYPE precharge_cnt_type IS ARRAY (0 TO BankNum) OF natural; -- self refresh array VARIABLE sf_array : natural; --cycles elapsed since read or write command before precharge command VARIABLE precharge_cnt : precharge_cnt_type; --cycles elapsed since write command before end of write burst VARIABLE wr_rd_cnt : precharge_cnt_type; --cycles elapsed since read command before bank returns to active state VARIABLE rd_act_cnt : precharge_cnt_type; --cycles elapsed since read command before write command --rd_wr_cnt is RL+tCCD/2+2tCK-WL for BL=4 or -- RL+tCCD+2tCK-WL for BL=8 cycles VARIABLE rd_wr_cnt : natural; --elapsed since read command VARIABLE RTW_elapsed : boolean := TRUE; --cycles elapsed since write command before another write command VARIABLE wr_wr_cnt : natural; --cycles elapsed since read command before another read command VARIABLE rd_rd_cnt : natural; VARIABLE WR : natural RANGE 0 TO 12; VARIABLE read_permit : boolean;--read command accepted VARIABLE write_permit : boolean;--write command accepted TYPE command_type is ( ILL, MRS, REF, PRE, ACT, WRIT, READ, NOP, DESL, ZQCL, ZQCS ); VARIABLE Command : Command_type; -- states during initialization TYPE State_type IS (illegal, init0, init1, init2, init3, init4, init5, init6); VARIABLE Current_state : State_type := init0; VARIABLE Next_state : State_type := init0; VARIABLE defined_logic_levels : boolean := TRUE; VARIABLE CK_cnt : natural;--between commands during initialization VARIABLE power_down_cond : boolean;--pd can be entered VARIABLE active_pd_cond : boolean;--active pd can be entered VARIABLE PD_exit_cnt : natural := 1;--cycles since CKE went high VARIABLE PD_read_delay : boolean := FALSE;--tXP OR tXPDLL elapsed VARIABLE PD_read_del_cnt : natural := 1;--cycles of tXSRD VARIABLE ODT_off : boolean;--ODT turned off when precharge pd entered VARIABLE WL_on_en : boolean := FALSE; VARIABLE freq_change : boolean := FALSE;--frequency has changed during --precharge pd VARIABLE freq_ch_cnt : natural;--cycles before frequency can change VARIABLE DLL_reset_needed : boolean := FALSE;--DLL must be reset prior --to read command VARIABLE ZQINIT : boolean := TRUE; -- For ZQ calibration after power-up -- If FALSE ZQ calibration after reset --needed for CKE pulse width check VARIABLE CKEcnt : natural RANGE 0 TO 3 := 3; VARIABLE CKErise : boolean := FALSE; VARIABLE CKEfall : boolean := TRUE; FUNCTION find_free(sch : write_sch_type) RETURN natural IS VARIABLE Temp : natural; BEGIN Temp := 0; WHILE sch(Temp) LOOP Temp := Temp + 1; END LOOP; RETURN Temp; END find_free; PROCEDURE CheckRead IS VARIABLE WTR_viol : boolean; VARIABLE rd_rd_viol : boolean; VARIABLE rd_DLL_viol : boolean; VARIABLE rd_PD_viol : boolean; VARIABLE rd_lock_viol : boolean; BEGIN read_permit := TRUE; WTR_viol := FALSE; rd_rd_viol := FALSE; rd_DLL_viol := FALSE; rd_PD_viol := FALSE; rd_lock_viol := FALSE; FOR J IN 0 TO BankNum LOOP IF NOT WTR_elapsed(J) OR tWTR_out(J) = '0' THEN WTR_viol := TRUE; read_permit := FALSE; END IF; END LOOP; IF rd_rd_cnt >= 1 and rd_rd_cnt < 4 THEN rd_rd_viol := TRUE; read_permit := FALSE; END IF; IF NOT DLL_delay_elapsed THEN rd_DLL_viol := TRUE; read_permit := FALSE; END IF; IF PD_read_delay THEN rd_PD_viol := TRUE; read_permit := FALSE; END IF; IF DLL_reset_needed THEN rd_lock_viol := TRUE; read_permit := FALSE; END IF; ASSERT NOT WTR_viol REPORT "tWTR has not elapsed since the end of last write burst" SEVERITY warning; ASSERT NOT rd_rd_viol REPORT "4 cycles must elapse between consecutive READ commands" SEVERITY warning; ASSERT NOT rd_DLL_viol REPORT "512 cycles must elapse between DLL reset and READ " & "command" SEVERITY warning; ASSERT NOT rd_PD_viol REPORT "tXPDLL has not elapsed since slow-exit power-down exit" SEVERITY warning; ASSERT NOT rd_lock_viol REPORT "DLL must be reset prior to read command" SEVERITY warning; END CheckRead; PROCEDURE CheckWrite IS VARIABLE RTW_viol : boolean; VARIABLE wr_wr_viol : boolean; BEGIN write_permit := TRUE; RTW_viol := FALSE; wr_wr_viol := FALSE; IF NOT RTW_elapsed THEN RTW_viol := TRUE; write_permit := FALSE; END IF; IF wr_wr_cnt < 4 THEN wr_wr_viol := TRUE; write_permit := FALSE; END IF; ASSERT NOT RTW_viol REPORT "RL+tCCD/2+2tCK-WL for BL=4 or" & "RL+tCCD+2tCK-WL for BL=8" & "cycles must elapse " & "between READ and WRITE commands" SEVERITY warning; ASSERT NOT wr_wr_viol REPORT "4 cycles must elapse between " & "consecutive WRITE commands" SEVERITY warning; END CheckWrite; BEGIN --ok IF rising_edge(CKDiff) THEN IF CK_rise /= 0 ns THEN CK_stable <= TRUE; IF CK_stable THEN IF NOW - CK_rise /= CK_period THEN IF (Pre_PD AND ODT_off AND freq_ch_cnt = 0) OR SelfRefresh THEN freq_change := TRUE; ELSE ASSERT SR_enter_cycle OR Reset_enter_cycle REPORT "Input clock frequency is not stable" SEVERITY warning; END IF; END IF; SimulationEnd <= FALSE AFTER 1 ns, TRUE AFTER 2*CK_period; ASSERT CK_period <= tdevice_tCKAVGMAX OR SR_enter_cycle OR Reset_enter_cycle REPORT "Input clock period exceeds tCKAVG(max)" SEVERITY warning; END IF; END IF; CK_period := NOW - CK_rise; CK_rise := NOW; defined_logic_levels := TRUE; IF (CKE /= '0' AND CKE /= '1') OR (RASNeg /= '0' AND RASNeg /= '1') OR (CASNeg /= '0' AND CASNeg /= '1') OR (WENeg /= '0' AND WENeg /= '1') THEN defined_logic_levels := FALSE; END IF; FOR I IN 0 TO 2 LOOP IF BAIn(I) /= '0' AND BAIn(I) /= '1' THEN defined_logic_levels := FALSE; END IF; END LOOP; FOR I IN 0 TO 12 LOOP IF AIn(I) /= '0' AND AIn(I) /= '1' THEN defined_logic_levels := FALSE; END IF; END LOOP; Command := ILL; IF defined_logic_levels THEN IF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '0' AND WENeg = '0' THEN Command := MRS; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '0' AND WENeg = '1' THEN Command := REF; ELSIF CSNeg = '1' THEN Command := DESL; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '1' THEN Command := NOP; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '1' AND WENeg = '0' THEN Command := PRE; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '1' AND WENeg = '1' THEN Command := ACT; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '0' AND WENeg = '0' THEN Command := WRIT; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '0' AND WENeg = '1' THEN Command := READ; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '0' AND AIn(10) = '1' THEN Command := ZQCL; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '0' AND AIn(10) = '0' THEN Command := ZQCS; END IF; END IF; CASE Current_state IS WHEN init0 => IF CKE = '1' THEN IF PoweredUp AND (Command = NOP OR Command = DESL) THEN Next_state := init1; In_d <= TRUE; ASSERT ((CK_period >= tperiod_CK_CL5 AND to_nat(MR0(6 DOWNTO 4)) = 1) OR (CK_period >= tperiod_CK_CL6 AND to_nat(MR0(6 DOWNTO 4)) = 2) OR (CK_period >= tperiod_CK_CL7 AND to_nat(MR0(6 DOWNTO 4)) = 3) OR (CK_period >= tperiod_CK_CL8 AND to_nat(MR0(6 DOWNTO 4)) = 4) OR (CK_period >= tperiod_CK_CL9 AND to_nat(MR0(6 DOWNTO 4)) = 5) OR (CK_period >= tperiod_CK_CL10 AND to_nat(MR0(6 DOWNTO 4)) = 6) OR to_nat(MR0(6 DOWNTO 4)) = 0 OR to_nat(MR0(6 DOWNTO 4)) = 7) AND CK_period <= tdevice_tCKAVGMAX REPORT "Clock must be stable before CKE is " & "raised high" SEVERITY warning; ELSE ASSERT FALSE REPORT "Invalid start of initialization" SEVERITY warning; Next_state := illegal; END IF; END IF; --ok WHEN init1 => IF Init_delay AND Command = MRS THEN Next_state := init2; In_d <= FALSE; In_d1 <= TRUE; MR2(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR2(15 DOWNTO 13) := BAIn; ELSIF (NOT Init_delay) AND Command /= NOP AND Command /= DESL THEN ASSERT FALSE REPORT "Only NOP Command are valid during tXPR" SEVERITY warning; END IF; WHEN init2 => IF Init_delay1 AND Command = MRS THEN Next_state := init3; In_d <= FALSE; In_d1 <= TRUE; MR3(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR3(15 DOWNTO 13) := BAIn; END IF; WHEN init3 => IF Init_delay1 AND Command = MRS THEN Next_state := init4; In_d <= FALSE; In_d1 <= TRUE; MR1(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR1(15 DOWNTO 13) := BAIn; END IF; WHEN init4 => IF Init_delay1 AND Command = MRS THEN Next_state := init5; In_d <= FALSE; In_d1 <= TRUE; DLL_delay <= '1', '0' AFTER 1 ns; MR0(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR0(15 DOWNTO 13) := BAIn; END IF; WHEN init5 => IF Init_delay1 AND (Command = ZQCS OR Command = ZQCL) THEN In_d <= FALSE; In_d1 <= FALSE; IF Command = ZQCL AND ZQINIT THEN In_d2 <= TRUE; Next_state := init6; ELSIF Command = ZQCL AND NOT ZQINIT THEN In_d3 <= TRUE; Next_state := init6; END IF; DQOut_zd <= (OTHERS => 'Z'); ODT_off := TRUE; END IF; WHEN init6 => IF (Init_delay2 OR Init_delay3) AND (Command = NOP OR Command = DESL) THEN Initialized <= TRUE; In_d2 <= FALSE; In_d3 <= FALSE; ZQINIT := FALSE; ELSIF (NOT Initialized) AND (Command /= NOP AND Command /= DESL) THEN ASSERT FALSE REPORT "Illegal command during tZQINIT" SEVERITY warning; END IF; WHEN illegal => Next_state := init0; END CASE; Current_state := Next_state; IF Initialized THEN idle := TRUE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) /= precharged THEN idle := FALSE; END IF; END LOOP; IF Command = REF AND CKE = '0' AND NOT idle THEN ASSERT FALSE REPORT "The SELF REFRESH command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; IF CKE = '1' AND NOT (SelfRefresh OR Pre_PD OR Act_PD OR Reset) THEN IF Command = MRS THEN IF idle THEN mrs_active <= '0', '1' AFTER 1 ns; tMOD_in_tmp <= '1' , '0' AFTER 1 ns; FOR I IN 0 TO BankNum LOOP Next_bank_state(I) := MRsetting; END LOOP; IF to_nat(BAIn) = 0 THEN MR0(12 DOWNTO 0) := AIn(12 DOWNTO 0); IF MR0(8) = '1' THEN DLL_delay <= '1', '0' AFTER 1 ns; ODT_off := FALSE; freq_change := FALSE; DLL_reset_needed := FALSE; END IF; ASSERT (to_nat(MR0(11 DOWNTO 9)) /= 0 AND to_nat(MR0(11 DOWNTO 9)) <= 6) AND (to_nat(MR0(6 DOWNTO 4)) >= 1 AND to_nat(MR0(6 DOWNTO 4)) /= 7) AND (to_nat(MR0(1 DOWNTO 0)) >= 0 AND to_nat(MR0(1 DOWNTO 0)) < 3) REPORT "Invalid value programmed to " & "mode register" SEVERITY warning; TimModTemp(1 TO TimingModel'LENGTH) := TimingModel; IF ((TimModTemp(13 to 14) = "DG" AND to_nat(MR0(6 downto 4)) = 6) OR (TimModTemp(13 to 14) = "DJ" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 3 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AC" AND (to_nat(MR0(6 DOWNTO 4)) = 5 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AE" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 5 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AG" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 3 OR to_nat(MR0(6 DOWNTO 4)) = 4 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "8A" AND (to_nat(MR0(6 DOWNTO 4)) >= 3 AND to_nat(MR0(6 DOWNTO 4)) <= 6)) OR (TimModTemp(13 to 14) = "8C" AND to_nat(MR0(6 DOWNTO 4)) /= 2) ) THEN ASSERT FALSE REPORT "Programmed CL value is not " & "supported in this speed grade" SEVERITY warning; END IF; ASSERT MR0(7) = '0' REPORT "Mode should be set to normal, " & "not test" SEVERITY warning; ELSIF to_nat(BAIn) = 1 THEN MR1(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR1(9) & MR1(6) & MR1(2)) <= 5 AND to_nat(MR1(4 DOWNTO 3)) <= 2 AND to_nat(MR1(10)) = 0 AND to_nat(MR1(8)) = 0 AND to_nat(MR1(5)) = 0 REPORT "Invalid value programmed to " & "extended mode register" SEVERITY warning; ASSERT MR1(0) = '0' REPORT "DLL must be enabled for normal " & "operation" SEVERITY warning; ELSIF to_nat(BAIn) = 2 THEN MR2(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR2(5 DOWNTO 3)) <= 3 AND to_nat(MR2(10 DOWNTO 9)) <= 2 AND to_nat(MR2(8))= 0 AND to_nat(MR2(12 DOWNTO 11)) = 0 REPORT "Invalid value programmed to " & "extended mode register 2" SEVERITY warning; ELSE MR3(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR3(1 DOWNTO 0)) = 0 AND to_nat(MR3(12 DOWNTO 4)) = 0 REPORT "Invalid value programmed to " & "extended mode register 3" SEVERITY warning; ASSERT MR3(2) = '0' REPORT "MPR must be set for normal " & "operation" SEVERITY warning; END IF; ELSE ASSERT FALSE REPORT "The MRS command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; END IF; IF (mrs_cnt < 4 AND tMOD_out_tmp = '0' AND (Command /= NOP AND Command /= DESL)) THEN ASSERT FALSE REPORT "Only NOP or DESELECT commands are valid " & "during tMRD after MRS command" SEVERITY warning; END IF; IF (mrs_cnt = 4 AND tMOD_out_tmp = '0' AND (Command /= NOP AND Command /= DESL AND Command /= MRS)) THEN ASSERT FALSE REPORT "Command are issued during during tMOD " & "after MRS " SEVERITY warning; END IF; IF Command = REF THEN IF idle THEN FOR I IN 0 TO BankNum LOOP Next_bank_state(I) := refreshing; END LOOP; tRFCMIN_in <= '0', '1' AFTER 1 ns; tREFPer_in <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "The REFRESH command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; END IF; ASSERT Curr_bank_state(0) /= refreshing OR Command = NOP OR Command = DESL REPORT "Only NOP or DESELECT commands are valid during " & "tRFC(min) after REFRESH command" SEVERITY warning; prechall_viol := FALSE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = prechall AND Command /= NOP AND Command /= DESL THEN prechall_viol := TRUE; END IF; END LOOP; ASSERT NOT prechall_viol REPORT "Only NOP or DESELECT commands are valid during " & "tRPA after PRECHARGE ALL command" SEVERITY warning; ASSERT Command /= PRE OR AIn(10) /= '1' OR tRASMIN_out = "11111111" REPORT "tRAS(min) has not elapsed since activation of the" & " last activated bank" SEVERITY warning; FOR I IN 0 TO BankNum LOOP CASE Curr_bank_state(I) IS WHEN precharged => IF Command = ACT AND to_nat(BAIn) = I AND tMOD_out_tmp = '1' THEN IF NOT active_forbid THEN IF tRRD_out = '1' THEN IF tRC_out(I) = '1' THEN Next_bank_state(I) := activating; active_row(I) := to_nat(AIn); tRCD_in(I) <= '0', '1' AFTER 1 ns; tRASMIN_in(I) <= '0', '1' AFTER 1 ns; tRASMAX_in(I) <= '1'; tRRD_in <= '0', '1' AFTER 1 ns; tRC_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSE ASSERT FALSE REPORT "tRRD has not elapsed " & "since activation of the " & "last activated bank" SEVERITY warning; END IF; END IF; ELSIF Command = ZQCS AND tMOD_out_tmp = '1' THEN Next_bank_state(I) := ZQ_calib; ELSIF (Command = READ OR Command = WRIT) AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command when idle" SEVERITY warning; END IF; WHEN MRsetting => Next_bank_state(I) := precharged; WHEN ZQ_calib => In_d4 <= TRUE; DQOut_zd <= (OTHERS => 'Z'); ODT_off := TRUE; IF Init_delay4 THEN Next_bank_state(I) := precharged; In_d4 <= FALSE; END IF; WHEN precharging => ASSERT Command = NOP OR Command = DESL OR to_nat(BAIn) /= I REPORT "Illegal command during precharging" SEVERITY warning; WHEN prechall => ASSERT Command = NOP OR Command = DESL REPORT "Illegal command during precharging" SEVERITY warning; IF tRP_out(I) = '1' THEN Next_bank_state(I) := precharged; END IF; WHEN active => IF Command = PRE AND AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "tRAS(min) has not elapsed " & "since activation of the bank" SEVERITY warning; END IF; ELSIF Command = PRE AND AIn(10) = '1' THEN IF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(0) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; write_sch(I)(0) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(0) := TRUE; AL_elapsed(I)(0) := FALSE; RTP_elapsed(I) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; rd_wr_cnt := 0; precharge_cnt(I) := 0; rd_act_cnt(I) := 0; rd_pd_cnt := 0; -- tCCD is required between two read --operations (4 tCK) IF rd_rd_cnt >= 3 THEN preamble(I)(0) := TRUE; ELSE preamble(I)(0) := FALSE; END IF; rd_rd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; END IF; ASSERT Command /= ACT OR to_nat(BAIn) /= I REPORT "Previous active row in same bank has " & "not been closed (precharged)" SEVERITY warning; WHEN activating => ASSERT Command = NOP OR Command = DESL OR to_nat(BAIn) /= I REPORT "During activating the bank " & "only valid commands are " & "NOP and DESELECT" SEVERITY warning; WHEN writting => IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF last_write(I) THEN precharge_cnt(I) := precharge_cnt(I) + 1; wr_rd_cnt(I) := wr_rd_cnt(I) + 1; IF to_nat(MR0(11 DOWNTO 9)) <= 3 THEN WR := to_nat(MR0(11 DOWNTO 9))+ 4; ELSE WR := 2*to_nat(MR0(11 DOWNTO 9)); END IF; IF precharge_cnt(I) = burst_len/2 + WL(I)(0) - 1 THEN -- PAGE 94 tWR_in(I) <= '0', '1' AFTER 1 ns; ELSIF precharge_cnt(I) = burst_len/2 + WL(I)(0) + WR THEN WR_elapsed(I) := TRUE; END IF; IF wr_rd_cnt(I)= WL(I)(0) + burst_len/2 THEN tWTR_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; FOR J IN 0 TO 10 LOOP IF write_sch(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSIF WL(I)(J) > 5 THEN WL(I)(J) := WL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); IF burst_len = 4 THEN In_data <= '0', '1' AFTER (2*burst_len+3)*CK_period/4; ELSE In_data <= '0', '1' AFTER (burst_len+1)*CK_period/4 - 1 ns; END IF; write_sch(I)(J) := FALSE; last_write(I) := TRUE; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; WR_elapsed(I) := FALSE; WTR_elapsed(I) := FALSE; END IF; END IF; END LOOP; IF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; last_write(I) := FALSE; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; WR_elapsed(I) := FALSE; WTR_elapsed(I) := FALSE; free_slot := find_free(write_sch(I)); start_column(I)(free_slot):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); CL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(free_slot) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(free_slot) := 0; END IF; write_sch(I)(free_slot) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(0) := TRUE; AL_elapsed(I)(0) := FALSE; RTP_elapsed(I) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; rd_wr_cnt := 0; precharge_cnt(I) := 0; rd_act_cnt(I) := 0; preamble(I)(0) := TRUE; rd_rd_cnt := 0; rd_pd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF WR_elapsed(I) THEN IF tWR_out(I) = '1' THEN IF Command = PRE AND AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = PRE AND AIn(10) = '1' THEN IF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSE Next_bank_state(I) := active; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE during WRITE" SEVERITY warning; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE during WRITE" SEVERITY warning; END IF; IF wr_rd_cnt(I) = 3 THEN WTR_elapsed(I) := TRUE; END IF; IF Command = ACT AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command ACT during WRITE" SEVERITY warning; END IF; WHEN writtingAP => IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF last_write(I) THEN wr_rd_cnt(I) := wr_rd_cnt(I) + 1; precharge_cnt(I) := precharge_cnt(I) + 1; IF to_nat(MR0(11 DOWNTO 9)) <= 3 THEN WR := to_nat(MR0(11 DOWNTO 9))+ 4; ELSE WR := 2*to_nat(MR0(11 DOWNTO 9)); END IF; IF precharge_cnt(I) = burst_len/2 + WL(I)(0) - 1 THEN --page 94 tWR_in(I) <= '0', '1' AFTER 1 ns; ELSIF precharge_cnt(I) = burst_len/2 + WL(I)(0) + WR THEN WR_elapsed(I) := TRUE; END IF; --page 95 IF wr_rd_cnt(I) = WL(I)(0)+ burst_len/2 THEN tWTR_in(I) <= '0', '1' AFTER 1 ns; ELSIF wr_rd_cnt(I) = WL(I)(0)+ burst_len/2 + 3 THEN WTR_elapsed(I) := TRUE; END IF; END IF; FOR J IN 0 TO 10 LOOP IF write_sch(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSIF WL(I)(J) > 5 THEN WL(I)(J) := WL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); IF burst_len = 4 THEN In_data <= '0', '1' AFTER (2*burst_len+3)*CK_period/4; ELSE In_data <= '0', '1' AFTER (burst_len+1)*CK_period/4 -1 ns; END IF; write_sch(I)(J) := FALSE; last_write(I) := TRUE; precharge_cnt(I) := 0; WR_elapsed(I) := FALSE; END IF; END IF; END LOOP; IF ((Command = ACT OR Command = READ OR Command = WRIT) AND to_nat(BAIn) = I) OR (Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1')) THEN ASSERT FALSE REPORT "Illegal command after WRITE AP" SEVERITY warning; END IF; IF WR_elapsed(I) THEN IF tWR_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; WHEN reading => precharge_cnt(I) := precharge_cnt(I) + 1; rd_act_cnt(I) := rd_act_cnt(I) + 1; IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF precharge_cnt(I) = 4 THEN -- tRTRP tRTP_in(I) <= '0', '1' AFTER 1 ns; ELSIF tRTP_out(I) = '1' THEN RTP_elapsed(I) := TRUE; END IF; FOR J IN 0 TO 10 LOOP IF read_sch(I)(J) AND NOT AL_elapsed(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); read_delay := CL(I)(J); IF read_delay = 3 THEN IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; END IF; wait_read(I)(J) <= '0', '1' AFTER 1 ns; AL_elapsed(I)(J) := TRUE; END IF; END IF; END LOOP; IF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN precharge_cnt(I) := 0; rd_wr_cnt := 0; rd_act_cnt(I) := 0; RTP_elapsed(I) := FALSE; RTW_elapsed := FALSE; free_slot := find_free(read_sch(I)); start_column(I)(free_slot) := to_nat(AIn(11)& AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(free_slot) := 0; END IF; CL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(free_slot) := TRUE; AL_elapsed(I)(free_slot) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; IF rd_rd_cnt >= 3 THEN preamble(I)(free_slot) := TRUE; ELSE preamble(I)(free_slot) := FALSE; END IF; rd_rd_cnt := 0; rd_pd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; start_column(I)(0) := to_nat(AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(0) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; write_sch(I)(0) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF RTP_elapsed(I) AND tRTP_out(I) = '1' AND Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN IF AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "tRAS(min) has not " & "elapsed since " & "activation of the bank" SEVERITY warning; END IF; ELSIF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE while reading" SEVERITY warning; END IF; IF Command = ACT AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command ACT after READ" SEVERITY warning; END IF; WHEN readingAP => precharge_cnt(I) := precharge_cnt(I) + 1; IF MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1') THEN burst_len := 8; ELSE burst_len := 4; END IF; IF precharge_cnt(I) = to_nat(MR0(6 DOWNTO 4))+ 4 - to_nat(MR1(4 DOWNTO 3)) + burst_len/2 THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; ELSIF tRTP_out(I) = '1' THEN RTP_elapsed(I) := TRUE; END IF; FOR J IN 0 TO 10 LOOP IF read_sch(I)(J) AND NOT AL_elapsed(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); read_delay := CL(I)(J); IF read_delay = 3 THEN IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; END IF; wait_read(I)(J) <= '0', '1' AFTER 1 ns; AL_elapsed(I)(J) := TRUE; END IF; END IF; END LOOP; IF ((Command = ACT OR Command = READ OR Command = WRIT) AND to_nat(BAIn) = I) OR (Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1')) THEN ASSERT FALSE REPORT "Illegal command after READ AP" SEVERITY warning; END IF; IF RTP_elapsed(I) AND tRTP_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; WHEN OTHERS => END CASE; Curr_bank_state(I) := Next_bank_state(I); END LOOP; IF rd_rd_cnt < 4 THEN --tCCD rd_rd_cnt := rd_rd_cnt + 1; END IF; IF wr_wr_cnt < 4 THEN --tCCD wr_wr_cnt := wr_wr_cnt + 1; END IF; IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL_tmp := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL_tmp := 0; END IF; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL_tmp := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; CL_tmp := to_nat(MR0(6 DOWNTO 4))+4; IF rd_wr_cnt = CL_tmp+AL_tmp-WL_tmp+2+burst_len/8 THEN RTW_elapsed := TRUE; END IF; IF rd_wr_cnt < CL_tmp+AL_tmp-WL_tmp+2+burst_len/8 THEN rd_wr_cnt := rd_wr_cnt + 1; END IF; -- WRITE LEVELING PROCEDURE IF idle AND Command = MRS AND ((MR1(7) = '1' AND MR1(12) = '1') OR (MR1(7) = '1' AND MR1(12) = '0' AND to_nat(MR1(9) & MR1(6)& MR1(2)) <= 3)) THEN tWLODTEN_in <= '0', '1' AFTER 1 ns; tWLDQSEN_in <= '0', '1' AFTER 1 ns; tWLMRD_in <= '0', '1' AFTER 1 ns; END IF; IF tWLODTEN_out = '1' AND ODT = '1' THEN ODT_off := FALSE; END IF; IF tWLDQSEN_out = '1' AND ODT = '1' THEN WL_on <= TRUE; END IF; IF MR1(7) = '0' THEN WL_on <= FALSE; -- END OF WRITE LEVELING PROCEDURE END IF; END IF; IF (tWLDQSEN_in = '1' AND tWLDQSEN_out = '0' AND DQS = '0') THEN ASSERT FALSE REPORT "DQS should not be asserted during tWLDQSEN" SEVERITY warning; END IF; IF (tWLMRD_in = '1' AND tWLMRD_out = '0' AND DQS = '1') THEN ASSERT FALSE REPORT "DQS should not be deasserted during tWLMRD" SEVERITY warning; END IF; IF CKE = '0' AND NOT CKEfall THEN CKEfall := TRUE; CKErise := FALSE; ASSERT CKEcnt = 3 REPORT "CKE has not been high for tCKE(min)" SEVERITY warning; CKEcnt := 0; END IF; IF CKE = '1' AND NOT CKErise THEN CKErise := TRUE; CKEfall := FALSE; ASSERT CKEcnt = 3 REPORT "CKE has not been low for tCKE(min)" SEVERITY warning; CKEcnt := 0; END IF; IF CKEcnt < 3 THEN CKEcnt := CKEcnt + 1; END IF; IF CKE = '0' AND idle AND Command = REF AND NOT SelfRefresh AND (ODT = '0' OR (MR1(6) = '0' AND MR1(2) = '0' AND MR1(9) = '0')) AND NOT Act_PD AND NOT Pre_PD AND NOT Reset AND NOT WL_on AND tMOD_out_tmp = '1' THEN SR_cond := TRUE; SelfRefresh <= TRUE; IF MR2(2 DOWNTO 0) /= "000" THEN PartialSelfRefresh <= TRUE; END IF; SR_exit <= FALSE; END IF; IF CKE = '0' AND idle AND Command = REF AND tMOD_out_tmp = '0' THEN ASSERT FALSE REPORT "SELF REFRESH command is issued during tMOD" SEVERITY warning; END IF; IF SelfRefresh AND NOT SR_exit AND NOT SR_enter_cycle AND CKE = '0' THEN SR_enter_cycle := TRUE; IF to_nat(MR2(2 DOWNTO 0)) < 4 THEN sf_array := 2**(3 - to_nat(MR2(2 DOWNTO 0)))-1; FOR J IN 0 TO sf_array LOOP tCKESR_in(J) <= '0', '1' AFTER 1 ns; FOR K IN sf_array TO BankNum LOOP IF to_nat(MR2(2 DOWNTO 0)) /= 0 THEN FOR L IN 0 TO MemSize LOOP Mem(K)(L) := -1; END LOOP; END IF; END LOOP; END LOOP; ELSIF to_nat(MR2(2 DOWNTO 0)) >= 4 and to_nat(MR2(2 DOWNTO 0)) < 7 THEN sf_array := 2*(to_nat(MR2(2 DOWNTO 0))-3); FOR J IN sf_array TO 7 LOOP tCKESR_in(J) <= '0', '1' AFTER 1 ns; FOR K IN 0 TO sf_array LOOP FOR L IN 0 TO MemSize LOOP Mem(K)(L) := -1; END LOOP; END LOOP; END LOOP; ELSE tCKESR_in <= "00000001"; FOR K IN 0 TO 6 LOOP FOR J IN 0 TO MemSize LOOP Mem(K)(J) := -1; END LOOP; END LOOP; END IF; END IF; IF CKE = '1' AND SelfRefresh AND NOT SR_exit AND tCKESR_out = "11111111" THEN SR_exit <= TRUE; tXS_in <= '0', '1' AFTER 1 ns; DLL_delay <= '1', '0' AFTER 1 ns; IF freq_change AND to_nat(MR1(0))= 1 THEN DLL_reset_needed := TRUE; ELSE DLL_reset_needed := FALSE; END IF; END IF; ASSERT Command = NOP OR Command = DESL OR NOT SelfRefresh OR NOT SR_exit REPORT "Only NOP and DESELECT commands are valid for tXS " & "after self refresh exit" SEVERITY warning; RL_tmp := AL_tmp + CL_tmp + 5; IF rd_pd_cnt <= RL_tmp THEN rd_pd_cnt := rd_pd_cnt + 1; END IF; IF CKE = '0' AND (Command = NOP OR Command = DESL) AND NOT Act_PD AND NOT Pre_PD AND NOT SelfRefresh AND NOT Reset AND NOT WL_on THEN power_down_cond := TRUE; active_pd_cond := FALSE; FOR I IN 0 TO BankNum LOOP IF (Curr_bank_state(I) = reading AND rd_pd_cnt < RL_tmp) OR Curr_bank_state(I) = readingAP THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tRDPDEN after READ" SEVERITY warning; ELSIF (Curr_bank_state(I) = writting AND NOT (WTR_elapsed(I) AND tWTR_out(I) = '1')) THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tWRPDEN after WRITE" SEVERITY warning; ELSIF Curr_bank_state(I) = writtingAP THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tWRAPDEN after WRITE" SEVERITY warning; ELSIF Curr_bank_state(I) = MRsetting OR tMOD_out_tmp = '0' THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tMRSPDEN after MRS" SEVERITY warning; ELSIF ReadStart OR Read_Start THEN power_down_cond := FALSE; ELSIF Curr_bank_state(I) = activating OR Curr_bank_state(I) = active OR (Curr_bank_state(I) = writting AND WTR_elapsed(I) AND tWTR_out(I) = '1') THEN active_pd_cond := TRUE; END IF; END LOOP; IF power_down_cond THEN IF NOT DLL_delay_elapsed AND to_nat(MR0(8))= 1 THEN DLL_reset_needed := TRUE; END IF; IF active_pd_cond THEN Act_PD <= TRUE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = activating OR Curr_bank_state(I) = writting OR Curr_bank_state(I) = active THEN Curr_bank_state(I) := active; ELSE Curr_bank_state(I) := precharged; END IF; Curr_bank_state(I) := Next_bank_state(I); END LOOP; ELSE Pre_PD <= TRUE; IF ODT = '0' OR (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') THEN ODT_off := TRUE; END IF; freq_ch_cnt := 5; --tCKSRE Curr_bank_state := (OTHERS => precharged); Next_bank_state := (OTHERS => precharged); END IF; END IF; END IF; IF freq_ch_cnt > 0 THEN freq_ch_cnt := freq_ch_cnt - 1; END IF; IF CKE = '1' AND Pre_PD THEN IF PD_exit_cnt = 0 THEN power_down_cond := FALSE; PD_exit_cnt := 1; Pre_PD <= FALSE; ELSE PD_exit_cnt := 0; -- slow exit precharge power-down to read IF NOT PD_read_delay AND MR0(12) = '0' THEN PD_read_delay := TRUE; PD_read_del_cnt := 10; --tXPDLL -- fast exit precharge power-down to read ELSIF NOT PD_read_delay AND MR0(12) = '1' THEN PD_read_delay := TRUE; PD_read_del_cnt := 3; --tXP END IF; IF freq_change THEN DLL_reset_needed := TRUE; END IF; END IF; END IF; IF DLL_delay_elapsed THEN DLL_reset_needed := FALSE; END IF; IF CKE = '1' AND Act_PD THEN IF PD_exit_cnt = 0 THEN PD_exit_cnt := 1; Act_PD <= FALSE; ELSE PD_exit_cnt := 0; -- slow exit active power-down to read IF NOT PD_read_delay AND MR0(12) = '0' THEN PD_read_delay := TRUE; PD_read_del_cnt := 10; --tXPDLL -- fast exit active power-down to read ELSIF NOT PD_read_delay AND MR0(12) = '1' THEN PD_read_delay := TRUE; PD_read_del_cnt := 3; --tXP END IF; END IF; END IF; IF PD_read_del_cnt > 1 AND PD_read_delay THEN PD_read_del_cnt := PD_read_del_cnt - 1; ELSE PD_read_delay := FALSE; END IF; END IF; END IF; IF falling_edge(CKE) AND NOT Initialized THEN ASSERT FALSE REPORT "CKE must be driven high during initialization" SEVERITY warning; Current_state := illegal; Next_state := illegal; END IF; IF falling_edge(RST) AND RESETNeg = '0' AND PoweredUp THEN Reset_enter_cycle := TRUE; Reset <= TRUE; SR_cond := FALSE; power_down_cond := FALSE; Act_PD <= FALSE; Pre_PD <= FALSE; SelfRefresh <= FALSE; WL_on <= FALSE; END IF; IF rising_edge(tRFCMIN_out) THEN FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = refreshing THEN Curr_bank_state(I) := precharged; Next_bank_state(I) := precharged; END IF; END LOOP; END IF; IF rising_edge(CKDiff) AND mrs_cnt < 4 THEN mrs_cnt := mrs_cnt + 1; END IF; IF tREFPer_out'EVENT AND tREFPer_out = '1' THEN ASSERT FALSE REPORT "tREFPer(max) has elapsed since last REFRESH command" SEVERITY warning; END IF; IF rising_edge(ODT) THEN ASSERT NOT SelfRefresh OR NOT SR_exit OR (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') REPORT "After exiting self refresh, ODT must remain turned " & "off until tXS is satisfied" SEVERITY warning; END IF; IF rising_edge(ODT) AND ODT_off AND NOT (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') THEN ODT_off := FALSE; END IF; IF rising_edge(tXS_out) AND SelfRefresh AND SR_exit THEN SR_cond := FALSE; SelfRefresh <= FALSE; SR_exit <= FALSE; PartialSelfRefresh <= FALSE; END IF; IF rising_edge(CKE) AND SelfRefresh AND NOT SR_exit THEN SR_enter_cycle := FALSE; ASSERT ((CK_period >= tperiod_CK_CL5 AND to_nat(MR0(6 DOWNTO 4))= 5) OR (CK_period >= tperiod_CK_CL6 AND to_nat(MR0(6 DOWNTO 4)) = 6) OR (CK_period >= tperiod_CK_CL7 AND to_nat(MR0(6 DOWNTO 4)) = 7) OR (CK_period >= tperiod_CK_CL8 AND to_nat(MR0(6 DOWNTO 4)) = 8) OR (CK_period >= tperiod_CK_CL9 AND to_nat(MR0(6 DOWNTO 4)) = 9) OR (CK_period >= tperiod_CK_CL10 AND to_nat(MR0(6 DOWNTO 4)) = 10) OR to_nat(MR0(6 DOWNTO 4)) < 5 OR to_nat(MR0(6 DOWNTO 4)) > 11) AND CK_period <= tdevice_tCKAVGMAX REPORT "Clock must be stable and meeting tCKSRX " & "specifications at least 5 x tCK prior to exiting" & "self refresh mode" SEVERITY warning; END IF; IF falling_edge(CKE) THEN ASSERT NOT SelfRefresh OR NOT SR_exit REPORT "CKE must stay high until tXS is met" SEVERITY warning; END IF; IF rising_edge(CKE) AND Reset THEN Reset <= FALSE; Reset_enter_cycle := FALSE; Initialized <= FALSE; Current_state := init0; Curr_bank_state := (OTHERS => precharged); END IF; END PROCESS Functionality; PROCESS(mrs_active) BEGIN IF rising_edge(mrs_active) THEN mrs_cnt := 1; END IF; END PROCESS; Write_leveling: PROCESS(tMRD_out,DQSDiff,tWLOMAX_out,ODT,tMOD_out,AIn,WL_on) BEGIN IF rising_edge(ODT) THEN ODTLOFF := FALSE; END IF; IF tWLMRD_out = '1' AND rising_edge(DQSDiff) AND NOT DQ_driven THEN tWLOMAX_in <= '0', '1' AFTER 1 ns; ELSIF tWLOMAX_out = '1' AND NOT DQ_driven AND ODT = '1' THEN DQout_zd <= (OTHERS => '0'); DQ_driven <= TRUE; ELSIF DQ_driven AND rising_edge(DQSDiff) AND DQ_driven AND ODT = '1' THEN tWLOMAX_in <= '0', '1' AFTER 1 ns; ELSIF tWLOMAX_out = '1' AND DQ_driven AND ODT = '1' THEN DQout_zd <= (OTHERS => '1'); DQ_driven <= FALSE; ELSIF falling_edge(ODT) THEN ODTLOFF := TRUE; ELSIF ODT = '0' AND MR1(7) = '0' AND WL_on'EVENT AND NOT WL_on THEN tMRD_in <= '0', '1' AFTER 1 ns; tMOD_in <= '0', '1' AFTER 1 ns; ELSIF ODT = '0' AND MR1(7) = '0' AND tMOD_out = '1' THEN DQout_zd <= (OTHERS => 'Z'); END IF; END PROCESS Write_leveling; TRCDOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRCD_out(I)) BEGIN IF rising_edge(tRCD_out(I)) AND Curr_bank_state(I) = activating THEN Curr_bank_state(I) := active; Next_bank_state(I) := active; END IF; END PROCESS; END GENERATE TRCDOUT; TRPOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRP_out(I)) BEGIN IF rising_edge(tRP_out(I)) AND Curr_bank_state(I) = precharging THEN Curr_bank_state(I) := precharged; Next_bank_state(I) := precharged; END IF; END PROCESS; END GENERATE TRPOUT; TRASMAXOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRASMAX_out(I)) BEGIN ASSERT tRASMAX_out(I) = '0' REPORT "tRAS(max) has elapsed since activation of bank, and " & "PRECHARGE command still hasn't been issued" SEVERITY warning; END PROCESS; END GENERATE TRASMAXOUT; Refresh_period: PROCESS(Initialized, Ref_per_expired, --tREFPer_in, SelfRefresh, SR_exit, SimulationEnd, Reset) VARIABLE Ref_cnt : natural; BEGIN IF (Initialized'EVENT AND Initialized) OR rising_edge(Ref_per_expired) OR (SR_exit'EVENT AND SR_exit) THEN Ref_per_start <= '0', '1' AFTER 1 ns; Ref_cnt := 0; END IF; IF (SelfRefresh'EVENT AND SelfRefresh) OR (SimulationEnd'EVENT AND SimulationEnd AND NOT SR_enter_cycle AND NOT Reset_enter_cycle) OR (Reset'EVENT AND Reset) THEN Ref_per_start <= '0'; END IF; END PROCESS Refresh_period; PROCESS(Ref_per_start) VARIABLE industrial : natural RANGE 0 TO 1; BEGIN IF rising_edge(Ref_per_start) THEN industrial := bool_to_nat(MR2(7) = '1'); Ref_per_expired <= '1' AFTER tdevice_tREFPer/(industrial+1) - 1 ns; ELSIF falling_edge(Ref_per_start) THEN Ref_per_expired <= '0' AFTER 1 ns; END IF; END PROCESS; -- Write to memory process Indata: PROCESS(DQSIn, In_data) VARIABLE In_col : natural RANGE 0 TO ColNum; VARIABLE Start_bank : natural RANGE 0 TO BankNum; VARIABLE Start_row : natural RANGE 0 TO RowNum; VARIABLE Start_col : natural RANGE 0 TO ColNum; VARIABLE burst_cnt : natural := 8; VARIABLE burst_cnt_aux : natural := 0; VARIABLE cross1 : boolean := FALSE; VARIABLE cross : boolean := FALSE; VARIABLE burst_seq : sequence; PROCEDURE Write_Mem IS VARIABLE addr_temp : natural; BEGIN addr_temp := Start_row*(ColNum+1) + In_col; IF DM /= '1' THEN Mem(Start_bank)(addr_temp) := -1; IF Viol = '0' THEN Mem(Start_bank)(addr_temp) := to_nat(DQIn); END IF; END IF; END Write_Mem; BEGIN FOR I IN 0 TO BankNum LOOP IF rising_edge(In_data) THEN preamble_check <= TRUE, FALSE AFTER CK_period/2 + 1 ns; Start_bank := current_bank; Start_row := current_row; Start_col := current_column; IF (burst_len = 4) THEN Start_col := current_column - (current_column MOD 4); ELSE Start_col := current_column - (current_column MOD 8); END IF; In_col := Start_col; burst_cnt := 0; burst_cnt_aux := 0; IF MR0(3) = '0' THEN burst_seq := seq(0); ELSE burst_seq := inl(0); END IF; END IF; IF (rising_edge(DQSIn) AND MR1(11) = '0') AND burst_cnt_aux < 2 AND (Curr_bank_state(I) = writting OR Curr_bank_state(I) = writtingAP) AND NOT cross THEN burst_cnt_aux := burst_cnt_aux + 1; cross := TRUE; END IF; IF ( DQSIn'EVENT ) AND burst_cnt < burst_len AND burst_cnt_aux > 1 AND (Curr_bank_state(I) = writting OR Curr_bank_state(I) = writtingAP) AND NOT cross1 THEN In_col := Start_col + burst_seq(burst_cnt); cross1 := TRUE; IF burst_cnt = burst_len - 1 THEN postamble_check <= TRUE, FALSE AFTER CK_period; burst_cnt_aux := 0; IF burst_len = 8 THEN burst_cnt := 8; ELSE burst_cnt := 4; END IF; ELSE burst_cnt := burst_cnt + 1; END IF; Write_Mem; END IF; END LOOP; cross := FALSE; cross1 := FALSE; END PROCESS Indata; WaitRead: FOR I IN 0 TO BankNum GENERATE Inner: FOR J IN 0 TO 10 GENERATE PROCESS (CKDiff, wait_read(I)(J)) VARIABLE delay : natural RANGE 0 TO 10; VARIABLE temp_bank : natural; VARIABLE temp_row : natural; VARIABLE temp_column : natural; BEGIN IF rising_edge(wait_read(I)(J)) THEN Read_Start := TRUE; delay := read_delay; temp_bank := current_bank; temp_row := current_row; temp_column := current_column; END IF; IF rising_edge(CKDiff) THEN IF delay > 4 THEN delay := delay - 1; ELSIF delay = 4 THEN delay := delay - 1; IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; ELSIF delay = 3 THEN delay := delay - 1; read_bank := temp_bank; read_row := temp_row; read_column := temp_column; Out_data <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; read_sch(I)(J) := FALSE; END IF; END IF; END PROCESS; END GENERATE Inner; END GENERATE WaitRead; Outdata: PROCESS(CKInt, preamble_gen, Out_data) VARIABLE preamble_done : boolean := FALSE; VARIABLE preamble_allow : boolean; VARIABLE In_col : natural RANGE 0 TO ColNum; VARIABLE Start_bank : natural RANGE 0 TO BankNum; VARIABLE Start_row : natural RANGE 0 TO RowNum; VARIABLE Start_col : natural RANGE 0 TO ColNum; VARIABLE burst_cnt : natural := 9; VARIABLE burst_seq : sequence; VARIABLE out_buffer : std_logic_vector(3 DOWNTO 0); PROCEDURE Read_Mem IS VARIABLE addr_temp : natural; VARIABLE data_temp : integer; BEGIN addr_temp := Start_row*(ColNum+1) + In_col; out_buffer := (OTHERS => 'X'); data_temp := Mem(Start_bank)(addr_temp); IF data_temp = -2 THEN out_buffer(3 DOWNTO 0) := (OTHERS => 'U'); ELSIF data_temp /= -1 THEN out_buffer(3 DOWNTO 0) := to_slv(data_temp, 4); END IF; END Read_Mem; BEGIN IF rising_edge(CKInt) THEN preamble_allow := FALSE; END IF; IF rising_edge(preamble_gen) THEN preamble_done := FALSE; END IF; IF rising_edge(CKInt) AND NOT preamble_done THEN preamble_allow := TRUE; preamble_done := TRUE; IF MR1(12) = '0' THEN DQSOut_zd <= NOT CKInt; DQSNegOut_zd <= CKInt; END IF; END IF; IF rising_edge(Out_data) THEN Start_bank := read_bank; Start_row := read_row; Start_col := read_column; burst_cnt := 0; In_col := Start_col; IF MR0(3) = '0' THEN burst_seq := seq(In_col MOD 8); ELSE burst_seq := inl(In_col MOD 8); END IF; END IF; IF rising_edge(CKInt) AND burst_cnt = 0 THEN burst_cnt := 1; Read_Mem; IF MR1(12) = '0' THEN DQSOut_zd <= CKInt; DQSNegOut_zd <= NOT CKInt; DQOut_zd <= out_buffer; END IF; ELSIF CKInt'EVENT AND burst_cnt > 0 AND burst_cnt < burst_len THEN ReadStart <= TRUE; In_col := Start_col + burst_seq(burst_cnt); burst_cnt := burst_cnt + 1; Read_Mem; IF MR1(12) = '0' THEN DQSOut_zd <= CKInt; DQSNegOut_zd <= NOT CKInt; DQOut_zd <= out_buffer; END IF; ELSIF CKInt'EVENT AND burst_cnt = burst_len AND NOT preamble_allow THEN burst_cnt := 9; DQSOut_zd <= 'Z'; DQSNegOut_zd <= 'Z'; DQOut_zd <= (OTHERS => 'Z'); ReadStart <= FALSE AFTER CK_period/4 + 1 ns; Read_Start := FALSE; END IF; END PROCESS Outdata; active_number: PROCESS(tRRD_in, tFAW_out) TYPE act_num_type IS ARRAY (0 TO 3) OF natural RANGE 0 TO 3; VARIABLE act_num : act_num_type := (OTHERS => 0); VARIABLE next_slot : boolean := FALSE; BEGIN IF rising_edge(tRRD_in) THEN FOR I IN 0 TO 3 LOOP IF act_num(I) = 0 THEN IF I = 0 THEN act_num(0) := 1; tFAW_in(0) <= '0', '1' AFTER 1 ns; ELSE next_slot := TRUE; FOR J IN 0 TO I-1 LOOP IF act_num(J) = 0 THEN next_slot := FALSE; END IF; END LOOP; IF next_slot THEN act_num(I) := 1; tFAW_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; ELSE IF act_num(I) = 3 THEN active_forbid := TRUE; ELSE act_num(I) := act_num(I) + 1; END IF; END IF; END LOOP; END IF; IF rising_edge(tFAW_out(0)) THEN act_num(0) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(1)) THEN act_num(1) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(2)) THEN act_num(2) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(3)) THEN act_num(3) := 0; active_forbid := FALSE; END IF; END PROCESS active_number; DQValueGen : PROCESS( DQOut_zd ) BEGIN IF DQOut_zd(0) /= 'Z' THEN DOut_Pass <= DQOut_zd AFTER 0.27 ns; ELSE DOut_Pass <= DQOut_zd; END IF; END PROCESS DQValueGen; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- DQOut_PathDelay_Gen: FOR I IN DOut_Pass'RANGE GENERATE PROCESS(DOut_Pass(I)) VARIABLE DQ0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQOut(I), OutSignalName => "DQOut", OutTemp => DOut_Pass(I), GlitchData => DQ0_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQ0, PathCondition => TRUE) ) ); END PROCESS; END GENERATE DQOut_PathDelay_Gen; PROCESS(DQSOut_zd) VARIABLE DQSOut_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQSOut, OutSignalName => "DQSOut", OutTemp => DQSOut_zd, GlitchData => DQSOut_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQS, PathCondition => TRUE) ) ); END PROCESS; PROCESS(DQSNegOut_zd) VARIABLE DQSNegOut_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQSNegOut, OutSignalName => "DQSNegOut", OutTemp => DQSNegOut_zd, GlitchData => DQSNegOut_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQS, PathCondition => TRUE) ) ); END PROCESS; default: PROCESS -- Text file input variables FILE mem_file : text IS mem_file_name; VARIABLE ind : natural := 0; VARIABLE buf : line; BEGIN -- Preload Control ------------------------------------------------------------------------ -- File Read Section ------------------------------------------------------------------------ ------------------------------------------------------------------------ ----- edj5304ba memory preload file format ---------------------------- ------------------------------------------------------------------------ -- / - comment -- @aaaaaaa - stands for address within memory, -- 24 LSBits determine address within bank, -- other bits determine bank address, -- bytes within bank are written row by row -- d - is 4-bits to be written at address aaaaaaa++ -- (aaaaaaa is incremented at every load), -- only first 1-8 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------ IF UserPreload AND (mem_file_name /= "none" ) THEN ind := 0; Mem := (OTHERS => (OTHERS => -2)); WHILE (NOT ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 TO 8)); --address ELSE IF ind < (BankNum+1)*(MemSize+1) THEN Mem(ind/(MemSize+1))(ind MOD (MemSize+1)) := h(buf(1 to 1)); ind := ind + 1; ELSE REPORT "Memory address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS default; END BLOCK behavior; END vhdl_behavioral_static_memory_allocation; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_dynamic_memory_allocation OF edj5304ba IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral_dynamic_memory_allocation : ARCHITECTURE IS TRUE; CONSTANT PartID : string := "EDJ5304BA"; CONSTANT BankNum : natural := 7; CONSTANT MaxData : natural := 16#F#; CONSTANT MemSize : natural := 16#FFFFFF#; CONSTANT RowNum : natural := 16#1FFF#; CONSTANT ColNum : natural := 16#7FF#; -- ipd SIGNAL ODT_ipd : std_ulogic := 'U'; SIGNAL CK_ipd : std_ulogic := 'U'; SIGNAL CKNeg_ipd : std_ulogic := 'U'; SIGNAL CKE_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL DM_ipd : std_ulogic := 'U'; SIGNAL BA0_ipd : std_ulogic := 'U'; SIGNAL BA1_ipd : std_ulogic := 'U'; SIGNAL BA2_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQS_ipd : std_ulogic := 'U'; SIGNAL DQSNeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; -- nwv SIGNAL ODT_nwv : std_ulogic := 'U'; SIGNAL CK_nwv : std_ulogic := 'U'; SIGNAL CKNeg_nwv : std_ulogic := 'U'; SIGNAL CKE_nwv : std_ulogic := 'U'; SIGNAL CSNeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL BA0_nwv : std_ulogic := 'U'; SIGNAL BA1_nwv : std_ulogic := 'U'; SIGNAL BA2_nwv : std_ulogic := 'U'; SIGNAL A0_nwv : std_ulogic := 'U'; SIGNAL A1_nwv : std_ulogic := 'U'; SIGNAL A2_nwv : std_ulogic := 'U'; SIGNAL A3_nwv : std_ulogic := 'U'; SIGNAL A4_nwv : std_ulogic := 'U'; SIGNAL A5_nwv : std_ulogic := 'U'; SIGNAL A6_nwv : std_ulogic := 'U'; SIGNAL A7_nwv : std_ulogic := 'U'; SIGNAL A8_nwv : std_ulogic := 'U'; SIGNAL A9_nwv : std_ulogic := 'U'; SIGNAL A10_nwv : std_ulogic := 'U'; SIGNAL A11_nwv : std_ulogic := 'U'; SIGNAL A12_nwv : std_ulogic := 'U'; SIGNAL DQ0_nwv : std_ulogic := 'U'; SIGNAL DQ1_nwv : std_ulogic := 'U'; SIGNAL DQ2_nwv : std_ulogic := 'U'; SIGNAL DQ3_nwv : std_ulogic := 'U'; SIGNAL DM_nwv : std_ulogic := 'U'; SIGNAL DQS_nwv : std_ulogic := 'U'; SIGNAL DQSNeg_nwv : std_ulogic := 'U'; SIGNAL RESETNeg_nwv : std_ulogic := 'U'; --- internal delays SIGNAL tRC_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRC_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRRD_in : std_ulogic := '1'; SIGNAL tRRD_out : std_ulogic := '1'; SIGNAL tRCD_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRCD_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_in : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_out : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMIN_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMIN_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMAX_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMAX_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRTP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRTP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRFCMIN_in : std_ulogic := '0'; SIGNAL tRFCMIN_out : std_ulogic := '0'; SIGNAL tXS_in : std_ulogic := '0'; SIGNAL tXS_out : std_ulogic := '0'; SIGNAL tREFPer_in : std_ulogic := '0'; SIGNAL tREFPer_out : std_ulogic := '0'; SIGNAL tCKAVGMAX_in : std_ulogic := '0'; SIGNAL tCKAVGMAX_out : std_ulogic := '0'; SIGNAL tWPSTMAX_in : std_ulogic := '0'; SIGNAL tWPSTMAX_out : std_ulogic := '0'; SIGNAL tCKSRX_in : std_ulogic := '0'; SIGNAL tCKSRX_out : std_ulogic := '0'; SIGNAL tCKSRE_in : std_ulogic := '0'; SIGNAL tCKSRE_out : std_ulogic := '0'; SIGNAL tWLODTEN_in : std_ulogic := '0'; SIGNAL tWLODTEN_out : std_ulogic := '0'; SIGNAL tWLDQSEN_in : std_ulogic := '0'; SIGNAL tWLDQSEN_out : std_ulogic := '0'; SIGNAL tWLMRD_in : std_ulogic := '0'; SIGNAL tWLMRD_out : std_ulogic := '0'; SIGNAL tWLOMAX_in : std_ulogic := '0'; SIGNAL tWLOMAX_out : std_ulogic := '0'; SIGNAL tWLOEMAX_in : std_ulogic := '0'; SIGNAL tWLOEMAX_out : std_ulogic := '0'; SIGNAL tODTLOFF_in : std_ulogic := '0'; SIGNAL tODTLOFF_out : std_ulogic := '0'; SIGNAL tMRD_in : std_ulogic := '0'; SIGNAL tMRD_out : std_ulogic := '0'; SIGNAL tMOD_in : std_ulogic := '0'; SIGNAL tMOD_out : std_ulogic := '0'; SIGNAL tMOD_in_tmp : std_ulogic := '0'; SIGNAL tMOD_out_tmp : std_ulogic := '0'; SIGNAL tXPR_in : std_ulogic := '0'; SIGNAL tXPR_out : std_ulogic := '0'; SIGNAL tZQINIT_in : std_ulogic := '0'; SIGNAL tZQINIT_out : std_ulogic := '0'; SIGNAL tZQOPER_in : std_ulogic := '0'; SIGNAL tZQOPER_out : std_ulogic := '0'; SIGNAL tZQCS_in : std_ulogic := '0'; SIGNAL tZQCS_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- TRC : VitalBuf(tRC_out(0), tRC_in(0), (tdevice_tRC - 1 ns, UnitDelay)); TRC1 : VitalBuf(tRC_out(1), tRC_in(1), (tdevice_tRC - 1 ns, UnitDelay)); TRC2 : VitalBuf(tRC_out(2), tRC_in(2), (tdevice_tRC - 1 ns, UnitDelay)); TRC3 : VitalBuf(tRC_out(3), tRC_in(3), (tdevice_tRC - 1 ns, UnitDelay)); TRC4 : VitalBuf(tRC_out(4), tRC_in(4), (tdevice_tRC - 1 ns, UnitDelay)); TRC5 : VitalBuf(tRC_out(5), tRC_in(5), (tdevice_tRC - 1 ns, UnitDelay)); TRC6 : VitalBuf(tRC_out(6), tRC_in(6), (tdevice_tRC - 1 ns, UnitDelay)); TRC7 : VitalBuf(tRC_out(7), tRC_in(7), (tdevice_tRC - 1 ns, UnitDelay)); TRRD : VitalBuf(tRRD_out, tRRD_in, (tdevice_tRRD - 1 ns, UnitDelay)); TRCD : VitalBuf(tRCD_out(0), tRCD_in(0), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD1 : VitalBuf(tRCD_out(1), tRCD_in(1), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD2 : VitalBuf(tRCD_out(2), tRCD_in(2), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD3 : VitalBuf(tRCD_out(3), tRCD_in(3), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD4 : VitalBuf(tRCD_out(4), tRCD_in(4), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD5 : VitalBuf(tRCD_out(5), tRCD_in(5), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD6 : VitalBuf(tRCD_out(6), tRCD_in(6), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD7 : VitalBuf(tRCD_out(7), tRCD_in(7), (tdevice_tRCD - 1 ns, UnitDelay)); TFAW : VitalBuf(tFAW_out(0), tFAW_in(0), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW1 : VitalBuf(tFAW_out(1), tFAW_in(1), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW2 : VitalBuf(tFAW_out(2), tFAW_in(2), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW3 : VitalBuf(tFAW_out(3), tFAW_in(3), (tdevice_tFAW - 2 ns, UnitDelay)); TRASMIN : VitalBuf(tRASMIN_out(0), tRASMIN_in(0), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN1 : VitalBuf(tRASMIN_out(1), tRASMIN_in(1), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN2 : VitalBuf(tRASMIN_out(2), tRASMIN_in(2), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN3 : VitalBuf(tRASMIN_out(3), tRASMIN_in(3), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN4 : VitalBuf(tRASMIN_out(4), tRASMIN_in(4), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN5 : VitalBuf(tRASMIN_out(5), tRASMIN_in(5), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN6 : VitalBuf(tRASMIN_out(6), tRASMIN_in(6), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN7 : VitalBuf(tRASMIN_out(7), tRASMIN_in(7), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMAX : VitalBuf(tRASMAX_out(0), tRASMAX_in(0), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX1 : VitalBuf(tRASMAX_out(1), tRASMAX_in(1), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX2 : VitalBuf(tRASMAX_out(2), tRASMAX_in(2), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX3 : VitalBuf(tRASMAX_out(3), tRASMAX_in(3), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX4 : VitalBuf(tRASMAX_out(4), tRASMAX_in(4), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX5 : VitalBuf(tRASMAX_out(5), tRASMAX_in(5), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX6 : VitalBuf(tRASMAX_out(6), tRASMAX_in(6), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX7 : VitalBuf(tRASMAX_out(7), tRASMAX_in(7), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRTP : VitalBuf(tRTP_out(0), tRTP_in(0), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP1 : VitalBuf(tRTP_out(1), tRTP_in(1), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP2 : VitalBuf(tRTP_out(2), tRTP_in(2), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP3 : VitalBuf(tRTP_out(3), tRTP_in(3), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP4 : VitalBuf(tRTP_out(4), tRTP_in(4), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP5 : VitalBuf(tRTP_out(5), tRTP_in(5), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP6 : VitalBuf(tRTP_out(6), tRTP_in(6), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP7 : VitalBuf(tRTP_out(7), tRTP_in(7), (tdevice_tRTP - 1 ns, UnitDelay)); TWR : VitalBuf(tWR_out(0), tWR_in(0), (tdevice_tWR - 1 ns, UnitDelay)); TWR1 : VitalBuf(tWR_out(1), tWR_in(1), (tdevice_tWR - 1 ns, UnitDelay)); TWR2 : VitalBuf(tWR_out(2), tWR_in(2), (tdevice_tWR - 1 ns, UnitDelay)); TWR3 : VitalBuf(tWR_out(3), tWR_in(3), (tdevice_tWR - 1 ns, UnitDelay)); TWR4 : VitalBuf(tWR_out(4), tWR_in(4), (tdevice_tWR - 1 ns, UnitDelay)); TWR5 : VitalBuf(tWR_out(5), tWR_in(5), (tdevice_tWR - 1 ns, UnitDelay)); TWR6 : VitalBuf(tWR_out(6), tWR_in(6), (tdevice_tWR - 1 ns, UnitDelay)); TWR7 : VitalBuf(tWR_out(7), tWR_in(7), (tdevice_tWR - 1 ns, UnitDelay)); TWTR : VitalBuf(tWTR_out(0), tWTR_in(0), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR1 : VitalBuf(tWTR_out(1), tWTR_in(1), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR2 : VitalBuf(tWTR_out(2), tWTR_in(2), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR3 : VitalBuf(tWTR_out(3), tWTR_in(3), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR4 : VitalBuf(tWTR_out(4), tWTR_in(4), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR5 : VitalBuf(tWTR_out(5), tWTR_in(5), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR6 : VitalBuf(tWTR_out(6), tWTR_in(6), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR7 : VitalBuf(tWTR_out(7), tWTR_in(7), (tdevice_tWTR - 1 ns, UnitDelay)); TRP : VitalBuf(tRP_out(0), tRP_in(0), (tdevice_tRP - 1 ns, UnitDelay)); TRP1 : VitalBuf(tRP_out(1), tRP_in(1), (tdevice_tRP - 1 ns, UnitDelay)); TRP2 : VitalBuf(tRP_out(2), tRP_in(2), (tdevice_tRP - 1 ns, UnitDelay)); TRP3 : VitalBuf(tRP_out(3), tRP_in(3), (tdevice_tRP - 1 ns, UnitDelay)); TRP4 : VitalBuf(tRP_out(4), tRP_in(4), (tdevice_tRP - 1 ns, UnitDelay)); TRP5 : VitalBuf(tRP_out(5), tRP_in(5), (tdevice_tRP - 1 ns, UnitDelay)); TRP6 : VitalBuf(tRP_out(6), tRP_in(6), (tdevice_tRP - 1 ns, UnitDelay)); TRP7 : VitalBuf(tRP_out(7), tRP_in(7), (tdevice_tRP - 1 ns, UnitDelay)); TCKESR : VitalBuf(tCKESR_out(0), tCKESR_in(0), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR1 : VitalBuf(tCKESR_out(1), tCKESR_in(1), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR2 : VitalBuf(tCKESR_out(2), tCKESR_in(2), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR3 : VitalBuf(tCKESR_out(3), tCKESR_in(3), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR4 : VitalBuf(tCKESR_out(4), tCKESR_in(4), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR5 : VitalBuf(tCKESR_out(5), tCKESR_in(5), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR6 : VitalBuf(tCKESR_out(6), tCKESR_in(6), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR7 : VitalBuf(tCKESR_out(7), tCKESR_in(7), (tdevice_tCKESR - 1 ns, UnitDelay)); TRFCMIN : VitalBuf(tRFCMIN_out, tRFCMIN_in, (tdevice_tRFCMIN - 1 ns, UnitDelay)); TXS : VitalBuf(tXS_out, tXS_in, (tdevice_tRFCMIN + 9 ns, UnitDelay)); TREFPER : VitalBuf(tREFPer_out, tREFPer_in, (tdevice_tREFPer - 1 ns, UnitDelay)); TCKAVGMAX: VitalBuf(tCKAVGMAX_out, tCKAVGMAX_in, (tdevice_tCKAVGMAX - 1 ns, UnitDelay)); TMRD: VitalBuf(tMRD_out, tMRD_in, (tdevice_tMRD - 1 ns, UnitDelay)); TMOD: VitalBuf(tMOD_out, tMOD_in, (tdevice_tMOD - 1 ns, UnitDelay)); TXPR: VitalBuf(tXPR_out, tXPR_in, (tdevice_tXPR - 1 ns, UnitDelay)); TZQINIT: VitalBuf(tZQINIT_out, tZQINIT_in, (tdevice_tZQINIT - 1 ns, UnitDelay)); TZQOPER: VitalBuf(tZQOPER_out, tZQOPER_in, (tdevice_tZQOPER - 1 ns, UnitDelay)); TZQCS: VitalBuf(tZQCS_out, tZQCS_in, (tdevice_tZQCS - 1 ns, UnitDelay)); TCKSRX : VitalBuf(tCKSRX_out, tCKSRX_in, (tdevice_tCKSRX - 1 ns, UnitDelay)); TCKSRE : VitalBuf(tCKSRE_out, tCKSRE_in, (tdevice_tCKSRE - 1 ns, UnitDelay)); TWLODTEN : VitalBuf(tWLODTEN_out, tWLODTEN_in, (tdevice_tMOD -1 ns, UnitDelay)); TWLDQSEN : VitalBuf(tWLDQSEN_out, tWLDQSEN_in,(tdevice_tWLDQSEN - 1 ns, UnitDelay)); TWLMRD : VitalBuf(tWLMRD_out, tWLMRD_in, (tdevice_tWLMRD - 1 ns, UnitDelay)); TWLOMAX : VitalBuf(tWLOMAX_out, tWLOMAX_in, (tdevice_tWLOMAX - 1 ns, UnitDelay)); TWLOEMAX : VitalBuf(tWLOEMAX_out, tWLOEMAX_in, (tdevice_tWLOEMAX - 1 ns, UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (ODT_ipd, ODT, tipd_ODT); w_02 : VitalWireDelay (CK_ipd, CK, tipd_CK); w_03 : VitalWireDelay (CKNeg_ipd, CKNeg, tipd_CKNeg); w_04 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE); w_05 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg); w_06 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg); w_07 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg); w_08 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_09 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0); w_10 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1); w_11 : VitalWireDelay (BA2_ipd, BA2, tipd_BA2); w_12 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_13 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_14 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_15 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_18 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_19 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_20 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_21 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_22 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_23 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_24 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_25 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_26 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_27 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_28 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_29 : VitalWireDelay (DQS_ipd, DQS, tipd_DQS); w_30 : VitalWireDelay (DQSNeg_ipd, DQSNeg, tipd_DQSNeg); w_31 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_32 : VitalWireDelay (DM_ipd, DM, tipd_DM); END BLOCK; ODT_nwv <= To_UX01(ODT_ipd); CK_nwv <= To_UX01(CK_ipd); CKNeg_nwv <= To_UX01(CKNeg_ipd); CKE_nwv <= To_UX01(CKE_ipd); CSNeg_nwv <= To_UX01(CSNeg_ipd); RASNeg_nwv <= To_UX01(RASNeg_ipd); CASNeg_nwv <= To_UX01(CASNeg_ipd); WENeg_nwv <= To_UX01(WENeg_ipd); DM_nwv <= To_UX01(DM_ipd); BA0_nwv <= To_UX01(BA0_ipd); BA1_nwv <= To_UX01(BA1_ipd); BA2_nwv <= To_UX01(BA2_ipd); A0_nwv <= To_UX01(A0_ipd); A1_nwv <= To_UX01(A1_ipd); A2_nwv <= To_UX01(A2_ipd); A3_nwv <= To_UX01(A3_ipd); A4_nwv <= To_UX01(A4_ipd); A5_nwv <= To_UX01(A5_ipd); A6_nwv <= To_UX01(A6_ipd); A7_nwv <= To_UX01(A7_ipd); A8_nwv <= To_UX01(A8_ipd); A9_nwv <= To_UX01(A9_ipd); A10_nwv <= To_UX01(A10_ipd); A11_nwv <= To_UX01(A11_ipd); A12_nwv <= To_UX01(A12_ipd); DQ0_nwv <= To_UX01(DQ0_ipd); DQ1_nwv <= To_UX01(DQ1_ipd); DQ2_nwv <= To_UX01(DQ2_ipd); DQ3_nwv <= To_UX01(DQ3_ipd); DQS_nwv <= To_UX01(DQS_ipd); DQSNeg_nwv <= To_UX01(DQSNeg_ipd); RESETNeg_nwv <= To_UX01(RESETNeg_ipd); ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ODT : IN std_ulogic := 'U'; CK : IN std_ulogic := 'U'; CKNeg : IN std_ulogic := 'U'; CKE : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; CASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; DM : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; BAIn : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => 'U'); AIn : IN std_logic_vector(12 DOWNTO 0) := (OTHERS => 'U'); DQIn : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => 'U'); DQOut : OUT std_ulogic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); DQSIn : IN std_ulogic := 'U'; DQSOut : OUT std_ulogic := 'Z'; DQSNegIn : IN std_ulogic := 'U'; DQSNegOut : OUT std_ulogic := 'Z' ); PORT MAP ( ODT => ODT_nwv, CK => CK_nwv, CKNeg => CKNeg_nwv, CKE => CKE_nwv, CSNeg => CSNeg_nwv, RASNeg => RASNeg_nwv, CASNeg => CASNeg_nwv, WENeg => WENeg_nwv, DM => DM_nwv, BAIn(0) => BA0_nwv, BAIn(1) => BA1_nwv, BAIn(2) => BA2_nwv, AIn(0) => A0_nwv, AIn(1) => A1_nwv, AIn(2) => A2_nwv, AIn(3) => A3_nwv, AIn(4) => A4_nwv, AIn(5) => A5_nwv, AIn(6) => A6_nwv, AIn(7) => A7_nwv, AIn(8) => A8_nwv, AIn(9) => A9_nwv, AIn(10) => A10_nwv, AIn(11) => A11_nwv, AIn(12) => A12_nwv, DQIn(0) => DQ0_nwv, DQIn(1) => DQ1_nwv, DQIn(2) => DQ2_nwv, DQIn(3) => DQ3_nwv, DQOut(0) => DQ0, DQOut(1) => DQ1, DQOut(2) => DQ2, DQOut(3) => DQ3, RESETNeg => RESETNeg_nwv, DQSIn => DQS_nwv, DQSOut => DQS, DQSNegIn => DQSNeg_nwv, DQSNegOut => DQSNeg ); --zero delay signals SIGNAL DQOut_zd : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL DQSOut_zd : std_logic := 'Z'; SIGNAL DQSNegOut_zd : std_logic := 'Z'; SIGNAL DOut_Pass : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); --differential inputs SIGNAL CKDiff : std_logic := 'Z'; SIGNAL DQSDiff : std_logic := 'Z'; --DLL implementation SIGNAL CKPeriod : time := 3 ns; SIGNAL CKInt : std_ulogic := '0'; SIGNAL CKtemp : std_ulogic := '1'; SIGNAL CKHalfPer : time := 0 ns; SIGNAL CKDLLDelay: time := 0 ns; SIGNAL CK_stable : boolean := FALSE; SIGNAL PoweredUp : boolean := FALSE; SIGNAL In_d : boolean := FALSE; --delay before first MRS command tXPR SIGNAL In_d1 : boolean := FALSE; --mode register set comand cycle time --during initialization SIGNAL In_d2 : boolean := FALSE; -- delay during initial ZQ calibration SIGNAL In_d3 : boolean := FALSE; -- delay during reset ZQ calibration SIGNAL In_d4 : boolean := FALSE; -- delay during ZQ calibration SIGNAL Init_delay : boolean := FALSE;--command during initialization SIGNAL Init_delay1 : boolean := FALSE;--command during initialization SIGNAL Init_delay2 : boolean := FALSE;--command during initialization SIGNAL Init_delay3 : boolean := FALSE;--command during reset ZQ --calibration SIGNAL Init_delay4 : boolean := FALSE;--command during ZQ calibration SIGNAL Initialized : boolean := FALSE;--initialization completed SIGNAL DLL_delay : std_logic := '0'; --delay between DLL SIGNAL DLL_delay_elapsed : boolean := TRUE;--reset and read command SIGNAL In_data : std_ulogic := '0';--start of write operation SIGNAL preamble_gen : std_logic := 'Z';--preamble before read operation SIGNAL Out_data : std_logic := 'Z';--start of read operation SIGNAL fly_flag : std_logic := '0'; --Determine weather read or write -- command is BL4 or BL8 on the fly SIGNAL DQ_driven : boolean;-- DQ driven during Write Leveling procedure -- timing check violation SIGNAL Viol : X01 := '0'; SIGNAL CK_COUNT : natural := 0; --burst sequences TYPE sequence IS ARRAY (0 TO 7) OF integer RANGE -7 TO 7; TYPE seqtab IS ARRAY (0 TO 7) OF sequence; CONSTANT seq0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT seq1 : sequence := (0, 1, 2,-1, 4, 5, 6, 3); CONSTANT seq2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT seq3 : sequence := (0,-3,-2,-1, 4, 1, 2, 3); CONSTANT seq4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT seq5 : sequence := (0, 1, 2,-1,-4,-3,-2,-5); CONSTANT seq6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT seq7 : sequence := (0,-3,-2,-1,-4,-7,-6,-5); CONSTANT seq : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5, seq6, seq7); CONSTANT inl0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT inl1 : sequence := (0,-1, 2, 1, 4, 3, 6, 5); CONSTANT inl2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT inl3 : sequence := (0,-1,-2,-3, 4, 3, 2, 1); CONSTANT inl4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT inl5 : sequence := (0,-1, 2, 1,-4,-5,-2,-3); CONSTANT inl6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT inl7 : sequence := (0,-1,-2,-3,-4,-5,-6,-7); CONSTANT inl : seqtab := (inl0, inl1, inl2, inl3, inl4, inl5, inl6, inl7); --mode registers SHARED VARIABLE MR0 : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0'); SHARED VARIABLE MR1 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR2 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR3 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE F_KEY : integer; SHARED VARIABLE KEY : integer; SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active --commands during tFAW --bank, row and column of scheduled read or write operation SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE current_row : natural RANGE 0 TO RowNum; SHARED VARIABLE current_column : natural RANGE 0 TO ColNum; --bank, row and column of read operation that starts SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE read_row : natural RANGE 0 TO RowNum; SHARED VARIABLE read_column : natural RANGE 0 TO ColNum; -- WRITE LEVELING PROCEDURE SIGNAL WL_on : boolean := FALSE;--Write Leveling enabled SHARED VARIABLE ODTLOFF : boolean := FALSE; TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean; TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type; --all scheduled reads within all banks SHARED VARIABLE read_sch : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); --reads that should be preceeded by preamble SHARED VARIABLE preamble : write_sch_bank_type := (OTHERS => (OTHERS => TRUE)); TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic; TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type; --wait_read triggers process that counts remaining cycles to the --beggining of scheduled read when aditive latency has elapsed, and --read_delay keeps information of number of remaining cycles SIGNAL wait_read : wait_read_bank_type; SHARED VARIABLE read_delay : natural RANGE 0 TO 10; --needed for check if all rows were refreshed during refresh period SIGNAL Ref_per_start : std_ulogic := '0'; SIGNAL Ref_per_expired : std_ulogic := '0'; SHARED VARIABLE CK_rise : time := 0 ns; SHARED VARIABLE CK_period : time := 0 ns; TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating, active, reading, readingAP, writting, writtingAP, precharging, prechall,ZQ_calib); TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type; SHARED VARIABLE Curr_bank_state : Bank_state_array_type; SHARED VARIABLE Next_bank_state : Bank_state_array_type; SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered SIGNAL SelfRefresh : boolean := FALSE;--self refresh active --Partial self refresh active SIGNAL PartialSelfRefresh : boolean := FALSE; SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be --turned off SIGNAL Pre_PD : boolean := FALSE;--precharge power down active SIGNAL Act_PD : boolean := FALSE;--active power down active SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress, SIGNAL ReadStart : boolean := FALSE; --no pd entry SIGNAL Reset : boolean := FALSE;--reset function active SIGNAL RST : std_logic := '1'; SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be --turned off SIGNAL SimulationEnd : boolean := FALSE; SHARED VARIABLE mrs_cnt : natural; SIGNAL mrs_active : std_logic := '0'; SIGNAL preamble_check : boolean := FALSE; SIGNAL postamble_check : boolean := FALSE; FUNCTION bool_to_nat(tm : boolean) RETURN natural IS VARIABLE Temp : natural; BEGIN Temp := 0; IF tm THEN Temp := 1; END IF; RETURN Temp; END bool_to_nat; -- part of code for dynamic alocation SHARED VARIABLE Corrupt_Sec: std_logic_vector(BankNum downto 0):=--??? (OTHERS => '0'); --memory definition TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData; TYPE MemBlock IS ARRAY (0 TO BankNum) OF MemStore; -- ---------------------------------------------------------------------- -- Data types required to implement link list structure -- ---------------------------------------------------------------------- TYPE mem_data_t; TYPE mem_data_pointer_t IS ACCESS mem_data_t; TYPE mem_data_t IS RECORD key_address : INTEGER; val_data : INTEGER; successor : mem_data_pointer_t; END RECORD; -- ---------------------------------------------------------------------- -- Array of linked lists. -- Support memory region partitioning for faster access. -- ---------------------------------------------------------------------- TYPE mem_data_pointer_array_t IS ARRAY(NATURAL RANGE <>) OF mem_data_pointer_t; ------------------------------------------------------------------------- -- Handle dynamic memory allocation ------------------------------------------------------------------------- -- Partition dynamically allocated space for performance CONSTANT list_num : INTEGER := 7; CONSTANT list_size : INTEGER := 16#FFFFFF#; -- Access dynamically allocated space SHARED VARIABLE linked_list : mem_data_pointer_array_t(0 TO list_num); SHARED VARIABLE list_id_v : NATURAL; -- ------------------------------------------------------------------------- -- Create linked listed -- ------------------------------------------------------------------------- PROCEDURE create_list( key_address : IN INTEGER; val_data : IN INTEGER; root : INOUT mem_data_pointer_t) IS BEGIN root := NEW mem_data_t; root.successor := NULL; root.key_address := key_address; root.val_data := val_data; END PROCEDURE create_list; -- ------------------------------------------------------------------------- -- Iterate through linked listed comapring key values -- Stop when key value greater or equal -- ------------------------------------------------------------------------- PROCEDURE position_list( key_address : IN INTEGER; root : INOUT mem_data_pointer_t; found : INOUT mem_data_pointer_t; prev : INOUT mem_data_pointer_t) IS BEGIN found := root; prev := NULL; WHILE ((found /= NULL) AND (found.key_address < key_address)) LOOP prev := found; found := found.successor; END LOOP; END PROCEDURE position_list; -- ------------------------------------------------------------------------- -- Add new element to a linked list -- ------------------------------------------------------------------------- PROCEDURE insert_list( key_address : IN INTEGER; val_data : IN INTEGER; root : INOUT mem_data_pointer_t) IS VARIABLE new_element : mem_data_pointer_t; VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; BEGIN position_list(key_address, root, found, prev); -- Insert at list tail IF (found = NULL) THEN prev.successor := NEW mem_data_t; prev.successor.key_address := key_address; prev.successor.val_data := val_data; prev.successor.successor := NULL; ELSE -- Element exists, update memory data value IF (found.key_address = key_address) THEN found.val_data := val_data; ELSE -- No element found, allocate and link new_element := NEW mem_data_t; new_element.key_address := key_address; new_element.val_data := val_data; new_element.successor := found; -- Possible root position IF (prev /= NULL) THEN prev.successor := new_element; ELSE root := new_element; END IF; END IF; END IF; END PROCEDURE insert_list; -- ------------------------------------------------------------------------- -- Remove element from a linked list -- ------------------------------------------------------------------------- PROCEDURE remove_list( key_address : IN INTEGER; root : INOUT mem_data_pointer_t) IS VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; BEGIN position_list(key_address, root, found, prev); IF (found /= NULL) THEN -- Key value match IF (found.key_address = key_address) THEN -- Handle root position removal IF (prev /= NULL) THEN prev.successor := found.successor; ELSE root := found.successor; END IF; DEALLOCATE(found); END IF; END IF; END PROCEDURE remove_list; -- ------------------------------------------------------------------------- -- Remove range of elements from a linked list -- Higher performance than one-by-one removal -- ------------------------------------------------------------------------- PROCEDURE remove_list_range( address_low : IN INTEGER; address_high : IN INTEGER; root : INOUT mem_data_pointer_t) IS VARIABLE iter : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; VARIABLE link_element : mem_data_pointer_t; BEGIN iter := root; prev := NULL; -- Find first linked list element belonging to -- a specified address range [address_low, address_high] WHILE ((iter /= NULL) AND NOT ( (iter.key_address >= address_low) AND (iter.key_address <= address_high))) LOOP prev := iter; iter := iter.successor; END LOOP; -- Continue until address_high reached -- Deallocate linked list elements pointed by iterator IF (iter /= NULL) THEN WHILE ((iter /= NULL) AND (iter.key_address >= address_low) AND (iter.key_address <= address_high)) LOOP link_element := iter.successor; DEALLOCATE(iter); iter := link_element; END LOOP; -- Handle possible root value change IF prev /= NULL THEN prev.successor := link_element; ELSE root := link_element; END IF; END IF; END PROCEDURE remove_list_range; -- ------------------------------------------------------------------------- -- Create side linked list modelling corrupted memory area -- ------------------------------------------------------------------------- PROCEDURE create_list_range( address_low : IN INTEGER; address_high : IN INTEGER; root : INOUT mem_data_pointer_t; last : INOUT mem_data_pointer_t) IS VARIABLE new_element : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; BEGIN create_list(address_low, -1, root); prev := root; -- Linked list representing memory region : -- [address_low, address_high], memory data value corrupted -- Heightens corrupt and erase operation performance FOR I IN (address_low + 1) TO address_high LOOP new_element := NEW mem_data_t; new_element.key_address := I; new_element.val_data := -1; prev.successor := new_element; prev := new_element; END LOOP; prev.successor := NULL; last := prev; END PROCEDURE create_list_range; -- ------------------------------------------------------------------------- -- Merge corrupted with memory area -- ------------------------------------------------------------------------- PROCEDURE insert_list_range( root_dst : INOUT mem_data_pointer_t; root_src : INOUT mem_data_pointer_t; root_src_last : INOUT mem_data_pointer_t) IS VARIABLE key : INTEGER; VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; BEGIN IF (root_dst /= NULL) THEN key := root_src.key_address; -- Insert side created corrupted memory region -- into corresponding linked list position_list(key, root_dst, found, prev); IF (found = NULL) THEN prev.successor := root_src; ELSE root_src_last.successor := found; IF (prev /= NULL) THEN prev.successor := root_src; ELSE root_dst := root_src; END IF; END IF; ELSE root_dst := root_src; END IF; END PROCEDURE insert_list_range; -- ------------------------------------------------------------------------- -- Address range to be corrupted -- ------------------------------------------------------------------------- PROCEDURE corrupt_mem( address_low : IN INTEGER; address_high : IN INTEGER; linked_list : INOUT mem_data_pointer_t) IS VARIABLE sub_linked_list : mem_data_pointer_t; VARIABLE sub_linked_list_last : mem_data_pointer_t; BEGIN sub_linked_list := NULL; sub_linked_list_last := NULL; IF (linked_list /= NULL) THEN remove_list_range( address_low, address_high, linked_list ); END IF; create_list_range( address_low, address_high, sub_linked_list, sub_linked_list_last ); insert_list_range( linked_list, sub_linked_list, sub_linked_list_last ); END PROCEDURE corrupt_mem; -- ------------------------------------------------------------------------- -- Address range to be erased -- ------------------------------------------------------------------------- PROCEDURE erase_mem( address_low : IN INTEGER; address_high : IN INTEGER; linked_list : INOUT mem_data_pointer_t) IS BEGIN remove_list_range( address_low, address_high, linked_list ); END PROCEDURE erase_mem; -- ------------------------------------------------------------------------- -- Memory READ operation performed above dynamically allocated space -- ------------------------------------------------------------------------- PROCEDURE read_mem( linked_list : INOUT mem_data_pointer_t; data : INOUT INTEGER; address : IN INTEGER) IS VARIABLE found : mem_data_pointer_t; VARIABLE prev : mem_data_pointer_t; VARIABLE mem_data : INTEGER; BEGIN IF (linked_list = NULL) THEN -- Not allocated, not written, initial value mem_data := -1; -- if memory is not allocated then read -1 ELSE position_list(address, linked_list, found, prev); IF (found /= NULL) THEN IF found.key_address = address THEN -- Allocated, val_data stored mem_data := found.val_data; ELSE -- Not allocated, not written, initial value mem_data := MaxData ; END IF; ELSE -- Not allocated, not written, initial value mem_data := MaxData ; END IF; END IF; data := mem_data; END PROCEDURE read_mem; -- ------------------------------------------------------------------------- -- Memory WRITE operation performed above dynamically allocated space -- ------------------------------------------------------------------------- PROCEDURE write_mem( linked_list : INOUT mem_data_pointer_t; address : IN INTEGER; data : IN INTEGER) IS BEGIN IF (data /= MaxData ) THEN -- Handle possible root value update IF (linked_list /= NULL) THEN insert_list(address, data, linked_list); ELSE create_list(address, data, linked_list); END IF; ELSE -- Deallocate if initial value written -- No linked list, NOP, initial value implicit IF (linked_list /= NULL) THEN remove_list(address, linked_list); END IF; END IF; END PROCEDURE write_mem; -- Asure proper initialization PROCEDURE initialize IS VARIABLE I : INTEGER; BEGIN FOR I IN 0 TO list_num LOOP linked_list(I) := NULL; END LOOP; END PROCEDURE initialize; -- Memory region parition map, DUT specific FUNCTION list_id( list_address : IN INTEGER) RETURN NATURAL IS BEGIN RETURN (list_address / list_size); END FUNCTION list_id; PROCEDURE WRITE_DATA( BankAddr : IN NATURAL RANGE 0 TO BankNum; Address : IN NATURAL RANGE 0 TO MemSize; Datay : IN INTEGER) IS VARIABLE WData : INTEGER; BEGIN IF(Corrupt_Sec(BankAddr) = '1' AND Datay = MaxData) THEN WData := MaxData + 1; ELSE WData := Datay; END IF; write_mem(linked_list(BankAddr), Address, WData); END PROCEDURE WRITE_DATA; PROCEDURE READ_DATA( BankAddr : IN NATURAL RANGE 0 TO BankNum; Address : IN NATURAL RANGE 0 TO MemSize; Datax : INOUT INTEGER) IS BEGIN read_mem(linked_list(BankAddr), Datax, Address); IF (Corrupt_Sec(BankAddr) = '1') THEN IF (Datax = MaxData) THEN Datax := -1; ELSIF (Datax = MaxData + 1) THEN Datax := MaxData; END IF; END IF; END PROCEDURE READ_DATA; BEGIN RST <= RESETNeg AFTER 100 ns; CK_DLL: PROCESS(CKDiff) VARIABLE Previous : time := 0 ns; VARIABLE TmpPer : time := 0 ns; BEGIN IF rising_edge(CKDiff) THEN TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN CKPeriod <= TmpPer; END IF; Previous := NOW; CKHalfPer <= CKPeriod / 2; CKDLLDelay <= CKPeriod + tpd_CK_DQ1; END IF; END PROCESS CK_DLL; CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL BEGIN CKtemp <= NOT CKtemp AFTER CKHalfPer; END PROCESS CK_temp; CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay; Clock_init: PROCESS(CK) BEGIN IF rising_edge(CK) AND NOT PoweredUp THEN CK_COUNT <= CK_COUNT + 1; END IF; END PROCESS Clock_init; Power_up: PROCESS(CK_stable,CK_COUNT) BEGIN IF CK_stable AND (CK_COUNT >= 5) AND NOT PoweredUp THEN PoweredUp <= TRUE; END IF; END PROCESS Power_up; Init_d: PROCESS(In_d) BEGIN IF In_d THEN Init_delay <= TRUE AFTER tdevice_tXPR; ELSE Init_delay <= FALSE; END IF; END PROCESS Init_d; Init_d1: PROCESS(In_d1) BEGIN IF In_d1 THEN Init_delay1 <= TRUE AFTER tdevice_tMRD; ELSE Init_delay1 <= FALSE; END IF; END PROCESS Init_d1; Init_d2: PROCESS(In_d2) BEGIN IF In_d2 THEN Init_delay2 <= TRUE AFTER tdevice_tZQINIT; ELSE Init_delay2 <= FALSE; END IF; END PROCESS Init_d2; Init_d3: PROCESS(In_d3) BEGIN IF In_d3 THEN Init_delay3 <= TRUE AFTER tdevice_tZQOPER; ELSE Init_delay3 <= FALSE; END IF; END PROCESS Init_d3; Init_d4: PROCESS(In_d4) BEGIN IF In_d4 THEN Init_delay4 <= TRUE AFTER tdevice_tZQCS; ELSE Init_delay4 <= FALSE; END IF; END PROCESS Init_d4; PROCESS (tMOD_in_tmp) BEGIN IF rising_edge(tMOD_in_tmp) THEN tMOD_out_tmp <= '0', '1' AFTER tdevice_tMOD; END IF; END PROCESS; DLLdelay: PROCESS(DLL_delay, CKDiff) VARIABLE cnt : natural; BEGIN IF rising_edge(DLL_delay) THEN cnt := 0; DLL_delay_elapsed <= FALSE; ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN cnt := cnt + 1; IF cnt = 511 THEN DLL_delay_elapsed <= TRUE; END IF; END IF; END PROCESS DLLdelay; ---------------------------------------------------------------------------- -- Vital Behavior Process ---------------------------------------------------------------------------- VITALBehaviour: PROCESS(CKDiff, DQSDiff, DQSIn, DQIn, DM, ODT, CKE, CSNeg, RASNeg, CASNeg, WENeg, BAIn, AIn, RESETNeg) -- Timing Check Variables VARIABLE Tviol_DQ0_DQS : X01 := '0'; VARIABLE TD_DQ0_DQS : VitalTimingDataType; VARIABLE Tviol_DQ0_DQS1 : X01 := '0'; VARIABLE TD_DQ0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS : X01 := '0'; VARIABLE TD_DQ1_DQS : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS1 : X01 := '0'; VARIABLE TD_DQ1_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM0_DQS : X01 := '0'; VARIABLE TD_DM0_DQS : VitalTimingDataType; VARIABLE Tviol_DM0_DQS1 : X01 := '0'; VARIABLE TD_DM0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM1_DQS : X01 := '0'; VARIABLE TD_DM1_DQS : VitalTimingDataType; VARIABLE Tviol_DM1_DQS1 : X01 := '0'; VARIABLE TD_DM1_DQS1 : VitalTimingDataType; VARIABLE Tviol_ODT_CK : X01 := '0'; VARIABLE TD_ODT_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK : X01 := '0'; VARIABLE TD_CKE_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK_RESET : X01 := '0'; VARIABLE TD_CKE_CK_RESET : VitalTimingDataType; VARIABLE Tviol_CSNeg_CK : X01 := '0'; VARIABLE TD_CSNeg_CK : VitalTimingDataType; VARIABLE Tviol_RASNeg_CK : X01 := '0'; VARIABLE TD_RASNeg_CK : VitalTimingDataType; VARIABLE Tviol_CASNeg_CK : X01 := '0'; VARIABLE TD_CASNeg_CK : VitalTimingDataType; VARIABLE Tviol_WENeg_CK : X01 := '0'; VARIABLE TD_WENeg_CK : VitalTimingDataType; VARIABLE Tviol_BA0_CK : X01 := '0'; VARIABLE TD_BA0_CK : VitalTimingDataType; VARIABLE Tviol_A0_CK : X01 := '0'; VARIABLE TD_A0_CK : VitalTimingDataType; VARIABLE Tviol_DQS_CK5 : X01 := '0'; VARIABLE TD_DQS_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS_CK6 : X01 := '0'; VARIABLE TD_DQS_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS_CK7 : X01 := '0'; VARIABLE TD_DQS_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS_CK8 : X01 := '0'; VARIABLE TD_DQS_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS_CK9 : X01 := '0'; VARIABLE TD_DQS_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS_CK10 : X01 := '0'; VARIABLE TD_DQS_CK10 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK5 : X01 := '0'; VARIABLE TD_DQS1_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK6 : X01 := '0'; VARIABLE TD_DQS1_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK7 : X01 := '0'; VARIABLE TD_DQS1_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK8 : X01 := '0'; VARIABLE TD_DQS1_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK9 : X01 := '0'; VARIABLE TD_DQS1_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK10 : X01 := '0'; VARIABLE TD_DQS1_CK10 : VitalTimingDataType; VARIABLE Tviol_CKE_RESETNeg : X01 := '0'; VARIABLE TD_CKE_RESETNeg : VitalTimingDataType; VARIABLE Tviol_CK_DQSDiff : X01 := '0'; VARIABLE TD_CK_DQSDiff : VitalTimingDataType; VARIABLE Tviol_CK_DQSIn : X01 := '0'; VARIABLE TD_CK_DQSIn : VitalTimingDataType; VARIABLE Pviol_A05 : X01 := '0'; VARIABLE PD_A05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A06 : X01 := '0'; VARIABLE PD_A06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A07 : X01 := '0'; VARIABLE PD_A07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A08 : X01 := '0'; VARIABLE PD_A08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A09 : X01 := '0'; VARIABLE PD_A09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A010 : X01 := '0'; VARIABLE PD_A010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT5 : X01 := '0'; VARIABLE PD_ODT5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT6 : X01 := '0'; VARIABLE PD_ODT6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT7 : X01 := '0'; VARIABLE PD_ODT7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT8 : X01 := '0'; VARIABLE PD_ODT8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT9 : X01 := '0'; VARIABLE PD_ODT9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT10 : X01 := '0'; VARIABLE PD_ODT10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg5 : X01 := '0'; VARIABLE PD_CSNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg6 : X01 := '0'; VARIABLE PD_CSNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg7 : X01 := '0'; VARIABLE PD_CSNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg8 : X01 := '0'; VARIABLE PD_CSNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg9 : X01 := '0'; VARIABLE PD_CSNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg10 : X01 := '0'; VARIABLE PD_CSNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg5 : X01 := '0'; VARIABLE PD_RASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg6 : X01 := '0'; VARIABLE PD_RASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg7 : X01 := '0'; VARIABLE PD_RASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg8 : X01 := '0'; VARIABLE PD_RASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg9 : X01 := '0'; VARIABLE PD_RASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg10 : X01 := '0'; VARIABLE PD_RASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg5 : X01 := '0'; VARIABLE PD_CASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg6 : X01 := '0'; VARIABLE PD_CASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg7 : X01 := '0'; VARIABLE PD_CASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg8 : X01 := '0'; VARIABLE PD_CASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg9 : X01 := '0'; VARIABLE PD_CASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg10 : X01 := '0'; VARIABLE PD_CASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg5 : X01 := '0'; VARIABLE PD_WENeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg6 : X01 := '0'; VARIABLE PD_WENeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg7 : X01 := '0'; VARIABLE PD_WENeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg8 : X01 := '0'; VARIABLE PD_WENeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg9 : X01 := '0'; VARIABLE PD_WENeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg10 : X01 := '0'; VARIABLE PD_WENeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ05 : X01 := '0'; VARIABLE PD_DQ05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ06 : X01 := '0'; VARIABLE PD_DQ06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ07 : X01 := '0'; VARIABLE PD_DQ07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ08 : X01 := '0'; VARIABLE PD_DQ08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ09 : X01 := '0'; VARIABLE PD_DQ09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ010 : X01 := '0'; VARIABLE PD_DQ010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM5 : X01 := '0'; VARIABLE PD_DM5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM6 : X01 := '0'; VARIABLE PD_DM6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM7 : X01 := '0'; VARIABLE PD_DM7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM8 : X01 := '0'; VARIABLE PD_DM8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM9 : X01 := '0'; VARIABLE PD_DM9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM10 : X01 := '0'; VARIABLE PD_DM10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS15 : X01 := '0'; VARIABLE PD_DQS15 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS16 : X01 := '0'; VARIABLE PD_DQS16 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS17 : X01 := '0'; VARIABLE PD_DQS17 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS18 : X01 := '0'; VARIABLE PD_DQS18 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS19 : X01 := '0'; VARIABLE PD_DQS19 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS110 : X01 := '0'; VARIABLE PD_DQS110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS115 : X01 := '0'; VARIABLE PD_DQS115 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS116 : X01 := '0'; VARIABLE PD_DQS116 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS117 : X01 := '0'; VARIABLE PD_DQS117 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS118 : X01 := '0'; VARIABLE PD_DQS118 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS119 : X01 := '0'; VARIABLE PD_DQS119 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS1110 : X01 := '0'; VARIABLE PD_DQS1110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS35 : X01 := '0'; VARIABLE PD_DQS35 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS36 : X01 := '0'; VARIABLE PD_DQS36 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS37 : X01 := '0'; VARIABLE PD_DQS37 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS38 : X01 := '0'; VARIABLE PD_DQS38 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS39 : X01 := '0'; VARIABLE PD_DQS39 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS310 : X01 := '0'; VARIABLE PD_DQS310 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS315 : X01 := '0'; VARIABLE PD_DQS315 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS316 : X01 := '0'; VARIABLE PD_DQS316 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS317 : X01 := '0'; VARIABLE PD_DQS317 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS318 : X01 := '0'; VARIABLE PD_DQS318 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS319 : X01 := '0'; VARIABLE PD_DQS319 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS3110 : X01 := '0'; VARIABLE PD_DQS3110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CKE : X01 := '0'; VARIABLE PD_CKE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg_PoweredUp : X01 := '0'; VARIABLE PD_RESETNeg_PoweredUp : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK5 : X01 := '0'; VARIABLE PD_CK5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK6 : X01 := '0'; VARIABLE PD_CK6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK7 : X01 := '0'; VARIABLE PD_CK7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK8 : X01 := '0'; VARIABLE PD_CK8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK9 : X01 := '0'; VARIABLE PD_CK9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK10 : X01 := '0'; VARIABLE PD_CK10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS, Violation => Tviol_DQ0_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS1, Violation => Tviol_DQ0_DQS1 ); -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS, Violation => Tviol_DQ1_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS1, Violation => Tviol_DQ1_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS, Violation => Tviol_DM0_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS1, Violation => Tviol_DM0_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS, Violation => Tviol_DM1_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS1, Violation => Tviol_DM1_DQS1 ); -- Setup/Hold Check between ODT and CKDiff VitalSetupHoldCheck ( TestSignal => ODT, TestSignalName => "ODT", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ODT_CK, Violation => Tviol_ODT_CK ); -- Setup/Hold Check between CKE and CKDiff VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK, Violation => Tviol_CKE_CK ); -- Setup/Hold Check between CKE and CK VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CK, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => Reset_enter_cycle AND CK_COUNT = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK_RESET, Violation => Tviol_CKE_CK_RESET ); -- Setup/Hold Check between CSNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_CK, Violation => Tviol_CSNeg_CK ); -- Setup/Hold Check between RASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CK, Violation => Tviol_RASNeg_CK ); -- Setup/Hold Check between CASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_CK, Violation => Tviol_CASNeg_CK ); -- Setup/Hold Check between WENeg and CKDiff VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CK, Violation => Tviol_WENeg_CK ); -- Setup/Hold Check between BAIn and CKDiff VitalSetupHoldCheck ( TestSignal => BAIn, TestSignalName => "BAIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BA0_CK, Violation => Tviol_BA0_CK ); -- Setup/Hold Check between AIn and CKDiff VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CK, Violation => Tviol_A0_CK ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK5, Violation => Tviol_DQS_CK5 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK6, Violation => Tviol_DQS_CK6 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK7, Violation => Tviol_DQS_CK7 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK8, Violation => Tviol_DQS_CK8 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK9, Violation => Tviol_DQS_CK9 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK10, Violation => Tviol_DQS_CK10 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK5, Violation => Tviol_DQS1_CK5 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK6, Violation => Tviol_DQS1_CK6 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK7, Violation => Tviol_DQS1_CK7 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK8, Violation => Tviol_DQS1_CK8 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK9, Violation => Tviol_DQS1_CK9 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK10, Violation => Tviol_DQS1_CK10 ); -- Setup Check between CKE and RESETNeg VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKEIn", RefSignal => RESETNeg, RefSignalName => "RESETNeg", SetupLow => tsetup_CKE_RESETNeg, HoldLow => thold_CKE_RESETNeg, CheckEnabled => Reset_enter_cycle, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_RESETNeg, Violation => Tviol_CKE_RESETNeg ); -- Setup Check between CK and DQSIn VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSIn, Violation => Tviol_CK_DQSIn ); -- Setup Check between CK and DQSDiff VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSDiff, Violation => Tviol_CK_DQSDiff ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_A05, Violation => Pviol_A05 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_A06, Violation => Pviol_A06 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_A07, Violation => Pviol_A07 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_A08, Violation => Pviol_A08 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_A09, Violation => Pviol_A09 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_A010, Violation => Pviol_A010 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT5, Violation => Pviol_ODT5 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT6, Violation => Pviol_ODT6 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT7, Violation => Pviol_ODT7 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT8, Violation => Pviol_ODT8 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT9, Violation => Pviol_ODT9 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT10, Violation => Pviol_ODT10 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg5, Violation => Pviol_CSNeg5 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg6, Violation => Pviol_CSNeg6 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg7, Violation => Pviol_CSNeg7 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg8, Violation => Pviol_CSNeg8 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg9, Violation => Pviol_CSNeg9 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg10, Violation => Pviol_CSNeg10 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg5, Violation => Pviol_RASNeg5 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg6, Violation => Pviol_RASNeg6 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg7, Violation => Pviol_RASNeg7 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg8, Violation => Pviol_RASNeg8 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg9, Violation => Pviol_RASNeg9 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg10, Violation => Pviol_RASNeg10 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg5, Violation => Pviol_CASNeg5 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg6, Violation => Pviol_CASNeg6 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg7, Violation => Pviol_CASNeg7 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg8, Violation => Pviol_CASNeg8 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg9, Violation => Pviol_CASNeg9 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg10, Violation => Pviol_CASNeg10 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg5, Violation => Pviol_WENeg5 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg6, Violation => Pviol_WENeg6 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg7, Violation => Pviol_WENeg7 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg8, Violation => Pviol_WENeg8 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg9, Violation => Pviol_WENeg9 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg10, Violation => Pviol_WENeg10 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ05, Violation => Pviol_DQ05 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ06, Violation => Pviol_DQ06 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ07, Violation => Pviol_DQ07 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ08, Violation => Pviol_DQ08 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ09, Violation => Pviol_DQ09 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ010, Violation => Pviol_DQ010 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM5, Violation => Pviol_DM5 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM6, Violation => Pviol_DM6 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM7, Violation => Pviol_DM7 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM8, Violation => Pviol_DM8 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM9, Violation => Pviol_DM9 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM10, Violation => Pviol_DM10 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS15, Violation => Pviol_DQS15 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS16, Violation => Pviol_DQS16 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS17, Violation => Pviol_DQS17 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS18, Violation => Pviol_DQS18 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS19, Violation => Pviol_DQS19 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS110, Violation => Pviol_DQS110 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS115, Violation => Pviol_DQS115 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS116, Violation => Pviol_DQS116 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS117, Violation => Pviol_DQS117 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS118, Violation => Pviol_DQS118 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS119, Violation => Pviol_DQS119 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS1110, Violation => Pviol_DQS1110 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS35, Violation => Pviol_DQS35 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS36, Violation => Pviol_DQS36 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS37, Violation => Pviol_DQS37 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS38, Violation => Pviol_DQS38 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS39, Violation => Pviol_DQS39 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS310, Violation => Pviol_DQS310 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS315, Violation => Pviol_DQS315 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS316, Violation => Pviol_DQS316 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS317, Violation => Pviol_DQS317 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS318, Violation => Pviol_DQS318 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS319, Violation => Pviol_DQS319 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS3110, Violation => Pviol_DQS3110 ); -- PulseWidth Check for CKE VitalPeriodPulseCheck ( TestSignal => CKE, TestSignalName => "CKE", PulseWidthLow => tpw_CKE_SelfRefresh_negedge, CheckEnabled => SelfRefresh, HeaderMsg => InstancePath & PartID, PeriodData => PD_CKE, Violation => Pviol_CKE ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_0_negedge, CheckEnabled => NOT PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg_PoweredUp, Violation => Pviol_RESETNeg_PoweredUp ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_1_negedge, CheckEnabled => PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL5, PulseWidthLow => tpw_CK_CL5_negedge, PulseWidthHigh => tpw_CK_CL5_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK5, Violation => Pviol_CK5 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL6, PulseWidthLow => tpw_CK_CL6_negedge, PulseWidthHigh => tpw_CK_CL6_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK6, Violation => Pviol_CK6 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL7, PulseWidthLow => tpw_CK_CL7_negedge, PulseWidthHigh => tpw_CK_CL7_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK7, Violation => Pviol_CK7 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL8, PulseWidthLow => tpw_CK_CL8_negedge, PulseWidthHigh => tpw_CK_CL8_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK8, Violation => Pviol_CK8 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL9, PulseWidthLow => tpw_CK_CL9_negedge, PulseWidthHigh => tpw_CK_CL9_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK9, Violation => Pviol_CK9 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL10, PulseWidthLow => tpw_CK_CL10_negedge, PulseWidthHigh => tpw_CK_CL10_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK10, Violation => Pviol_CK10 ); Violation := Tviol_DQ0_DQS OR Tviol_DQ0_DQS1 OR Tviol_DQ1_DQS OR Tviol_DQ1_DQS1 OR Tviol_DM0_DQS OR Tviol_DM0_DQS1 OR Tviol_DM1_DQS OR Tviol_DM1_DQS1 OR Tviol_ODT_CK OR Tviol_CKE_CK OR Tviol_CKE_CK_RESET OR Tviol_CSNeg_CK OR Tviol_RASNeg_CK OR Tviol_CASNeg_CK OR Tviol_WENeg_CK OR Tviol_BA0_CK OR Tviol_A0_CK OR Tviol_DQS_CK5 OR Tviol_DQS_CK6 OR Tviol_DQS_CK7 OR Tviol_DQS_CK8 OR Tviol_DQS_CK9 OR Tviol_DQS_CK10 OR Tviol_DQS1_CK5 OR Tviol_DQS1_CK6 OR Tviol_DQS1_CK7 OR Tviol_DQS1_CK8 OR Tviol_DQS1_CK9 OR Tviol_DQS1_CK10 OR Tviol_CKE_RESETNeg OR Tviol_CK_DQSIn OR Tviol_CK_DQSDiff OR Pviol_A05 OR Pviol_A06 OR Pviol_A07 OR Pviol_A08 OR Pviol_A09 OR Pviol_A010 OR Pviol_ODT5 OR Pviol_ODT6 OR Pviol_ODT7 OR Pviol_ODT8 OR Pviol_ODT9 OR Pviol_ODT10 OR Pviol_CSNeg5 OR Pviol_CSNeg6 OR Pviol_CSNeg7 OR Pviol_CSNeg8 OR Pviol_CSNeg9 OR Pviol_CSNeg10 OR Pviol_RASNeg5 OR Pviol_RASNeg6 OR Pviol_RASNeg7 OR Pviol_RASNeg8 OR Pviol_RASNeg9 OR Pviol_RASNeg10 OR Pviol_CASNeg5 OR Pviol_CASNeg6 OR Pviol_CASNeg7 OR Pviol_CASNeg8 OR Pviol_CASNeg9 OR Pviol_CASNeg10 OR Pviol_WENeg5 OR Pviol_WENeg6 OR Pviol_WENeg7 OR Pviol_WENeg8 OR Pviol_WENeg9 OR Pviol_WENeg10 OR Pviol_DQ05 OR Pviol_DQ06 OR Pviol_DQ07 OR Pviol_DQ08 OR Pviol_DQ09 OR Pviol_DQ010 OR Pviol_DM5 OR Pviol_DM6 OR Pviol_DM7 OR Pviol_DM8 OR Pviol_DM9 OR Pviol_DM10 OR Pviol_DQS15 OR Pviol_DQS16 OR Pviol_DQS17 OR Pviol_DQS18 OR Pviol_DQS19 OR Pviol_DQS110 OR Pviol_DQS115 OR Pviol_DQS116 OR Pviol_DQS117 OR Pviol_DQS118 OR Pviol_DQS119 OR Pviol_DQS1110 OR Pviol_DQS35 OR Pviol_DQS36 OR Pviol_DQS37 OR Pviol_DQS38 OR Pviol_DQS39 OR Pviol_DQS310 OR Pviol_DQS315 OR Pviol_DQS316 OR Pviol_DQS317 OR Pviol_DQS318 OR Pviol_DQS319 OR Pviol_DQS3110 OR Pviol_CKE OR Pviol_RESETNeg_PoweredUp OR Pviol_RESETNeg OR Pviol_CK5 OR Pviol_CK6 OR Pviol_CK7 OR Pviol_CK8 OR Pviol_CK9 OR Pviol_CK10; Viol <= Violation; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY warning; END IF; END PROCESS VITALBehaviour; DiffRecCK: PROCESS(CK, CKNeg) VARIABLE CKDiff_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 1); VARIABLE CK_GlitchData : VitalGlitchDataType; BEGIN VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (CK, CKNeg), Result => CKDiff_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CKDiff, OutSignalName => "CKDiff", OutTemp => CKDiff_zd, GlitchData => CK_GlitchData, Paths => ( 0 => (InputChangeTime => CK'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS DiffRecCK; DiffRecDQS: PROCESS(DQSIn, DQSNegIn) VARIABLE DQSDiff_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 TO 1); VARIABLE DQS_GlitchData : VitalGlitchDataType; BEGIN VitalStateTable ( StateTable => Diff_rec_tab, DataIn => (DQSIn, DQSNegIn), Result => DQSDiff_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => DQSDiff, OutSignalName => "DQSDiff", OutTemp => DQSDiff_zd, GlitchData => DQS_GlitchData, Paths => ( 0 => (InputChangeTime => DQSIn'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS DiffRecDQS; Functionality: PROCESS(CKDiff, CKE, tRFCMIN_out, ODT, tXS_out, SimulationEnd, SelfRefresh, SR_exit,tCKESR_out, tREFPer_out,Init_delay2, Init_delay3,AIn,tMRD_out, tWLDQSEN_out,tWLODTEN_out,RESETNeg,RST,tRC_out,tRRD_out) VARIABLE TimModTemp : string(1 TO 20) := (OTHERS => 'X');--extended TM --latencies of scheduled read and write operations TYPE Lat_type IS ARRAY (0 TO 10) OF natural RANGE 0 TO 10; TYPE Lat_bank_type IS ARRAY (0 TO BankNum) OF Lat_type; VARIABLE AL : Lat_bank_type; VARIABLE CL : Lat_bank_type; VARIABLE WL : Lat_bank_type; VARIABLE AL_tmp : natural; VARIABLE CL_tmp : natural; VARIABLE WL_tmp : natural; VARIABLE RL_tmp : natural; VARIABLE rd_pd_cnt : natural; VARIABLE prechall_viol : boolean;--command other than NOP or DESL issued --tRPA after precharge all VARIABLE idle : boolean;--all banks idle state TYPE row_type IS ARRAY (0 TO BankNum) OF integer RANGE 0 TO RowNum; VARIABLE active_row : row_type;--activated rows --starting columns of scheduled read or write operations TYPE col_type IS ARRAY (0 TO 10) OF natural RANGE 0 TO ColNum; TYPE col_bank_type IS ARRAY (0 TO BankNum) OF col_type; VARIABLE start_column : col_bank_type; --needed when multiple reads or writes scheduled in same bank VARIABLE free_slot : natural RANGE 0 TO 10; --all scheduled writes within all banks VARIABLE write_sch : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); --elapsed aditive latencies of scheduled reads VARIABLE AL_elapsed : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); TYPE last_write_type IS ARRAY (0 TO BankNum) OF boolean; --needed for verification of durations measured since end of write burst VARIABLE last_write : last_write_type := (OTHERS => FALSE); --programmed write latency elapsed since end of write burst VARIABLE WR_elapsed : last_write_type := (OTHERS => TRUE); --2 cycles elapsed since end of write burst VARIABLE WTR_elapsed : last_write_type := (OTHERS => TRUE); --AL + BL/2 elapsed since read command VARIABLE RTP_elapsed : last_write_type := (OTHERS => TRUE); TYPE precharge_cnt_type IS ARRAY (0 TO BankNum) OF natural; -- self refresh array VARIABLE sf_array : natural; --cycles elapsed since read or write command before precharge command VARIABLE precharge_cnt : precharge_cnt_type; --cycles elapsed since write command before end of write burst VARIABLE wr_rd_cnt : precharge_cnt_type; --cycles elapsed since read command before bank returns to active state VARIABLE rd_act_cnt : precharge_cnt_type; --cycles elapsed since read command before write command --rd_wr_cnt is RL+tCCD/2+2tCK-WL for BL=4 or -- RL+tCCD+2tCK-WL for BL=8 cycles VARIABLE rd_wr_cnt : natural; --elapsed since read command VARIABLE RTW_elapsed : boolean := TRUE; --cycles elapsed since write command before another write command VARIABLE wr_wr_cnt : natural; --cycles elapsed since read command before another read command VARIABLE rd_rd_cnt : natural; VARIABLE WR : natural RANGE 0 TO 12; VARIABLE read_permit : boolean;--read command accepted VARIABLE write_permit : boolean;--write command accepted TYPE command_type is ( ILL, MRS, REF, PRE, ACT, WRIT, READ, NOP, DESL, ZQCL, ZQCS ); VARIABLE Command : Command_type; -- states during initialization TYPE State_type IS (illegal, init0, init1, init2, init3, init4, init5, init6); VARIABLE Current_state : State_type := init0; VARIABLE Next_state : State_type := init0; VARIABLE defined_logic_levels : boolean := TRUE; VARIABLE CK_cnt : natural;--between commands during initialization VARIABLE power_down_cond : boolean;--pd can be entered VARIABLE active_pd_cond : boolean;--active pd can be entered VARIABLE PD_exit_cnt : natural := 1;--cycles since CKE went high VARIABLE PD_read_delay : boolean := FALSE;--tXP OR tXPDLL elapsed VARIABLE PD_read_del_cnt : natural := 1;--cycles of tXSRD VARIABLE ODT_off : boolean;--ODT turned off when precharge pd entered VARIABLE WL_on_en : boolean := FALSE; VARIABLE freq_change : boolean := FALSE;--frequency has changed during --precharge pd VARIABLE freq_ch_cnt : natural;--cycles before frequency can change VARIABLE DLL_reset_needed : boolean := FALSE;--DLL must be reset prior --to read command VARIABLE ZQINIT : boolean := TRUE; -- For ZQ calibration after power-up -- If FALSE ZQ calibration after reset --needed for CKE pulse width check VARIABLE CKEcnt : natural RANGE 0 TO 3 := 3; VARIABLE CKErise : boolean := FALSE; VARIABLE CKEfall : boolean := TRUE; FUNCTION find_free(sch : write_sch_type) RETURN natural IS VARIABLE Temp : natural; BEGIN Temp := 0; WHILE sch(Temp) LOOP Temp := Temp + 1; END LOOP; RETURN Temp; END find_free; PROCEDURE CheckRead IS VARIABLE WTR_viol : boolean; VARIABLE rd_rd_viol : boolean; VARIABLE rd_DLL_viol : boolean; VARIABLE rd_PD_viol : boolean; VARIABLE rd_lock_viol : boolean; BEGIN read_permit := TRUE; WTR_viol := FALSE; rd_rd_viol := FALSE; rd_DLL_viol := FALSE; rd_PD_viol := FALSE; rd_lock_viol := FALSE; FOR J IN 0 TO BankNum LOOP IF NOT WTR_elapsed(J) OR tWTR_out(J) = '0' THEN WTR_viol := TRUE; read_permit := FALSE; END IF; END LOOP; IF rd_rd_cnt >= 1 and rd_rd_cnt < 4 THEN rd_rd_viol := TRUE; read_permit := FALSE; END IF; IF NOT DLL_delay_elapsed THEN rd_DLL_viol := TRUE; read_permit := FALSE; END IF; IF PD_read_delay THEN rd_PD_viol := TRUE; read_permit := FALSE; END IF; IF DLL_reset_needed THEN rd_lock_viol := TRUE; read_permit := FALSE; END IF; ASSERT NOT WTR_viol REPORT "tWTR has not elapsed since the end of last write burst" SEVERITY warning; ASSERT NOT rd_rd_viol REPORT "4 cycles must elapse between consecutive READ commands" SEVERITY warning; ASSERT NOT rd_DLL_viol REPORT "512 cycles must elapse between DLL reset and READ " & "command" SEVERITY warning; ASSERT NOT rd_PD_viol REPORT "tXPDLL has not elapsed since slow-exit power-down exit" SEVERITY warning; ASSERT NOT rd_lock_viol REPORT "DLL must be reset prior to read command" SEVERITY warning; END CheckRead; PROCEDURE CheckWrite IS VARIABLE RTW_viol : boolean; VARIABLE wr_wr_viol : boolean; BEGIN write_permit := TRUE; RTW_viol := FALSE; wr_wr_viol := FALSE; IF NOT RTW_elapsed THEN RTW_viol := TRUE; write_permit := FALSE; END IF; IF wr_wr_cnt < 4 THEN wr_wr_viol := TRUE; write_permit := FALSE; END IF; ASSERT NOT RTW_viol REPORT "RL+tCCD/2+2tCK-WL for BL=4 or" & "RL+tCCD+2tCK-WL for BL=8" & "cycles must elapse " & "between READ and WRITE commands" SEVERITY warning; ASSERT NOT wr_wr_viol REPORT "4 cycles must elapse between " & "consecutive WRITE commands" SEVERITY warning; END CheckWrite; BEGIN IF rising_edge(CKDiff) THEN IF CK_rise /= 0 ns THEN CK_stable <= TRUE; IF CK_stable THEN IF NOW - CK_rise /= CK_period THEN IF (Pre_PD AND ODT_off AND freq_ch_cnt = 0) OR SelfRefresh THEN freq_change := TRUE; ELSE ASSERT SR_enter_cycle OR Reset_enter_cycle REPORT "Input clock frequency is not stable" SEVERITY warning; END IF; END IF; SimulationEnd <= FALSE AFTER 1 ns, TRUE AFTER 2*CK_period; ASSERT CK_period <= tdevice_tCKAVGMAX OR SR_enter_cycle OR Reset_enter_cycle REPORT "Input clock period exceeds tCKAVG(max)" SEVERITY warning; END IF; END IF; CK_period := NOW - CK_rise; CK_rise := NOW; defined_logic_levels := TRUE; IF (CKE /= '0' AND CKE /= '1') OR (RASNeg /= '0' AND RASNeg /= '1') OR (CASNeg /= '0' AND CASNeg /= '1') OR (WENeg /= '0' AND WENeg /= '1') THEN defined_logic_levels := FALSE; END IF; FOR I IN 0 TO 2 LOOP IF BAIn(I) /= '0' AND BAIn(I) /= '1' THEN defined_logic_levels := FALSE; END IF; END LOOP; FOR I IN 0 TO 12 LOOP IF AIn(I) /= '0' AND AIn(I) /= '1' THEN defined_logic_levels := FALSE; END IF; END LOOP; Command := ILL; IF defined_logic_levels THEN IF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '0' AND WENeg = '0' THEN Command := MRS; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '0' AND WENeg = '1' THEN Command := REF; ELSIF CSNeg = '1' THEN Command := DESL; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '1' THEN Command := NOP; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '1' AND WENeg = '0' THEN Command := PRE; ELSIF CSNeg = '0' AND RASNeg = '0' AND CASNeg = '1' AND WENeg = '1' THEN Command := ACT; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '0' AND WENeg = '0' THEN Command := WRIT; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '0' AND WENeg = '1' THEN Command := READ; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '0' AND AIn(10) = '1' THEN Command := ZQCL; ELSIF CSNeg = '0' AND RASNeg = '1' AND CASNeg = '1' AND WENeg = '0' AND AIn(10) = '0' THEN Command := ZQCS; END IF; END IF; CASE Current_state IS WHEN init0 => IF CKE = '1' THEN IF PoweredUp AND (Command = NOP OR Command = DESL) THEN Next_state := init1; In_d <= TRUE; ASSERT ((CK_period >= tperiod_CK_CL5 AND to_nat(MR0(6 DOWNTO 4)) = 1) OR (CK_period >= tperiod_CK_CL6 AND to_nat(MR0(6 DOWNTO 4)) = 2) OR (CK_period >= tperiod_CK_CL7 AND to_nat(MR0(6 DOWNTO 4)) = 3) OR (CK_period >= tperiod_CK_CL8 AND to_nat(MR0(6 DOWNTO 4)) = 4) OR (CK_period >= tperiod_CK_CL9 AND to_nat(MR0(6 DOWNTO 4)) = 5) OR (CK_period >= tperiod_CK_CL10 AND to_nat(MR0(6 DOWNTO 4)) = 6) OR to_nat(MR0(6 DOWNTO 4)) = 0 OR to_nat(MR0(6 DOWNTO 4)) = 7) AND CK_period <= tdevice_tCKAVGMAX REPORT "Clock must be stable before CKE is " & "raised high" SEVERITY warning; ELSE ASSERT FALSE REPORT "Invalid start of initialization" SEVERITY warning; Next_state := illegal; END IF; END IF; --ok WHEN init1 => IF Init_delay AND Command = MRS THEN Next_state := init2; In_d <= FALSE; In_d1 <= TRUE; MR2(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR2(15 DOWNTO 13) := BAIn; ELSIF (NOT Init_delay) AND Command /= NOP AND Command /= DESL THEN ASSERT FALSE REPORT "Only NOP Command are valid during tXPR" SEVERITY warning; END IF; WHEN init2 => IF Init_delay1 AND Command = MRS THEN Next_state := init3; In_d <= FALSE; In_d1 <= TRUE; MR3(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR3(15 DOWNTO 13) := BAIn; END IF; WHEN init3 => IF Init_delay1 AND Command = MRS THEN Next_state := init4; In_d <= FALSE; In_d1 <= TRUE; MR1(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR1(15 DOWNTO 13) := BAIn; END IF; WHEN init4 => IF Init_delay1 AND Command = MRS THEN Next_state := init5; In_d <= FALSE; In_d1 <= TRUE; DLL_delay <= '1', '0' AFTER 1 ns; MR0(12 DOWNTO 0) := AIn(12 DOWNTO 0); MR0(15 DOWNTO 13) := BAIn; END IF; WHEN init5 => IF Init_delay1 AND (Command = ZQCS OR Command = ZQCL) THEN In_d <= FALSE; In_d1 <= FALSE; IF Command = ZQCL AND ZQINIT THEN In_d2 <= TRUE; Next_state := init6; ELSIF Command = ZQCL AND NOT ZQINIT THEN In_d3 <= TRUE; Next_state := init6; END IF; DQOut_zd <= (OTHERS => 'Z'); ODT_off := TRUE; END IF; WHEN init6 => IF (Init_delay2 OR Init_delay3) AND (Command = NOP OR Command = DESL) THEN Initialized <= TRUE; In_d2 <= FALSE; In_d3 <= FALSE; ZQINIT := FALSE; ELSIF (NOT Initialized) AND (Command /= NOP AND Command /= DESL) THEN ASSERT FALSE REPORT "Illegal command during tZQINIT" SEVERITY warning; END IF; WHEN illegal => Next_state := init0; END CASE; Current_state := Next_state; IF Initialized THEN idle := TRUE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) /= precharged THEN idle := FALSE; END IF; END LOOP; IF Command = REF AND CKE = '0' AND NOT idle THEN ASSERT FALSE REPORT "The SELF REFRESH command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; IF CKE = '1' AND NOT (SelfRefresh OR Pre_PD OR Act_PD OR Reset) THEN IF Command = MRS THEN IF idle THEN mrs_active <= '0', '1' AFTER 1 ns; tMOD_in_tmp <= '1' , '0' AFTER 1 ns; FOR I IN 0 TO BankNum LOOP Next_bank_state(I) := MRsetting; END LOOP; IF to_nat(BAIn) = 0 THEN MR0(12 DOWNTO 0) := AIn(12 DOWNTO 0); IF MR0(8) = '1' THEN DLL_delay <= '1', '0' AFTER 1 ns; ODT_off := FALSE; freq_change := FALSE; DLL_reset_needed := FALSE; END IF; ASSERT (to_nat(MR0(11 DOWNTO 9)) /= 0 AND to_nat(MR0(11 DOWNTO 9)) <= 6) AND (to_nat(MR0(6 DOWNTO 4)) >= 1 AND to_nat(MR0(6 DOWNTO 4)) /= 7) AND (to_nat(MR0(1 DOWNTO 0)) >= 0 AND to_nat(MR0(1 DOWNTO 0)) < 3) REPORT "Invalid value programmed to " & "mode register" SEVERITY warning; TimModTemp(1 TO TimingModel'LENGTH) := TimingModel; IF ((TimModTemp(13 to 14) = "DG" AND to_nat(MR0(6 downto 4)) = 6) OR (TimModTemp(13 to 14) = "DJ" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 3 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AC" AND (to_nat(MR0(6 DOWNTO 4)) = 5 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AE" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 5 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "AG" AND (to_nat(MR0(6 DOWNTO 4)) = 1 OR to_nat(MR0(6 DOWNTO 4)) = 3 OR to_nat(MR0(6 DOWNTO 4)) = 4 OR to_nat(MR0(6 DOWNTO 4)) = 6)) OR (TimModTemp(13 to 14) = "8A" AND (to_nat(MR0(6 DOWNTO 4)) >= 3 AND to_nat(MR0(6 DOWNTO 4)) <= 6)) OR (TimModTemp(13 to 14) = "8C" AND to_nat(MR0(6 DOWNTO 4)) /= 2) ) THEN ASSERT FALSE REPORT "Programmed CL value is not " & "supported in this speed grade" SEVERITY warning; END IF; ASSERT MR0(7) = '0' REPORT "Mode should be set to normal, " & "not test" SEVERITY warning; ELSIF to_nat(BAIn) = 1 THEN MR1(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR1(9) & MR1(6) & MR1(2)) <= 5 AND to_nat(MR1(4 DOWNTO 3)) <= 2 AND to_nat(MR1(10)) = 0 AND to_nat(MR1(8)) = 0 AND to_nat(MR1(5)) = 0 REPORT "Invalid value programmed to " & "extended mode register" SEVERITY warning; ASSERT MR1(0) = '0' REPORT "DLL must be enabled for normal " & "operation" SEVERITY warning; ELSIF to_nat(BAIn) = 2 THEN MR2(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR2(5 DOWNTO 3)) <= 3 AND to_nat(MR2(10 DOWNTO 9)) <= 2 AND to_nat(MR2(8))= 0 AND to_nat(MR2(12 DOWNTO 11)) = 0 REPORT "Invalid value programmed to " & "extended mode register 2" SEVERITY warning; ELSE MR3(12 DOWNTO 0) := AIn(12 DOWNTO 0); ASSERT to_nat(MR3(1 DOWNTO 0)) = 0 AND to_nat(MR3(12 DOWNTO 4)) = 0 REPORT "Invalid value programmed to " & "extended mode register 3" SEVERITY warning; ASSERT MR3(2) = '0' REPORT "MPR must be set for normal " & "operation" SEVERITY warning; END IF; ELSE ASSERT FALSE REPORT "The MRS command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; END IF; IF (mrs_cnt < 4 AND tMOD_out_tmp = '0' AND (Command /= NOP AND Command /= DESL)) THEN ASSERT FALSE REPORT "Only NOP or DESELECT commands are valid " & "during tMRD after MRS command" SEVERITY warning; END IF; IF (mrs_cnt = 4 AND tMOD_out_tmp = '0' AND (Command /= NOP AND Command /= DESL AND Command /= MRS)) THEN ASSERT FALSE REPORT "Command are issued during during tMOD " & "after MRS " SEVERITY warning; END IF; IF Command = REF THEN IF idle THEN FOR I IN 0 TO BankNum LOOP Next_bank_state(I) := refreshing; END LOOP; tRFCMIN_in <= '0', '1' AFTER 1 ns; tREFPer_in <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "The REFRESH command can only be " & "issued when all banks are idle" SEVERITY warning; END IF; END IF; ASSERT Curr_bank_state(0) /= refreshing OR Command = NOP OR Command = DESL REPORT "Only NOP or DESELECT commands are valid during " & "tRFC(min) after REFRESH command" SEVERITY warning; prechall_viol := FALSE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = prechall AND Command /= NOP AND Command /= DESL THEN prechall_viol := TRUE; END IF; END LOOP; ASSERT NOT prechall_viol REPORT "Only NOP or DESELECT commands are valid during " & "tRPA after PRECHARGE ALL command" SEVERITY warning; ASSERT Command /= PRE OR AIn(10) /= '1' OR tRASMIN_out = "11111111" REPORT "tRAS(min) has not elapsed since activation of the" & " last activated bank" SEVERITY warning; FOR I IN 0 TO BankNum LOOP CASE Curr_bank_state(I) IS WHEN precharged => IF Command = ACT AND to_nat(BAIn) = I AND tMOD_out_tmp = '1' THEN IF NOT active_forbid THEN IF tRRD_out = '1' THEN IF tRC_out(I) = '1' THEN Next_bank_state(I) := activating; active_row(I) := to_nat(AIn); tRCD_in(I) <= '0', '1' AFTER 1 ns; tRASMIN_in(I) <= '0', '1' AFTER 1 ns; tRASMAX_in(I) <= '1'; tRRD_in <= '0', '1' AFTER 1 ns; tRC_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSE ASSERT FALSE REPORT "tRRD has not elapsed " & "since activation of the " & "last activated bank" SEVERITY warning; END IF; END IF; ELSIF Command = ZQCS AND tMOD_out_tmp = '1' THEN Next_bank_state(I) := ZQ_calib; ELSIF (Command = READ OR Command = WRIT) AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command when idle" SEVERITY warning; END IF; WHEN MRsetting => Next_bank_state(I) := precharged; WHEN ZQ_calib => In_d4 <= TRUE; DQOut_zd <= (OTHERS => 'Z'); ODT_off := TRUE; IF Init_delay4 THEN Next_bank_state(I) := precharged; In_d4 <= FALSE; END IF; WHEN precharging => ASSERT Command = NOP OR Command = DESL OR to_nat(BAIn) /= I REPORT "Illegal command during precharging" SEVERITY warning; WHEN prechall => ASSERT Command = NOP OR Command = DESL REPORT "Illegal command during precharging" SEVERITY warning; IF tRP_out(I) = '1' THEN Next_bank_state(I) := precharged; END IF; WHEN active => IF Command = PRE AND AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "tRAS(min) has not elapsed " & "since activation of the bank" SEVERITY warning; END IF; ELSIF Command = PRE AND AIn(10) = '1' THEN IF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(0) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; write_sch(I)(0) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(0) := TRUE; AL_elapsed(I)(0) := FALSE; RTP_elapsed(I) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; rd_wr_cnt := 0; precharge_cnt(I) := 0; rd_act_cnt(I) := 0; rd_pd_cnt := 0; -- tCCD is required between two read --operations (4 tCK) IF rd_rd_cnt >= 3 THEN preamble(I)(0) := TRUE; ELSE preamble(I)(0) := FALSE; END IF; rd_rd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; END IF; ASSERT Command /= ACT OR to_nat(BAIn) /= I REPORT "Previous active row in same bank has " & "not been closed (precharged)" SEVERITY warning; WHEN activating => ASSERT Command = NOP OR Command = DESL OR to_nat(BAIn) /= I REPORT "During activating the bank " & "only valid commands are " & "NOP and DESELECT" SEVERITY warning; WHEN writting => IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF last_write(I) THEN precharge_cnt(I) := precharge_cnt(I) + 1; wr_rd_cnt(I) := wr_rd_cnt(I) + 1; IF to_nat(MR0(11 DOWNTO 9)) <= 3 THEN WR := to_nat(MR0(11 DOWNTO 9))+ 4; ELSE WR := 2*to_nat(MR0(11 DOWNTO 9)); END IF; IF precharge_cnt(I) = burst_len/2 + WL(I)(0) - 1 THEN -- PAGE 94 tWR_in(I) <= '0', '1' AFTER 1 ns; ELSIF precharge_cnt(I) = burst_len/2 + WL(I)(0) + WR THEN WR_elapsed(I) := TRUE; END IF; IF wr_rd_cnt(I)= WL(I)(0) + burst_len/2 THEN tWTR_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; FOR J IN 0 TO 10 LOOP IF write_sch(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSIF WL(I)(J) > 5 THEN WL(I)(J) := WL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); IF burst_len = 4 THEN In_data <= '0', '1' AFTER (2*burst_len+3)*CK_period/4; ELSE In_data <= '0', '1' AFTER (burst_len+1)*CK_period/4 - 1 ns; END IF; write_sch(I)(J) := FALSE; last_write(I) := TRUE; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; WR_elapsed(I) := FALSE; WTR_elapsed(I) := FALSE; END IF; END IF; END LOOP; IF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; last_write(I) := FALSE; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; WR_elapsed(I) := FALSE; WTR_elapsed(I) := FALSE; free_slot := find_free(write_sch(I)); start_column(I)(free_slot):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); CL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(free_slot) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(free_slot) := 0; END IF; write_sch(I)(free_slot) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN start_column(I)(0):=to_nat(AIn(11) & AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(0) := TRUE; AL_elapsed(I)(0) := FALSE; RTP_elapsed(I) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; rd_wr_cnt := 0; precharge_cnt(I) := 0; rd_act_cnt(I) := 0; preamble(I)(0) := TRUE; rd_rd_cnt := 0; rd_pd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF WR_elapsed(I) THEN IF tWR_out(I) = '1' THEN IF Command = PRE AND AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = PRE AND AIn(10) = '1' THEN IF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSE Next_bank_state(I) := active; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE during WRITE" SEVERITY warning; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE during WRITE" SEVERITY warning; END IF; IF wr_rd_cnt(I) = 3 THEN WTR_elapsed(I) := TRUE; END IF; IF Command = ACT AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command ACT during WRITE" SEVERITY warning; END IF; WHEN writtingAP => IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF last_write(I) THEN wr_rd_cnt(I) := wr_rd_cnt(I) + 1; precharge_cnt(I) := precharge_cnt(I) + 1; IF to_nat(MR0(11 DOWNTO 9)) <= 3 THEN WR := to_nat(MR0(11 DOWNTO 9))+ 4; ELSE WR := 2*to_nat(MR0(11 DOWNTO 9)); END IF; IF precharge_cnt(I) = burst_len/2 + WL(I)(0) - 1 THEN --page 94 tWR_in(I) <= '0', '1' AFTER 1 ns; ELSIF precharge_cnt(I) = burst_len/2 + WL(I)(0) + WR THEN WR_elapsed(I) := TRUE; END IF; --page 95 IF wr_rd_cnt(I) = WL(I)(0)+ burst_len/2 THEN tWTR_in(I) <= '0', '1' AFTER 1 ns; ELSIF wr_rd_cnt(I) = WL(I)(0)+ burst_len/2 + 3 THEN WTR_elapsed(I) := TRUE; END IF; END IF; FOR J IN 0 TO 10 LOOP IF write_sch(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSIF WL(I)(J) > 5 THEN WL(I)(J) := WL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); IF burst_len = 4 THEN In_data <= '0', '1' AFTER (2*burst_len+3)*CK_period/4; ELSE In_data <= '0', '1' AFTER (burst_len+1)*CK_period/4 -1 ns; END IF; write_sch(I)(J) := FALSE; last_write(I) := TRUE; precharge_cnt(I) := 0; WR_elapsed(I) := FALSE; END IF; END IF; END LOOP; IF ((Command = ACT OR Command = READ OR Command = WRIT) AND to_nat(BAIn) = I) OR (Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1')) THEN ASSERT FALSE REPORT "Illegal command after WRITE AP" SEVERITY warning; END IF; IF WR_elapsed(I) THEN IF tWR_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; WHEN reading => precharge_cnt(I) := precharge_cnt(I) + 1; rd_act_cnt(I) := rd_act_cnt(I) + 1; IF (MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1')) THEN burst_len := 8; ELSE burst_len := 4; END IF; IF precharge_cnt(I) = 4 THEN -- tRTRP tRTP_in(I) <= '0', '1' AFTER 1 ns; ELSIF tRTP_out(I) = '1' THEN RTP_elapsed(I) := TRUE; END IF; FOR J IN 0 TO 10 LOOP IF read_sch(I)(J) AND NOT AL_elapsed(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); read_delay := CL(I)(J); IF read_delay = 3 THEN IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; END IF; wait_read(I)(J) <= '0', '1' AFTER 1 ns; AL_elapsed(I)(J) := TRUE; END IF; END IF; END LOOP; IF Command = READ AND to_nat(BAIn) = I THEN CheckRead; IF read_permit THEN precharge_cnt(I) := 0; rd_wr_cnt := 0; rd_act_cnt(I) := 0; RTP_elapsed(I) := FALSE; RTW_elapsed := FALSE; free_slot := find_free(read_sch(I)); start_column(I)(free_slot) := to_nat(AIn(11)& AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(free_slot) := 0; END IF; CL(I)(free_slot) := to_nat(MR0(6 DOWNTO 4))+4; read_sch(I)(free_slot) := TRUE; AL_elapsed(I)(free_slot) := FALSE; tRTP_in(I) <= '0'; RTW_elapsed := FALSE; IF rd_rd_cnt >= 3 THEN preamble(I)(free_slot) := TRUE; ELSE preamble(I)(free_slot) := FALSE; END IF; rd_rd_cnt := 0; rd_pd_cnt := 0; IF MR1(4 DOWNTO 3) = "00" AND MR0(1 DOWNTO 0) = "10" THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; END IF; IF AIn(10) = '0' THEN Next_bank_state(I) := reading; fly_flag <= AIn(12); ELSE Next_bank_state(I) := readingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF Command = WRIT AND to_nat(BAIn) = I THEN CheckWrite; IF write_permit THEN wr_wr_cnt := 0; start_column(I)(0) := to_nat(AIn(9 DOWNTO 0)); IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL(I)(0) := 0; END IF; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL(I)(0) := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; CL(I)(0) := to_nat(MR0(6 DOWNTO 4))+4; write_sch(I)(0) := TRUE; WR_elapsed(I) := FALSE; tWR_in(I) <= '0'; WTR_elapsed(I) := FALSE; tWTR_in(I) <= '0'; precharge_cnt(I) := 0; wr_rd_cnt(I) := 0; IF AIn(10) = '0' THEN Next_bank_state(I) := writting; fly_flag <= AIn(12); ELSE Next_bank_state(I) := writtingAP; fly_flag <= AIn(12); END IF; END IF; ELSIF RTP_elapsed(I) AND tRTP_out(I) = '1' AND Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN IF AIn(10) = '0' AND to_nat(BAIn) = I THEN IF tRASMIN_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; ELSE ASSERT FALSE REPORT "tRAS(min) has not " & "elapsed since " & "activation of the bank" SEVERITY warning; END IF; ELSIF tRASMIN_out = "11111111" THEN Next_bank_state(I) := prechall; tRASMAX_in <= (OTHERS => '0'); tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; ELSIF Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1') THEN ASSERT FALSE REPORT "Illegal command PRE while reading" SEVERITY warning; END IF; IF Command = ACT AND to_nat(BAIn) = I THEN ASSERT FALSE REPORT "Illegal command ACT after READ" SEVERITY warning; END IF; WHEN readingAP => precharge_cnt(I) := precharge_cnt(I) + 1; IF MR0(1 DOWNTO 0) = "00" OR (MR0(1 DOWNTO 0) = "01" AND fly_flag = '1') THEN burst_len := 8; ELSE burst_len := 4; END IF; IF precharge_cnt(I) = to_nat(MR0(6 DOWNTO 4))+ 4 - to_nat(MR1(4 DOWNTO 3)) + burst_len/2 THEN tRTP_in(I) <= '0', '1' AFTER 1 ns; ELSIF tRTP_out(I) = '1' THEN RTP_elapsed(I) := TRUE; END IF; FOR J IN 0 TO 10 LOOP IF read_sch(I)(J) AND NOT AL_elapsed(I)(J) THEN IF AL(I)(J) > 0 THEN AL(I)(J) := AL(I)(J) - 1; ELSE current_bank := I; current_row := active_row(I); current_column := start_column(I)(J); read_delay := CL(I)(J); IF read_delay = 3 THEN IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; END IF; wait_read(I)(J) <= '0', '1' AFTER 1 ns; AL_elapsed(I)(J) := TRUE; END IF; END IF; END LOOP; IF ((Command = ACT OR Command = READ OR Command = WRIT) AND to_nat(BAIn) = I) OR (Command = PRE AND (to_nat(BAIn) = I OR AIn(10) = '1')) THEN ASSERT FALSE REPORT "Illegal command after READ AP" SEVERITY warning; END IF; IF RTP_elapsed(I) AND tRTP_out(I) = '1' THEN Next_bank_state(I) := precharging; tRASMAX_in(I) <= '0'; tRP_in(I) <= '0', '1' AFTER 1 ns; END IF; WHEN OTHERS => END CASE; Curr_bank_state(I) := Next_bank_state(I); END LOOP; IF rd_rd_cnt < 4 THEN --tCCD rd_rd_cnt := rd_rd_cnt + 1; END IF; IF wr_wr_cnt < 4 THEN --tCCD wr_wr_cnt := wr_wr_cnt + 1; END IF; IF to_nat(MR1(4 DOWNTO 3)) /= 0 THEN AL_tmp := to_nat(MR0(6 DOWNTO 4))+4 - to_nat(MR1(4 DOWNTO 3)); ELSE AL_tmp := 0; END IF; IF to_nat(MR2(5 DOWNTO 3)) <= 3 THEN WL_tmp := to_nat(MR2(5 DOWNTO 3))+ 5; END IF; CL_tmp := to_nat(MR0(6 DOWNTO 4))+4; IF rd_wr_cnt = CL_tmp+AL_tmp-WL_tmp+2+burst_len/8 THEN RTW_elapsed := TRUE; END IF; IF rd_wr_cnt < CL_tmp+AL_tmp-WL_tmp+2+burst_len/8 THEN rd_wr_cnt := rd_wr_cnt + 1; END IF; -- WRITE LEVELING PROCEDURE IF idle AND Command = MRS AND ((MR1(7) = '1' AND MR1(12) = '1') OR (MR1(7) = '1' AND MR1(12) = '0' AND to_nat(MR1(9) & MR1(6)& MR1(2)) <= 3)) THEN tWLODTEN_in <= '0', '1' AFTER 1 ns; tWLDQSEN_in <= '0', '1' AFTER 1 ns; tWLMRD_in <= '0', '1' AFTER 1 ns; END IF; IF tWLODTEN_out = '1' AND ODT = '1' THEN ODT_off := FALSE; END IF; IF tWLDQSEN_out = '1' AND ODT = '1' THEN WL_on <= TRUE; END IF; IF MR1(7) = '0' THEN WL_on <= FALSE; -- END OF WRITE LEVELING PROCEDURE END IF; END IF; IF (tWLDQSEN_in = '1' AND tWLDQSEN_out = '0' AND DQS = '0') THEN ASSERT FALSE REPORT "DQS should not be asserted during tWLDQSEN" SEVERITY warning; END IF; IF (tWLMRD_in = '1' AND tWLMRD_out = '0' AND DQS = '1') THEN ASSERT FALSE REPORT "DQS should not be deasserted during tWLMRD" SEVERITY warning; END IF; IF CKE = '0' AND NOT CKEfall THEN CKEfall := TRUE; CKErise := FALSE; ASSERT CKEcnt = 3 REPORT "CKE has not been high for tCKE(min)" SEVERITY warning; CKEcnt := 0; END IF; IF CKE = '1' AND NOT CKErise THEN CKErise := TRUE; CKEfall := FALSE; ASSERT CKEcnt = 3 REPORT "CKE has not been low for tCKE(min)" SEVERITY warning; CKEcnt := 0; END IF; IF CKEcnt < 3 THEN CKEcnt := CKEcnt + 1; END IF; IF CKE = '0' AND idle AND Command = REF AND NOT SelfRefresh AND (ODT = '0' OR (MR1(6) = '0' AND MR1(2) = '0' AND MR1(9) = '0')) AND NOT Act_PD AND NOT Pre_PD AND NOT Reset AND NOT WL_on AND tMOD_out_tmp = '1' THEN SR_cond := TRUE; SelfRefresh <= TRUE; IF MR2(2 DOWNTO 0) /= "000" THEN PartialSelfRefresh <= TRUE; END IF; SR_exit <= FALSE; END IF; IF CKE = '0' AND idle AND Command = REF AND tMOD_out_tmp = '0' THEN ASSERT FALSE REPORT "SELF REFRESH command is issued during tMOD" SEVERITY warning; END IF; IF SelfRefresh AND NOT SR_exit AND NOT SR_enter_cycle AND CKE = '0' THEN SR_enter_cycle := TRUE; IF to_nat(MR2(2 DOWNTO 0)) < 4 THEN sf_array := 2**(3 - to_nat(MR2(2 DOWNTO 0)))-1; FOR J IN 0 TO sf_array LOOP tCKESR_in(J) <= '0', '1' AFTER 1 ns; FOR K IN sf_array TO BankNum LOOP IF to_nat(MR2(2 DOWNTO 0)) /= 0 THEN erase_mem(0, MemSize, linked_list(K)); END IF; END LOOP; END LOOP; ELSIF to_nat(MR2(2 DOWNTO 0)) >= 4 and to_nat(MR2(2 DOWNTO 0)) < 7 THEN sf_array := 2*(to_nat(MR2(2 DOWNTO 0))-3); FOR J IN sf_array TO 7 LOOP tCKESR_in(J) <= '0', '1' AFTER 1 ns; FOR K IN 0 TO sf_array LOOP erase_mem(0, MemSize, linked_list(K)); END LOOP; END LOOP; ELSE tCKESR_in <= "00000001"; FOR K IN 0 TO 6 LOOP erase_mem(0, MemSize, linked_list(K)); END LOOP; END IF; END IF; IF CKE = '1' AND SelfRefresh AND NOT SR_exit AND tCKESR_out = "11111111" THEN SR_exit <= TRUE; tXS_in <= '0', '1' AFTER 1 ns; DLL_delay <= '1', '0' AFTER 1 ns; IF freq_change AND to_nat(MR1(0))= 1 THEN DLL_reset_needed := TRUE; ELSE DLL_reset_needed := FALSE; END IF; END IF; ASSERT Command = NOP OR Command = DESL OR NOT SelfRefresh OR NOT SR_exit REPORT "Only NOP and DESELECT commands are valid for tXS " & "after self refresh exit" SEVERITY warning; RL_tmp := AL_tmp + CL_tmp + 5; IF rd_pd_cnt <= RL_tmp THEN rd_pd_cnt := rd_pd_cnt + 1; END IF; IF CKE = '0' AND (Command = NOP OR Command = DESL) AND NOT Act_PD AND NOT Pre_PD AND NOT SelfRefresh AND NOT Reset AND NOT WL_on THEN power_down_cond := TRUE; active_pd_cond := FALSE; FOR I IN 0 TO BankNum LOOP IF (Curr_bank_state(I) = reading AND rd_pd_cnt < RL_tmp) OR Curr_bank_state(I) = readingAP THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tRDPDEN after READ" SEVERITY warning; ELSIF (Curr_bank_state(I) = writting AND NOT (WTR_elapsed(I) AND tWTR_out(I) = '1')) THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tWRPDEN after WRITE" SEVERITY warning; ELSIF Curr_bank_state(I) = writtingAP THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tWRAPDEN after WRITE" SEVERITY warning; ELSIF Curr_bank_state(I) = MRsetting OR tMOD_out_tmp = '0' THEN power_down_cond := FALSE; ASSERT FALSE REPORT "not elapsed tMRSPDEN after MRS" SEVERITY warning; ELSIF ReadStart OR Read_Start THEN power_down_cond := FALSE; ELSIF Curr_bank_state(I) = activating OR Curr_bank_state(I) = active OR (Curr_bank_state(I) = writting AND WTR_elapsed(I) AND tWTR_out(I) = '1') THEN active_pd_cond := TRUE; END IF; END LOOP; IF power_down_cond THEN IF NOT DLL_delay_elapsed AND to_nat(MR0(8))= 1 THEN DLL_reset_needed := TRUE; END IF; IF active_pd_cond THEN Act_PD <= TRUE; FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = activating OR Curr_bank_state(I) = writting OR Curr_bank_state(I) = active THEN Curr_bank_state(I) := active; ELSE Curr_bank_state(I) := precharged; END IF; Curr_bank_state(I) := Next_bank_state(I); END LOOP; ELSE Pre_PD <= TRUE; IF ODT = '0' OR (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') THEN ODT_off := TRUE; END IF; freq_ch_cnt := 5; --tCKSRE Curr_bank_state := (OTHERS => precharged); Next_bank_state := (OTHERS => precharged); END IF; END IF; END IF; IF freq_ch_cnt > 0 THEN freq_ch_cnt := freq_ch_cnt - 1; END IF; IF CKE = '1' AND Pre_PD THEN IF PD_exit_cnt = 0 THEN power_down_cond := FALSE; PD_exit_cnt := 1; Pre_PD <= FALSE; ELSE PD_exit_cnt := 0; -- slow exit precharge power-down to read IF NOT PD_read_delay AND MR0(12) = '0' THEN PD_read_delay := TRUE; PD_read_del_cnt := 10; --tXPDLL -- fast exit precharge power-down to read ELSIF NOT PD_read_delay AND MR0(12) = '1' THEN PD_read_delay := TRUE; PD_read_del_cnt := 3; --tXP END IF; IF freq_change THEN DLL_reset_needed := TRUE; END IF; END IF; END IF; IF DLL_delay_elapsed THEN DLL_reset_needed := FALSE; END IF; IF CKE = '1' AND Act_PD THEN IF PD_exit_cnt = 0 THEN PD_exit_cnt := 1; Act_PD <= FALSE; ELSE PD_exit_cnt := 0; -- slow exit active power-down to read IF NOT PD_read_delay AND MR0(12) = '0' THEN PD_read_delay := TRUE; PD_read_del_cnt := 10; --tXPDLL -- fast exit active power-down to read ELSIF NOT PD_read_delay AND MR0(12) = '1' THEN PD_read_delay := TRUE; PD_read_del_cnt := 3; --tXP END IF; END IF; END IF; IF PD_read_del_cnt > 1 AND PD_read_delay THEN PD_read_del_cnt := PD_read_del_cnt - 1; ELSE PD_read_delay := FALSE; END IF; END IF; END IF; IF falling_edge(CKE) AND NOT Initialized THEN ASSERT FALSE REPORT "CKE must be driven high during initialization" SEVERITY warning; Current_state := illegal; Next_state := illegal; END IF; IF falling_edge(RST) AND RESETNeg = '0' AND PoweredUp THEN Reset_enter_cycle := TRUE; Reset <= TRUE; SR_cond := FALSE; power_down_cond := FALSE; Act_PD <= FALSE; Pre_PD <= FALSE; SelfRefresh <= FALSE; WL_on <= FALSE; END IF; IF rising_edge(tRFCMIN_out) THEN FOR I IN 0 TO BankNum LOOP IF Curr_bank_state(I) = refreshing THEN Curr_bank_state(I) := precharged; Next_bank_state(I) := precharged; END IF; END LOOP; END IF; IF rising_edge(CKDiff) AND mrs_cnt < 4 THEN mrs_cnt := mrs_cnt + 1; END IF; IF tREFPer_out'EVENT AND tREFPer_out = '1' THEN ASSERT FALSE REPORT "tREFPer(max) has elapsed since last REFRESH command" SEVERITY warning; END IF; IF rising_edge(ODT) THEN ASSERT NOT SelfRefresh OR NOT SR_exit OR (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') REPORT "After exiting self refresh, ODT must remain turned " & "off until tXS is satisfied" SEVERITY warning; END IF; IF rising_edge(ODT) AND ODT_off AND NOT (MR1(9) = '0' AND MR1(6) = '0' AND MR1(2) = '0') THEN ODT_off := FALSE; END IF; IF rising_edge(tXS_out) AND SelfRefresh AND SR_exit THEN SR_cond := FALSE; SelfRefresh <= FALSE; SR_exit <= FALSE; PartialSelfRefresh <= FALSE; END IF; IF rising_edge(CKE) AND SelfRefresh AND NOT SR_exit THEN SR_enter_cycle := FALSE; ASSERT ((CK_period >= tperiod_CK_CL5 AND to_nat(MR0(6 DOWNTO 4))= 5) OR (CK_period >= tperiod_CK_CL6 AND to_nat(MR0(6 DOWNTO 4)) = 6) OR (CK_period >= tperiod_CK_CL7 AND to_nat(MR0(6 DOWNTO 4)) = 7) OR (CK_period >= tperiod_CK_CL8 AND to_nat(MR0(6 DOWNTO 4)) = 8) OR (CK_period >= tperiod_CK_CL9 AND to_nat(MR0(6 DOWNTO 4)) = 9) OR (CK_period >= tperiod_CK_CL10 AND to_nat(MR0(6 DOWNTO 4)) = 10) OR to_nat(MR0(6 DOWNTO 4)) < 5 OR to_nat(MR0(6 DOWNTO 4)) > 11) AND CK_period <= tdevice_tCKAVGMAX REPORT "Clock must be stable and meeting tCKSRX " & "specifications at least 5 x tCK prior to exiting" & "self refresh mode" SEVERITY warning; END IF; IF falling_edge(CKE) THEN ASSERT NOT SelfRefresh OR NOT SR_exit REPORT "CKE must stay high until tXS is met" SEVERITY warning; END IF; IF rising_edge(CKE) AND Reset THEN Reset <= FALSE; Reset_enter_cycle := FALSE; Initialized <= FALSE; Current_state := init0; Curr_bank_state := (OTHERS => precharged); END IF; END PROCESS Functionality; PROCESS(mrs_active) BEGIN IF rising_edge(mrs_active) THEN mrs_cnt := 1; END IF; END PROCESS; Write_leveling: PROCESS(tMRD_out,DQSDiff,tWLOMAX_out,ODT,tMOD_out,AIn,WL_on) BEGIN IF rising_edge(ODT) THEN ODTLOFF := FALSE; END IF; IF tWLMRD_out = '1' AND rising_edge(DQSDiff) AND NOT DQ_driven THEN tWLOMAX_in <= '0', '1' AFTER 1 ns; ELSIF tWLOMAX_out = '1' AND NOT DQ_driven AND ODT = '1' THEN DQout_zd <= (OTHERS => '0'); DQ_driven <= TRUE; ELSIF DQ_driven AND rising_edge(DQSDiff) AND DQ_driven AND ODT = '1' THEN tWLOMAX_in <= '0', '1' AFTER 1 ns; ELSIF tWLOMAX_out = '1' AND DQ_driven AND ODT = '1' THEN DQout_zd <= (OTHERS => '1'); DQ_driven <= FALSE; ELSIF falling_edge(ODT) THEN ODTLOFF := TRUE; ELSIF ODT = '0' AND MR1(7) = '0' AND WL_on'EVENT AND NOT WL_on THEN tMRD_in <= '0', '1' AFTER 1 ns; tMOD_in <= '0', '1' AFTER 1 ns; ELSIF ODT = '0' AND MR1(7) = '0' AND tMOD_out = '1' THEN DQout_zd <= (OTHERS => 'Z'); END IF; END PROCESS Write_leveling; TRCDOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRCD_out(I)) BEGIN IF rising_edge(tRCD_out(I)) AND Curr_bank_state(I) = activating THEN Curr_bank_state(I) := active; Next_bank_state(I) := active; END IF; END PROCESS; END GENERATE TRCDOUT; TRPOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRP_out(I)) BEGIN IF rising_edge(tRP_out(I)) AND Curr_bank_state(I) = precharging THEN Curr_bank_state(I) := precharged; Next_bank_state(I) := precharged; END IF; END PROCESS; END GENERATE TRPOUT; TRASMAXOUT: FOR I IN 0 TO BankNum GENERATE PROCESS(tRASMAX_out(I)) BEGIN ASSERT tRASMAX_out(I) = '0' REPORT "tRAS(max) has elapsed since activation of bank, and " & "PRECHARGE command still hasn't been issued" SEVERITY warning; END PROCESS; END GENERATE TRASMAXOUT; Refresh_period: PROCESS(Initialized, Ref_per_expired, --tREFPer_in, SelfRefresh, SR_exit, SimulationEnd, Reset) VARIABLE Ref_cnt : natural; BEGIN IF (Initialized'EVENT AND Initialized) OR rising_edge(Ref_per_expired) OR (SR_exit'EVENT AND SR_exit) THEN Ref_per_start <= '0', '1' AFTER 1 ns; Ref_cnt := 0; END IF; IF (SelfRefresh'EVENT AND SelfRefresh) OR (SimulationEnd'EVENT AND SimulationEnd AND NOT SR_enter_cycle AND NOT Reset_enter_cycle) OR (Reset'EVENT AND Reset) THEN Ref_per_start <= '0'; END IF; END PROCESS Refresh_period; PROCESS(Ref_per_start) VARIABLE industrial : natural RANGE 0 TO 1; BEGIN IF rising_edge(Ref_per_start) THEN industrial := bool_to_nat(MR2(7) = '1'); Ref_per_expired <= '1' AFTER tdevice_tREFPer/(industrial+1) - 1 ns; ELSIF falling_edge(Ref_per_start) THEN Ref_per_expired <= '0' AFTER 1 ns; END IF; END PROCESS; -- Write to memory process Indata: PROCESS(DQSIn, In_data) VARIABLE In_col : natural RANGE 0 TO ColNum; VARIABLE Start_bank : natural RANGE 0 TO BankNum; VARIABLE Start_row : natural RANGE 0 TO RowNum; VARIABLE Start_col : natural RANGE 0 TO ColNum; VARIABLE burst_cnt : natural := 8; VARIABLE burst_cnt_aux : natural := 0; VARIABLE cross1 : boolean := FALSE; VARIABLE cross : boolean := FALSE; VARIABLE burst_seq : sequence; PROCEDURE Write_Mem IS VARIABLE addr_temp : natural; BEGIN addr_temp := Start_row*(ColNum+1) + In_col; IF DM /= '1' THEN Write_Data(Start_bank,addr_temp, -1); IF Viol = '0' THEN Write_Data(Start_bank,addr_temp, to_nat(DQIn)); END IF; END IF; END Write_Mem; BEGIN FOR I IN 0 TO BankNum LOOP IF rising_edge(In_data) THEN preamble_check <= TRUE, FALSE AFTER CK_period/2 + 1 ns; Start_bank := current_bank; Start_row := current_row; Start_col := current_column; IF (burst_len = 4) THEN Start_col := current_column - (current_column MOD 4); ELSE Start_col := current_column - (current_column MOD 8); END IF; In_col := Start_col; burst_cnt := 0; burst_cnt_aux := 0; IF MR0(3) = '0' THEN burst_seq := seq(0); ELSE burst_seq := inl(0); END IF; END IF; IF (rising_edge(DQSIn) AND MR1(11) = '0') AND burst_cnt_aux < 2 AND (Curr_bank_state(I) = writting OR Curr_bank_state(I) = writtingAP) AND NOT cross THEN burst_cnt_aux := burst_cnt_aux + 1; cross := TRUE; END IF; IF ( DQSIn'EVENT ) AND burst_cnt < burst_len AND burst_cnt_aux > 1 AND (Curr_bank_state(I) = writting OR Curr_bank_state(I) = writtingAP) AND NOT cross1 THEN In_col := Start_col + burst_seq(burst_cnt); cross1 := TRUE; IF burst_cnt = burst_len - 1 THEN postamble_check <= TRUE, FALSE AFTER CK_period; burst_cnt_aux := 0; IF burst_len = 8 THEN burst_cnt := 8; ELSE burst_cnt := 4; END IF; ELSE burst_cnt := burst_cnt + 1; END IF; Write_Mem; END IF; END LOOP; cross := FALSE; cross1 := FALSE; END PROCESS Indata; WaitRead: FOR I IN 0 TO BankNum GENERATE Inner: FOR J IN 0 TO 10 GENERATE PROCESS (CKDiff, wait_read(I)(J)) VARIABLE delay : natural RANGE 0 TO 10; VARIABLE temp_bank : natural; VARIABLE temp_row : natural; VARIABLE temp_column : natural; BEGIN IF rising_edge(wait_read(I)(J)) THEN Read_Start := TRUE; delay := read_delay; temp_bank := current_bank; temp_row := current_row; temp_column := current_column; END IF; IF rising_edge(CKDiff) THEN IF delay > 4 THEN delay := delay - 1; ELSIF delay = 4 THEN delay := delay - 1; IF preamble(I)(J) THEN preamble_gen <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; END IF; ELSIF delay = 3 THEN delay := delay - 1; read_bank := temp_bank; read_row := temp_row; read_column := temp_column; Out_data <= '0', '1' AFTER 3*CK_period/4 - 1 ns, 'Z' AFTER CK_period; read_sch(I)(J) := FALSE; END IF; END IF; END PROCESS; END GENERATE Inner; END GENERATE WaitRead; Outdata: PROCESS(CKInt, preamble_gen, Out_data) VARIABLE preamble_done : boolean := FALSE; VARIABLE preamble_allow : boolean; VARIABLE In_col : natural RANGE 0 TO ColNum; VARIABLE Start_bank : natural RANGE 0 TO BankNum; VARIABLE Start_row : natural RANGE 0 TO RowNum; VARIABLE Start_col : natural RANGE 0 TO ColNum; VARIABLE burst_cnt : natural := 9; VARIABLE burst_seq : sequence; VARIABLE out_buffer : std_logic_vector(3 DOWNTO 0); PROCEDURE Read_Mem IS VARIABLE addr_temp : natural; VARIABLE data_temp : integer; BEGIN addr_temp := Start_row*(ColNum+1) + In_col; out_buffer := (OTHERS => 'X'); Read_Data(Start_bank,addr_temp, data_temp); IF data_temp = -2 THEN out_buffer(3 DOWNTO 0) := (OTHERS => 'U'); ELSIF data_temp /= -1 THEN out_buffer(3 DOWNTO 0) := to_slv(data_temp, 4); END IF; END Read_Mem; BEGIN IF rising_edge(CKInt) THEN preamble_allow := FALSE; END IF; IF rising_edge(preamble_gen) THEN preamble_done := FALSE; END IF; IF rising_edge(CKInt) AND NOT preamble_done THEN preamble_allow := TRUE; preamble_done := TRUE; IF MR1(12) = '0' THEN DQSOut_zd <= NOT CKInt; DQSNegOut_zd <= CKInt; END IF; END IF; IF rising_edge(Out_data) THEN Start_bank := read_bank; Start_row := read_row; Start_col := read_column; burst_cnt := 0; In_col := Start_col; IF MR0(3) = '0' THEN burst_seq := seq(In_col MOD 8); ELSE burst_seq := inl(In_col MOD 8); END IF; END IF; IF rising_edge(CKInt) AND burst_cnt = 0 THEN burst_cnt := 1; Read_Mem; IF MR1(12) = '0' THEN DQSOut_zd <= CKInt; DQSNegOut_zd <= NOT CKInt; DQOut_zd <= out_buffer; END IF; ELSIF CKInt'EVENT AND burst_cnt > 0 AND burst_cnt < burst_len THEN ReadStart <= TRUE; In_col := Start_col + burst_seq(burst_cnt); burst_cnt := burst_cnt + 1; Read_Mem; IF MR1(12) = '0' THEN DQSOut_zd <= CKInt; DQSNegOut_zd <= NOT CKInt; DQOut_zd <= out_buffer; END IF; ELSIF CKInt'EVENT AND burst_cnt = burst_len AND NOT preamble_allow THEN burst_cnt := 9; DQSOut_zd <= 'Z'; DQSNegOut_zd <= 'Z'; DQOut_zd <= (OTHERS => 'Z'); ReadStart <= FALSE AFTER CK_period/4 + 1 ns; Read_Start := FALSE; END IF; END PROCESS Outdata; active_number: PROCESS(tRRD_in, tFAW_out) TYPE act_num_type IS ARRAY (0 TO 3) OF natural RANGE 0 TO 3; VARIABLE act_num : act_num_type := (OTHERS => 0); VARIABLE next_slot : boolean := FALSE; BEGIN IF rising_edge(tRRD_in) THEN FOR I IN 0 TO 3 LOOP IF act_num(I) = 0 THEN IF I = 0 THEN act_num(0) := 1; tFAW_in(0) <= '0', '1' AFTER 1 ns; ELSE next_slot := TRUE; FOR J IN 0 TO I-1 LOOP IF act_num(J) = 0 THEN next_slot := FALSE; END IF; END LOOP; IF next_slot THEN act_num(I) := 1; tFAW_in(I) <= '0', '1' AFTER 1 ns; END IF; END IF; ELSE IF act_num(I) = 3 THEN active_forbid := TRUE; ELSE act_num(I) := act_num(I) + 1; END IF; END IF; END LOOP; END IF; IF rising_edge(tFAW_out(0)) THEN act_num(0) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(1)) THEN act_num(1) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(2)) THEN act_num(2) := 0; active_forbid := FALSE; END IF; IF rising_edge(tFAW_out(3)) THEN act_num(3) := 0; active_forbid := FALSE; END IF; END PROCESS active_number; DQValueGen : PROCESS( DQOut_zd ) BEGIN IF DQOut_zd(0) /= 'Z' THEN DOut_Pass <= DQOut_zd AFTER 0.27 ns; ELSE DOut_Pass <= DQOut_zd; END IF; END PROCESS DQValueGen; ---------------------------------------------------------------------------- -- Path Delay Section ---------------------------------------------------------------------------- DQOut_PathDelay_Gen: FOR I IN DOut_Pass'RANGE GENERATE PROCESS(DOut_Pass(I)) VARIABLE DQ0_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQOut(I), OutSignalName => "DQOut", OutTemp => DOut_Pass(I), GlitchData => DQ0_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQ0, PathCondition => TRUE) ) ); END PROCESS; END GENERATE DQOut_PathDelay_Gen; PROCESS(DQSOut_zd) VARIABLE DQSOut_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQSOut, OutSignalName => "DQSOut", OutTemp => DQSOut_zd, GlitchData => DQSOut_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQS, PathCondition => TRUE) ) ); END PROCESS; PROCESS(DQSNegOut_zd) VARIABLE DQSNegOut_GlitchData : VitalGlitchDataType; BEGIN VitalPathDelay01Z( OutSignal => DQSNegOut, OutSignalName => "DQSNegOut", OutTemp => DQSNegOut_zd, GlitchData => DQSNegOut_GlitchData, Paths => ( 0 => (InputChangeTime => CKInt'LAST_EVENT, PathDelay => tpd_CK_DQS, PathCondition => TRUE) ) ); END PROCESS; default: PROCESS -- Text file input variables FILE mem_file : text IS mem_file_name; VARIABLE ind : natural := 0; VARIABLE buf : line; BEGIN -- Preload Control ------------------------------------------------------------------------ -- File Read Section ------------------------------------------------------------------------ ------------------------------------------------------------------------ ----- edj5304ba memory preload file format ---------------------------- ------------------------------------------------------------------------ -- / - comment -- @aaaaaaa - stands for address within memory, -- 24 LSBits determine address within bank, -- other bits determine bank address, -- bytes within bank are written row by row -- d - is 4-bits to be written at address aaaaaaa++ -- (aaaaaaa is incremented at every load), -- only first 1-8 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! ------------------------------------------------------------------------ IF UserPreload AND (mem_file_name /= "none" ) THEN ind := 0; WHILE (NOT ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); IF buf(1) = '/' THEN NEXT; ELSIF buf(1) = '@' THEN ind := h(buf(2 TO 8)); --address ELSE IF ind < (BankNum+1)*(MemSize+1) THEN Write_Data(ind/(MemSize+1),ind MOD (MemSize+1), h(buf(1 to 1))); ind := ind + 1; ELSE REPORT "Memory address out of range" SEVERITY warning; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS default; --ok END BLOCK behavior; END vhdl_behavioral_dynamic_memory_allocation;