-------------------------------------------------------------------------------- -- File Name: edj5304ba.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2006-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 M.Novkovic 06 Nov 20 Initial release -- V1.1 M.Novkovic 06 Dec 21 Dinamic memory -- allocation added -- V1.2 S.Janevski 07 June 19 Correction of state -- transitions with warnings; -- Implemented warnings for -- time delays; -- Additive latency is fixed; -- Start address of write -- burst is corrected; -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: CMOS -- Part: EDJ5304BA -- -- Description: 512 Mb (16 M Words x 4 bits x 8 banks) DDR3 SDRAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY edj5304ba IS GENERIC ( -- tipd delays: interconnect path delays tipd_ODT : VitalDelayType01 := VitalZeroDelay01; tipd_CK : VitalDelayType01 := VitalZeroDelay01; tipd_CKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CKE : VitalDelayType01 := VitalZeroDelay01; tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CASNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_BA0 : VitalDelayType01 := VitalZeroDelay01; tipd_BA1 : VitalDelayType01 := VitalZeroDelay01; tipd_BA2 : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQ3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQS : VitalDelayType01 := VitalZeroDelay01; tipd_DQSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_DM : VitalDelayType01 := VitalZeroDelay01; tipd_RESETNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CK_DQ0 : VitalDelayType01Z := UnitDelay01Z; -- tHZ(max) tpd_CK_DQ1 : VitalDelayType := UnitDelay; -- tHZ(min) tpd_CK_DQS : VitalDelayType01Z := UnitDelay01Z; -- tDQSCK(max) -- tsetup values tsetup_DQ0_DQS : VitalDelayType := UnitDelay; -- tDS tsetup_A0_CK : VitalDelayType := UnitDelay; -- tIS tsetup_DQS_CK_CL5_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL6_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL7_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL8_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL9_negedge_posedge : VitalDelayType := UnitDelay; -- tDSS tsetup_DQS_CK_CL10_negedge_posedge: VitalDelayType := UnitDelay; -- tDSS tsetup_CKE_RESETNeg : VitalDelayType := UnitDelay; tsetup_CK_DQS : VitalDelayType := UnitDelay; -- tWLS -- thold values thold_DQ0_DQS : VitalDelayType := UnitDelay; -- tDH thold_A0_CK : VitalDelayType := UnitDelay; -- tIH thold_DQS_CK_CL5_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL6_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL7_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL8_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL9_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_DQS_CK_CL10_posedge_posedge : VitalDelayType := UnitDelay; -- tDSH thold_CKE_RESETNeg : VitalDelayType := UnitDelay; thold_CK_DQS : VitalDelayType := UnitDelay; -- tWLH -- tpw values tpw_CK_CL5_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL5_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL6_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL6_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL7_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL7_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL8_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL8_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL9_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL9_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_CK_CL10_posedge : VitalDelayType := UnitDelay; -- tCHAVG tpw_CK_CL10_negedge : VitalDelayType := UnitDelay; -- tCLAVG tpw_A0_CL5 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL6 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL7 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL8 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL9 : VitalDelayType := UnitDelay; -- tIPW tpw_A0_CL10 : VitalDelayType := UnitDelay; -- tIPW tpw_DQ0_CL5 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL6 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL7 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL8 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL9 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQ0_CL10 : VitalDelayType := UnitDelay; -- tDIPW tpw_DQS_normCL5_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL5_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL6_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL6_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL7_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL7_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL8_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL8_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL9_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL9_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_normCL10_posedge : VitalDelayType := UnitDelay; -- tDQSH tpw_DQS_normCL10_negedge : VitalDelayType := UnitDelay; -- tDQSL tpw_DQS_postCL5_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL6_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL7_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL8_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL9_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_DQS_postCL10_negedge : VitalDelayType := UnitDelay; -- tWPST tpw_CKE_SelfRefresh_negedge : VitalDelayType := UnitDelay; -- tCKESR -- 200 us from diagram on page 58. tpw_RESETNeg_PoweredUp_eq_0_negedge : VitalDelayType := UnitDelay; -- 100 ns from diagram on page 58. tpw_RESETNeg_PoweredUp_eq_1_negedge : VitalDelayType := UnitDelay; -- tperiod values tperiod_CK_CL5 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL6 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL7 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL8 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL9 : VitalDelayType := UnitDelay; -- tCKAVG(min) tperiod_CK_CL10 : VitalDelayType := UnitDelay; -- tCKAVG(min) -- tskew values tskew_CK_DQS_CL5_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL6_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL7_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL8_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL9_posedge_posedge : VitalDelayType := UnitDelay; -- tDQSS tskew_CK_DQS_CL10_posedge_posedge: VitalDelayType := UnitDelay; -- tDQSS -- tdevice values: values for internal delays tdevice_tRC : VitalDelayType := 49.5 ns; -- tRC- tdevice_tRRD : VitalDelayType := 6 ns; -- tRRD- tdevice_tRCD : VitalDelayType := 13.5 ns; -- tRCD- tdevice_tFAW : VitalDelayType := 30 ns; -- tFAW- tdevice_tRASMIN : VitalDelayType := 36 ns; -- tRAS(min)- tdevice_tRASMAX : VitalDelayType := 70.2 us; -- tRAS(max)- tdevice_tRTP : VitalDelayType := 7.5 ns; -- tRTP- tdevice_tWR : VitalDelayType := 15 ns; -- tWR- tdevice_tWTR : VitalDelayType := 7.5 ns; -- tWTR- tdevice_tRP : VitalDelayType := 13.5 ns; -- tRP- tdevice_tRFCMIN : VitalDelayType := 90 ns; -- tRFC(min)- tdevice_tREFPer : VitalDelayType := 7.8 us; -- refresh period tdevice_tCKAVGMAX : VitalDelayType := 3.333 ns; -- tCKAVG(max)- tdevice_tMRD : VitalDelayType := 6 ns; -- tMRD - tdevice_tMOD : VitalDelayType := 22.5 ns; -- tMOD - tdevice_tXPR : VitalDelayType := 7.5 ns; -- tXPR - tdevice_tZQINIT : VitalDelayType := 384 ns; -- tZQINIT tdevice_tZQOPER : VitalDelayType := 768 ns; -- tZQOPER tdevice_tZQCS : VitalDelayType := 96 ns; -- tZQCS tdevice_tCKSRX : VitalDelayType := 7.5 ns; -- tCKSRX tdevice_tCKSRE : VitalDelayType := 7.5 ns; -- tCKSRE tdevice_tCKESR : VitalDelayType := 6 ns; -- tCKESR tdevice_tWLDQSEN : VitalDelayType := 37.5 ns; -- tWLDQSEN tdevice_tWLMRD : VitalDelayType := 60 ns; -- tWLMRD tdevice_tWLOMAX : VitalDelayType := 10 ns; -- tWLO(MAX) tdevice_tWLOEMAX : VitalDelayType := 2 ns; -- tWLOE(MAX) -- generic control parameters InstancePath : string := DefaultInstancePath; TimingChecksOn : boolean := DefaultTimingChecks; MsgOn : boolean := DefaultMsgOn; XOn : boolean := DefaultXon; -- memory file to be loaded mem_file_name : string := "none"; UserPreload : boolean := FALSE; -- For FMF SDF technology file usage TimingModel : string := DefaultTimingModel ); PORT ( ODT : IN std_ulogic := 'U'; CK : IN std_ulogic := 'U'; CKNeg : IN std_ulogic := 'U'; CKE : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; CASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; BA0 : IN std_ulogic := 'U'; BA1 : IN std_ulogic := 'U'; BA2 : IN std_ulogic := 'U'; A0 : IN std_ulogic := 'U'; A1 : IN std_ulogic := 'U'; A2 : IN std_ulogic := 'U'; A3 : IN std_ulogic := 'U'; A4 : IN std_ulogic := 'U'; A5 : IN std_ulogic := 'U'; A6 : IN std_ulogic := 'U'; A7 : IN std_ulogic := 'U'; A8 : IN std_ulogic := 'U'; A9 : IN std_ulogic := 'U'; A10 : IN std_ulogic := 'U'; A11 : IN std_ulogic := 'U'; A12 : IN std_ulogic := 'U'; DQ0 : INOUT std_ulogic := 'U'; DQ1 : INOUT std_ulogic := 'U'; DQ2 : INOUT std_ulogic := 'U'; DQ3 : INOUT std_ulogic := 'U'; DM : IN std_ulogic := 'U'; DQS : INOUT std_ulogic := 'U'; DQSNeg : INOUT std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 OF edj5304ba : ENTITY IS TRUE; END edj5304ba; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral_static_memory_allocation OF edj5304ba IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral_static_memory_allocation : ARCHITECTURE IS TRUE; CONSTANT PartID : string := "EDJ5304BA"; CONSTANT BankNum : natural := 7; CONSTANT MaxData : natural := 16#F#; CONSTANT MemSize : natural := 16#FFFFFF#; CONSTANT RowNum : natural := 16#1FFF#; CONSTANT ColNum : natural := 16#7FF#; -- ipd SIGNAL ODT_ipd : std_ulogic := 'U'; SIGNAL CK_ipd : std_ulogic := 'U'; SIGNAL CKNeg_ipd : std_ulogic := 'U'; SIGNAL CKE_ipd : std_ulogic := 'U'; SIGNAL CSNeg_ipd : std_ulogic := 'U'; SIGNAL RASNeg_ipd : std_ulogic := 'U'; SIGNAL CASNeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL DM_ipd : std_ulogic := 'U'; SIGNAL BA0_ipd : std_ulogic := 'U'; SIGNAL BA1_ipd : std_ulogic := 'U'; SIGNAL BA2_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL DQ0_ipd : std_ulogic := 'U'; SIGNAL DQ1_ipd : std_ulogic := 'U'; SIGNAL DQ2_ipd : std_ulogic := 'U'; SIGNAL DQ3_ipd : std_ulogic := 'U'; SIGNAL DQS_ipd : std_ulogic := 'U'; SIGNAL DQSNeg_ipd : std_ulogic := 'U'; SIGNAL RESETNeg_ipd : std_ulogic := 'U'; -- nwv SIGNAL ODT_nwv : std_ulogic := 'U'; SIGNAL CK_nwv : std_ulogic := 'U'; SIGNAL CKNeg_nwv : std_ulogic := 'U'; SIGNAL CKE_nwv : std_ulogic := 'U'; SIGNAL CSNeg_nwv : std_ulogic := 'U'; SIGNAL RASNeg_nwv : std_ulogic := 'U'; SIGNAL CASNeg_nwv : std_ulogic := 'U'; SIGNAL WENeg_nwv : std_ulogic := 'U'; SIGNAL BA0_nwv : std_ulogic := 'U'; SIGNAL BA1_nwv : std_ulogic := 'U'; SIGNAL BA2_nwv : std_ulogic := 'U'; SIGNAL A0_nwv : std_ulogic := 'U'; SIGNAL A1_nwv : std_ulogic := 'U'; SIGNAL A2_nwv : std_ulogic := 'U'; SIGNAL A3_nwv : std_ulogic := 'U'; SIGNAL A4_nwv : std_ulogic := 'U'; SIGNAL A5_nwv : std_ulogic := 'U'; SIGNAL A6_nwv : std_ulogic := 'U'; SIGNAL A7_nwv : std_ulogic := 'U'; SIGNAL A8_nwv : std_ulogic := 'U'; SIGNAL A9_nwv : std_ulogic := 'U'; SIGNAL A10_nwv : std_ulogic := 'U'; SIGNAL A11_nwv : std_ulogic := 'U'; SIGNAL A12_nwv : std_ulogic := 'U'; SIGNAL DQ0_nwv : std_ulogic := 'U'; SIGNAL DQ1_nwv : std_ulogic := 'U'; SIGNAL DQ2_nwv : std_ulogic := 'U'; SIGNAL DQ3_nwv : std_ulogic := 'U'; SIGNAL DM_nwv : std_ulogic := 'U'; SIGNAL DQS_nwv : std_ulogic := 'U'; SIGNAL DQSNeg_nwv : std_ulogic := 'U'; SIGNAL RESETNeg_nwv : std_ulogic := 'U'; --- internal delays SIGNAL tRC_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRC_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRRD_in : std_ulogic := '1'; SIGNAL tRRD_out : std_ulogic := '1'; SIGNAL tRCD_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRCD_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_in : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tFAW_out : std_ulogic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMIN_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMIN_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRASMAX_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRASMAX_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRTP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRTP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tWTR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '1'); SIGNAL tRP_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRP_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_in : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tCKESR_out : std_ulogic_vector(BankNum DOWNTO 0) := (OTHERS => '0'); SIGNAL tRFCMIN_in : std_ulogic := '0'; SIGNAL tRFCMIN_out : std_ulogic := '0'; SIGNAL tXS_in : std_ulogic := '0'; SIGNAL tXS_out : std_ulogic := '0'; SIGNAL tREFPer_in : std_ulogic := '0'; SIGNAL tREFPer_out : std_ulogic := '0'; SIGNAL tCKAVGMAX_in : std_ulogic := '0'; SIGNAL tCKAVGMAX_out : std_ulogic := '0'; SIGNAL tWPSTMAX_in : std_ulogic := '0'; SIGNAL tWPSTMAX_out : std_ulogic := '0'; SIGNAL tCKSRX_in : std_ulogic := '0'; SIGNAL tCKSRX_out : std_ulogic := '0'; SIGNAL tCKSRE_in : std_ulogic := '0'; SIGNAL tCKSRE_out : std_ulogic := '0'; SIGNAL tWLODTEN_in : std_ulogic := '0'; SIGNAL tWLODTEN_out : std_ulogic := '0'; SIGNAL tWLDQSEN_in : std_ulogic := '0'; SIGNAL tWLDQSEN_out : std_ulogic := '0'; SIGNAL tWLMRD_in : std_ulogic := '0'; SIGNAL tWLMRD_out : std_ulogic := '0'; SIGNAL tWLOMAX_in : std_ulogic := '0'; SIGNAL tWLOMAX_out : std_ulogic := '0'; SIGNAL tWLOEMAX_in : std_ulogic := '0'; SIGNAL tWLOEMAX_out : std_ulogic := '0'; SIGNAL tODTLOFF_in : std_ulogic := '0'; SIGNAL tODTLOFF_out : std_ulogic := '0'; SIGNAL tMRD_in : std_ulogic := '0'; SIGNAL tMRD_out : std_ulogic := '0'; SIGNAL tMOD_in : std_ulogic := '0'; SIGNAL tMOD_out : std_ulogic := '0'; SIGNAL tMOD_in_tmp : std_ulogic := '0'; SIGNAL tMOD_out_tmp : std_ulogic := '0'; SIGNAL tXPR_in : std_ulogic := '0'; SIGNAL tXPR_out : std_ulogic := '0'; SIGNAL tZQINIT_in : std_ulogic := '0'; SIGNAL tZQINIT_out : std_ulogic := '0'; SIGNAL tZQOPER_in : std_ulogic := '0'; SIGNAL tZQOPER_out : std_ulogic := '0'; SIGNAL tZQCS_in : std_ulogic := '0'; SIGNAL tZQCS_out : std_ulogic := '0'; BEGIN ---------------------------------------------------------------------------- -- Internal Delays ---------------------------------------------------------------------------- TRC : VitalBuf(tRC_out(0), tRC_in(0), (tdevice_tRC - 1 ns, UnitDelay)); TRC1 : VitalBuf(tRC_out(1), tRC_in(1), (tdevice_tRC - 1 ns, UnitDelay)); TRC2 : VitalBuf(tRC_out(2), tRC_in(2), (tdevice_tRC - 1 ns, UnitDelay)); TRC3 : VitalBuf(tRC_out(3), tRC_in(3), (tdevice_tRC - 1 ns, UnitDelay)); TRC4 : VitalBuf(tRC_out(4), tRC_in(4), (tdevice_tRC - 1 ns, UnitDelay)); TRC5 : VitalBuf(tRC_out(5), tRC_in(5), (tdevice_tRC - 1 ns, UnitDelay)); TRC6 : VitalBuf(tRC_out(6), tRC_in(6), (tdevice_tRC - 1 ns, UnitDelay)); TRC7 : VitalBuf(tRC_out(7), tRC_in(7), (tdevice_tRC - 1 ns, UnitDelay)); TRRD : VitalBuf(tRRD_out, tRRD_in, (tdevice_tRRD - 1 ns, UnitDelay)); TRCD : VitalBuf(tRCD_out(0), tRCD_in(0), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD1 : VitalBuf(tRCD_out(1), tRCD_in(1), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD2 : VitalBuf(tRCD_out(2), tRCD_in(2), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD3 : VitalBuf(tRCD_out(3), tRCD_in(3), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD4 : VitalBuf(tRCD_out(4), tRCD_in(4), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD5 : VitalBuf(tRCD_out(5), tRCD_in(5), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD6 : VitalBuf(tRCD_out(6), tRCD_in(6), (tdevice_tRCD - 1 ns, UnitDelay)); TRCD7 : VitalBuf(tRCD_out(7), tRCD_in(7), (tdevice_tRCD - 1 ns, UnitDelay)); TFAW : VitalBuf(tFAW_out(0), tFAW_in(0), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW1 : VitalBuf(tFAW_out(1), tFAW_in(1), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW2 : VitalBuf(tFAW_out(2), tFAW_in(2), (tdevice_tFAW - 2 ns, UnitDelay)); TFAW3 : VitalBuf(tFAW_out(3), tFAW_in(3), (tdevice_tFAW - 2 ns, UnitDelay)); TRASMIN : VitalBuf(tRASMIN_out(0), tRASMIN_in(0), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN1 : VitalBuf(tRASMIN_out(1), tRASMIN_in(1), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN2 : VitalBuf(tRASMIN_out(2), tRASMIN_in(2), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN3 : VitalBuf(tRASMIN_out(3), tRASMIN_in(3), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN4 : VitalBuf(tRASMIN_out(4), tRASMIN_in(4), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN5 : VitalBuf(tRASMIN_out(5), tRASMIN_in(5), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN6 : VitalBuf(tRASMIN_out(6), tRASMIN_in(6), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMIN7 : VitalBuf(tRASMIN_out(7), tRASMIN_in(7), (tdevice_tRASMIN - 1 ns, UnitDelay)); TRASMAX : VitalBuf(tRASMAX_out(0), tRASMAX_in(0), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX1 : VitalBuf(tRASMAX_out(1), tRASMAX_in(1), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX2 : VitalBuf(tRASMAX_out(2), tRASMAX_in(2), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX3 : VitalBuf(tRASMAX_out(3), tRASMAX_in(3), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX4 : VitalBuf(tRASMAX_out(4), tRASMAX_in(4), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX5 : VitalBuf(tRASMAX_out(5), tRASMAX_in(5), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX6 : VitalBuf(tRASMAX_out(6), tRASMAX_in(6), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRASMAX7 : VitalBuf(tRASMAX_out(7), tRASMAX_in(7), (tdevice_tRASMAX - 1 ns, UnitDelay)); TRTP : VitalBuf(tRTP_out(0), tRTP_in(0), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP1 : VitalBuf(tRTP_out(1), tRTP_in(1), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP2 : VitalBuf(tRTP_out(2), tRTP_in(2), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP3 : VitalBuf(tRTP_out(3), tRTP_in(3), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP4 : VitalBuf(tRTP_out(4), tRTP_in(4), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP5 : VitalBuf(tRTP_out(5), tRTP_in(5), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP6 : VitalBuf(tRTP_out(6), tRTP_in(6), (tdevice_tRTP - 1 ns, UnitDelay)); TRTP7 : VitalBuf(tRTP_out(7), tRTP_in(7), (tdevice_tRTP - 1 ns, UnitDelay)); TWR : VitalBuf(tWR_out(0), tWR_in(0), (tdevice_tWR - 1 ns, UnitDelay)); TWR1 : VitalBuf(tWR_out(1), tWR_in(1), (tdevice_tWR - 1 ns, UnitDelay)); TWR2 : VitalBuf(tWR_out(2), tWR_in(2), (tdevice_tWR - 1 ns, UnitDelay)); TWR3 : VitalBuf(tWR_out(3), tWR_in(3), (tdevice_tWR - 1 ns, UnitDelay)); TWR4 : VitalBuf(tWR_out(4), tWR_in(4), (tdevice_tWR - 1 ns, UnitDelay)); TWR5 : VitalBuf(tWR_out(5), tWR_in(5), (tdevice_tWR - 1 ns, UnitDelay)); TWR6 : VitalBuf(tWR_out(6), tWR_in(6), (tdevice_tWR - 1 ns, UnitDelay)); TWR7 : VitalBuf(tWR_out(7), tWR_in(7), (tdevice_tWR - 1 ns, UnitDelay)); TWTR : VitalBuf(tWTR_out(0), tWTR_in(0), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR1 : VitalBuf(tWTR_out(1), tWTR_in(1), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR2 : VitalBuf(tWTR_out(2), tWTR_in(2), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR3 : VitalBuf(tWTR_out(3), tWTR_in(3), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR4 : VitalBuf(tWTR_out(4), tWTR_in(4), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR5 : VitalBuf(tWTR_out(5), tWTR_in(5), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR6 : VitalBuf(tWTR_out(6), tWTR_in(6), (tdevice_tWTR - 1 ns, UnitDelay)); TWTR7 : VitalBuf(tWTR_out(7), tWTR_in(7), (tdevice_tWTR - 1 ns, UnitDelay)); TRP : VitalBuf(tRP_out(0), tRP_in(0), (tdevice_tRP - 1 ns, UnitDelay)); TRP1 : VitalBuf(tRP_out(1), tRP_in(1), (tdevice_tRP - 1 ns, UnitDelay)); TRP2 : VitalBuf(tRP_out(2), tRP_in(2), (tdevice_tRP - 1 ns, UnitDelay)); TRP3 : VitalBuf(tRP_out(3), tRP_in(3), (tdevice_tRP - 1 ns, UnitDelay)); TRP4 : VitalBuf(tRP_out(4), tRP_in(4), (tdevice_tRP - 1 ns, UnitDelay)); TRP5 : VitalBuf(tRP_out(5), tRP_in(5), (tdevice_tRP - 1 ns, UnitDelay)); TRP6 : VitalBuf(tRP_out(6), tRP_in(6), (tdevice_tRP - 1 ns, UnitDelay)); TRP7 : VitalBuf(tRP_out(7), tRP_in(7), (tdevice_tRP - 1 ns, UnitDelay)); TCKESR : VitalBuf(tCKESR_out(0), tCKESR_in(0), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR1 : VitalBuf(tCKESR_out(1), tCKESR_in(1), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR2 : VitalBuf(tCKESR_out(2), tCKESR_in(2), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR3 : VitalBuf(tCKESR_out(3), tCKESR_in(3), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR4 : VitalBuf(tCKESR_out(4), tCKESR_in(4), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR5 : VitalBuf(tCKESR_out(5), tCKESR_in(5), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR6 : VitalBuf(tCKESR_out(6), tCKESR_in(6), (tdevice_tCKESR - 1 ns, UnitDelay)); TCKESR7 : VitalBuf(tCKESR_out(7), tCKESR_in(7), (tdevice_tCKESR - 1 ns, UnitDelay)); TRFCMIN : VitalBuf(tRFCMIN_out, tRFCMIN_in, (tdevice_tRFCMIN - 1 ns, UnitDelay)); TXS : VitalBuf(tXS_out, tXS_in, (tdevice_tRFCMIN + 9 ns, UnitDelay)); TREFPER : VitalBuf(tREFPer_out, tREFPer_in, (tdevice_tREFPer - 1 ns, UnitDelay)); TCKAVGMAX: VitalBuf(tCKAVGMAX_out, tCKAVGMAX_in, (tdevice_tCKAVGMAX - 1 ns, UnitDelay)); TMRD: VitalBuf(tMRD_out, tMRD_in, (tdevice_tMRD - 1 ns, UnitDelay)); TMOD: VitalBuf(tMOD_out, tMOD_in, (tdevice_tMOD - 1 ns, UnitDelay)); TXPR: VitalBuf(tXPR_out, tXPR_in, (tdevice_tXPR - 1 ns, UnitDelay)); TZQINIT: VitalBuf(tZQINIT_out, tZQINIT_in, (tdevice_tZQINIT - 1 ns, UnitDelay)); TZQOPER: VitalBuf(tZQOPER_out, tZQOPER_in, (tdevice_tZQOPER - 1 ns, UnitDelay)); TZQCS: VitalBuf(tZQCS_out, tZQCS_in, (tdevice_tZQCS - 1 ns, UnitDelay)); TCKSRX : VitalBuf(tCKSRX_out, tCKSRX_in, (tdevice_tCKSRX - 1 ns, UnitDelay)); TCKSRE : VitalBuf(tCKSRE_out, tCKSRE_in, (tdevice_tCKSRE - 1 ns, UnitDelay)); TWLODTEN : VitalBuf(tWLODTEN_out, tWLODTEN_in, (tdevice_tMOD -1 ns, UnitDelay)); TWLDQSEN : VitalBuf(tWLDQSEN_out, tWLDQSEN_in,(tdevice_tWLDQSEN - 1 ns, UnitDelay)); TWLMRD : VitalBuf(tWLMRD_out, tWLMRD_in, (tdevice_tWLMRD - 1 ns, UnitDelay)); TWLOMAX : VitalBuf(tWLOMAX_out, tWLOMAX_in, (tdevice_tWLOMAX - 1 ns, UnitDelay)); TWLOEMAX : VitalBuf(tWLOEMAX_out, tWLOEMAX_in, (tdevice_tWLOEMAX - 1 ns, UnitDelay)); ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (ODT_ipd, ODT, tipd_ODT); w_02 : VitalWireDelay (CK_ipd, CK, tipd_CK); w_03 : VitalWireDelay (CKNeg_ipd, CKNeg, tipd_CKNeg); w_04 : VitalWireDelay (CKE_ipd, CKE, tipd_CKE); w_05 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg); w_06 : VitalWireDelay (RASNeg_ipd, RASNeg, tipd_RASNeg); w_07 : VitalWireDelay (CASNeg_ipd, CASNeg, tipd_CASNeg); w_08 : VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_09 : VitalWireDelay (BA0_ipd, BA0, tipd_BA0); w_10 : VitalWireDelay (BA1_ipd, BA1, tipd_BA1); w_11 : VitalWireDelay (BA2_ipd, BA2, tipd_BA2); w_12 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_13 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_14 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_15 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_16 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_17 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_18 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_19 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_20 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_21 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_22 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_23 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_24 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_25 : VitalWireDelay (DQ0_ipd, DQ0, tipd_DQ0); w_26 : VitalWireDelay (DQ1_ipd, DQ1, tipd_DQ1); w_27 : VitalWireDelay (DQ2_ipd, DQ2, tipd_DQ2); w_28 : VitalWireDelay (DQ3_ipd, DQ3, tipd_DQ3); w_29 : VitalWireDelay (DQS_ipd, DQS, tipd_DQS); w_30 : VitalWireDelay (DQSNeg_ipd, DQSNeg, tipd_DQSNeg); w_31 : VitalWireDelay (RESETNeg_ipd, RESETNeg, tipd_RESETNeg); w_32 : VitalWireDelay (DM_ipd, DM, tipd_DM); END BLOCK; ODT_nwv <= To_UX01(ODT_ipd); CK_nwv <= To_UX01(CK_ipd); CKNeg_nwv <= To_UX01(CKNeg_ipd); CKE_nwv <= To_UX01(CKE_ipd); CSNeg_nwv <= To_UX01(CSNeg_ipd); RASNeg_nwv <= To_UX01(RASNeg_ipd); CASNeg_nwv <= To_UX01(CASNeg_ipd); WENeg_nwv <= To_UX01(WENeg_ipd); DM_nwv <= To_UX01(DM_ipd); BA0_nwv <= To_UX01(BA0_ipd); BA1_nwv <= To_UX01(BA1_ipd); BA2_nwv <= To_UX01(BA2_ipd); A0_nwv <= To_UX01(A0_ipd); A1_nwv <= To_UX01(A1_ipd); A2_nwv <= To_UX01(A2_ipd); A3_nwv <= To_UX01(A3_ipd); A4_nwv <= To_UX01(A4_ipd); A5_nwv <= To_UX01(A5_ipd); A6_nwv <= To_UX01(A6_ipd); A7_nwv <= To_UX01(A7_ipd); A8_nwv <= To_UX01(A8_ipd); A9_nwv <= To_UX01(A9_ipd); A10_nwv <= To_UX01(A10_ipd); A11_nwv <= To_UX01(A11_ipd); A12_nwv <= To_UX01(A12_ipd); DQ0_nwv <= To_UX01(DQ0_ipd); DQ1_nwv <= To_UX01(DQ1_ipd); DQ2_nwv <= To_UX01(DQ2_ipd); DQ3_nwv <= To_UX01(DQ3_ipd); DQS_nwv <= To_UX01(DQS_ipd); DQSNeg_nwv <= To_UX01(DQSNeg_ipd); RESETNeg_nwv <= To_UX01(RESETNeg_ipd); ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ODT : IN std_ulogic := 'U'; CK : IN std_ulogic := 'U'; CKNeg : IN std_ulogic := 'U'; CKE : IN std_ulogic := 'U'; CSNeg : IN std_ulogic := 'U'; RASNeg : IN std_ulogic := 'U'; CASNeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; DM : IN std_ulogic := 'U'; RESETNeg : IN std_ulogic := 'U'; BAIn : IN std_logic_vector(2 DOWNTO 0) := (OTHERS => 'U'); AIn : IN std_logic_vector(12 DOWNTO 0) := (OTHERS => 'U'); DQIn : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => 'U'); DQOut : OUT std_ulogic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); DQSIn : IN std_ulogic := 'U'; DQSOut : OUT std_ulogic := 'Z'; DQSNegIn : IN std_ulogic := 'U'; DQSNegOut : OUT std_ulogic := 'Z' ); PORT MAP ( ODT => ODT_nwv, CK => CK_nwv, CKNeg => CKNeg_nwv, CKE => CKE_nwv, CSNeg => CSNeg_nwv, RASNeg => RASNeg_nwv, CASNeg => CASNeg_nwv, WENeg => WENeg_nwv, DM => DM_nwv, BAIn(0) => BA0_nwv, BAIn(1) => BA1_nwv, BAIn(2) => BA2_nwv, AIn(0) => A0_nwv, AIn(1) => A1_nwv, AIn(2) => A2_nwv, AIn(3) => A3_nwv, AIn(4) => A4_nwv, AIn(5) => A5_nwv, AIn(6) => A6_nwv, AIn(7) => A7_nwv, AIn(8) => A8_nwv, AIn(9) => A9_nwv, AIn(10) => A10_nwv, AIn(11) => A11_nwv, AIn(12) => A12_nwv, DQIn(0) => DQ0_nwv, DQIn(1) => DQ1_nwv, DQIn(2) => DQ2_nwv, DQIn(3) => DQ3_nwv, DQOut(0) => DQ0, DQOut(1) => DQ1, DQOut(2) => DQ2, DQOut(3) => DQ3, RESETNeg => RESETNeg_nwv, DQSIn => DQS_nwv, DQSOut => DQS, DQSNegIn => DQSNeg_nwv, DQSNegOut => DQSNeg ); --zero delay signals SIGNAL DQOut_zd : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL DQSOut_zd : std_logic := 'Z'; SIGNAL DQSNegOut_zd : std_logic := 'Z'; SIGNAL DOut_Pass : std_logic_vector(3 DOWNTO 0) := (OTHERS => 'Z'); --differential inputs SIGNAL CKDiff : std_logic := 'Z'; SIGNAL DQSDiff : std_logic := 'Z'; --DLL implementation SIGNAL CKPeriod : time := 3 ns; SIGNAL CKInt : std_ulogic := '0'; SIGNAL CKtemp : std_ulogic := '1'; SIGNAL CKHalfPer : time := 0 ns; SIGNAL CKDLLDelay: time := 0 ns; SIGNAL CK_stable : boolean := FALSE; SIGNAL PoweredUp : boolean := FALSE; SIGNAL In_d : boolean := FALSE; --delay before first MRS command tXPR SIGNAL In_d1 : boolean := FALSE; --mode register set comand cycle time --during initialization SIGNAL In_d2 : boolean := FALSE; -- delay during initial ZQ calibration SIGNAL In_d3 : boolean := FALSE; -- delay during reset ZQ calibration SIGNAL In_d4 : boolean := FALSE; -- delay during ZQ calibration SIGNAL Init_delay : boolean := FALSE;--command during initialization SIGNAL Init_delay1 : boolean := FALSE;--command during initialization SIGNAL Init_delay2 : boolean := FALSE;--command during initialization SIGNAL Init_delay3 : boolean := FALSE;--command during reset ZQ --calibration SIGNAL Init_delay4 : boolean := FALSE;--command during ZQ calibration SIGNAL Initialized : boolean := FALSE;--initialization completed SIGNAL DLL_delay : std_logic := '0'; --delay between DLL SIGNAL DLL_delay_elapsed : boolean := TRUE;--reset and read command SIGNAL In_data : std_ulogic := '0';--start of write operation SIGNAL preamble_gen : std_logic := 'Z';--preamble before read operation SIGNAL Out_data : std_logic := 'Z';--start of read operation SIGNAL fly_flag : std_logic := '0'; --Determine weather read or write -- command is BL4 or BL8 on the fly SIGNAL DQ_driven : boolean;-- DQ driven during Write Leveling procedure -- timing check violation SIGNAL Viol : X01 := '0'; SIGNAL CK_COUNT : natural := 0; --burst sequences TYPE sequence IS ARRAY (0 TO 7) OF integer RANGE -7 TO 7; TYPE seqtab IS ARRAY (0 TO 7) OF sequence; CONSTANT seq0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT seq1 : sequence := (0, 1, 2,-1, 4, 5, 6, 3); CONSTANT seq2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT seq3 : sequence := (0,-3,-2,-1, 4, 1, 2, 3); CONSTANT seq4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT seq5 : sequence := (0, 1, 2,-1,-4,-3,-2,-5); CONSTANT seq6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT seq7 : sequence := (0,-3,-2,-1,-4,-7,-6,-5); CONSTANT seq : seqtab := (seq0, seq1, seq2, seq3, seq4, seq5, seq6, seq7); CONSTANT inl0 : sequence := (0, 1, 2, 3, 4, 5, 6, 7); CONSTANT inl1 : sequence := (0,-1, 2, 1, 4, 3, 6, 5); CONSTANT inl2 : sequence := (0, 1,-2,-1, 4, 5, 2, 3); CONSTANT inl3 : sequence := (0,-1,-2,-3, 4, 3, 2, 1); CONSTANT inl4 : sequence := (0, 1, 2, 3,-4,-3,-2,-1); CONSTANT inl5 : sequence := (0,-1, 2, 1,-4,-5,-2,-3); CONSTANT inl6 : sequence := (0, 1,-2,-1,-4,-3,-6,-5); CONSTANT inl7 : sequence := (0,-1,-2,-3,-4,-5,-6,-7); CONSTANT inl : seqtab := (inl0, inl1, inl2, inl3, inl4, inl5, inl6, inl7); --memory definition TYPE MemStore IS ARRAY (0 TO MemSize) OF integer RANGE -2 TO MaxData; TYPE MemBlock IS ARRAY (0 TO BankNum) OF MemStore; SHARED VARIABLE Mem : MemBlock; --mode registers SHARED VARIABLE MR0 : std_logic_vector(15 DOWNTO 0) := (OTHERS => '0'); SHARED VARIABLE MR1 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR2 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE MR3 : std_logic_vector(15 DOWNTO 0); SHARED VARIABLE burst_len : natural RANGE 4 TO 8;--burst length SHARED VARIABLE active_forbid : boolean := FALSE;--more than 4 active --commands during tFAW --bank, row and column of scheduled read or write operation SHARED VARIABLE current_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE current_row : natural RANGE 0 TO RowNum; SHARED VARIABLE current_column : natural RANGE 0 TO ColNum; --bank, row and column of read operation that starts SHARED VARIABLE read_bank : natural RANGE 0 TO BankNum; SHARED VARIABLE read_row : natural RANGE 0 TO RowNum; SHARED VARIABLE read_column : natural RANGE 0 TO ColNum; -- WRITE LEVELING PROCEDURE SIGNAL WL_on : boolean := FALSE;--Write Leveling enabled SHARED VARIABLE ODTLOFF : boolean := FALSE; TYPE write_sch_type IS ARRAY (0 TO 10) OF boolean; TYPE write_sch_bank_type IS ARRAY (0 TO BankNum) OF write_sch_type; --all scheduled reads within all banks SHARED VARIABLE read_sch : write_sch_bank_type := (OTHERS => (OTHERS => FALSE)); --reads that should be preceeded by preamble SHARED VARIABLE preamble : write_sch_bank_type := (OTHERS => (OTHERS => TRUE)); TYPE wait_read_type IS ARRAY (0 TO 10) OF std_ulogic; TYPE wait_read_bank_type IS ARRAY (0 TO BankNum) OF wait_read_type; --wait_read triggers process that counts remaining cycles to the --beggining of scheduled read when aditive latency has elapsed, and --read_delay keeps information of number of remaining cycles SIGNAL wait_read : wait_read_bank_type; SHARED VARIABLE read_delay : natural RANGE 0 TO 10; --needed for check if all rows were refreshed during refresh period SIGNAL Ref_per_start : std_ulogic := '0'; SIGNAL Ref_per_expired : std_ulogic := '0'; SHARED VARIABLE CK_rise : time := 0 ns; SHARED VARIABLE CK_period : time := 0 ns; TYPE Bank_state_type IS (precharged, refreshing, MRsetting, activating, active, reading, readingAP, writting, writtingAP, precharging, prechall,ZQ_calib); TYPE Bank_state_array_type IS ARRAY (0 TO BankNum) OF Bank_state_type; SHARED VARIABLE Curr_bank_state : Bank_state_array_type; SHARED VARIABLE Next_bank_state : Bank_state_array_type; SHARED VARIABLE SR_cond : boolean := FALSE;--self refresh can be entered SIGNAL SelfRefresh : boolean := FALSE;--self refresh active --Partial self refresh active SIGNAL PartialSelfRefresh : boolean := FALSE; SIGNAL SR_exit : boolean := FALSE;--CKE high, self refresh exit SHARED VARIABLE SR_enter_cycle : boolean := FALSE;--clock can be --turned off SIGNAL Pre_PD : boolean := FALSE;--precharge power down active SIGNAL Act_PD : boolean := FALSE;--active power down active SHARED VARIABLE Read_Start : boolean := FALSE;--read burst in progress, SIGNAL ReadStart : boolean := FALSE; --no pd entry SIGNAL Reset : boolean := FALSE;--reset function active SIGNAL RST : std_logic := '1'; SHARED VARIABLE Reset_enter_cycle : boolean := FALSE;--clocks can be --turned off SIGNAL SimulationEnd : boolean := FALSE; SHARED VARIABLE mrs_cnt : natural; SIGNAL mrs_active : std_logic := '0'; SIGNAL preamble_check : boolean := FALSE; SIGNAL postamble_check : boolean := FALSE; FUNCTION bool_to_nat(tm : boolean) RETURN natural IS VARIABLE Temp : natural; BEGIN Temp := 0; IF tm THEN Temp := 1; END IF; RETURN Temp; END bool_to_nat; BEGIN RST <= RESETNeg AFTER 100 ns; CK_DLL: PROCESS(CKDiff) VARIABLE Previous : time := 0 ns; VARIABLE TmpPer : time := 0 ns; BEGIN IF rising_edge(CKDiff) THEN TmpPer := NOW - Previous; IF TmpPer > 0 ns THEN CKPeriod <= TmpPer; END IF; Previous := NOW; CKHalfPer <= CKPeriod / 2; CKDLLDelay <= CKPeriod + tpd_CK_DQ1; END IF; END PROCESS CK_DLL; CK_temp: PROCESS(CKDiff) -- generating internal clock from DLL BEGIN CKtemp <= NOT CKtemp AFTER CKHalfPer; END PROCESS CK_temp; CKInt <= TRANSPORT CKtemp AFTER CKDLLDelay; Clock_init: PROCESS(CK) BEGIN IF rising_edge(CK) AND NOT PoweredUp THEN CK_COUNT <= CK_COUNT + 1; END IF; END PROCESS Clock_init; Power_up: PROCESS(CK_stable,CK_COUNT) BEGIN IF CK_stable AND (CK_COUNT >= 5) AND NOT PoweredUp THEN PoweredUp <= TRUE; END IF; END PROCESS Power_up; Init_d: PROCESS(In_d) BEGIN IF In_d THEN Init_delay <= TRUE AFTER tdevice_tXPR; ELSE Init_delay <= FALSE; END IF; END PROCESS Init_d; Init_d1: PROCESS(In_d1) BEGIN IF In_d1 THEN Init_delay1 <= TRUE AFTER tdevice_tMRD; ELSE Init_delay1 <= FALSE; END IF; END PROCESS Init_d1; Init_d2: PROCESS(In_d2) BEGIN IF In_d2 THEN Init_delay2 <= TRUE AFTER tdevice_tZQINIT; ELSE Init_delay2 <= FALSE; END IF; END PROCESS Init_d2; Init_d3: PROCESS(In_d3) BEGIN IF In_d3 THEN Init_delay3 <= TRUE AFTER tdevice_tZQOPER; ELSE Init_delay3 <= FALSE; END IF; END PROCESS Init_d3; Init_d4: PROCESS(In_d4) BEGIN IF In_d4 THEN Init_delay4 <= TRUE AFTER tdevice_tZQCS; ELSE Init_delay4 <= FALSE; END IF; END PROCESS Init_d4; PROCESS (tMOD_in_tmp) BEGIN IF rising_edge(tMOD_in_tmp) THEN tMOD_out_tmp <= '0', '1' AFTER tdevice_tMOD; END IF; END PROCESS; DLLdelay: PROCESS(DLL_delay, CKDiff) VARIABLE cnt : natural; BEGIN IF rising_edge(DLL_delay) THEN cnt := 0; DLL_delay_elapsed <= FALSE; ELSIF rising_edge(CKDiff) AND NOT DLL_delay_elapsed THEN cnt := cnt + 1; IF cnt = 511 THEN DLL_delay_elapsed <= TRUE; END IF; END IF; END PROCESS DLLdelay; ---------------------------------------------------------------------------- -- Vital Behavior Process ---------------------------------------------------------------------------- VITALBehaviour: PROCESS(CKDiff, DQSDiff, DQSIn, DQIn, DM, ODT, CKE, CSNeg, RASNeg, CASNeg, WENeg, BAIn, AIn, RESETNeg) -- Timing Check Variables VARIABLE Tviol_DQ0_DQS : X01 := '0'; VARIABLE TD_DQ0_DQS : VitalTimingDataType; VARIABLE Tviol_DQ0_DQS1 : X01 := '0'; VARIABLE TD_DQ0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS : X01 := '0'; VARIABLE TD_DQ1_DQS : VitalTimingDataType; VARIABLE Tviol_DQ1_DQS1 : X01 := '0'; VARIABLE TD_DQ1_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM0_DQS : X01 := '0'; VARIABLE TD_DM0_DQS : VitalTimingDataType; VARIABLE Tviol_DM0_DQS1 : X01 := '0'; VARIABLE TD_DM0_DQS1 : VitalTimingDataType; VARIABLE Tviol_DM1_DQS : X01 := '0'; VARIABLE TD_DM1_DQS : VitalTimingDataType; VARIABLE Tviol_DM1_DQS1 : X01 := '0'; VARIABLE TD_DM1_DQS1 : VitalTimingDataType; VARIABLE Tviol_ODT_CK : X01 := '0'; VARIABLE TD_ODT_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK : X01 := '0'; VARIABLE TD_CKE_CK : VitalTimingDataType; VARIABLE Tviol_CKE_CK_RESET : X01 := '0'; VARIABLE TD_CKE_CK_RESET : VitalTimingDataType; VARIABLE Tviol_CSNeg_CK : X01 := '0'; VARIABLE TD_CSNeg_CK : VitalTimingDataType; VARIABLE Tviol_RASNeg_CK : X01 := '0'; VARIABLE TD_RASNeg_CK : VitalTimingDataType; VARIABLE Tviol_CASNeg_CK : X01 := '0'; VARIABLE TD_CASNeg_CK : VitalTimingDataType; VARIABLE Tviol_WENeg_CK : X01 := '0'; VARIABLE TD_WENeg_CK : VitalTimingDataType; VARIABLE Tviol_BA0_CK : X01 := '0'; VARIABLE TD_BA0_CK : VitalTimingDataType; VARIABLE Tviol_A0_CK : X01 := '0'; VARIABLE TD_A0_CK : VitalTimingDataType; VARIABLE Tviol_DQS_CK5 : X01 := '0'; VARIABLE TD_DQS_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS_CK6 : X01 := '0'; VARIABLE TD_DQS_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS_CK7 : X01 := '0'; VARIABLE TD_DQS_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS_CK8 : X01 := '0'; VARIABLE TD_DQS_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS_CK9 : X01 := '0'; VARIABLE TD_DQS_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS_CK10 : X01 := '0'; VARIABLE TD_DQS_CK10 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK5 : X01 := '0'; VARIABLE TD_DQS1_CK5 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK6 : X01 := '0'; VARIABLE TD_DQS1_CK6 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK7 : X01 := '0'; VARIABLE TD_DQS1_CK7 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK8 : X01 := '0'; VARIABLE TD_DQS1_CK8 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK9 : X01 := '0'; VARIABLE TD_DQS1_CK9 : VitalTimingDataType; VARIABLE Tviol_DQS1_CK10 : X01 := '0'; VARIABLE TD_DQS1_CK10 : VitalTimingDataType; VARIABLE Tviol_CKE_RESETNeg : X01 := '0'; VARIABLE TD_CKE_RESETNeg : VitalTimingDataType; VARIABLE Tviol_CK_DQSDiff : X01 := '0'; VARIABLE TD_CK_DQSDiff : VitalTimingDataType; VARIABLE Tviol_CK_DQSIn : X01 := '0'; VARIABLE TD_CK_DQSIn : VitalTimingDataType; VARIABLE Pviol_A05 : X01 := '0'; VARIABLE PD_A05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A06 : X01 := '0'; VARIABLE PD_A06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A07 : X01 := '0'; VARIABLE PD_A07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A08 : X01 := '0'; VARIABLE PD_A08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A09 : X01 := '0'; VARIABLE PD_A09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_A010 : X01 := '0'; VARIABLE PD_A010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT5 : X01 := '0'; VARIABLE PD_ODT5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT6 : X01 := '0'; VARIABLE PD_ODT6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT7 : X01 := '0'; VARIABLE PD_ODT7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT8 : X01 := '0'; VARIABLE PD_ODT8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT9 : X01 := '0'; VARIABLE PD_ODT9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_ODT10 : X01 := '0'; VARIABLE PD_ODT10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg5 : X01 := '0'; VARIABLE PD_CSNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg6 : X01 := '0'; VARIABLE PD_CSNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg7 : X01 := '0'; VARIABLE PD_CSNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg8 : X01 := '0'; VARIABLE PD_CSNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg9 : X01 := '0'; VARIABLE PD_CSNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CSNeg10 : X01 := '0'; VARIABLE PD_CSNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg5 : X01 := '0'; VARIABLE PD_RASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg6 : X01 := '0'; VARIABLE PD_RASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg7 : X01 := '0'; VARIABLE PD_RASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg8 : X01 := '0'; VARIABLE PD_RASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg9 : X01 := '0'; VARIABLE PD_RASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RASNeg10 : X01 := '0'; VARIABLE PD_RASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg5 : X01 := '0'; VARIABLE PD_CASNeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg6 : X01 := '0'; VARIABLE PD_CASNeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg7 : X01 := '0'; VARIABLE PD_CASNeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg8 : X01 := '0'; VARIABLE PD_CASNeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg9 : X01 := '0'; VARIABLE PD_CASNeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CASNeg10 : X01 := '0'; VARIABLE PD_CASNeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg5 : X01 := '0'; VARIABLE PD_WENeg5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg6 : X01 := '0'; VARIABLE PD_WENeg6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg7 : X01 := '0'; VARIABLE PD_WENeg7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg8 : X01 := '0'; VARIABLE PD_WENeg8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg9 : X01 := '0'; VARIABLE PD_WENeg9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WENeg10 : X01 := '0'; VARIABLE PD_WENeg10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ05 : X01 := '0'; VARIABLE PD_DQ05 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ06 : X01 := '0'; VARIABLE PD_DQ06 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ07 : X01 := '0'; VARIABLE PD_DQ07 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ08 : X01 := '0'; VARIABLE PD_DQ08 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ09 : X01 := '0'; VARIABLE PD_DQ09 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQ010 : X01 := '0'; VARIABLE PD_DQ010 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM5 : X01 := '0'; VARIABLE PD_DM5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM6 : X01 := '0'; VARIABLE PD_DM6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM7 : X01 := '0'; VARIABLE PD_DM7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM8 : X01 := '0'; VARIABLE PD_DM8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM9 : X01 := '0'; VARIABLE PD_DM9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DM10 : X01 := '0'; VARIABLE PD_DM10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS15 : X01 := '0'; VARIABLE PD_DQS15 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS16 : X01 := '0'; VARIABLE PD_DQS16 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS17 : X01 := '0'; VARIABLE PD_DQS17 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS18 : X01 := '0'; VARIABLE PD_DQS18 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS19 : X01 := '0'; VARIABLE PD_DQS19 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS110 : X01 := '0'; VARIABLE PD_DQS110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS115 : X01 := '0'; VARIABLE PD_DQS115 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS116 : X01 := '0'; VARIABLE PD_DQS116 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS117 : X01 := '0'; VARIABLE PD_DQS117 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS118 : X01 := '0'; VARIABLE PD_DQS118 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS119 : X01 := '0'; VARIABLE PD_DQS119 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS1110 : X01 := '0'; VARIABLE PD_DQS1110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS35 : X01 := '0'; VARIABLE PD_DQS35 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS36 : X01 := '0'; VARIABLE PD_DQS36 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS37 : X01 := '0'; VARIABLE PD_DQS37 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS38 : X01 := '0'; VARIABLE PD_DQS38 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS39 : X01 := '0'; VARIABLE PD_DQS39 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS310 : X01 := '0'; VARIABLE PD_DQS310 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS315 : X01 := '0'; VARIABLE PD_DQS315 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS316 : X01 := '0'; VARIABLE PD_DQS316 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS317 : X01 := '0'; VARIABLE PD_DQS317 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS318 : X01 := '0'; VARIABLE PD_DQS318 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS319 : X01 := '0'; VARIABLE PD_DQS319 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_DQS3110 : X01 := '0'; VARIABLE PD_DQS3110 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CKE : X01 := '0'; VARIABLE PD_CKE : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg_PoweredUp : X01 := '0'; VARIABLE PD_RESETNeg_PoweredUp : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RESETNeg : X01 := '0'; VARIABLE PD_RESETNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK5 : X01 := '0'; VARIABLE PD_CK5 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK6 : X01 := '0'; VARIABLE PD_CK6 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK7 : X01 := '0'; VARIABLE PD_CK7 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK8 : X01 := '0'; VARIABLE PD_CK8 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK9 : X01 := '0'; VARIABLE PD_CK9 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_CK10 : X01 := '0'; VARIABLE PD_CK10 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS, Violation => Tviol_DQ0_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ0_DQS1, Violation => Tviol_DQ0_DQS1 ); -- Setup/Hold Check between DQIn and DQSDiff VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd AND MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS, Violation => Tviol_DQ1_DQS ); -- Setup/Hold Check between DQIn and DQSIn VitalSetupHoldCheck ( TestSignal => DQIn, TestSignalName => "DQIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => DQIn /= DQOut_zd, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DQ1_DQS1, Violation => Tviol_DQ1_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS, Violation => Tviol_DM0_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DM0_DQS1, Violation => Tviol_DM0_DQS1 ); -- Setup/Hold Check between DM and DQSDiff VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => MR1(11) = '0', RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS, Violation => Tviol_DM1_DQS ); -- Setup/Hold Check between DM and DQSIn VitalSetupHoldCheck ( TestSignal => DM, TestSignalName => "DM", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupHigh => tsetup_DQ0_DQS, SetupLow => tsetup_DQ0_DQS, HoldHigh => thold_DQ0_DQS, HoldLow => thold_DQ0_DQS, CheckEnabled => TRUE, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_DM1_DQS1, Violation => Tviol_DM1_DQS1 ); -- Setup/Hold Check between ODT and CKDiff VitalSetupHoldCheck ( TestSignal => ODT, TestSignalName => "ODT", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ODT_CK, Violation => Tviol_ODT_CK ); -- Setup/Hold Check between CKE and CKDiff VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK, Violation => Tviol_CKE_CK ); -- Setup/Hold Check between CKE and CK VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKE", RefSignal => CK, RefSignalName => "CK", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => Reset_enter_cycle AND CK_COUNT = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_CK_RESET, Violation => Tviol_CKE_CK_RESET ); -- Setup/Hold Check between CSNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CSNeg_CK, Violation => Tviol_CSNeg_CK ); -- Setup/Hold Check between RASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RASNeg_CK, Violation => Tviol_RASNeg_CK ); -- Setup/Hold Check between CASNeg and CKDiff VitalSetupHoldCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CASNeg_CK, Violation => Tviol_CASNeg_CK ); -- Setup/Hold Check between WENeg and CKDiff VitalSetupHoldCheck ( TestSignal => WENeg, TestSignalName => "WENeg", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENeg_CK, Violation => Tviol_WENeg_CK ); -- Setup/Hold Check between BAIn and CKDiff VitalSetupHoldCheck ( TestSignal => BAIn, TestSignalName => "BAIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BA0_CK, Violation => Tviol_BA0_CK ); -- Setup/Hold Check between AIn and CKDiff VitalSetupHoldCheck ( TestSignal => AIn, TestSignalName => "AIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupHigh => tsetup_A0_CK, SetupLow => tsetup_A0_CK, HoldHigh => thold_A0_CK, HoldLow => thold_A0_CK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_CK, Violation => Tviol_A0_CK ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK5, Violation => Tviol_DQS_CK5 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK6, Violation => Tviol_DQS_CK6 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK7, Violation => Tviol_DQS_CK7 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK8, Violation => Tviol_DQS_CK8 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK9, Violation => Tviol_DQS_CK9 ); -- Setup/Hold Check between DQSDiff and CKDiff VitalSetupHoldCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSDiff /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS_CK10, Violation => Tviol_DQS_CK10 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL5_negedge_posedge, HoldHigh => thold_DQS_CK_CL5_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 1, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK5, Violation => Tviol_DQS1_CK5 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL6_negedge_posedge, HoldHigh => thold_DQS_CK_CL6_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 2, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK6, Violation => Tviol_DQS1_CK6 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL7_negedge_posedge, HoldHigh => thold_DQS_CK_CL7_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 3, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK7, Violation => Tviol_DQS1_CK7 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL8_negedge_posedge, HoldHigh => thold_DQS_CK_CL8_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 4, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK8, Violation => Tviol_DQS1_CK8 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL9_negedge_posedge, HoldHigh => thold_DQS_CK_CL9_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 5, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK9, Violation => Tviol_DQS1_CK9 ); -- Setup/Hold Check between DQSIn and CKDiff VitalSetupHoldCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", RefSignal => CKDiff, RefSignalName => "CKDiff", SetupLow => tsetup_DQS_CK_CL10_negedge_posedge, HoldHigh => thold_DQS_CK_CL10_posedge_posedge, CheckEnabled => DQSIn /= DQSOut_zd AND (DQSIn = '0' OR DQSIn = '1') AND NOT postamble_check AND In_data = '1' AND to_nat(MR0(6 DOWNTO 4)) = 6, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DQS1_CK10, Violation => Tviol_DQS1_CK10 ); -- Setup Check between CKE and RESETNeg VitalSetupHoldCheck ( TestSignal => CKE, TestSignalName => "CKEIn", RefSignal => RESETNeg, RefSignalName => "RESETNeg", SetupLow => tsetup_CKE_RESETNeg, HoldLow => thold_CKE_RESETNeg, CheckEnabled => Reset_enter_cycle, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CKE_RESETNeg, Violation => Tviol_CKE_RESETNeg ); -- Setup Check between CK and DQSIn VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSIn, RefSignalName => "DQSIn", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSIn, Violation => Tviol_CK_DQSIn ); -- Setup Check between CK and DQSDiff VitalSetupHoldCheck ( TestSignal => CK, TestSignalName => "CKIn", RefSignal => DQSDiff, RefSignalName => "DQSDiff", SetupLow => tsetup_CK_DQS, SetupHigh => tsetup_CK_DQS, HoldLow => thold_CK_DQS, HoldHigh => thold_CK_DQS, CheckEnabled => WL_on AND MR1(11) = '0', RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CK_DQSDiff, Violation => Tviol_CK_DQSDiff ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_A05, Violation => Pviol_A05 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_A06, Violation => Pviol_A06 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_A07, Violation => Pviol_A07 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_A08, Violation => Pviol_A08 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_A09, Violation => Pviol_A09 ); -- PulseWidth Check for AIn(0) VitalPeriodPulseCheck ( TestSignal => AIn(0), TestSignalName => "AIn(0)", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_A010, Violation => Pviol_A010 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT5, Violation => Pviol_ODT5 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT6, Violation => Pviol_ODT6 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT7, Violation => Pviol_ODT7 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT8, Violation => Pviol_ODT8 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT9, Violation => Pviol_ODT9 ); -- PulseWidth Check for ODT VitalPeriodPulseCheck ( TestSignal => ODT, TestSignalName => "ODT", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_ODT10, Violation => Pviol_ODT10 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg5, Violation => Pviol_CSNeg5 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg6, Violation => Pviol_CSNeg6 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg7, Violation => Pviol_CSNeg7 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg8, Violation => Pviol_CSNeg8 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg9, Violation => Pviol_CSNeg9 ); -- PulseWidth Check for CSNeg VitalPeriodPulseCheck ( TestSignal => CSNeg, TestSignalName => "CSNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CSNeg10, Violation => Pviol_CSNeg10 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg5, Violation => Pviol_RASNeg5 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg6, Violation => Pviol_RASNeg6 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg7, Violation => Pviol_RASNeg7 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg8, Violation => Pviol_RASNeg8 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg9, Violation => Pviol_RASNeg9 ); -- PulseWidth Check for RASNeg VitalPeriodPulseCheck ( TestSignal => RASNeg, TestSignalName => "RASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_RASNeg10, Violation => Pviol_RASNeg10 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg5, Violation => Pviol_CASNeg5 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg6, Violation => Pviol_CASNeg6 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg7, Violation => Pviol_CASNeg7 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg8, Violation => Pviol_CASNeg8 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg9, Violation => Pviol_CASNeg9 ); -- PulseWidth Check for CASNeg VitalPeriodPulseCheck ( TestSignal => CASNeg, TestSignalName => "CASNeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CASNeg10, Violation => Pviol_CASNeg10 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL5, PulseWidthHigh => tpw_A0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg5, Violation => Pviol_WENeg5 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL6, PulseWidthHigh => tpw_A0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg6, Violation => Pviol_WENeg6 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL7, PulseWidthHigh => tpw_A0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg7, Violation => Pviol_WENeg7 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL8, PulseWidthHigh => tpw_A0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg8, Violation => Pviol_WENeg8 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL9, PulseWidthHigh => tpw_A0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg9, Violation => Pviol_WENeg9 ); -- PulseWidth Check for WENeg VitalPeriodPulseCheck ( TestSignal => WENeg, TestSignalName => "WENeg", PulseWidthLow => tpw_A0_CL10, PulseWidthHigh => tpw_A0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_WENeg10, Violation => Pviol_WENeg10 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ05, Violation => Pviol_DQ05 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ06, Violation => Pviol_DQ06 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ07, Violation => Pviol_DQ07 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ08, Violation => Pviol_DQ08 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ09, Violation => Pviol_DQ09 ); -- PulseWidth Check for DQIn(0) VitalPeriodPulseCheck ( TestSignal => DQIn(0), TestSignalName => "DQIn(0)", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQ010, Violation => Pviol_DQ010 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL5, PulseWidthHigh => tpw_DQ0_CL5, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM5, Violation => Pviol_DM5 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL6, PulseWidthHigh => tpw_DQ0_CL6, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM6, Violation => Pviol_DM6 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL7, PulseWidthHigh => tpw_DQ0_CL7, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM7, Violation => Pviol_DM7 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL8, PulseWidthHigh => tpw_DQ0_CL8, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM8, Violation => Pviol_DM8 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL9, PulseWidthHigh => tpw_DQ0_CL9, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM9, Violation => Pviol_DM9 ); -- PulseWidth Check for DM VitalPeriodPulseCheck ( TestSignal => DM, TestSignalName => "DM", PulseWidthLow => tpw_DQ0_CL10, PulseWidthHigh => tpw_DQ0_CL10, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DM10, Violation => Pviol_DM10 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS15, Violation => Pviol_DQS15 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS16, Violation => Pviol_DQS16 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS17, Violation => Pviol_DQS17 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS18, Violation => Pviol_DQS18 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS19, Violation => Pviol_DQS19 ); -- PulseWidth Check for DQSDiff (normal) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS110, Violation => Pviol_DQS110 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL5_negedge, PulseWidthHigh => tpw_DQS_normCL5_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS115, Violation => Pviol_DQS115 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL6_negedge, PulseWidthHigh => tpw_DQS_normCL6_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS116, Violation => Pviol_DQS116 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL7_negedge, PulseWidthHigh => tpw_DQS_normCL7_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS117, Violation => Pviol_DQS117 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL8_negedge, PulseWidthHigh => tpw_DQS_normCL8_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS118, Violation => Pviol_DQS118 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL9_negedge, PulseWidthHigh => tpw_DQS_normCL9_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS119, Violation => Pviol_DQS119 ); -- PulseWidth Check for DQSIn (normal) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_normCL10_negedge, PulseWidthHigh => tpw_DQS_normCL10_posedge, CheckEnabled => to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS1110, Violation => Pviol_DQS1110 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS35, Violation => Pviol_DQS35 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS36, Violation => Pviol_DQS36 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS37, Violation => Pviol_DQS37 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS38, Violation => Pviol_DQS38 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS39, Violation => Pviol_DQS39 ); -- PulseWidth Check for DQSDiff (postamble) VitalPeriodPulseCheck ( TestSignal => DQSDiff, TestSignalName => "DQSDiff", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6 AND MR1(11) = '0', HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS310, Violation => Pviol_DQS310 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL5_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS315, Violation => Pviol_DQS315 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL6_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS316, Violation => Pviol_DQS316 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL7_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS317, Violation => Pviol_DQS317 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL8_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS318, Violation => Pviol_DQS318 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL9_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS319, Violation => Pviol_DQS319 ); -- PulseWidth Check for DQSIn (postamble) VitalPeriodPulseCheck ( TestSignal => DQSIn, TestSignalName => "DQSIn", PulseWidthLow => tpw_DQS_postCL10_negedge, CheckEnabled => postamble_check AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_DQS3110, Violation => Pviol_DQS3110 ); -- PulseWidth Check for CKE VitalPeriodPulseCheck ( TestSignal => CKE, TestSignalName => "CKE", PulseWidthLow => tpw_CKE_SelfRefresh_negedge, CheckEnabled => SelfRefresh, HeaderMsg => InstancePath & PartID, PeriodData => PD_CKE, Violation => Pviol_CKE ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_0_negedge, CheckEnabled => NOT PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg_PoweredUp, Violation => Pviol_RESETNeg_PoweredUp ); -- PulseWidth Check for RESETNeg VitalPeriodPulseCheck ( TestSignal => RESETNeg, TestSignalName => "RESETNeg", PulseWidthLow => tpw_RESETNeg_PoweredUp_eq_1_negedge, CheckEnabled => PoweredUp, HeaderMsg => InstancePath & PartID, PeriodData => PD_RESETNeg, Violation => Pviol_RESETNeg ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL5, PulseWidthLow => tpw_CK_CL5_negedge, PulseWidthHigh => tpw_CK_CL5_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 1, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK5, Violation => Pviol_CK5 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL6, PulseWidthLow => tpw_CK_CL6_negedge, PulseWidthHigh => tpw_CK_CL6_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 2, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK6, Violation => Pviol_CK6 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL7, PulseWidthLow => tpw_CK_CL7_negedge, PulseWidthHigh => tpw_CK_CL7_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 3, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK7, Violation => Pviol_CK7 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL8, PulseWidthLow => tpw_CK_CL8_negedge, PulseWidthHigh => tpw_CK_CL8_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 4, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK8, Violation => Pviol_CK8 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL9, PulseWidthLow => tpw_CK_CL9_negedge, PulseWidthHigh => tpw_CK_CL9_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 5, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK9, Violation => Pviol_CK9 ); -- PulseWidth and Period Check for CKDiff VitalPeriodPulseCheck ( TestSignal => CKDiff, TestSignalName => "CKDiff", Period => tperiod_CK_CL10, PulseWidthLow => tpw_CK_CL10_negedge, PulseWidthHigh => tpw_CK_CL10_posedge, CheckEnabled => CK_stable AND NOT SR_enter_cycle AND NOT Reset_enter_cycle AND to_nat(MR0(6 DOWNTO 4)) = 6, HeaderMsg => InstancePath & PartID, PeriodData => PD_CK10, Violation => Pviol_CK10 ); Violation := Tviol_DQ0_DQS OR Tviol_DQ0_DQS1 OR Tviol_DQ1_DQS OR Tviol_DQ1_DQS1 OR Tviol_DM0_DQS OR Tviol_DM0_DQS1 OR Tviol_DM1_DQS OR Tviol_DM1_DQS1 OR Tviol_ODT_CK OR Tviol_CKE_CK OR Tviol_CKE_CK_RESET OR Tviol_CSNeg_CK OR Tviol_RASNeg_CK OR Tviol_CASNeg_CK OR Tviol_WENeg_CK OR Tviol_BA0_CK OR Tviol_A0_CK OR Tviol_DQS_CK5 OR Tviol_DQS_CK6 OR Tviol_DQS_CK7 OR Tviol_DQS_CK8 OR Tviol_DQS_CK9 OR Tviol_DQS_CK10 OR Tviol_DQS1_CK5 OR Tviol_DQS1_CK6 OR Tviol_DQS1_CK7 OR Tviol_DQS1_CK8 OR Tviol_DQS1_CK9 OR Tviol_DQS1_CK10 OR Tviol_CKE_RESETNeg OR Tviol_CK_DQSIn OR Tviol_CK_DQSDiff OR Pviol_A05 OR Pviol_A06 OR Pviol_A07 OR