-------------------------------------------------------------------------------- -- File Name: cy7c185.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 00 DEC 13 Initial release -- V2.0 R. Munden 01 NOV 23 Rewritten to use VITAL2000 memory package -- V2.1 R. Munden 02 DEC 28 Changed VITAL2000 to IEEE -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: not ECL -- Part: CY7C185 -- -- Description: 8K X 8 SRAM -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.vital_memory.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; USE FMF.memory.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY cy7c185 IS GENERIC ( -- tipd delays: interconnect path delays tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_OENeg_D0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_WENeg_D0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_CE1Neg_D0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_CE2_D0 : VitalDelayType01ZX := UnitDelay01ZX; tpd_A0_D0 : VitalDelayType01ZX := UnitDelay01ZX; -- tpw values: pulse widths tpw_WENeg_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_A0_WENeg : VitalDelayType := UnitDelay; tsetup_D0_WENeg : VitalDelayType := UnitDelay; -- thold values: hold times thold_D0_WENeg : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; SeverityMode : SEVERITY_LEVEL := WARNING; MemLoadFileName : STRING := "cy7c185.data"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : IN std_ulogic := 'U'; A1 : IN std_ulogic := 'U'; A2 : IN std_ulogic := 'U'; A3 : IN std_ulogic := 'U'; A4 : IN std_ulogic := 'U'; A5 : IN std_ulogic := 'U'; A6 : IN std_ulogic := 'U'; A7 : IN std_ulogic := 'U'; A8 : IN std_ulogic := 'U'; A9 : IN std_ulogic := 'U'; A10 : IN std_ulogic := 'U'; A11 : IN std_ulogic := 'U'; A12 : IN std_ulogic := 'U'; D0 : INOUT std_ulogic := 'U'; D1 : INOUT std_ulogic := 'U'; D2 : INOUT std_ulogic := 'U'; D3 : INOUT std_ulogic := 'U'; D4 : INOUT std_ulogic := 'U'; D5 : INOUT std_ulogic := 'U'; D6 : INOUT std_ulogic := 'U'; D7 : INOUT std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; WENeg : IN std_ulogic := 'U'; CE1Neg : IN std_ulogic := 'U'; CE2 : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy7c185 : ENTITY IS TRUE; END cy7c185; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of cy7c185 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "CY7C185"; CONSTANT MaxData : NATURAL := 255; CONSTANT TotalLOC : NATURAL := 8191; CONSTANT HiAbit : NATURAL := 12; CONSTANT HiDbit : NATURAL := 7; CONSTANT DataWidth : NATURAL := 8; CONSTANT DlyArraySize : NATURAL := 103; SIGNAL D0_ipd : std_ulogic := 'U'; SIGNAL D1_ipd : std_ulogic := 'U'; SIGNAL D2_ipd : std_ulogic := 'U'; SIGNAL D3_ipd : std_ulogic := 'U'; SIGNAL D4_ipd : std_ulogic := 'U'; SIGNAL D5_ipd : std_ulogic := 'U'; SIGNAL D6_ipd : std_ulogic := 'U'; SIGNAL D7_ipd : std_ulogic := 'U'; SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL WENeg_ipd : std_ulogic := 'U'; SIGNAL CE1Neg_ipd : std_ulogic := 'U'; SIGNAL CE2_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_2: VitalWireDelay (WENeg_ipd, WENeg, tipd_WENeg); w_3: VitalWireDelay (CE1Neg_ipd, CE1Neg, tipd_CE1Neg); w_4: VitalWireDelay (CE2_ipd, CE2, tipd_CE2); w_5: VitalWireDelay (D0_ipd, D0, tipd_D0); w_6: VitalWireDelay (D1_ipd, D1, tipd_D1); w_7: VitalWireDelay (D2_ipd, D2, tipd_D2); w_8: VitalWireDelay (D3_ipd, D3, tipd_D3); w_9: VitalWireDelay (D4_ipd, D4, tipd_D4); w_10: VitalWireDelay (D5_ipd, D5, tipd_D5); w_11: VitalWireDelay (D6_ipd, D6, tipd_D6); w_12: VitalWireDelay (D7_ipd, D7, tipd_D7); w_13: VitalWireDelay (A0_ipd, A0, tipd_A0); w_14: VitalWireDelay (A1_ipd, A1, tipd_A1); w_15: VitalWireDelay (A2_ipd, A2, tipd_A2); w_16: VitalWireDelay (A3_ipd, A3, tipd_A3); w_17: VitalWireDelay (A4_ipd, A4, tipd_A4); w_18: VitalWireDelay (A5_ipd, A5, tipd_A5); w_19: VitalWireDelay (A6_ipd, A6, tipd_A6); w_20: VitalWireDelay (A7_ipd, A7, tipd_A7); w_21: VitalWireDelay (A8_ipd, A8, tipd_A8); w_22: VitalWireDelay (A9_ipd, A9, tipd_A9); w_23: VitalWireDelay (A10_ipd, A10, tipd_A10); w_24: VitalWireDelay (A11_ipd, A11, tipd_A11); w_25: VitalWireDelay (A12_ipd, A12, tipd_A12); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( AddressIn : IN std_logic_vector(HiAbit downto 0); DataIn : IN std_logic_vector(HiDbit downto 0); DataOut : OUT std_logic_vector(HiDbit downto 0); OENegIn : IN std_ulogic := 'U'; WENegIn : IN std_ulogic := 'U'; CE1NegIn : IN std_ulogic := 'U'; CE2In : IN std_ulogic := 'U' ); PORT MAP ( DataOut(0) => D0, DataOut(1) => D1, DataOut(2) => D2, DataOut(3) => D3, DataOut(4) => D4, DataOut(5) => D5, DataOut(6) => D6, DataOut(7) => D7, DataIn(0) => D0_ipd, DataIn(1) => D1_ipd, DataIn(2) => D2_ipd, DataIn(3) => D3_ipd, DataIn(4) => D4_ipd, DataIn(5) => D5_ipd, DataIn(6) => D6_ipd, DataIn(7) => D7_ipd, AddressIn(0) => A0_ipd, AddressIn(1) => A1_ipd, AddressIn(2) => A2_ipd, AddressIn(3) => A3_ipd, AddressIn(4) => A4_ipd, AddressIn(5) => A5_ipd, AddressIn(6) => A6_ipd, AddressIn(7) => A7_ipd, AddressIn(8) => A8_ipd, AddressIn(9) => A9_ipd, AddressIn(10) => A10_ipd, AddressIn(11) => A11_ipd, AddressIn(12) => A12_ipd, OENegIn => OENeg_ipd, WENegIn => WENeg_ipd, CE1NegIn => CE1Neg_ipd, CE2In => CE2_ipd ); SIGNAL weneg_int : std_ulogic; BEGIN weneg_int <= (WENegIn OR CE1NegIn) OR not CE2In; ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Behavior : PROCESS (OENegIn, WENegIn, CE1NegIn, CE2In, AddressIn, DataIn, weneg_int) CONSTANT OENeg_D_Delay : VitalDelayArrayType01ZX (HiDbit downto 0) := (OTHERS => tpd_OENeg_D0); CONSTANT CE1Neg_D_Delay :VitalDelayArrayType01ZX (HiDbit downto 0) := (OTHERS => tpd_CE1Neg_D0); CONSTANT CE2_D_Delay :VitalDelayArrayType01ZX (HiDbit downto 0) := (OTHERS => tpd_CE2_D0); CONSTANT Addr_D_Delay : VitalDelayArrayType01ZX (DlyArraySize downto 0) := (OTHERS => tpd_A0_D0); -- Timing Check Variables VARIABLE Tviol_A0_WENeg: X01 := '0'; VARIABLE TD_A0_WENeg : VitalTimingDataType; VARIABLE Tviol_D0_WENeg: X01 := '0'; VARIABLE TD_D0_WENeg : VitalTimingDataType; VARIABLE Tviol_D0_CENeg: X01 := '0'; VARIABLE TD_D0_CENeg : VitalTimingDataType; VARIABLE Pviol_WENeg : X01 := '0'; VARIABLE PD_WENeg : VitalPeriodDataType := VitalPeriodDataInit; -- VITAL Memory Declaration VARIABLE Memdat : VitalMemoryDataType := VitalDeclareMemory ( NoOfWords => TotalLOC, NoOfBitsPerWord => DataWidth, NoOfBitsPerSubWord => DataWidth, MemoryLoadFile => MemLoadFileName, BinaryLoadFile => FALSE ); -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE D_zd : std_logic_vector(HiDbit DOWNTO 0); VARIABLE Prevcntls : std_logic_vector(0 to 3); VARIABLE PrevData : std_logic_vector(HiDbit downto 0); VARIABLE Prevaddr : std_logic_vector(HiAbit downto 0); VARIABLE PFlag : VitalPortFlagVectorType(0 downto 0); VARIABLE Addrvalue : VitalAddressValueType; VARIABLE OENegChange : TIME := 0 ns; VARIABLE CE1NegChange : TIME := 0 ns; VARIABLE CE2Change : TIME := 0 ns; VARIABLE AddrChangeArray : VitalTimeArrayT(HiAbit downto 0); VARIABLE D_GlitchData : VitalGlitchDataArrayType(HiDbit Downto 0); VARIABLE DSchedData : VitalMemoryScheduleDataVectorType (HiDbit Downto 0); BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => weneg_int, RefSignalName => "WENeg", SetupHigh => tsetup_A0_WENeg, SetupLow => tsetup_A0_WENeg, CheckEnabled => (CE1NegIn ='0' AND CE2In = '1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_A0_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_A0_WENeg ); VitalSetupHoldCheck ( TestSignal => DataIn, TestSignalName => "Data", RefSignal => weneg_int, RefSignalName => "Write End", SetupHigh => tsetup_D0_WENeg, SetupLow => tsetup_D0_WENeg, HoldHigh => thold_D0_WENeg, HoldLow => thold_D0_WENeg, CheckEnabled => (CE1NegIn ='0' AND CE2In = '1' AND OENeg ='1'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D0_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WENeg ); VitalPeriodPulseCheck ( TestSignal => WENegIn, TestSignalName => "WENeg", PulseWidthLow => tpw_WENeg_negedge, PeriodData => PD_WENeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WENeg, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); Violation := Pviol_WENeg OR Tviol_D0_WENeg OR Tviol_D0_CENeg; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- VitalMemoryTable ( DataOutBus => D_zd, MemoryData => Memdat, PrevControls => Prevcntls, PrevDataInBus => Prevdata, PrevAddressBus => Prevaddr, PortFlag => PFlag, Controls => (CE2In, CE1NegIn, OENegIn, WENegIn), DataInBus => DataIn, AddressBus => AddressIn, AddressValue => Addrvalue, MemoryTable => Table_generic_sram ); -------------------------------------------------------------------- -- Output Section -------------------------------------------------------------------- VitalMemoryInitPathDelay ( ScheduleDataArray => DSchedData, OutputDataArray => D_zd ); VitalMemoryAddPathDelay ( ScheduleDataArray => DSchedData, InputSignal => OENegIn, OutputSignalName => "D", InputChangeTime => OENegChange, PathDelayArray => OENeg_D_Delay, ArcType => CrossArc, PathCondition => true, OutputRetainFlag => true ); VitalMemoryAddPathDelay ( ScheduleDataArray => DSchedData, InputSignal => CE1NegIn, OutputSignalName => "D", InputChangeTime => CE1NegChange, PathDelayArray => CE1Neg_D_Delay, ArcType => CrossArc, PathCondition => true, OutputRetainFlag => false ); VitalMemoryAddPathDelay ( ScheduleDataArray => DSchedData, InputSignal => CE2In, OutputSignalName => "D", InputChangeTime => CE2Change, PathDelayArray => CE2_D_Delay, ArcType => CrossArc, PathCondition => true, OutputRetainFlag => false ); VitalMemoryAddPathDelay ( ScheduleDataArray => DSchedData, InputSignal => AddressIn, OutputSignalName => "D", InputChangeTimeArray => AddrChangeArray, PathDelayArray => Addr_D_Delay, ArcType => CrossArc, OutputRetainFlag => true, OutputRetainBehavior => BitCorrupt, PathCondition => OENegIn = '0' ); VitalMemorySchedulePathDelay ( OutSignal => DataOut, OutputSignalName => "D", ScheduleDataArray => DSchedData ); END PROCESS; END BLOCK; END vhdl_behavioral;