version: | author: | mod date: | changes made: V1.0 M.Milanovic 05 Nov 30 Initial release V1.1 R. Munden 07 Sep 07 Changed support Micron part numbers 1ns cy7c1362 CY7C1362A-225AJCCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-225ACCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-225BGCCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.05:2.80) (1.25:2.05:2.80) (1.25:2.15:3.00) (1.25:2.05:2.80) (1.25:2.15:3.00) (1.25:2.05:2.80)) (IOPATH OENeg DQA0 () () (0.00:1.40:2.80) (0.93:1.87:2.80) (0.00:1.40:2.80) (0.93:1.87:2.80)) )) (TIMINGCHECK (PERIOD (posedge CLK) (4.40)) (WIDTH (posedge CLK)(1.80)) (WIDTH (negedge CLK)(1.80)) (SETUP A0 CLK (1.40)) (SETUP DQA0 CLK (1.40)) (SETUP ADVNeg CLK (1.40)) (SETUP ADSCNeg CLK (1.40)) (SETUP BWANeg CLK (1.40)) (SETUP CE2 CLK (1.40)) (HOLD A0 CLK (0.40)) (HOLD DQA0 CLK (0.40)) (HOLD ADSCNeg CLK (0.40)) (HOLD BWANeg CLK (0.40)) (HOLD ADVNeg CLK (0.40)) (HOLD CE2 CLK (0.40)) ) CY7C1362A-200AJCCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-200AJICypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-200ACCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-200AICypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-200BGCCypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-200BGICypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.20:3.10) (1.25:2.20:3.10) (1.25:1.95:2.60) (1.25:2.20:3.10) (1.25:1.95:2.60) (1.25:2.20:3.10)) (IOPATH OENeg DQA0 () () (0.00:1.50:3.00) (1.00:2.00:3.00) (0.00:1.50:3.00) (1.00:2.00:3.00)) )) (TIMINGCHECK (PERIOD (posedge CLK) (5.00)) (WIDTH (posedge CLK)(2.00)) (WIDTH (negedge CLK)(2.00)) (SETUP A0 CLK (1.40)) (SETUP DQA0 CLK (1.40)) (SETUP ADVNeg CLK (1.40)) (SETUP ADSCNeg CLK (1.40)) (SETUP BWANeg CLK (1.40)) (SETUP CE2 CLK (1.40)) (HOLD A0 CLK (0.40)) (HOLD DQA0 CLK (0.40)) (HOLD ADSCNeg CLK (0.40)) (HOLD BWANeg CLK (0.40)) (HOLD ADVNeg CLK (0.40)) (HOLD CE2 CLK (0.40)) ) CY7C1362A-166AJC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AJI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166BGC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166BGI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=3.3V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.00:1.90:2.80) (1.25:2.40:3.50) (1.00:1.90:2.80) (1.25:2.40:3.50)) (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(2.40)) (WIDTH (negedge CLK)(2.40)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362A-166AJC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AJI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166AI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166BGC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-166BGI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=2.5V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.65:4.00) (1.25:2.65:4.00) (1.00:1.90:2.80) (1.25:2.65:4.00) (1.00:1.90:2.80) (1.25:2.65:4.00)) (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.33:2.67:4.00) (0.00:1.75:3.50) (1.33:2.67:4.00)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(2.40)) (WIDTH (negedge CLK)(2.40)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362A-150AJC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AJI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150BGC_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150BGI_3V3Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=3.3V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.65:4.00) (1.25:2.40:3.50) (1.25:2.65:4.00) (1.25:2.40:3.50)) (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.70)) (WIDTH (posedge CLK)(2.60)) (WIDTH (negedge CLK)(2.60)) (SETUP A0 CLK (2.00)) (SETUP DQA0 CLK (2.00)) (SETUP ADVNeg CLK (2.00)) (SETUP ADSCNeg CLK (2.00)) (SETUP BWANeg CLK (2.00)) (SETUP CE2 CLK (2.00)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362A-150AJC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AJI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150AI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150BGC_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 CY7C1362A-150BGI_2V5Cypress Semiconductor Corporation, 38-05258, Rev C, January 18, 2003 The values listed are for VCC=3.3V-5%/+10%, commercial TA=0Cto+70C, industrial TA=-40Cto+85C, VCCQ=2.5V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:3.00:4.50) (1.50:3.00:4.50) (1.25:2.65:4.00) (1.50:3.00:4.50) (1.25:2.65:4.00) (1.50:3.00:4.50)) (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.50:3.00:4.50) (0.00:1.75:3.50) (1.50:3.00:4.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.70)) (WIDTH (posedge CLK)(2.60)) (WIDTH (negedge CLK)(2.60)) (SETUP A0 CLK (2.00)) (SETUP DQA0 CLK (2.00)) (SETUP ADVNeg CLK (2.00)) (SETUP ADSCNeg CLK (2.00)) (SETUP BWANeg CLK (2.00)) (SETUP CE2 CLK (2.00)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) MT58L512L18PT-6Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PT-6ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-6Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-6ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-6Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-6ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.50:3.50) (1.50:2.50:3.50) (1.17:2.33:3.50) (1.50:2.50:3.50) (1.17:2.33:3.50) (1.50:2.50:3.50)) (IOPATH OENeg DQA0 () () (1.17:2.33:3.50) (1.17:2.33:3.50) (1.17:2.33:3.50) (1.17:2.33:3.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(2.30)) (WIDTH (negedge CLK)(2.30)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) MT58L512L18PT-7.5Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PT-7.5ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-7.5Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-7.5ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-7.5Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-7.5ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.75:4.00) (1.50:2.75:4.00) (1.40:2.80:4.20) (1.50:2.75:4.00) (1.40:2.80:4.20) (1.50:2.75:4.00)) (IOPATH OENeg DQA0 () () (1.40:2.80:4.20) (1.40:2.80:4.20) (1.40:2.80:4.20) (1.40:2.80:4.20)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.50)) (WIDTH (posedge CLK)(2.50)) (WIDTH (negedge CLK)(2.50)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) MT58L512L18PT-10Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PT-10ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-10Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PS-10ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-10Micron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 MT58L512L18PF-10ITMicron Technology, Inc., MT58L512L18P.p65 - Rev 2/02 The values listed are for VDD=+3.3V+0.3V/-0.165V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00) (1.67:3.33:5.00)) (IOPATH OENeg DQA0 () () (1.50:3.00:4.50) (1.67:3.33:5.00) (1.50:3.00:4.50) (1.67:3.33:5.00)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10.00)) (WIDTH (posedge CLK)(3.00)) (WIDTH (negedge CLK)(3.00)) (SETUP A0 CLK (2.00)) (SETUP DQA0 CLK (2.00)) (SETUP ADVNeg CLK (2.00)) (SETUP ADSCNeg CLK (2.00)) (SETUP BWANeg CLK (2.00)) (SETUP CE2 CLK (2.00)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) GS88118AT-250Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-250IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.00:2.50) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50) (1.50:2.00:2.30) (1.50:2.00:2.50)) (IOPATH OENeg DQA0 () () (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30) (0.77:1.53:2.30)) )) (TIMINGCHECK (PERIOD (posedge CLK) (4.00)) (WIDTH (posedge CLK)(1.30)) (WIDTH (negedge CLK)(1.50)) (SETUP A0 CLK (1.20)) (SETUP DQA0 CLK (1.20)) (SETUP ADVNeg CLK (1.20)) (SETUP ADSCNeg CLK (1.20)) (SETUP BWANeg CLK (1.20)) (SETUP CE2 CLK (1.20)) (HOLD A0 CLK (0.20)) (HOLD DQA0 CLK (0.20)) (HOLD ADSCNeg CLK (0.20)) (HOLD BWANeg CLK (0.20)) (HOLD ADVNeg CLK (0.20)) (HOLD CE2 CLK (0.20)) ) GS88118AT-225Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-225IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.10:2.70) (1.50:2.10:2.70) (1.50:2.10:2.50) (1.50:2.10:2.70) (1.50:2.10:2.50) (1.50:2.10:2.70)) (IOPATH OENeg DQA0 () () (0.83:1.67:2.50) (0.83:1.67:2.50) (0.83:1.67:2.50) (0.83:1.67:2.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (4.40)) (WIDTH (posedge CLK)(1.30)) (WIDTH (negedge CLK)(1.50)) (SETUP A0 CLK (1.30)) (SETUP DQA0 CLK (1.30)) (SETUP ADVNeg CLK (1.30)) (SETUP ADSCNeg CLK (1.30)) (SETUP BWANeg CLK (1.30)) (SETUP CE2 CLK (1.30)) (HOLD A0 CLK (0.30)) (HOLD DQA0 CLK (0.30)) (HOLD ADSCNeg CLK (0.30)) (HOLD BWANeg CLK (0.30)) (HOLD ADVNeg CLK (0.30)) (HOLD CE2 CLK (0.30)) ) GS88118AT-200Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-200IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.25:3.00) (1.50:2.25:3.00) (1.50:2.40:3.00) (1.50:2.25:3.00) (1.50:2.40:3.00) (1.50:2.25:3.00)) (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.07:2.13:3.20) (1.00:2.00:3.00) (1.07:2.13:3.20)) )) (TIMINGCHECK (PERIOD (posedge CLK) (5.00)) (WIDTH (posedge CLK)(1.30)) (WIDTH (negedge CLK)(1.50)) (SETUP A0 CLK (1.40)) (SETUP DQA0 CLK (1.40)) (SETUP ADVNeg CLK (1.40)) (SETUP ADSCNeg CLK (1.40)) (SETUP BWANeg CLK (1.40)) (SETUP CE2 CLK (1.40)) (HOLD A0 CLK (0.40)) (HOLD DQA0 CLK (0.40)) (HOLD ADSCNeg CLK (0.40)) (HOLD BWANeg CLK (0.40)) (HOLD ADVNeg CLK (0.40)) (HOLD CE2 CLK (0.40)) ) GS88118AT-166Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-166IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.45:3.40) (1.50:2.45:3.40) (1.50:2.40:3.00) (1.50:2.45:3.40) (1.50:2.40:3.00) (1.50:2.45:3.40)) (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.17:2.33:3.50) (1.00:2.00:3.00) (1.17:2.33:3.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(1.30)) (WIDTH (negedge CLK)(1.50)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) GS88118AT-150Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-150IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.65:3.80) (1.50:2.65:3.80) (1.50:2.40:3.00) (1.50:2.65:3.80) (1.50:2.40:3.00) (1.50:2.65:3.80)) (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.27:2.53:3.80) (1.00:2.00:3.00) (1.27:2.53:3.80)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.70)) (WIDTH (posedge CLK)(1.50)) (WIDTH (negedge CLK)(1.70)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) GS88118AT-133Giga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 GS88118AT-133IGiga Semiconductor, Inc., 88118A_r1_02, Rev 1.02, 9/2002 The values listed are for VDD=3.0Vto3.6V, commercial TA=0Cto+70C, industrial TA=-40Cto+85C (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.50:2.75:4.00) (1.50:2.75:4.00) (1.50:2.40:3.00) (1.50:2.75:4.00) (1.50:2.40:3.00) (1.50:2.75:4.00)) (IOPATH OENeg DQA0 () () (1.00:2.00:3.00) (1.33:2.67:4.00) (1.00:2.00:3.00) (1.33:2.67:4.00)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.50)) (WIDTH (posedge CLK)(1.70)) (WIDTH (negedge CLK)(2.00)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362B-250AC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250AJC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250BGC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250BZC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:1.90:2.60) (1.25:1.90:2.60) (1.25:1.90:2.60) (1.25:1.90:2.60) (1.25:1.90:2.60) (1.25:1.90:2.60)) (IOPATH OENeg DQA0 () () (0.00:1.30:2.60) (0.87:1.73:2.60) (0.00:1.30:2.60) (0.87:1.73:2.60)) )) (TIMINGCHECK (PERIOD (posedge CLK) (4.00)) (WIDTH (posedge CLK)(1.70)) (WIDTH (negedge CLK)(1.70)) (SETUP A0 CLK (1.20)) (SETUP DQA0 CLK (1.20)) (SETUP ADVNeg CLK (1.20)) (SETUP ADSCNeg CLK (1.20)) (SETUP BWANeg CLK (1.20)) (SETUP CE2 CLK (1.20)) (HOLD A0 CLK (0.30)) (HOLD DQA0 CLK (0.30)) (HOLD ADSCNeg CLK (0.30)) (HOLD BWANeg CLK (0.30)) (HOLD ADVNeg CLK (0.30)) (HOLD CE2 CLK (0.30)) ) CY7C1362B-250AC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250AJC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250BGC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-250BZC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=2.5V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.35:3.40) (1.25:2.35:3.40) (1.25:2.35:3.40) (1.25:2.35:3.40) (1.25:2.35:3.40) (1.25:2.35:3.40)) (IOPATH OENeg DQA0 () () (0.00:1.70:3.40) (1.13:2.27:3.40) (0.00:1.70:3.40) (1.13:2.27:3.40)) )) (TIMINGCHECK (PERIOD (posedge CLK) (4.00)) (WIDTH (posedge CLK)(1.70)) (WIDTH (negedge CLK)(1.70)) (SETUP A0 CLK (1.20)) (SETUP DQA0 CLK (1.20)) (SETUP ADVNeg CLK (1.20)) (SETUP ADSCNeg CLK (1.20)) (SETUP BWANeg CLK (1.20)) (SETUP CE2 CLK (1.20)) (HOLD A0 CLK (0.80)) (HOLD DQA0 CLK (0.80)) (HOLD ADSCNeg CLK (0.80)) (HOLD BWANeg CLK (0.80)) (HOLD ADVNeg CLK (0.80)) (HOLD CE2 CLK (0.80)) ) CY7C1362B-200AC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200AJC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200BGC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200BZC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00) (1.25:2.15:3.00)) (IOPATH OENeg DQA0 () () (0.00:1.50:3.00) (1.00:2.00:3.00) (0.00:1.50:3.00) (1.00:2.00:3.00)) )) (TIMINGCHECK (PERIOD (posedge CLK) (5.00)) (WIDTH (posedge CLK)(2.00)) (WIDTH (negedge CLK)(2.00)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362B-200AC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200AJC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200BGC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-200BZC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=2.5V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.27:2.53:3.80) (1.27:2.53:3.80) (1.25:2.55:3.80) (1.27:2.53:3.80) (1.25:2.55:3.80) (1.27:2.53:3.80)) (IOPATH OENeg DQA0 () () (0.00:1.90:3.80) (1.27:2.53:3.80) (0.00:1.90:3.80) (1.27:2.53:3.80)) )) (TIMINGCHECK (PERIOD (posedge CLK) (5.00)) (WIDTH (posedge CLK)(2.00)) (WIDTH (negedge CLK)(2.00)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.80)) (HOLD DQA0 CLK (0.80)) (HOLD ADSCNeg CLK (0.80)) (HOLD BWANeg CLK (0.80)) (HOLD ADVNeg CLK (0.80)) (HOLD CE2 CLK (0.80)) ) CY7C1362B-166AC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166AJC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166BGC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166BZC_3V3Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=3.3V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50) (1.25:2.40:3.50)) (IOPATH OENeg DQA0 () () (0.00:1.75:3.50) (1.17:2.33:3.50) (0.00:1.75:3.50) (1.17:2.33:3.50)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(2.40)) (WIDTH (negedge CLK)(2.40)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.50)) (HOLD DQA0 CLK (0.50)) (HOLD ADSCNeg CLK (0.50)) (HOLD BWANeg CLK (0.50)) (HOLD ADVNeg CLK (0.50)) (HOLD CE2 CLK (0.50)) ) CY7C1362B-166AC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166AJC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166BGC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 CY7C1362B-166BZC_2V5Cypress Semiconductor Corporation, 38-05291, Rev A, August 15, 2002 The values listed are for VDD=3.135Vto3.6V, commercial TA=0Cto+70C, VDDQ=2.5V (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.43:2.87:4.30) (1.43:2.87:4.30) (1.25:2.80:4.30) (1.43:2.87:4.30) (1.25:2.80:4.30) (1.43:2.87:4.30)) (IOPATH OENeg DQA0 () () (0.00:2.15:4.30) (1.43:2.87:4.30) (0.00:2.15:4.30) (1.43:2.87:4.30)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.00)) (WIDTH (posedge CLK)(2.40)) (WIDTH (negedge CLK)(2.40)) (SETUP A0 CLK (1.50)) (SETUP DQA0 CLK (1.50)) (SETUP ADVNeg CLK (1.50)) (SETUP ADSCNeg CLK (1.50)) (SETUP BWANeg CLK (1.50)) (SETUP CE2 CLK (1.50)) (HOLD A0 CLK (0.80)) (HOLD DQA0 CLK (0.80)) (HOLD ADSCNeg CLK (0.80)) (HOLD BWANeg CLK (0.80)) (HOLD ADVNeg CLK (0.80)) (HOLD CE2 CLK (0.80)) )