-------------------------------------------------------------------------------- -- File Name: cy7c1361.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 D. Randjelovic 05 Nov 25 Inital Release -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: SRAM -- Technology: CMOS -- Part: CY7C1361 -- -- Description: 256K x36 Synchronous Flow-Thru Burst SRAM -- -- For correct simulation, simulator resolution should be set to 1ps -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; USE STD.textio.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY cy7c1361 IS GENERIC ( -- tipd delays: interconnect path delays tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQA8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQB8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQC8 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD0 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD1 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD2 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD3 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD4 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD5 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD6 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD7 : VitalDelayType01 := VitalZeroDelay01; tipd_DQD8 : VitalDelayType01 := VitalZeroDelay01; tipd_BWANeg : VitalDelayType01 := VitalZeroDelay01; tipd_BWBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BWCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BWDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_GWNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BWENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CENeg : VitalDelayType01 := VitalZeroDelay01; tipd_CE2 : VitalDelayType01 := VitalZeroDelay01; tipd_CE2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADVNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSPNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ADSCNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MODE : VitalDelayType01 := VitalZeroDelay01; tipd_ZZ : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_CLK_DQA0 : VitalDelayType01Z := UnitDelay01Z; tpd_CLK_DQA1 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_DQA0 : VitalDelayType01Z := UnitDelay01Z; tpd_OENeg_DQA1 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := UnitDelay; tpw_CLK_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) tperiod_CLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times tsetup_A0_CLK : VitalDelayType := UnitDelay; tsetup_DQA0_CLK : VitalDelayType := UnitDelay; tsetup_ADVNeg_CLK : VitalDelayType := UnitDelay; tsetup_ADSCNeg_CLK : VitalDelayType := UnitDelay; tsetup_CE2_CLK : VitalDelayType := UnitDelay; tsetup_BWANeg_CLK : VitalDelayType := UnitDelay; -- thold values: hold times thold_A0_CLK : VitalDelayType := UnitDelay; thold_DQA0_CLK : VitalDelayType := UnitDelay; thold_ADVNeg_CLK : VitalDelayType := UnitDelay; thold_ADSCNeg_CLK : VitalDelayType := UnitDelay; thold_CE2_CLK : VitalDelayType := UnitDelay; thold_BWANeg_CLK : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- memory file to be loaded mem_file_name : STRING := "none"; --"cy7c1361.mem"; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : IN std_logic := 'U'; A1 : IN std_logic := 'U'; A2 : IN std_logic := 'U'; A3 : IN std_logic := 'U'; A4 : IN std_logic := 'U'; A5 : IN std_logic := 'U'; A6 : IN std_logic := 'U'; A7 : IN std_logic := 'U'; A8 : IN std_logic := 'U'; A9 : IN std_logic := 'U'; A10 : IN std_logic := 'U'; A11 : IN std_logic := 'U'; A12 : IN std_logic := 'U'; A13 : IN std_logic := 'U'; A14 : IN std_logic := 'U'; A15 : IN std_logic := 'U'; A16 : IN std_logic := 'U'; A17 : IN std_logic := 'U'; DQA0 : INOUT std_logic := 'U'; DQA1 : INOUT std_logic := 'U'; DQA2 : INOUT std_logic := 'U'; DQA3 : INOUT std_logic := 'U'; DQA4 : INOUT std_logic := 'U'; DQA5 : INOUT std_logic := 'U'; DQA6 : INOUT std_logic := 'U'; DQA7 : INOUT std_logic := 'U'; DQA8 : INOUT std_logic := 'U'; DQB0 : INOUT std_logic := 'U'; DQB1 : INOUT std_logic := 'U'; DQB2 : INOUT std_logic := 'U'; DQB3 : INOUT std_logic := 'U'; DQB4 : INOUT std_logic := 'U'; DQB5 : INOUT std_logic := 'U'; DQB6 : INOUT std_logic := 'U'; DQB7 : INOUT std_logic := 'U'; DQB8 : INOUT std_logic := 'U'; DQC0 : INOUT std_logic := 'U'; DQC1 : INOUT std_logic := 'U'; DQC2 : INOUT std_logic := 'U'; DQC3 : INOUT std_logic := 'U'; DQC4 : INOUT std_logic := 'U'; DQC5 : INOUT std_logic := 'U'; DQC6 : INOUT std_logic := 'U'; DQC7 : INOUT std_logic := 'U'; DQC8 : INOUT std_logic := 'U'; DQD0 : INOUT std_logic := 'U'; DQD1 : INOUT std_logic := 'U'; DQD2 : INOUT std_logic := 'U'; DQD3 : INOUT std_logic := 'U'; DQD4 : INOUT std_logic := 'U'; DQD5 : INOUT std_logic := 'U'; DQD6 : INOUT std_logic := 'U'; DQD7 : INOUT std_logic := 'U'; DQD8 : INOUT std_logic := 'U'; BWANeg : IN std_logic := 'U'; BWBNeg : IN std_logic := 'U'; BWCNeg : IN std_logic := 'U'; BWDNeg : IN std_logic := 'U'; GWNeg : IN std_logic := 'U'; BWENeg : IN std_logic := 'U'; CLK : IN std_logic := 'U'; CENeg : IN std_logic := 'U'; CE2 : IN std_logic := 'U'; CE2Neg : IN std_logic := 'U'; OENeg : IN std_logic := 'U'; ADVNeg : IN std_logic := 'U'; ADSPNeg : IN std_logic := 'U'; ADSCNeg : IN std_logic := 'U'; MODE : IN std_logic := 'U'; ZZ : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy7c1361 : ENTITY IS TRUE; END cy7c1361; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of cy7c1361 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "cy7c1361"; -- ipd SIGNAL A0_ipd : std_ulogic := 'U'; SIGNAL A1_ipd : std_ulogic := 'U'; SIGNAL A2_ipd : std_ulogic := 'U'; SIGNAL A3_ipd : std_ulogic := 'U'; SIGNAL A4_ipd : std_ulogic := 'U'; SIGNAL A5_ipd : std_ulogic := 'U'; SIGNAL A6_ipd : std_ulogic := 'U'; SIGNAL A7_ipd : std_ulogic := 'U'; SIGNAL A8_ipd : std_ulogic := 'U'; SIGNAL A9_ipd : std_ulogic := 'U'; SIGNAL A10_ipd : std_ulogic := 'U'; SIGNAL A11_ipd : std_ulogic := 'U'; SIGNAL A12_ipd : std_ulogic := 'U'; SIGNAL A13_ipd : std_ulogic := 'U'; SIGNAL A14_ipd : std_ulogic := 'U'; SIGNAL A15_ipd : std_ulogic := 'U'; SIGNAL A16_ipd : std_ulogic := 'U'; SIGNAL A17_ipd : std_ulogic := 'U'; SIGNAL DQA0_ipd : std_ulogic := 'U'; SIGNAL DQA1_ipd : std_ulogic := 'U'; SIGNAL DQA2_ipd : std_ulogic := 'U'; SIGNAL DQA3_ipd : std_ulogic := 'U'; SIGNAL DQA4_ipd : std_ulogic := 'U'; SIGNAL DQA5_ipd : std_ulogic := 'U'; SIGNAL DQA6_ipd : std_ulogic := 'U'; SIGNAL DQA7_ipd : std_ulogic := 'U'; SIGNAL DQA8_ipd : std_ulogic := 'U'; SIGNAL DQB0_ipd : std_ulogic := 'U'; SIGNAL DQB1_ipd : std_ulogic := 'U'; SIGNAL DQB2_ipd : std_ulogic := 'U'; SIGNAL DQB3_ipd : std_ulogic := 'U'; SIGNAL DQB4_ipd : std_ulogic := 'U'; SIGNAL DQB5_ipd : std_ulogic := 'U'; SIGNAL DQB6_ipd : std_ulogic := 'U'; SIGNAL DQB7_ipd : std_ulogic := 'U'; SIGNAL DQB8_ipd : std_ulogic := 'U'; SIGNAL DQC0_ipd : std_ulogic := 'U'; SIGNAL DQC1_ipd : std_ulogic := 'U'; SIGNAL DQC2_ipd : std_ulogic := 'U'; SIGNAL DQC3_ipd : std_ulogic := 'U'; SIGNAL DQC4_ipd : std_ulogic := 'U'; SIGNAL DQC5_ipd : std_ulogic := 'U'; SIGNAL DQC6_ipd : std_ulogic := 'U'; SIGNAL DQC7_ipd : std_ulogic := 'U'; SIGNAL DQC8_ipd : std_ulogic := 'U'; SIGNAL DQD0_ipd : std_ulogic := 'U'; SIGNAL DQD1_ipd : std_ulogic := 'U'; SIGNAL DQD2_ipd : std_ulogic := 'U'; SIGNAL DQD3_ipd : std_ulogic := 'U'; SIGNAL DQD4_ipd : std_ulogic := 'U'; SIGNAL DQD5_ipd : std_ulogic := 'U'; SIGNAL DQD6_ipd : std_ulogic := 'U'; SIGNAL DQD7_ipd : std_ulogic := 'U'; SIGNAL DQD8_ipd : std_ulogic := 'U'; SIGNAL BWANeg_ipd : std_ulogic := 'U'; SIGNAL BWBNeg_ipd : std_ulogic := 'U'; SIGNAL BWCNeg_ipd : std_ulogic := 'U'; SIGNAL BWDNeg_ipd : std_ulogic := 'U'; SIGNAL GWNeg_ipd : std_ulogic := 'U'; SIGNAL BWENeg_ipd : std_ulogic := 'U'; SIGNAL CLK_ipd : std_ulogic := 'U'; SIGNAL CENeg_ipd : std_ulogic := 'U'; SIGNAL CE2_ipd : std_ulogic := 'U'; SIGNAL OENeg_ipd : std_ulogic := 'U'; SIGNAL CE2Neg_ipd : std_ulogic := 'U'; SIGNAL ADVNeg_ipd : std_ulogic := 'U'; SIGNAL ADSPNeg_ipd : std_ulogic := 'U'; SIGNAL ADSCNeg_ipd : std_ulogic := 'U'; SIGNAL MODE_ipd : std_ulogic := 'U'; SIGNAL ZZ_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_01 : VitalWireDelay (A0_ipd, A0, tipd_A0); w_02 : VitalWireDelay (A1_ipd, A1, tipd_A1); w_03 : VitalWireDelay (A2_ipd, A2, tipd_A2); w_04 : VitalWireDelay (A3_ipd, A3, tipd_A3); w_05 : VitalWireDelay (A4_ipd, A4, tipd_A4); w_06 : VitalWireDelay (A5_ipd, A5, tipd_A5); w_07 : VitalWireDelay (A6_ipd, A6, tipd_A6); w_08 : VitalWireDelay (A7_ipd, A7, tipd_A7); w_09 : VitalWireDelay (A8_ipd, A8, tipd_A8); w_10 : VitalWireDelay (A9_ipd, A9, tipd_A9); w_11 : VitalWireDelay (A10_ipd, A10, tipd_A10); w_12 : VitalWireDelay (A11_ipd, A11, tipd_A11); w_13 : VitalWireDelay (A12_ipd, A12, tipd_A12); w_14 : VitalWireDelay (A13_ipd, A13, tipd_A13); w_15 : VitalWireDelay (A14_ipd, A14, tipd_A14); w_16 : VitalWireDelay (A15_ipd, A15, tipd_A15); w_17 : VitalWireDelay (A16_ipd, A16, tipd_A16); w_18 : VitalWireDelay (A17_ipd, A17, tipd_A17); w_19 : VitalWireDelay (DQA0_ipd, DQA0, tipd_DQA0); w_20 : VitalWireDelay (DQA1_ipd, DQA1, tipd_DQA1); w_21 : VitalWireDelay (DQA2_ipd, DQA2, tipd_DQA2); w_22 : VitalWireDelay (DQA3_ipd, DQA3, tipd_DQA3); w_23 : VitalWireDelay (DQA4_ipd, DQA4, tipd_DQA4); w_24 : VitalWireDelay (DQA5_ipd, DQA5, tipd_DQA5); w_25 : VitalWireDelay (DQA6_ipd, DQA6, tipd_DQA6); w_26 : VitalWireDelay (DQA7_ipd, DQA7, tipd_DQA7); w_27 : VitalWireDelay (DQA8_ipd, DQA8, tipd_DQA8); w_28 : VitalWireDelay (DQB0_ipd, DQB0, tipd_DQB0); w_29 : VitalWireDelay (DQB1_ipd, DQB1, tipd_DQB1); w_30 : VitalWireDelay (DQB2_ipd, DQB2, tipd_DQB2); w_31 : VitalWireDelay (DQB3_ipd, DQB3, tipd_DQB3); w_32 : VitalWireDelay (DQB4_ipd, DQB4, tipd_DQB4); w_33 : VitalWireDelay (DQB5_ipd, DQB5, tipd_DQB5); w_34 : VitalWireDelay (DQB6_ipd, DQB6, tipd_DQB6); w_35 : VitalWireDelay (DQB7_ipd, DQB7, tipd_DQB7); w_36 : VitalWireDelay (DQB8_ipd, DQB8, tipd_DQB8); w_37 : VitalWireDelay (DQC0_ipd, DQC0, tipd_DQC0); w_38 : VitalWireDelay (DQC1_ipd, DQC1, tipd_DQC1); w_39 : VitalWireDelay (DQC2_ipd, DQC2, tipd_DQC2); w_40 : VitalWireDelay (DQC3_ipd, DQC3, tipd_DQC3); w_41 : VitalWireDelay (DQC4_ipd, DQC4, tipd_DQC4); w_42 : VitalWireDelay (DQC5_ipd, DQC5, tipd_DQC5); w_43 : VitalWireDelay (DQC6_ipd, DQC6, tipd_DQC6); w_44 : VitalWireDelay (DQC7_ipd, DQC7, tipd_DQC7); w_45 : VitalWireDelay (DQC8_ipd, DQC8, tipd_DQC8); w_46 : VitalWireDelay (DQD0_ipd, DQD0, tipd_DQD0); w_47 : VitalWireDelay (DQD1_ipd, DQD1, tipd_DQD1); w_48 : VitalWireDelay (DQD2_ipd, DQD2, tipd_DQD2); w_49 : VitalWireDelay (DQD3_ipd, DQD3, tipd_DQD3); w_50 : VitalWireDelay (DQD4_ipd, DQD4, tipd_DQD4); w_51 : VitalWireDelay (DQD5_ipd, DQD5, tipd_DQD5); w_52 : VitalWireDelay (DQD6_ipd, DQD6, tipd_DQD6); w_53 : VitalWireDelay (DQD7_ipd, DQD7, tipd_DQD7); w_54 : VitalWireDelay (DQD8_ipd, DQD8, tipd_DQD8); w_55 : VitalWireDelay (BWANeg_ipd, BWANeg, tipd_BWANeg); w_56 : VitalWireDelay (BWBNeg_ipd, BWBNeg, tipd_BWBNeg); w_57 : VitalWireDelay (BWCNeg_ipd, BWCNeg, tipd_BWCNeg); w_58 : VitalWireDelay (BWDNeg_ipd, BWDNeg, tipd_BWDNeg); w_59 : VitalWireDelay (GWNeg_ipd, GWNeg, tipd_GWNeg); w_60 : VitalWireDelay (BWENeg_ipd, BWENeg, tipd_BWENeg); w_61 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_62 : VitalWireDelay (CENeg_ipd, CENeg, tipd_CENeg); w_63 : VitalWireDelay (CE2_ipd, CE2, tipd_CE2); w_64 : VitalWireDelay (CE2Neg_ipd, CE2Neg, tipd_CE2Neg); w_65 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg); w_66 : VitalWireDelay (ADVNeg_ipd, ADVNeg, tipd_ADVNeg); w_67 : VitalWireDelay (ADSPNeg_ipd, ADSPNeg, tipd_ADSPNeg); w_68 : VitalWireDelay (ADSCNeg_ipd, ADSCNeg, tipd_ADSCNeg); w_69 : VitalWireDelay (MODE_ipd, MODE, tipd_MODE); w_70 : VitalWireDelay (ZZ_ipd, ZZ, tipd_ZZ); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( BWANIn : IN std_ulogic := 'U'; BWBNIn : IN std_ulogic := 'U'; BWCNIn : IN std_ulogic := 'U'; BWDNIn : IN std_ulogic := 'U'; GWNIn : IN std_ulogic := 'U'; BWENIn : IN std_ulogic := 'U'; DatAIn : IN std_logic_vector(8 downto 0); DatBIn : IN std_logic_vector(8 downto 0); DatCIn : IN std_logic_vector(8 downto 0); DatDIn : IN std_logic_vector(8 downto 0); DataOut : OUT std_logic_vector(35 downto 0) := (others => 'Z'); CLKIn : IN std_ulogic := 'U'; AddressIn : IN std_logic_vector(17 downto 0); OENegIn : IN std_ulogic := 'U'; ADVNIn : IN std_ulogic := 'U'; ADSPNIn : IN std_ulogic := 'U'; ADSCNIn : IN std_ulogic := 'U'; MODEIn : IN std_ulogic := 'U'; ZZIn : IN std_ulogic := 'U'; CE2In : IN std_ulogic := 'U'; CENegIn : IN std_ulogic := 'U'; CE2NegIn : IN std_ulogic := 'U' ); PORT MAP ( BWANIn => BWANeg_ipd, BWBNIn => BWBNeg_ipd, BWCNIn => BWCNeg_ipd, BWDNIn => BWDNeg_ipd, GWNIn => GWNeg_ipd, BWENIn => BWENeg_ipd, CLKIn => CLK_ipd, OENegIn => OENeg_ipd, ADVNIn => ADVNeg_ipd, ADSPNIn => ADSPNeg_ipd, ADSCNIn => ADSCNeg_ipd, MODEIn => MODE_ipd, ZZIn => ZZ_ipd, CE2In => CE2_ipd, CENegIn => CENeg_ipd, CE2NegIn => CE2Neg_ipd, DataOut(0) => DQA0, DataOut(1) => DQA1, DataOut(2) => DQA2, DataOut(3) => DQA3, DataOut(4) => DQA4, DataOut(5) => DQA5, DataOut(6) => DQA6, DataOut(7) => DQA7, DataOut(8) => DQA8, DataOut(9) => DQB0, DataOut(10) => DQB1, DataOut(11) => DQB2, DataOut(12) => DQB3, DataOut(13) => DQB4, DataOut(14) => DQB5, DataOut(15) => DQB6, DataOut(16) => DQB7, DataOut(17) => DQB8, DataOut(18) => DQC0, DataOut(19) => DQC1, DataOut(20) => DQC2, DataOut(21) => DQC3, DataOut(22) => DQC4, DataOut(23) => DQC5, DataOut(24) => DQC6, DataOut(25) => DQC7, DataOut(26) => DQC8, DataOut(27) => DQD0, DataOut(28) => DQD1, DataOut(29) => DQD2, DataOut(30) => DQD3, DataOut(31) => DQD4, DataOut(32) => DQD5, DataOut(33) => DQD6, DataOut(34) => DQD7, DataOut(35) => DQD8, DatAIn(0) => DQA0_ipd, DatAIn(1) => DQA1_ipd, DatAIn(2) => DQA2_ipd, DatAIn(3) => DQA3_ipd, DatAIn(4) => DQA4_ipd, DatAIn(5) => DQA5_ipd, DatAIn(6) => DQA6_ipd, DatAIn(7) => DQA7_ipd, DatAIn(8) => DQA8_ipd, DatBIn(0) => DQB0_ipd, DatBIn(1) => DQB1_ipd, DatBIn(2) => DQB2_ipd, DatBIn(3) => DQB3_ipd, DatBIn(4) => DQB4_ipd, DatBIn(5) => DQB5_ipd, DatBIn(6) => DQB6_ipd, DatBIn(7) => DQB7_ipd, DatBIn(8) => DQB8_ipd, DatCIn(0) => DQC0_ipd, DatCIn(1) => DQC1_ipd, DatCIn(2) => DQC2_ipd, DatCIn(3) => DQC3_ipd, DatCIn(4) => DQC4_ipd, DatCIn(5) => DQC5_ipd, DatCIn(6) => DQC6_ipd, DatCIn(7) => DQC7_ipd, DatCIn(8) => DQC8_ipd, DatDIn(0) => DQD0_ipd, DatDIn(1) => DQD1_ipd, DatDIn(2) => DQD2_ipd, DatDIn(3) => DQD3_ipd, DatDIn(4) => DQD4_ipd, DatDIn(5) => DQD5_ipd, DatDIn(6) => DQD6_ipd, DatDIn(7) => DQD7_ipd, DatDIn(8) => DQD8_ipd, AddressIn(0) => A0_ipd, AddressIn(1) => A1_ipd, AddressIn(2) => A2_ipd, AddressIn(3) => A3_ipd, AddressIn(4) => A4_ipd, AddressIn(5) => A5_ipd, AddressIn(6) => A6_ipd, AddressIn(7) => A7_ipd, AddressIn(8) => A8_ipd, AddressIn(9) => A9_ipd, AddressIn(10) => A10_ipd, AddressIn(11) => A11_ipd, AddressIn(12) => A12_ipd, AddressIn(13) => A13_ipd, AddressIn(14) => A14_ipd, AddressIn(15) => A15_ipd, AddressIn(16) => A16_ipd, AddressIn(17) => A17_ipd ); -- Type definition for state machine TYPE mem_state IS (desel, begin_rdwr, SPwrite, SCwrite, read ); SIGNAL state : mem_state; TYPE sequence IS ARRAY (0 to 3) OF INTEGER RANGE -3 to 3; TYPE seqtab IS ARRAY (0 to 3) OF sequence; FILE mem_file : text IS mem_file_name; CONSTANT il0 : sequence := (0, 1, 2, 3); CONSTANT il1 : sequence := (0, -1, 2, 1); CONSTANT il2 : sequence := (0, 1, -2, -1); CONSTANT il3 : sequence := (0, -1, -2, -3); CONSTANT il : seqtab := (il0, il1, il2, il3); CONSTANT ln0 : sequence := (0, 1, 2, 3); CONSTANT ln1 : sequence := (0, 1, 2, -1); CONSTANT ln2 : sequence := (0, 1, -2, -1); CONSTANT ln3 : sequence := (0, -3, -2, -1); CONSTANT ln : seqtab := (ln0, ln1, ln2, ln3); CONSTANT MemSize : INTEGER := 16#3FFFF#; -- 256K CONSTANT MaxData : INTEGER := 16#1FF#; -- 511 -- Memory array declaration TYPE MemStore IS ARRAY (0 to MemSize) OF INTEGER RANGE -2 TO MaxData; SHARED VARIABLE MemDataA : MemStore; SHARED VARIABLE MemDataB : MemStore; SHARED VARIABLE MemDataC : MemStore; SHARED VARIABLE MemDataD : MemStore; -- Functionality Results Variables SHARED VARIABLE Violation : X01 := '0'; SHARED VARIABLE OBuf1 : std_logic_vector(35 DOWNTO 0) := (OTHERS => 'Z'); SIGNAL Burst_Seq : seqtab := ln; SIGNAL D_zd : std_logic_vector(35 DOWNTO 0); PROCEDURE ReadMem (RAddr : IN natural) IS BEGIN IF MemDataA(RAddr) = -2 THEN OBuf1(8 downto 0) := (others => 'U'); ELSIF MemDataA(RAddr) = -1 THEN OBuf1(8 downto 0) := (others => 'X'); ELSE OBuf1(8 downto 0) := to_slv(MemDataA(RAddr),9); END IF; IF MemDataB(RAddr) = -2 THEN OBuf1(17 downto 9) := (others => 'U'); ELSIF MemDataB(RAddr) = -1 THEN OBuf1(17 downto 9) := (others => 'X'); ELSE OBuf1(17 downto 9) := to_slv(MemDataB(RAddr),9); END IF; IF MemDataC(RAddr) = -2 THEN OBuf1(26 downto 18) := (others => 'U'); ELSIF MemDataC(RAddr) = -1 THEN OBuf1(26 downto 18) := (others => 'X'); ELSE OBuf1(26 downto 18) := to_slv(MemDataC(RAddr),9); END IF; IF MemDataD(RAddr) = -2 THEN OBuf1(35 downto 27) := (others => 'U'); ELSIF MemDataD(RAddr) = -1 THEN OBuf1(35 downto 27) := (others => 'X'); ELSE OBuf1(35 downto 27) := to_slv(MemDataD(RAddr),9); END IF; END PROCEDURE ReadMem; PROCEDURE WriteMem (WAddr : IN natural; WDatA : IN std_logic_vector(8 downto 0); WDatB : IN std_logic_vector(8 downto 0); WDatC : IN std_logic_vector(8 downto 0); WDatD : IN std_logic_vector(8 downto 0); WGWN : IN std_logic; WBWA : IN std_logic; WBWB : IN std_logic; WBWC : IN std_logic; WBWD : IN std_logic) IS BEGIN IF WGWN = '0' THEN MemDataA(WAddr) := -1; MemDataB(WAddr) := -1; MemDataC(WAddr) := -1; MemDataD(WAddr) := -1; IF Violation /= 'X' THEN MemDataA(WAddr) := to_nat(WDatA); MemDataB(WAddr) := to_nat(WDatB); MemDataC(WAddr) := to_nat(WDatC); MemDataD(WAddr) := to_nat(WDatD); END IF; ELSE IF (WBWA = '0') THEN MemDataA(WAddr) := -1; IF Violation /= 'X' THEN MemDataA(WAddr) := to_nat(WDatA); END IF; END IF; IF (WBWB = '0') THEN MemDataB(WAddr) := -1; IF Violation /= 'X' THEN MemDataB(WAddr) := to_nat(WDatB); END IF; END IF; IF (WBWC = '0') THEN MemDataC(WAddr) := -1; IF Violation /= 'X' THEN MemDataC(WAddr) := to_nat(WDatC); END IF; END IF; IF (WBWD = '0') THEN MemDataD(WAddr) := -1; IF Violation /= 'X' THEN MemDataD(WAddr) := to_nat(WDatD); END IF; END IF; END IF; END PROCEDURE WriteMem; BEGIN Burst_Setup : PROCESS (MODEIn) BEGIN IF (MODEIn = '0') THEN Burst_Seq <= ln; -- linear burst ELSE Burst_Seq <= il; -- interleaved burst END IF; END PROCESS Burst_Setup; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- Behavior : PROCESS (BWANIn, BWBNIn, BWCNIn, BWDNIn, DatAIn, DatBIn, DatCIn, DatDIN, CLKIn, AddressIn, GWNIn, BWENIn, OENegIn, ADVNIn, ADSPNIn, ADSCNIn, CE2In, CENegIn, CE2NegIn, ZZIn) -- Type definition for commands TYPE command_type is (ds, SPwr_burst, SPwr_susp, SCwr, begin_rw, read_burst, read_susp ); -- Timing Check Variables VARIABLE Tviol_AddressIn_CLK : X01 := '0'; VARIABLE TD_AddressIn_CLK : VitalTimingDataType; VARIABLE Tviol_DatDIn_CLK : X01 := '0'; VARIABLE TD_DatDIn_CLK : VitalTimingDataType; VARIABLE Tviol_DatCIn_CLK : X01 := '0'; VARIABLE TD_DatCIn_CLK : VitalTimingDataType; VARIABLE Tviol_DatBIn_CLK : X01 := '0'; VARIABLE TD_DatBIn_CLK : VitalTimingDataType; VARIABLE Tviol_DatAIn_CLK : X01 := '0'; VARIABLE TD_DatAIn_CLK : VitalTimingDataType; VARIABLE Tviol_BWDN_CLK : X01 := '0'; VARIABLE TD_BWDN_CLK : VitalTimingDataType; VARIABLE Tviol_BWCN_CLK : X01 := '0'; VARIABLE TD_BWCN_CLK : VitalTimingDataType; VARIABLE Tviol_BWBN_CLK : X01 := '0'; VARIABLE TD_BWBN_CLK : VitalTimingDataType; VARIABLE Tviol_BWAN_CLK : X01 := '0'; VARIABLE TD_BWAN_CLK : VitalTimingDataType; VARIABLE Tviol_BWEN_CLK : X01 := '0'; VARIABLE TD_BWEN_CLK : VitalTimingDataType; VARIABLE Tviol_GWN_CLK : X01 := '0'; VARIABLE TD_GWN_CLK : VitalTimingDataType; VARIABLE Tviol_ADVNIn_CLK : X01 := '0'; VARIABLE TD_ADVNIn_CLK : VitalTimingDataType; VARIABLE Tviol_ADSCNIn_CLK : X01 := '0'; VARIABLE TD_ADSCNIn_CLK : VitalTimingDataType; VARIABLE Tviol_ADSPNIn_CLK : X01 := '0'; VARIABLE TD_ADSPNIn_CLK : VitalTimingDataType; VARIABLE Tviol_CENegIn_CLK : X01 := '0'; VARIABLE TD_CENegIn_CLK : VitalTimingDataType; VARIABLE Tviol_CE2NegIn_CLK : X01 := '0'; VARIABLE TD_CE2NegIn_CLK : VitalTimingDataType; VARIABLE Tviol_CE2In_CLK : X01 := '0'; VARIABLE TD_CE2In_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE MemAddr : NATURAL RANGE 0 TO MemSize; VARIABLE startaddr : NATURAL RANGE 0 TO MemSize; VARIABLE Burst_Cnt : NATURAL RANGE 0 TO 4 := 0; VARIABLE memstart : NATURAL RANGE 0 TO 3 := 0; VARIABLE offset : INTEGER RANGE -3 TO 3 := 0; VARIABLE command : command_type; VARIABLE R : std_logic; VARIABLE zz_set : BOOLEAN := false; VARIABLE zz_reset : BOOLEAN := true; VARIABLE zz_cnt : INTEGER RANGE 0 TO 2 := 0; BEGIN -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => AddressIn, TestSignalName => "Address", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_A0_CLK, SetupLow => tsetup_A0_CLK, HoldHigh => thold_A0_CLK, HoldLow => thold_A0_CLK, CheckEnabled => (ZZIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_AddressIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_AddressIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatDIn, TestSignalName => "DatD", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (ZZIn ='0') AND (DatDIn/=D_zd(35 downto 27)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatDIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatDIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatCIn, TestSignalName => "DatC", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (ZZIn ='0') AND (DatCIn/=D_zd(26 downto 18)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatCIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatCIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatBIn, TestSignalName => "DatB", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (ZZIn ='0') AND (DatBIn/=D_zd(17 downto 9)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatBIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatBIn_CLK ); VitalSetupHoldCheck ( TestSignal => DatAIn, TestSignalName => "DatA", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_DQA0_CLK, SetupLow => tsetup_DQA0_CLK, HoldHigh => thold_DQA0_CLK, HoldLow => thold_DQA0_CLK, CheckEnabled => (ZZIn ='0') AND (DatAIn/=D_zd(8 downto 0)), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_DatAIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_DatAIn_CLK ); VitalSetupHoldCheck ( TestSignal => GWNIn, TestSignalName => "GW", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_GWN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_GWN_CLK ); VitalSetupHoldCheck ( TestSignal => BWENIn, TestSignalName => "BWE", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BWEN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BWEN_CLK ); VitalSetupHoldCheck ( TestSignal => BWDNIn, TestSignalName => "BWD", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BWDN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BWDN_CLK ); VitalSetupHoldCheck ( TestSignal => BWCNIn, TestSignalName => "BWC", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BWCN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BWCN_CLK ); VitalSetupHoldCheck ( TestSignal => BWBNIn, TestSignalName => "BWB", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BWBN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BWBN_CLK ); VitalSetupHoldCheck ( TestSignal => BWANIn, TestSignalName => "BWA", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_BWANeg_CLK, SetupLow => tsetup_BWANeg_CLK, HoldHigh => thold_BWANeg_CLK, HoldLow => thold_BWANeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_BWAN_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_BWAN_CLK ); VitalSetupHoldCheck ( TestSignal => ADVNIn, TestSignalName => "ADV", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_ADVNeg_CLK, SetupLow => tsetup_ADVNeg_CLK, HoldHigh => thold_ADVNeg_CLK, HoldLow => thold_ADVNeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADVNIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADVNIn_CLK ); VitalSetupHoldCheck ( TestSignal => ADSPNIn, TestSignalName => "ADSP", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_ADSCNeg_CLK, SetupLow => tsetup_ADSCNeg_CLK, HoldHigh => thold_ADSCNeg_CLK, HoldLow => thold_ADSCNeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSPNIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSPNIn_CLK ); VitalSetupHoldCheck ( TestSignal => ADSCNIn, TestSignalName => "ADSC", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_ADSCNeg_CLK, SetupLow => tsetup_ADSCNeg_CLK, HoldHigh => thold_ADSCNeg_CLK, HoldLow => thold_ADSCNeg_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ADSCNIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ADSCNIn_CLK ); VitalSetupHoldCheck ( TestSignal => CENegIn, TestSignalName => "CENeg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CENegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CENegIn_CLK ); VitalSetupHoldCheck ( TestSignal => CE2NegIn, TestSignalName => "CE2Neg", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE2NegIn_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE2NegIn_CLK ); VitalSetupHoldCheck ( TestSignal => CE2In, TestSignalName => "CE2", RefSignal => CLKIn, RefSignalName => "CLK", SetupHigh => tsetup_CE2_CLK, SetupLow => tsetup_CE2_CLK, HoldHigh => thold_CE2_CLK, HoldLow => thold_CE2_CLK, CheckEnabled => (ZZIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CE2In_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CE2In_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKIn, TestSignalName => "CLK", Period => tperiod_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PulseWidthHigh => tpw_CLK_posedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & PartID, CheckEnabled => (ZZIn ='0') ); Violation := Pviol_CLK OR Tviol_DatAIn_CLK OR Tviol_DatBIn_CLK OR Tviol_DatCIn_CLK OR Tviol_DatDIn_CLK OR Tviol_AddressIn_CLK OR Tviol_ADSCNIn_CLK OR Tviol_CE2In_CLK OR Tviol_CE2NegIn_CLK OR Tviol_CENegIn_CLK OR Tviol_ADVNIn_CLK OR Tviol_ADSPNIn_CLK OR Tviol_BWAN_CLK OR Tviol_BWBN_CLK OR Tviol_BWCN_CLK OR Tviol_BWDN_CLK OR Tviol_BWEN_CLK OR Tviol_GWN_CLK; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; ---------------------------------------------------------------------------- -- Functional Section ---------------------------------------------------------------------------- IF rising_edge(CLKIn) AND (ZZIn = '0') AND zz_reset THEN ASSERT (not(Is_X(BWANIn))) REPORT InstancePath & partID & ": Unusable value for BWAN" SEVERITY SeverityMode; ASSERT (not(Is_X(BWBNIn))) REPORT InstancePath & partID & ": Unusable value for BWBN" SEVERITY SeverityMode; ASSERT (not(Is_X(BWCNIn))) REPORT InstancePath & partID & ": Unusable value for BWCN" SEVERITY SeverityMode; ASSERT (not(Is_X(BWDNIn))) REPORT InstancePath & partID & ": Unusable value for BWDN" SEVERITY SeverityMode; ASSERT (not(Is_X(GWNIn))) REPORT InstancePath & partID & ": Unusable value for GWN" SEVERITY SeverityMode; ASSERT (not(Is_X(BWENIn))) REPORT InstancePath & partID & ": Unusable value for BWEN" SEVERITY SeverityMode; ASSERT (not(Is_X(ADVNIn))) REPORT InstancePath & partID & ": Unusable value for ADVN" SEVERITY SeverityMode; ASSERT (not(Is_X(ADSPNIn))) REPORT InstancePath & partID & ": Unusable value for ADSPN" SEVERITY SeverityMode; ASSERT (not(Is_X(ADSCNIn))) REPORT InstancePath & partID & ": Unusable value for ADSCN" SEVERITY SeverityMode; ASSERT (not(Is_X(CE2In))) REPORT InstancePath & partID & ": Unusable value for CE2" SEVERITY SeverityMode; ASSERT (not(Is_X(CENegIn))) REPORT InstancePath & partID & ": Unusable value for CENeg" SEVERITY SeverityMode; ASSERT (not(Is_X(CE2NegIn))) REPORT InstancePath & partID & ": Unusable value for CE2Neg" SEVERITY SeverityMode; -- Command Decode IF (GWNIn = '1' AND (BWENIn = '1' OR (BWENIn = '0' AND BWANIn = '1' AND BWBNIn = '1' AND BWCNIn = '1' AND BWDNIn = '1'))) THEN R := '1'; ELSE R := '0'; END IF; IF ((CE2NegIn = '1' AND CENegIn = '0') AND (ADSPNIn = '0' OR (ADSPNIn = '1' AND ADSCNIn = '0'))) OR (CENegIn = '1' AND ADSCNIn = '0') OR ((CE2In = '0' AND CENegIn = '0') AND (ADSPNIn = '0' OR (ADSPNIn = '1' AND ADSCNIn = '0'))) THEN command := ds; ELSIF ((CE2NegIn = '0' AND CE2In = '1' AND CENegIn = '0') AND (ADSPNIn = '0' OR (ADSPNIn = '1' AND ADSCNIn = '0' AND R = '1'))) THEN command := begin_rw; ELSIF (ADSCNIn = '1' AND (ADSPNIn = '1' OR CENegIn = '1') AND R = '1') THEN IF ADVNIn = '0' THEN command := read_burst; ELSE command := read_susp; END IF; ELSIF (ADSCNIn = '1' AND (ADSPNIn = '1' OR CENegIn = '1') AND R = '0') THEN IF ADVNIn = '0' THEN command := SPwr_burst; ELSE command := SPwr_susp; END IF; ELSIF (CE2NegIn = '0' AND CE2In = '1' AND CENegIn = '0' AND ADSPNIn = '1' AND ADSCNIn = '0' AND R = '0') THEN command := SCwr; ELSE ASSERT false REPORT InstancePath & partID & ": Could not decode " & "command." SEVERITY SeverityMode; END IF; -- The State Machine CASE state IS WHEN desel => CASE command IS WHEN begin_rw => state <= begin_rdwr; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); ReadMem(MemAddr); WHEN SCwr => state <= SCwrite; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); OBuf1 := (others => 'Z'); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN others => null; END CASE; WHEN begin_rdwr => Burst_Cnt := 0; CASE command IS WHEN ds => state <= desel; OBuf1 := (others => 'Z'); WHEN begin_rw => MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); ReadMem(MemAddr); WHEN SCwr => state <= SCwrite; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); OBuf1 := (others => 'Z'); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN SPwr_burst => OBuf1 := (others => 'Z'); WHEN SPwr_susp => state <= SPwrite; OBuf1 := (others => 'Z'); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN read_burst => state <= read; Burst_Cnt := Burst_Cnt + 1; offset := Burst_Seq(memstart)(Burst_Cnt); MemAddr := startaddr + offset; ReadMem(MemAddr); WHEN read_susp => null; END CASE; WHEN SPwrite => CASE command IS WHEN ds => state <= desel; OBuf1 := (others => 'Z'); WHEN begin_rw => state <= begin_rdwr; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); ReadMem(MemAddr); WHEN SCwr => state <= SCwrite; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN SPwr_burst => Burst_Cnt := Burst_Cnt + 1; IF (Burst_Cnt = 4) THEN Burst_Cnt := 0; END IF; offset := Burst_Seq(memstart)(Burst_Cnt); MemAddr := startaddr + offset; WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN SPwr_susp => WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN others => null; END CASE; WHEN SCwrite => Burst_Cnt := 0; CASE command IS WHEN ds => state <= desel; WHEN begin_rw => state <= begin_rdwr; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); ReadMem(MemAddr); WHEN SCwr => MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN SPwr_burst => state <= SPwrite; Burst_Cnt := Burst_Cnt + 1; offset := Burst_Seq(memstart)(Burst_Cnt); MemAddr := startaddr + offset; WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN others => null; END CASE; WHEN read => CASE command IS WHEN ds => state <= desel; OBuf1 := (others => 'Z'); WHEN begin_rw => state <= begin_rdwr; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); ReadMem(MemAddr); WHEN SCwr => state <= SCwrite; MemAddr := to_nat(AddressIn); startaddr := MemAddr; memstart := to_nat(AddressIn(1 downto 0)); OBuf1 := (others => 'Z'); WriteMem( WAddr => MemAddr, WDatA => DatAIn, WDatB => DatBIn, WDatC => DatCIn, WDatD => DatDIn, WGWN => GWNIn, WBWA => BWANIn, WBWB => BWBNIn, WBWC => BWCNIn, WBWD => BWDNIn); WHEN SPwr_burst => OBuf1 := (others => 'Z'); WHEN SPwr_susp => OBuf1 := (others => 'Z'); WHEN read_burst => state <= read; Burst_Cnt := Burst_Cnt + 1; IF (Burst_Cnt = 4) THEN Burst_Cnt := 0; END IF; offset := Burst_Seq(memstart)(Burst_Cnt); MemAddr := startaddr + offset; ReadMem(MemAddr); WHEN read_susp => state <= read; END CASE; END CASE; IF (OENegIn = '0') THEN IF OBuf1(0) /= 'Z' AND command /= read_susp THEN D_zd <= (others => 'X'), OBuf1 AFTER 1 ns; ELSE D_zd <= OBuf1; END IF; END IF; END IF; IF (OENegIn = '1') THEN D_zd <= (others => 'Z'); ELSIF falling_edge(OENegIn) AND (ZZIn = '0') AND zz_reset THEN IF OBuf1(0) /= 'Z' THEN D_zd <= (others => 'X'), OBuf1 AFTER 1 ns; ELSE D_zd <= OBuf1; END IF; END IF; IF rising_edge(ZZIn) THEN IF state/= desel THEN ASSERT false REPORT InstancePath & partID & ": Device must be " & "deselected prior to entering the sleep mode." SEVERITY SeverityMode; END IF; zz_set := TRUE; IF NOT(zz_reset) THEN zz_set := FALSE; zz_reset := TRUE; zz_cnt := 0; ASSERT false REPORT InstancePath & partID & ": 2tCYC are " & "required to exit from sleep mode." SEVERITY SeverityMode; END IF; ELSIF falling_edge(ZZIn) THEN zz_reset := FALSE; IF zz_set THEN zz_set := FALSE; zz_reset := TRUE; zz_cnt := 0; ASSERT false REPORT InstancePath & partID & ": 2tCYC are " & "required to enter into sleep mode." SEVERITY SeverityMode; END IF; END IF; IF rising_edge(CLKIn) THEN IF zz_set THEN D_zd <= (others => 'Z'); IF zz_cnt = 2 THEN zz_set := FALSE; zz_cnt := 0; ELSE zz_cnt := zz_cnt + 1; END IF; ELSIF NOT(zz_reset) THEN IF zz_cnt = 2 THEN zz_reset := TRUE; zz_cnt := 0; ELSE zz_cnt := zz_cnt + 1; END IF; END IF; END IF; IF NOT(zz_reset) THEN IF (ADSPNIn = '0' OR ADSCNIn = '0' OR CENeg = '0' OR CE2 = '1' OR CE2Neg = '0') THEN ASSERT FALSE REPORT InstancePath & partID & ": ADSC, ADSP and Chip Enable "& "inputs must not be asserted for at least 2tCYC after leaving"& " ZZ state" SEVERITY SeverityMode; END IF; END IF; END PROCESS; ------------------------------------------------------------------------ -- Path Delay Process ------------------------------------------------------------------------ DataOutPath : FOR I IN 35 DOWNTO 0 GENERATE DataOut_Delay : PROCESS (D_zd(i)) VARIABLE D_GlitchData:VitalGlitchDataArrayType(35 Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => DataOut(i), OutSignalName => "Data", OutTemp => D_zd(i), Mode => VitalTransport, GlitchData => D_GlitchData(i), Paths => ( 0 => (InputChangeTime => CLKIn'LAST_EVENT, PathDelay => tpd_CLK_DQA0, PathCondition => OENegIn = '0' AND CLKIn = '1' AND D_zd(i) /= 'X'), 1 => (InputChangeTime => CLKIn'LAST_EVENT, PathDelay => tpd_CLK_DQA1, PathCondition => OENegIn = '0' AND CLKIn = '1' AND D_zd(i) = 'X'), 2 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_DQA0, PathCondition => D_zd(i) /= 'X'), 3 => (InputChangeTime => OENegIn'LAST_EVENT, PathDelay => tpd_OENeg_DQA1, PathCondition => D_zd(i) = 'X') ) ); END PROCESS; END GENERATE; -------------------------------------------------------------------------- -- File Read Section -------------------------------------------------------------------------- --cy7c1361 memory file --@aaaaa - stands for address --ddddddddd - is word to be written at MemDataA..D(aaaaa++) --(aaaaa is incremented at every load) --(ddddddddd is a 36-bit data, MemDataA(aaaaa++) is loaded with the lowest --nine bits, MemDataB(aaaaa++) is loaded with the next nine LSBs, --MemDataC(aaaaa++) with the next nine LSBs and MemDataD(aaaaa++) is --loaded with the highest nine bits) --only first 1-9 columns are loaded. NO empty lines !!!!!!!!!!!!!!!! default: PROCESS IS VARIABLE ind : NATURAL := 0; VARIABLE linecnt : NATURAL := 0; VARIABLE buf : line; BEGIN IF (mem_file_name /= "none") AND (NOW < 1 ns) THEN ind := 0; linecnt := 0; WHILE (not ENDFILE (mem_file)) LOOP READLINE (mem_file, buf); linecnt := linecnt +1; IF buf(1) = '/' THEN --comment NEXT; ELSIF buf(1) = '@' THEN --address ind := h(buf(2 to 6)); ELSE IF ind <= MemSize THEN MemDataA(ind) := (h(buf(7 to 9)) MOD 512); MemDataB(ind) := (h(buf(5 to 7)) MOD 1024)/2; MemDataC(ind) := (h(buf(3 to 5)) MOD 2048)/4; MemDataD(ind) := (h(buf(1 to 3))/8); ind := ind + 1; ELSE ASSERT FALSE REPORT "file: "&mem_file_name&" has size larger than " &to_int_str(MemSize+1)&" at line "&to_int_str(linecnt) SEVERITY warning; END IF; END IF; END LOOP; END IF; WAIT; END PROCESS default; END BLOCK; END vhdl_behavioral;