version: | author: | mod date: | changes made: V1.0 R. Munden 99 AUG 05 Initial release V1.1 R. Munden 08 MAY 23 Corrected DQA0 port name 1ns CY7C1334 CY7C1334-133ALCypress Semiconductor Data Sheet May 5, 1998 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:3.5:4.2) (2.5:3.5:4.2) (1.5:3.0:3.5) (2.5:3.5:4.2) (1.5:3.0:3.5) (2.5:3.5:4.2)) (IOPATH OENeg DQA0 () () (1.5:3.5:4.2) (1.0:3.5:4.2) (1.5:3.5:4.2) (1.0:3.5:4.2)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.5)) (WIDTH (posedge CLK) (2.2)) (WIDTH (negedge CLK) (2.2)) (SETUP A0 CLK (2.0)) (SETUP CLKENNeg CLK (2.0)) (SETUP DQA0 CLK (1.7)) (SETUP R CLK (2.0)) (SETUP ADV CLK (2.0)) (SETUP CE2 CLK (2.0)) (SETUP BWANeg CLK (2.0)) (HOLD A0 CLK (0.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) ) CY7C1334-100ALCypress Semiconductor Data Sheet May 5, 1998 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:4.0:5.0) (2.5:4.0:5.0) (1.5:3.0:3.5) (2.5:4.0:5.0) (1.5:3.0:3.5) (2.5:4.0:5.0)) (IOPATH OENeg DQA0 () () (2.5:4.0:5.0) (1.0:2.5:5.0) (2.5:4.0:5.0) (1.0:2.5:5.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK) (3.5)) (WIDTH (negedge CLK) (3.0)) (SETUP A0 CLK (2.2)) (SETUP CLKENNeg CLK (2.2)) (SETUP DQA0 CLK (2.0)) (SETUP R CLK (2.2)) (SETUP ADV CLK (2.2)) (SETUP CE2 CLK (2.2)) (SETUP BWANeg CLK (2.2)) (HOLD A0 CLK (0.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) ) CY7C1334-80ALCypress Semiconductor Data Sheet May 5, 1998 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:5.0:7.0) (2.5:5.0:7.0) (1.5:3.0:3.5) (2.5:5.0:7.0) (1.5:3.0:3.5) (2.5:5.0:7.0)) (IOPATH OENeg DQA0 () () (2.5:4.0:6.0) (1.0:5.0:7.0) (2.5:4.0:6.0) (1.0:5.0:7.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (12.5)) (WIDTH (posedge CLK) (4.0)) (WIDTH (negedge CLK) (4.0)) (SETUP A0 CLK (2.5)) (SETUP CLKENNeg CLK (2.5)) (SETUP DQA0 CLK (2.5)) (SETUP R CLK (2.5)) (SETUP ADV CLK (2.5)) (SETUP CE2 CLK (2.5)) (SETUP BWANeg CLK (2.5)) (HOLD A0 CLK (1.0)) (HOLD CLKENNeg CLK (1.0)) (HOLD DQA0 CLK (1.0)) (HOLD R CLK (1.0)) (HOLD ADV CLK (1.0)) (HOLD CE2 CLK (1.0)) (HOLD BWANeg CLK (1.0)) ) CY7C1334-50ALCypress Semiconductor Data Sheet May 5, 1998 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (2.5:8.0:10.0) (2.5:8.0:10.0) (1.5:3.0:3.5) (2.5:4.0:10.0) (1.5:3.0:3.5) (2.5:4.0:10.0)) (IOPATH OENeg DQA0 () () (2.5:4.0:6.0) (1.0:5.0:10.0) (2.5:4.0:6.0) (1.0:5.0:10.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (20)) (WIDTH (posedge CLK) (6.0)) (WIDTH (negedge CLK) (6.0)) (SETUP A0 CLK (3.0)) (SETUP CLKENNeg CLK (3.0)) (SETUP DQA0 CLK (3.0)) (SETUP R CLK (3.0)) (SETUP ADV CLK (3.0)) (SETUP CE2 CLK (3.0)) (SETUP BWANeg CLK (3.0)) (HOLD A0 CLK (1.5)) (HOLD CLKENNeg CLK (1.5)) (HOLD DQA0 CLK (1.5)) (HOLD R CLK (1.5)) (HOLD ADV CLK (1.5)) (HOLD CE2 CLK (1.5)) (HOLD BWANeg CLK (1.5)) ) MT55L64L32P1T-6Micron Technology MT55L128L18P1.p65 Rev. 6/99 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5) (1.5:3.0:3.5)) (IOPATH OENeg DQA0 () () (1.5:3.0:3.5) (0.0:2.1:3.5) (1.5:3.0:3.5) (0.0:2.1:3.5)) )) (TIMINGCHECK (PERIOD (posedge CLK) (6.0)) (WIDTH (posedge CLK) (2.0)) (WIDTH (negedge CLK) (2.0)) (SETUP A0 CLK (1.7)) (SETUP CLKENNeg CLK (1.7)) (SETUP DQA0 CLK (1.7)) (SETUP R CLK (1.7)) (SETUP ADV CLK (1.7)) (SETUP CE2 CLK (1.7)) (SETUP BWANeg CLK (1.7)) (HOLD A0 CLK (0.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) ) MT55L64L32P1T-7.5Micron Technology MT55L128L18P1.p65 Rev. 6/99 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:3.5:4.2) (1.5:3.5:4.2) (1.5:3.0:3.5) (1.5:3.5:4.2) (1.5:3.0:3.5) (1.5:3.5:4.2)) (IOPATH OENeg DQA0 () () (1.5:3.5:4.2) (0.0:2.1:4.2) (1.5:3.5:4.2) (0.0:2.1:4.2)) )) (TIMINGCHECK (PERIOD (posedge CLK) (7.5)) (WIDTH (posedge CLK) (2.2)) (WIDTH (negedge CLK) (2.2)) (SETUP A0 CLK (2.0)) (SETUP CLKENNeg CLK (2.0)) (SETUP DQA0 CLK (2.0)) (SETUP R CLK (2.0)) (SETUP ADV CLK (2.0)) (SETUP CE2 CLK (2.0)) (SETUP BWANeg CLK (2.0)) (HOLD A0 CLK (0.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) ) MT55L64L32P1T-10Micron Technology MT55L128L18P1.p65 Rev. 6/99 The values listed are for VCC=3.135V to 3.465V, CL=5pF, Ta=0 to 70 Celsius Typical values are derived (DELAY (ABSOLUTE (IOPATH CLK DQA0 (1.5:4.0:5.0) (1.5:4.0:5.0) (1.5:3.0:3.5) (1.5:4.0:5.0) (1.5:3.0:3.5) (1.5:4.0:5.0)) (IOPATH OENeg DQA0 () () (1.5:4.0:5.0) (0.0:2.5:5.0) (1.5:4.0:5.0) (0.0:2.5:5.0)) )) (TIMINGCHECK (PERIOD (posedge CLK) (10)) (WIDTH (posedge CLK) (3.5)) (WIDTH (negedge CLK) (3.5)) (SETUP A0 CLK (2.0)) (SETUP CLKENNeg CLK (2.0)) (SETUP DQA0 CLK (2.0)) (SETUP R CLK (2.0)) (SETUP ADV CLK (2.0)) (SETUP CE2 CLK (2.0)) (SETUP BWANeg CLK (2.0)) (HOLD A0 CLK (0.5)) (HOLD CLKENNeg CLK (0.5)) (HOLD DQA0 CLK (0.5)) (HOLD R CLK (0.5)) (HOLD ADV CLK (0.5)) (HOLD CE2 CLK (0.5)) (HOLD BWANeg CLK (0.5)) )