-------------------------------------------------------------------------------- -- File Name: cy7c131.vhd -------------------------------------------------------------------------------- -- Copyright (C) 2000-2008 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V1.0 R. Munden 00 APR 05 Initial release -- V1.1 R. Munden 08 MAY 23 Correct tsetup_IOL0_RWL generic name -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: RAM -- Technology: SRAM -- Part: CY7C131 -- -- Description: SRAM DUAL-PORT 1K X 8 -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY cy7c131 IS GENERIC ( -- tipd delays: interconnect path delays tipd_RWR : VitalDelayType01 := VitalZeroDelay01; tipd_RWL : VitalDelayType01 := VitalZeroDelay01; tipd_OERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_IOR7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOR0 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL7 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL6 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL5 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL4 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL3 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL2 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL1 : VitalDelayType01 := VitalZeroDelay01; tipd_IOL0 : VitalDelayType01 := VitalZeroDelay01; tipd_CERNeg : VitalDelayType01 := VitalZeroDelay01; tipd_CELNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BUSYRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_BUSYLNeg : VitalDelayType01 := VitalZeroDelay01; tipd_AR9 : VitalDelayType01 := VitalZeroDelay01; tipd_AL9 : VitalDelayType01 := VitalZeroDelay01; tipd_AR8 : VitalDelayType01 := VitalZeroDelay01; tipd_AL8 : VitalDelayType01 := VitalZeroDelay01; tipd_AR7 : VitalDelayType01 := VitalZeroDelay01; tipd_AL7 : VitalDelayType01 := VitalZeroDelay01; tipd_AR6 : VitalDelayType01 := VitalZeroDelay01; tipd_AL6 : VitalDelayType01 := VitalZeroDelay01; tipd_AR5 : VitalDelayType01 := VitalZeroDelay01; tipd_AL5 : VitalDelayType01 := VitalZeroDelay01; tipd_AR4 : VitalDelayType01 := VitalZeroDelay01; tipd_AL4 : VitalDelayType01 := VitalZeroDelay01; tipd_AR3 : VitalDelayType01 := VitalZeroDelay01; tipd_AL3 : VitalDelayType01 := VitalZeroDelay01; tipd_AR2 : VitalDelayType01 := VitalZeroDelay01; tipd_AL2 : VitalDelayType01 := VitalZeroDelay01; tipd_AR1 : VitalDelayType01 := VitalZeroDelay01; tipd_AL1 : VitalDelayType01 := VitalZeroDelay01; tipd_AR0 : VitalDelayType01 := VitalZeroDelay01; tipd_AL0 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_RWL_INTRNeg : VitalDelayType01 := UnitDelay01; tpd_OELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; tpd_CELNeg_IOL0 : VitalDelayType01Z := UnitDelay01Z; tpd_AL0_INTLNeg : VitalDelayType01 := UnitDelay01; tpd_AL0_IOL0 : VitalDelayType01 := UnitDelay01; tpd_AL0_BUSYLNeg : VitalDelayType01 := UnitDelay01; tpd_CELNeg_BUSYLNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths tpw_RWL_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tAS tsetup_AL0_CELNeg : VitalDelayType := UnitDelay; tsetup_AL0_RWL : VitalDelayType := UnitDelay; -- tAW tsetup_AL1_RWL : VitalDelayType := UnitDelay; -- tEW tsetup_CELNeg_RWL : VitalDelayType := UnitDelay; -- tDW tsetup_IOL0_RWL : VitalDelayType := UnitDelay; -- thold values: hold times -- tWR thold_AL0_CELNeg : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; SeverityMode : SEVERITY_LEVEL := WARNING; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( RWR : IN std_logic := 'U'; RWL : IN std_logic := 'U'; OERNeg : IN std_logic := 'U'; OELNeg : IN std_logic := 'U'; INTRNeg : OUT std_logic := '1'; INTLNeg : OUT std_logic := '1'; IOR7 : INOUT std_logic := 'U'; IOR6 : INOUT std_logic := 'U'; IOR5 : INOUT std_logic := 'U'; IOR4 : INOUT std_logic := 'U'; IOR3 : INOUT std_logic := 'U'; IOR2 : INOUT std_logic := 'U'; IOR1 : INOUT std_logic := 'U'; IOR0 : INOUT std_logic := 'U'; IOL7 : INOUT std_logic := 'U'; IOL6 : INOUT std_logic := 'U'; IOL5 : INOUT std_logic := 'U'; IOL4 : INOUT std_logic := 'U'; IOL3 : INOUT std_logic := 'U'; IOL2 : INOUT std_logic := 'U'; IOL1 : INOUT std_logic := 'U'; IOL0 : INOUT std_logic := 'U'; CERNeg : IN std_logic := 'U'; CELNeg : IN std_logic := 'U'; BUSYRNeg : OUT std_logic := '1'; BUSYLNeg : OUT std_logic := '1'; AR9 : IN std_logic := 'U'; AL9 : IN std_logic := 'U'; AR8 : IN std_logic := 'U'; AL8 : IN std_logic := 'U'; AR7 : IN std_logic := 'U'; AL7 : IN std_logic := 'U'; AR6 : IN std_logic := 'U'; AL6 : IN std_logic := 'U'; AR5 : IN std_logic := 'U'; AL5 : IN std_logic := 'U'; AR4 : IN std_logic := 'U'; AL4 : IN std_logic := 'U'; AR3 : IN std_logic := 'U'; AL3 : IN std_logic := 'U'; AR2 : IN std_logic := 'U'; AL2 : IN std_logic := 'U'; AR1 : IN std_logic := 'U'; AL1 : IN std_logic := 'U'; AR0 : IN std_logic := 'U'; AL0 : IN std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of cy7c131 : ENTITY IS TRUE; END cy7c131; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of cy7c131 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "CY7C131"; CONSTANT MaxData : NATURAL := 255; CONSTANT TotalLOC : NATURAL := 1023; CONSTANT HiAbit : NATURAL := 9; CONSTANT HiDbit : NATURAL := 7; CONSTANT DataWidth : NATURAL := 8; SIGNAL RWR_ipd : std_ulogic := 'U'; SIGNAL RWL_ipd : std_ulogic := 'U'; SIGNAL OERNeg_ipd : std_ulogic := 'U'; SIGNAL OELNeg_ipd : std_ulogic := 'U'; SIGNAL IOR7_ipd : std_ulogic := 'U'; SIGNAL IOR6_ipd : std_ulogic := 'U'; SIGNAL IOR5_ipd : std_ulogic := 'U'; SIGNAL IOR4_ipd : std_ulogic := 'U'; SIGNAL IOR3_ipd : std_ulogic := 'U'; SIGNAL IOR2_ipd : std_ulogic := 'U'; SIGNAL IOR1_ipd : std_ulogic := 'U'; SIGNAL IOR0_ipd : std_ulogic := 'U'; SIGNAL IOL7_ipd : std_ulogic := 'U'; SIGNAL IOL6_ipd : std_ulogic := 'U'; SIGNAL IOL5_ipd : std_ulogic := 'U'; SIGNAL IOL4_ipd : std_ulogic := 'U'; SIGNAL IOL3_ipd : std_ulogic := 'U'; SIGNAL IOL2_ipd : std_ulogic := 'U'; SIGNAL IOL1_ipd : std_ulogic := 'U'; SIGNAL IOL0_ipd : std_ulogic := 'U'; SIGNAL CERNeg_ipd : std_ulogic := 'U'; SIGNAL CELNeg_ipd : std_ulogic := 'U'; SIGNAL AR9_ipd : std_ulogic := 'U'; SIGNAL AL9_ipd : std_ulogic := 'U'; SIGNAL AR8_ipd : std_ulogic := 'U'; SIGNAL AL8_ipd : std_ulogic := 'U'; SIGNAL AR7_ipd : std_ulogic := 'U'; SIGNAL AL7_ipd : std_ulogic := 'U'; SIGNAL AR6_ipd : std_ulogic := 'U'; SIGNAL AL6_ipd : std_ulogic := 'U'; SIGNAL AR5_ipd : std_ulogic := 'U'; SIGNAL AL5_ipd : std_ulogic := 'U'; SIGNAL AR4_ipd : std_ulogic := 'U'; SIGNAL AL4_ipd : std_ulogic := 'U'; SIGNAL AR3_ipd : std_ulogic := 'U'; SIGNAL AL3_ipd : std_ulogic := 'U'; SIGNAL AR2_ipd : std_ulogic := 'U'; SIGNAL AL2_ipd : std_ulogic := 'U'; SIGNAL AR1_ipd : std_ulogic := 'U'; SIGNAL AL1_ipd : std_ulogic := 'U'; SIGNAL AR0_ipd : std_ulogic := 'U'; SIGNAL AL0_ipd : std_ulogic := 'U'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay (RWR_ipd, RWR, tipd_RWR); w_2 : VitalWireDelay (RWL_ipd, RWL, tipd_RWL); w_3 : VitalWireDelay (OERNeg_ipd, OERNeg, tipd_OERNeg); w_4 : VitalWireDelay (OELNeg_ipd, OELNeg, tipd_OELNeg); w_9 : VitalWireDelay (CERNeg_ipd, CERNeg, tipd_CERNeg); w_10 : VitalWireDelay (CELNeg_ipd, CELNeg, tipd_CELNeg); w_13 : VitalWireDelay (AR9_ipd, AR9, tipd_AR9); w_14 : VitalWireDelay (AL9_ipd, AL9, tipd_AL9); w_15 : VitalWireDelay (AR8_ipd, AR8, tipd_AR8); w_16 : VitalWireDelay (AL8_ipd, AL8, tipd_AL8); w_17 : VitalWireDelay (AR7_ipd, AR7, tipd_AR7); w_18 : VitalWireDelay (AL7_ipd, AL7, tipd_AL7); w_19 : VitalWireDelay (AR6_ipd, AR6, tipd_AR6); w_20 : VitalWireDelay (AL6_ipd, AL6, tipd_AL6); w_21 : VitalWireDelay (AR5_ipd, AR5, tipd_AR5); w_22 : VitalWireDelay (AL5_ipd, AL5, tipd_AL5); w_23 : VitalWireDelay (AR4_ipd, AR4, tipd_AR4); w_24 : VitalWireDelay (AL4_ipd, AL4, tipd_AL4); w_25 : VitalWireDelay (AR3_ipd, AR3, tipd_AR3); w_26 : VitalWireDelay (AL3_ipd, AL3, tipd_AL3); w_27 : VitalWireDelay (AR2_ipd, AR2, tipd_AR2); w_28 : VitalWireDelay (AL2_ipd, AL2, tipd_AL2); w_29 : VitalWireDelay (AR1_ipd, AR1, tipd_AR1); w_30 : VitalWireDelay (AL1_ipd, AL1, tipd_AL1); w_31 : VitalWireDelay (AR0_ipd, AR0, tipd_AR0); w_32 : VitalWireDelay (AL0_ipd, AL0, tipd_AL0); w_33 : VitalWireDelay (IOR7_ipd, IOR7, tipd_IOR7); w_34 : VitalWireDelay (IOR6_ipd, IOR6, tipd_IOR6); w_35 : VitalWireDelay (IOR5_ipd, IOR5, tipd_IOR5); w_36 : VitalWireDelay (IOR4_ipd, IOR4, tipd_IOR4); w_37 : VitalWireDelay (IOR3_ipd, IOR3, tipd_IOR3); w_38 : VitalWireDelay (IOR2_ipd, IOR2, tipd_IOR2); w_39 : VitalWireDelay (IOR1_ipd, IOR1, tipd_IOR1); w_40 : VitalWireDelay (IOR0_ipd, IOR0, tipd_IOR0); w_41 : VitalWireDelay (IOL7_ipd, IOL7, tipd_IOL7); w_42 : VitalWireDelay (IOL6_ipd, IOL6, tipd_IOL6); w_43 : VitalWireDelay (IOL5_ipd, IOL5, tipd_IOL5); w_44 : VitalWireDelay (IOL4_ipd, IOL4, tipd_IOL4); w_45 : VitalWireDelay (IOL3_ipd, IOL3, tipd_IOL3); w_46 : VitalWireDelay (IOL2_ipd, IOL2, tipd_IOL2); w_47 : VitalWireDelay (IOL1_ipd, IOL1, tipd_IOL1); w_48 : VitalWireDelay (IOL0_ipd, IOL0, tipd_IOL0); END BLOCK; ---------------------------------------------------------------------------- -- Main Behavior Block ---------------------------------------------------------------------------- Behavior: BLOCK PORT ( ALIn : IN std_logic_vector(HiAbit downto 0); ARIn : IN std_logic_vector(HiAbit downto 0); IOLIn : IN std_logic_vector(HiDbit downto 0); IORIn : IN std_logic_vector(HiDbit downto 0); IOLOut : OUT std_logic_vector(HiDbit downto 0); IOROut : OUT std_logic_vector(HiDbit downto 0); RWLIn : IN std_ulogic := 'U'; RWRIn : IN std_ulogic := 'U'; OELNegIn : IN std_ulogic := 'U'; OERNegIn : IN std_ulogic := 'U'; CELNegIn : IN std_ulogic := 'U'; CERNegIn : IN std_ulogic := 'U'; BUSYLNeg : OUT std_ulogic := '1'; BUSYRNeg : OUT std_ulogic := '1'; INTLNeg : OUT std_ulogic := '1'; INTRNeg : OUT std_ulogic := '1' ); PORT MAP ( ALIn(0) => AL0_ipd, ALIn(1) => AL1_ipd, ALIn(2) => AL2_ipd, ALIn(3) => AL3_ipd, ALIn(4) => AL4_ipd, ALIn(5) => AL5_ipd, ALIn(6) => AL6_ipd, ALIn(7) => AL7_ipd, ALIn(8) => AL8_ipd, ALIn(9) => AL9_ipd, ARIn(0) => AR0_ipd, ARIn(1) => AR1_ipd, ARIn(2) => AR2_ipd, ARIn(3) => AR3_ipd, ARIn(4) => AR4_ipd, ARIn(5) => AR5_ipd, ARIn(6) => AR6_ipd, ARIn(7) => AR7_ipd, ARIn(8) => AR8_ipd, ARIn(9) => AR9_ipd, IOLIn(0) => IOL0_ipd, IOLIn(1) => IOL1_ipd, IOLIn(2) => IOL2_ipd, IOLIn(3) => IOL3_ipd, IOLIn(4) => IOL4_ipd, IOLIn(5) => IOL5_ipd, IOLIn(6) => IOL6_ipd, IOLIn(7) => IOL7_ipd, IORIn(0) => IOR0_ipd, IORIn(1) => IOR1_ipd, IORIn(2) => IOR2_ipd, IORIn(3) => IOR3_ipd, IORIn(4) => IOR4_ipd, IORIn(5) => IOR5_ipd, IORIn(6) => IOR6_ipd, IORIn(7) => IOR7_ipd, IOLOut(0) => IOL0, IOLOut(1) => IOL1, IOLOut(2) => IOL2, IOLOut(3) => IOL3, IOLOut(4) => IOL4, IOLOut(5) => IOL5, IOLOut(6) => IOL6, IOLOut(7) => IOL7, IOROut(0) => IOR0, IOROut(1) => IOR1, IOROut(2) => IOR2, IOROut(3) => IOR3, IOROut(4) => IOR4, IOROut(5) => IOR5, IOROut(6) => IOR6, IOROut(7) => IOR7, RWLIn => RWL_ipd, RWRIn => RWR_ipd, OELNegIn => OELNeg_ipd, OERNegIn => OERNeg_ipd, CELNegIn => CELNeg_ipd, CERNegIn => CERNeg_ipd, BUSYLNeg => BUSYLNeg, BUSYRNeg => BUSYRNeg, INTLNeg => INTLNeg, INTRNeg => INTRNeg ); SIGNAL IOL_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL IOR_zd : std_logic_vector(HiDbit DOWNTO 0); SIGNAL WRTL_int : std_ulogic := '1'; SIGNAL WRTR_int : std_ulogic := '1'; BEGIN WRTL_int <= RWLIn OR CELNegIn; WRTR_int <= RWRIn OR CERNegIn; ------------------------------------------------------------------------ -- Behavior Process ------------------------------------------------------------------------ Memory : PROCESS (OELNegIn, OERNegIn, RWLIn, RWRIn, CELNegIn, CERNegIn, ALIn, ARIn, IOLIn, IORIn, WRTL_int, WRTR_int) -- Timing Check Variables VARIABLE Tviol_ALIn_CELNegIn : X01 := '0'; VARIABLE TD_ALIn_CELNegIn : VitalTimingDataType; VARIABLE Tviol_ALIn_CELNegInH : X01 := '0'; VARIABLE TD_ALIn_CELNegInH : VitalTimingDataType; VARIABLE Tviol_ALIn_RWLInL : X01 := '0'; VARIABLE TD_ALIn_RWLInL : VitalTimingDataType; VARIABLE Tviol_ALIn_RWLInH : X01 := '0'; VARIABLE TD_ALIn_RWLInH : VitalTimingDataType; VARIABLE Tviol_ARIn_CERNegIn : X01 := '0'; VARIABLE TD_ARIn_CERNegIn : VitalTimingDataType; VARIABLE Tviol_ARIn_CERNegInH : X01 := '0'; VARIABLE TD_ARIn_CERNegInH : VitalTimingDataType; VARIABLE Tviol_ARIn_RWRInL : X01 := '0'; VARIABLE TD_ARIn_RWRInL : VitalTimingDataType; VARIABLE Tviol_ARIn_RWRInH : X01 := '0'; VARIABLE TD_ARIn_RWRInH : VitalTimingDataType; VARIABLE Tviol_CELNegIn_RWLIn : X01 := '0'; VARIABLE TD_CELNegIn_RWLIn : VitalTimingDataType; VARIABLE Tviol_CERNegIn_RWRIn : X01 := '0'; VARIABLE TD_CERNegIn_RWRIn : VitalTimingDataType; VARIABLE Tviol_IOLIn_RWLIn : X01 := '0'; VARIABLE TD_IOLIn_RWLIn : VitalTimingDataType; VARIABLE Tviol_IORIn_RWRIn : X01 := '0'; VARIABLE TD_IORIn_RWRIn : VitalTimingDataType; VARIABLE Pviol_RWLIn : X01 := '0'; VARIABLE PD_RWLIn : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RWRIn : X01 := '0'; VARIABLE PD_RWRIn : VitalPeriodDataType := VitalPeriodDataInit; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER RANGE -2 TO MaxData; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE BUSYL_zd : std_logic; VARIABLE BUSYR_zd : std_logic; VARIABLE INTL_zd : std_logic; VARIABLE INTR_zd : std_logic; VARIABLE DataLDrive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'X'); VARIABLE DataRDrive : std_logic_vector(HiDbit DOWNTO 0) := (OTHERS => 'X'); VARIABLE DataTempL : INTEGER RANGE -2 TO MaxData := -2; VARIABLE DataTempR : INTEGER RANGE -2 TO MaxData := -2; VARIABLE Location : NATURAL RANGE 0 TO TotalLOC := 0; VARIABLE MemData : MemStore; -- Output Glitch Detection Variables VARIABLE INTL_GlitchData : VitalGlitchDataType; VARIABLE INTR_GlitchData : VitalGlitchDataType; VARIABLE BUSYL_GlitchData : VitalGlitchDataType; VARIABLE BUSYR_GlitchData : VitalGlitchDataType; -- No Weak Values Variables VARIABLE CELNeg_nwv : UX01 := 'X'; VARIABLE CERNeg_nwv : UX01 := 'X'; VARIABLE OELNeg_nwv : UX01 := 'X'; VARIABLE OERNeg_nwv : UX01 := 'X'; VARIABLE RWL_nwv : UX01 := 'X'; VARIABLE RWR_nwv : UX01 := 'X'; BEGIN CELNeg_nwv := To_UX01 (s => CELNegIn); CERNeg_nwv := To_UX01 (s => CERNegIn); OELNeg_nwv := To_UX01 (s => OELNegIn); OERNeg_nwv := To_UX01 (s => OERNegIn); RWL_nwv := To_UX01 (s => RWLIn); RWR_nwv := To_UX01 (s => RWRIn); -------------------------------------------------------------------- -- Timing Check Section -------------------------------------------------------------------- IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CELNegIn, RefSignalName => "CELNeg", SetupHigh => tsetup_AL0_CELNeg, SetupLow => tsetup_AL0_CELNeg, CheckEnabled => (RWLIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_CELNegIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_CELNegIn ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CERNegIn, RefSignalName => "CERNeg", SetupHigh => tsetup_AL0_CELNeg, SetupLow => tsetup_AL0_CELNeg, CheckEnabled => (RWRIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_CERNegIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_CERNegIn ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => RWLIn, RefSignalName => "RWL", SetupHigh => tsetup_AL0_RWL, SetupLow => tsetup_AL0_RWL, CheckEnabled => (CELNegIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_RWLInL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_RWLInL ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => RWRIn, RefSignalName => "RWR", SetupHigh => tsetup_AL0_RWL, SetupLow => tsetup_AL0_RWL, CheckEnabled => (CERNegIn ='0'), RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_RWRInL, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_RWRInL ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => CELNegIn, RefSignalName => "CELNeg", SetupHigh => tsetup_AL1_RWL, SetupLow => tsetup_AL1_RWL, HoldHigh => thold_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, CheckEnabled => (RWLIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_CELNegIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_CELNegIn ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => CERNegIn, RefSignalName => "CERNeg", SetupHigh => tsetup_AL1_RWL, SetupLow => tsetup_AL1_RWL, HoldHigh => thold_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, CheckEnabled => (RWRIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_CERNegInH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_CERNegInH ); VitalSetupHoldCheck ( TestSignal => ALIn, TestSignalName => "AL", RefSignal => RWLIn, RefSignalName => "RWL", SetupHigh => tsetup_AL1_RWL, SetupLow => tsetup_AL1_RWL, HoldHigh => thold_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, CheckEnabled => (CELNegIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ALIn_RWLInH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ALIn_RWLInH ); VitalSetupHoldCheck ( TestSignal => ARIn, TestSignalName => "AR", RefSignal => RWRIn, RefSignalName => "RWR", SetupHigh => tsetup_AL1_RWL, SetupLow => tsetup_AL1_RWL, HoldHigh => thold_AL0_CELNeg, HoldLow => thold_AL0_CELNeg, CheckEnabled => (CERNegIn ='0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_ARIn_RWRInH, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ARIn_RWRInH ); VitalSetupHoldCheck ( TestSignal => CELNegIn, TestSignalName => "CELNeg", RefSignal => RWLIn, RefSignalName => "RWL", SetupLow => tsetup_CELNeg_RWL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CELNegIn_RWLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CELNegIn_RWLIn ); VitalSetupHoldCheck ( TestSignal => CERNegIn, TestSignalName => "CERNeg", RefSignal => RWRIn, RefSignalName => "RWR", SetupLow => tsetup_CELNeg_RWL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_CERNegIn_RWRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_CERNegIn_RWRIn ); VitalSetupHoldCheck ( TestSignal => IOLIn, TestSignalName => "IOL", RefSignal => RWLIn, RefSignalName => "RWL", SetupHigh => tsetup_IOL0_RWL, SetupLow => tsetup_IOL0_RWL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IOLIn_RWLIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IOLIn_RWLIn ); VitalSetupHoldCheck ( TestSignal => IORIn, TestSignalName => "IOR", RefSignal => RWRIn, RefSignalName => "RWR", SetupHigh => tsetup_IOL0_RWL, SetupLow => tsetup_IOL0_RWL, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_IORIn_RWRIn, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_IORIn_RWRIn ); VitalPeriodPulseCheck ( TestSignal => RWLIn, TestSignalName => "RWL", PulseWidthLow => tpw_RWL_negedge, PeriodData => PD_RWLIn, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RWLIn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => RWRIn, TestSignalName => "RWR", PulseWidthLow => tpw_RWL_negedge, PeriodData => PD_RWRIn, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RWRIn, HeaderMsg => InstancePath & PartID, CheckEnabled => TRUE ); Violation := Tviol_ALIn_CELNegIn OR Tviol_ALIn_RWLInL OR Tviol_ALIn_RWLInH OR Tviol_ARIn_CERNegIn OR Tviol_ARIn_RWRInL OR Tviol_ARIn_RWRInH OR Tviol_CELNegIn_RWLIn OR Tviol_CERNegIn_RWRIn OR Tviol_IOLIn_RWLIn OR Pviol_RWLIn OR Tviol_IORIn_RWRIn OR Pviol_RWRIn; ASSERT Violation = '0' REPORT InstancePath & partID & ": simulation may be" & " inaccurate due to timing violations" SEVERITY SeverityMode; END IF; -- Timing Check Section -------------------------------------------------------------------- -- Functional Section -------------------------------------------------------------------- DataLDrive := (OTHERS => 'Z'); DataRDrive := (OTHERS => 'Z'); IF (CELNeg_nwv = '0' AND CERNeg_nwv = '0') THEN IF To_Nat(ALIn) = To_Nat(ARIn) THEN IF (ALIn'EVENT OR CELNegIn'EVENT) THEN BUSYL_zd := '0'; ELSIF (ARIn'EVENT OR CERNegIn'EVENT) THEN BUSYR_zd := '0'; END IF; ELSE BUSYL_zd := '1'; BUSYR_zd := '1'; END IF; ELSE BUSYL_zd := '1'; BUSYR_zd := '1'; END IF; IF rising_edge(WRTL_int) THEN IF Violation = '0' THEN DataTempL := To_Nat(IOLIn); ELSE DataTempL := -1; END IF; MemData(Location) := DataTempL; ELSIF (CELNeg_nwv = '0') THEN IF (OELNeg_nwv = '0' OR RWL_nwv = '0') THEN Location := To_Nat(ALIn); IF (OELNeg_nwv = '0' AND RWL_nwv = '1') THEN DataTempL := MemData(Location); IF DataTempL >= 0 THEN DataLDrive := To_slv(DataTempL, DataWidth); ELSIF DataTempL = -2 THEN DataLDrive := (OTHERS => 'U'); ELSE DataLDrive := (OTHERS => 'X'); END IF; END IF; END IF; IF RWL_nwv = '0' AND Location = 16#3FF# THEN IF BUSYL_zd = '1' THEN INTR_zd := '0'; END IF; END IF; IF (OELNeg_nwv = '0' AND Location = 16#3FF#) THEN IF BUSYL_zd = '1' THEN INTL_zd := '1'; END IF; END IF; END IF; IF rising_edge(WRTR_int) THEN IF Violation = '0' THEN DataTempR := To_Nat(IORIn); ELSE DataTempR := -1; END IF; MemData(Location) := DataTempR; ELSIF (CERNeg_nwv = '0') THEN IF (OERNeg_nwv = '0' OR RWR_nwv = '0') THEN Location := To_Nat(ARIn); IF (OERNeg_nwv = '0' AND RWR_nwv = '1') THEN DataTempR := MemData(Location); IF DataTempR >= 0 THEN DataRDrive := To_slv(DataTempR, DataWidth); ELSIF DataTempR = -2 THEN DataRDrive := (OTHERS => 'U'); ELSE DataRDrive := (OTHERS => 'X'); END IF; END IF; IF RWR_nwv = '0' AND Location = 16#3FF# THEN IF BUSYR_zd = '1' THEN INTL_zd := '0'; END IF; END IF; IF (OERNeg_nwv = '0' AND Location = 16#3FF#) THEN IF BUSYL_zd = '1' THEN INTR_zd := '1'; END IF; END IF; END IF; END IF; -------------------------------------------------------------------- -- Output Section -------------------------------------------------------------------- IOL_zd <= DataLDrive; IOR_zd <= DataRDrive; VitalPathDelay01 ( OutSignal => INTLNeg, OutSignalName => "INTL", OutTemp => INTL_zd, GlitchData => INTL_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ALIn'LAST_EVENT, PathDelay => tpd_AL0_INTLNeg, PathCondition => TRUE), 1 => (InputChangeTime => RWRIn'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 2 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 3 => (InputChangeTime => OELNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE)) ); VitalPathDelay01 ( OutSignal => INTRNeg, OutSignalName => "INTR", OutTemp => INTR_zd, GlitchData => INTR_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ARIn'LAST_EVENT, PathDelay => tpd_AL0_INTLNeg, PathCondition => TRUE), 1 => (InputChangeTime => RWLIn'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 2 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE), 3 => (InputChangeTime => OERNeg'LAST_EVENT, PathDelay => tpd_RWL_INTRNeg, PathCondition => TRUE)) ); VitalPathDelay01 ( OutSignal => BUSYLNeg, OutSignalName => "BUSYL", OutTemp => BUSYL_zd, GlitchData => BUSYL_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ARIn'LAST_EVENT, PathDelay => tpd_AL0_BUSYLNeg, PathCondition => TRUE), 1 => (InputChangeTime => ALIn'LAST_EVENT, PathDelay => tpd_AL0_BUSYLNeg, PathCondition => TRUE), 2 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_CELNeg_BUSYLNeg, PathCondition => TRUE), 3 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_CELNeg_BUSYLNeg, PathCondition => TRUE)) ); VitalPathDelay01 ( OutSignal => BUSYRNeg, OutSignalName => "BUSYR", OutTemp => BUSYR_zd, GlitchData => BUSYR_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => ARIn'LAST_EVENT, PathDelay => tpd_AL0_BUSYLNeg, PathCondition => TRUE), 1 => (InputChangeTime => ALIn'LAST_EVENT, PathDelay => tpd_AL0_BUSYLNeg, PathCondition => TRUE), 2 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_CELNeg_BUSYLNeg, PathCondition => TRUE), 3 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_CELNeg_BUSYLNeg, PathCondition => TRUE)) ); END PROCESS; ------------------------------------------------------------------------ -- Path Delay Processes generated as a function of data width ------------------------------------------------------------------------ DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE DataOut_Delay : PROCESS (IOR_zd(i), IOL_zd(i)) VARIABLE IOR_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); VARIABLE IOL_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0); BEGIN VitalPathDelay01Z ( OutSignal => IOLOut(i), OutSignalName => "IOL", OutTemp => IOL_zd(i), Mode => OnEvent, GlitchData => IOL_GlitchData(i), Paths => ( 0 => (InputChangeTime => OELNeg'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => TRUE), 1 => (InputChangeTime => CELNeg'LAST_EVENT, PathDelay => tpd_CELNeg_IOL0, PathCondition => TRUE), 2 => (InputChangeTime => ALIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_AL0_IOL0), PathCondition => TRUE) ) ); VitalPathDelay01Z ( OutSignal => IOROut(i), OutSignalName => "IOR", OutTemp => IOR_zd(i), Mode => OnEvent, GlitchData => IOR_GlitchData(i), Paths => ( 0 => (InputChangeTime => OERNeg'LAST_EVENT, PathDelay => tpd_OELNeg_IOL0, PathCondition => TRUE), 1 => (InputChangeTime => CERNeg'LAST_EVENT, PathDelay => tpd_CELNeg_IOL0, PathCondition => TRUE), 2 => (InputChangeTime => ARIn'LAST_EVENT, PathDelay => VitalExtendToFillDelay(tpd_AL0_IOL0), PathCondition => TRUE) ) ); END PROCESS; END GENERATE; END BLOCK; END vhdl_behavioral;