-------------------------------------------------------------------------------- -- File Name : nlb6282.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997, 2002 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V1.0 R. Munden 96 MAY 31 Initial release -- V2.0 R. Steele 96 SEP 30 Updated timing generics -- V2.1 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.2 R. Munden 98 SEP 23 Changed delay mode to transport -- V2.3 R. Munden 02 APR 03 Corrected Dummy VPD -- V2.4 R. Munden 07 JUL 02 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6282 -- -- Description: Decision circuit -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6282 IS GENERIC ( -- tipd delays: interconnect path delays tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_D : VitalDelayType01 := VitalZeroDelay01; tipd_DNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; tpd_D_DOUT : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D_CLK : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_CLK_posedge : VitalDelayType := ECLUnitDelay; tpw_CLK_negedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : BOOLEAN := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor, 1 pull-up -- (actually clamp circuit) CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '1'; D : IN std_ulogic := '0'; DNeg : IN std_ulogic := '1'; DOUTNeg : OUT std_ulogic := 'U'; DOUT : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; Q : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF nlb6282 : ENTITY IS TRUE; END nlb6282; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6282 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL D_ipd : std_ulogic := 'X'; SIGNAL DNeg_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Dint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_3: VitalWireDelay (D_ipd, D, tipd_D); w_4: VitalWireDelay (DNeg_ipd, DNeg, tipd_DNeg); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => DOUT, a => D_ipd, tpd_a_q => tpd_D_DOUT, ResultMap => ('U','X','Z','1')); a_4: VitalBUF (q => DOUTNeg, a => DNeg_ipd, tpd_a_q => tpd_D_DOUT, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- D inputs Process ---------------------------------------------------------------------------- Dinputs : PROCESS (D_ipd, DNeg_ipd) -- Functionality Results Variables VARIABLE Dint_zd : X01; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Dint_zd := ECL_s_or_d_inputs_tab (D_ipd, DNeg_ipd); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => Dint, OutSignalName => "Dint", OutTemp => Dint_zd, GlitchData => D_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => D_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- ECL CLock Process ---------------------------------------------------------------------------- ECLclock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode ), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VitalBehavior : PROCESS (CLKint, Dint) -- Timing Check Variables VARIABLE Tviol_D_CLK : X01 := '0'; VARIABLE TD_D_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation : X01 := '0'; -- Functionality Results Variables VARIABLE Q_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => Dint, TestSignalName => "Dint", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D_CLK, SetupLow => tsetup_D_CLK, HoldHigh => thold_D_CLK, HoldLow => thold_D_CLK, CheckEnabled => (TRUE), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6282", TimingData => TD_D_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & "/nlb6282", PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Tviol_D_CLK or Pviol_CLK; VitalStateTable ( StateTable => DFF_tab, DataIn => (Violation, CLKint, Dint), Result => Q_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, Mode => VitalTransport, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;