-------------------------------------------------------------------------------- -- File Name: nlb6281.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1996-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY: -- -- version: | author: | mod date: | changes made: -- V2.0 R. Steele 97 JAN 20 Conformed to style guide -- V2.1 R. Munden 98 SEP 23 Changed delay mode to transport -- V2.2 R. Munden 02 APR 03 Corrected Dummy VPD -- V2.3 R. Munden 07 JUN 27 Made resultmap locally static -- -------------------------------------------------------------------------------- -- PART DESCRIPTION: -- -- Library: NLB -- Technology: ECL -- Part: NLB6281 -- -- Description: Variable Delay Line/Duty Cycle Controller -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6281 IS GENERIC ( -- tipd delays: interconnect path delays tipd_DIN : VitalDelayType01 := VitalZeroDelay01; tipd_DINNeg : VitalDelayType01 := VitalZeroDelay01; tipd_S3 : VitalDelayType01 := VitalZeroDelay01; tipd_S2 : VitalDelayType01 := VitalZeroDelay01; tipd_S1 : VitalDelayType01 := VitalZeroDelay01; tipd_S0 : VitalDelayType01 := VitalZeroDelay01; -- tpd delays tpd_DIN_DOUT : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QP : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QM : VitalDelayType01 := ECLUnitDelay01; -- tpd selected delays tpd_DIN_QD_S3_AN_S2_AN_S1_AN_S0_EQ_1 --1111 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_AN_S2_AN_S1_AN_NT_S0_EQ_1 --1110 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_AN_S2_AN_NT_S1_AN_S0_EQ_1 --1101 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_NT_S3_OR_NT_S2_OR_S1_OR_S0_EQ_0 --1100 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_AN_NT_S2_AN_S1_AN_S0_EQ_1 --1011 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_NT_S3_OR_S2_OR_NT_S1_OR_S0_EQ_0 --1010 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_NT_S3_OR_S2_OR_S1_OR_NT_S0_EQ_0 --1001 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_NT_S3_OR_S2_OR_S1_OR_S0_EQ_0 --1000 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_NT_S3_AN_S2_AN_S1_AN_S0_EQ_1 --0111 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_NT_S2_OR_NT_S1_OR_S0_EQ_0 --0110 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_NT_S2_OR_S1_OR_NT_S0_EQ_0 --0101 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_NT_S2_OR_S1_OR_S0_EQ_0 --0100 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_S2_OR_NT_S1_OR_NT_S0_EQ_0 --0011 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_S2_OR_NT_S1_OR_S0_EQ_0 --0010 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_S2_OR_S1_OR_NT_S0_EQ_0 --0001 : VitalDelayType01 := ECLUnitDelay01; tpd_DIN_QD_S3_OR_S2_OR_S1_OR_S0_EQ_0 --0000 : VitalDelayType01 := ECLUnitDelay01; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; XGenerationOn : BOOLEAN := DefaultECLXGeneration ); PORT ( -- 0 denotes pull-down resistor DIN : IN std_ulogic := '0'; DINNeg : IN std_ulogic := '0'; S3 : IN std_ulogic := '0'; S2 : IN std_ulogic := '0'; S1 : IN std_ulogic := '0'; S0 : IN std_ulogic := '0'; DOUT : OUT std_ulogic := 'U'; DOUTNeg : OUT std_ulogic := 'U'; QD : OUT std_ulogic := 'U'; QDNeg : OUT std_ulogic := 'U'; QP : OUT std_ulogic := 'U'; QPNeg : OUT std_ulogic := 'U'; QM : OUT std_ulogic := 'U'; QMNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_LEVEL0 of nlb6281 : ENTITY IS TRUE; END nlb6281; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral of nlb6281 IS ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL DIN_ipd : std_ulogic := 'X'; SIGNAL DINNeg_ipd : std_ulogic := 'X'; SIGNAL S3_ipd : std_ulogic := 'X'; SIGNAL S2_ipd : std_ulogic := 'X'; SIGNAL S1_ipd : std_ulogic := 'X'; SIGNAL S0_ipd : std_ulogic := 'X'; SIGNAL QDint : std_ulogic := 'X'; SIGNAL QPint : std_ulogic := 'X'; SIGNAL QMint : std_ulogic := 'X'; SIGNAL DINint : std_ulogic := 'X'; SIGNAL DINintNeg : std_ulogic := 'X'; -- This is an approximate min. value for the OR and NOR gates that have no -- spec. for the path delays internal to the device (e.g. QDint to QPint). CONSTANT OneGateDelay : VitalDelayType01 := (50 ps, 50 ps); BEGIN ---------------------------------------------------------------------------- -- Wire Delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (DIN_ipd, DIN, tipd_DIN); w_2: VitalWireDelay (DINNeg_ipd, DINNeg, tipd_DINNeg); w_3: VitalWireDelay (S3_ipd, S3, tipd_S3); w_4: VitalWireDelay (S2_ipd, S2, tipd_S2); w_5: VitalWireDelay (S1_ipd, S1, tipd_S1); w_6: VitalWireDelay (S0_ipd, S0, tipd_S0); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent procedure calls ---------------------------------------------------------------------------- -- Differential output a_1: VitalINV (q => QDNeg, a => QDint, ResultMap => ('U','X','Z','1')); a_2: VitalBUF (q => QD, a => QDint, ResultMap => ('U','X','Z','1')); a_3: VitalINV (q => QPNeg, a => QPint, ResultMap => ('U','X','Z','1')); a_4: VitalBUF (q => QP, a => QPint, ResultMap => ('U','X','Z','1')); a_5: VitalINV (q => QMNeg, a => QMint, ResultMap => ('U','X','Z','1')); a_6: VitalBUF (q => QM, a => QMint, ResultMap => ('U','X','Z','1')); a_7: VitalINV ( q => DOUTNeg, a => DINint, tpd_a_q => tpd_DIN_DOUT, ResultMap => ('U','X','Z','1') ); a_8: VitalBUF ( q => DOUT, a => DINint, tpd_a_q => tpd_DIN_DOUT, ResultMap => ('U','X','Z','1') ); a_9: VitalOR2 ( q => QPint, a => DINint, b => QDint, tpd_a_q => tpd_DIN_QP, tpd_b_q => OneGateDelay ); a_10: VitalINV (q => DINintNeg, a => DINint); a_11: VitalNOR2 ( q => QMint, a => DINintNeg, b => QDint, tpd_a_q => tpd_DIN_QM, tpd_b_q => OneGateDelay ); ---------------------------------------------------------------------------- -- ECL CLock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (DIN_ipd, DINNeg_ipd, S3_ipd, S2_ipd, S1_ipd, S0_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE DIN_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); VARIABLE Sinputs : std_logic_vector4; -- Output Glitch Detection Variables VARIABLE D_GlitchData : VitalGlitchDataType; VARIABLE QD_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Sinputs(0) := S0_ipd; Sinputs(1) := S1_ipd; Sinputs(2) := S2_ipd; Sinputs(3) := S3_ipd; -- remove weak values before any decision Sinputs := To_UX01 (s => Sinputs); Mode := ECL_diff_mode_tab (DIN_ipd, DINNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (DIN_ipd, DINNeg_ipd, Mode), Result => DIN_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section for DINint (Dummy; actual delay done at output) ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => DINint, OutSignalName => "DINint", OutTemp => DIN_zd, GlitchData => D_GlitchData, Paths => ( 0 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); ------------------------------------------------------------------------ -- Path Delay Section for QDint (16 different paths depending on S0-S3) ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => QDint, OutSignalName => "QDint", OutTemp => DIN_zd, Mode => VitalTransport, GlitchData => QD_GlitchData, Paths => ( 0 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_AN_S2_AN_S1_AN_S0_EQ_1, PathCondition => (Sinputs = "1111")), 1 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_AN_S2_AN_S1_AN_NT_S0_EQ_1, PathCondition => (Sinputs = "1110")), 2 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_AN_S2_AN_NT_S1_AN_S0_EQ_1, PathCondition => (Sinputs = "1101")), 3 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_NT_S3_OR_NT_S2_OR_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "1100")), 4 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_AN_NT_S2_AN_S1_AN_S0_EQ_1, PathCondition => (Sinputs = "1011")), 5 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_NT_S3_OR_S2_OR_NT_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "1010")), 6 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_NT_S3_OR_S2_OR_S1_OR_NT_S0_EQ_0, PathCondition => (Sinputs = "1001")), 7 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_NT_S3_OR_S2_OR_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "1000")), 8 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_NT_S3_AN_S2_AN_S1_AN_S0_EQ_1, PathCondition => (Sinputs = "0111")), 9 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_NT_S2_OR_NT_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "0110")), 10 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_NT_S2_OR_S1_OR_NT_S0_EQ_0, PathCondition => (Sinputs = "0101")), 11 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_NT_S2_OR_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "0100")), 12 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_S2_OR_NT_S1_OR_NT_S0_EQ_0, PathCondition => (Sinputs = "0011")), 13 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_S2_OR_NT_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "0010")), 14 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_S2_OR_S1_OR_NT_S0_EQ_0, PathCondition => (Sinputs = "0001")), 15 => (InputChangeTime => DIN_ipd'LAST_EVENT, PathDelay => tpd_DIN_QD_S3_OR_S2_OR_S1_OR_S0_EQ_0, PathCondition => (Sinputs = "0000")) ) ); END PROCESS; END vhdl_behavioral;