-------------------------------------------------------------------------------- -- File name : nlb6254.vhd -------------------------------------------------------------------------------- -- Copyright (C) 1997-2007 Free Model Foundry; http://www.FreeModelFoundry.com -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License version 2 as -- published by the Free Software Foundation. -- -- MODIFICATION HISTORY : -- -- version | author | mod date | changes made -- V2.0 rev3 16 APR 96 Conformed to style guide, -- New ecl_utils package with more constants -- V2.1 R. Steele 96 OCT 21 Updated timing generics -- V2.2 R. Munden 97 MAR 01 Changed XGenerationOn to XOn, added MsgOn, and -- updated TimingChecks & PathDelays -- V2.3 R. Munden 98 SEP 22 Changed delay mode to transport -- V2.4 R. Munden 02 APR 03 Corrected Dummy VPD -- V2.5 R. Munden 07 JUN 18 Made resultmap locally static -------------------------------------------------------------------------------- -- PART DESCRIPTION : -- -- Library: NLB -- Technology: ECL -- Part: NLB6254 -- -- Description: 8-bit Mutiplexer -- -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_primitives.ALL; USE IEEE.VITAL_timing.ALL; LIBRARY FMF; USE FMF.ecl_utils.ALL; USE FMF.ff_package.ALL; USE FMF.state_tab_package.ALL; -------------------------------------------------------------------------------- -- ENTITY DECLARATION -------------------------------------------------------------------------------- ENTITY nlb6254 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_CLK : VitalDelayType01 := VitalZeroDelay01; tipd_CLKNeg : VitalDelayType01 := VitalZeroDelay01; tipd_R : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays tpd_CLK_Q : VitalDelayType01 := ECLUnitDelay01; tpd_CLK_COUT : VitalDelayType01 := ECLUnitDelay01; -- tsetup values: setup times tsetup_D0_CLK : VitalDelayType := ECLUnitDelay; -- thold values: hold times thold_D0_CLK : VitalDelayType := ECLUnitDelay; -- tpw values: pulse widths tpw_R_posedge : VitalDelayType := ECLUnitDelay; -- tperiod_min: minimum clock period = 1/max freq tperiod_CLK_posedge : VitalDelayType := ECLUnitDelay; -- generic control parameters InstancePath : STRING := DefaultECLInstancePath; TimingChecksOn : BOOLEAN := DefaultECLTimingChecks; MsgOn : BOOLEAN := DefaultECLMsgOn; XOn : Boolean := DefaultECLXOn; -- For FMF SDF technology file usage TimingModel : STRING := DefaultECLTimingModel ); PORT ( -- 0 denotes internal pull-down resistor D0 : IN std_ulogic := '0'; D1 : IN std_ulogic := '0'; D2 : IN std_ulogic := '0'; D3 : IN std_ulogic := '0'; D4 : IN std_ulogic := '0'; D5 : IN std_ulogic := '0'; D6 : IN std_ulogic := '0'; D7 : IN std_ulogic := '0'; CLK : IN std_ulogic := '0'; CLKNeg : IN std_ulogic := '0'; R : IN std_ulogic := '0'; COUT : OUT std_ulogic := 'U'; COUTNeg : OUT std_ulogic := 'U'; Q : OUT std_ulogic := 'U'; QNeg : OUT std_ulogic := 'U'; VBB : OUT std_ulogic := ECLVbbValue ); ATTRIBUTE VITAL_level0 OF nlb6254 : ENTITY IS TRUE; END nlb6254; -------------------------------------------------------------------------------- -- ARCHITECTURE DECLARATION -------------------------------------------------------------------------------- ARCHITECTURE vhdl_behavioral OF nlb6254 IS ATTRIBUTE VITAL_level1 OF vhdl_behavioral : ARCHITECTURE IS TRUE; SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL CLK_ipd : std_ulogic := 'X'; SIGNAL CLKNeg_ipd : std_ulogic := 'X'; SIGNAL R_ipd : std_ulogic := 'X'; SIGNAL CLKint : std_ulogic := 'X'; SIGNAL Qint : std_ulogic := 'X'; SIGNAL COUTint : std_ulogic := 'X'; BEGIN ---------------------------------------------------------------------------- -- Wire delays ---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D0_ipd, D0, tipd_D0); w_2: VitalWireDelay (D1_ipd, D1, tipd_D1); w_3: VitalWireDelay (D2_ipd, D2, tipd_D2); w_4: VitalWireDelay (D3_ipd, D3, tipd_D3); w_5: VitalWireDelay (D4_ipd, D4, tipd_D4); w_6: VitalWireDelay (D5_ipd, D5, tipd_D5); w_7: VitalWireDelay (D6_ipd, D6, tipd_D6); w_8: VitalWireDelay (D7_ipd, D7, tipd_D7); w_9: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); w_10: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg); w_11: VitalWireDelay (R_ipd, R, tipd_R); END BLOCK; ---------------------------------------------------------------------------- -- Concurrent Procedures ---------------------------------------------------------------------------- a_1: VitalBUF (q => Q, a => Qint, ResultMap => ('U','X','Z','1')); a_2: VitalINV (q => QNeg, a => Qint, ResultMap => ('U','X','Z','1')); a_3: VitalBUF (q => COUT, a => COUTint, ResultMap => ('U','X','Z','1')); a_4: VitalINV (q => COUTNeg, a => COUTint, ResultMap => ('U','X','Z','1')); ---------------------------------------------------------------------------- -- ECL Clock Process ---------------------------------------------------------------------------- ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd) -- Functionality Results Variables VARIABLE Mode : X01; VARIABLE CLKint_zd : std_ulogic; VARIABLE PrevData : std_logic_vector(0 to 2); -- Glitch Detection Variables VARIABLE CLK_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd); VitalStateTable ( StateTable => ECL_clk_tab, DataIn => (CLK_ipd, CLKNeg_ipd, Mode), Result => CLKint_zd, PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- (Dummy) Path Delay Section ------------------------------------------------------------------------ VitalPathDelay ( OutSignal => CLKint, OutSignalName => "CLKint", OutTemp => CLKint_zd, GlitchData => CLK_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLK_ipd'LAST_EVENT, PathDelay => VitalZeroDelay, PathCondition => FALSE)) ); END PROCESS; ---------------------------------------------------------------------------- -- Main Behavior Process ---------------------------------------------------------------------------- VITALBehavior : PROCESS (CLKint, R_ipd, D0_ipd, D1_ipd, D2_ipd, D3_ipd, D4_ipd, D5_ipd, D6_ipd, D7_ipd) -- Timing Check Variables VARIABLE Tviol_D0_CLK : X01 := '0'; VARIABLE TD_D0_CLK : VitalTimingDataType; VARIABLE Tviol_D1_CLK : X01 := '0'; VARIABLE TD_D1_CLK : VitalTimingDataType; VARIABLE Tviol_D2_CLK : X01 := '0'; VARIABLE TD_D2_CLK : VitalTimingDataType; VARIABLE Tviol_D3_CLK : X01 := '0'; VARIABLE TD_D3_CLK : VitalTimingDataType; VARIABLE Tviol_D4_CLK : X01 := '0'; VARIABLE TD_D4_CLK : VitalTimingDataType; VARIABLE Tviol_D5_CLK : X01 := '0'; VARIABLE TD_D5_CLK : VitalTimingDataType; VARIABLE Tviol_D6_CLK : X01 := '0'; VARIABLE TD_D6_CLK : VitalTimingDataType; VARIABLE Tviol_D7_CLK : X01 := '0'; VARIABLE TD_D7_CLK : VitalTimingDataType; VARIABLE Pviol_CLK : X01 := '0'; VARIABLE PD_CLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_R : X01 := '0'; VARIABLE PD_R : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE ViolationA : X01 := '0'; VARIABLE ViolationB : X01 := '0'; -- Functionality Results Variables VARIABLE PrevData : std_logic_vector(0 to 2); VARIABLE PrevDataQ1 : std_logic_vector(0 to 2); VARIABLE PrevDataQ2 : std_logic_vector(0 to 2); VARIABLE PrevDataQ3 : std_logic_vector(0 to 2); VARIABLE PrevDataQ4 : std_logic_vector(0 to 2); VARIABLE PrevDataQ5 : std_logic_vector(0 to 2); VARIABLE PrevDataQ6 : std_logic_vector(0 to 2); VARIABLE PrevDataQ7 : std_logic_vector(0 to 2); VARIABLE PrevDataQ8 : std_logic_vector(0 to 2); VARIABLE PrevDataCOUT : std_logic_vector(0 to 2); VARIABLE MuxSelect : std_logic_vector(2 downto 0); ALIAS Cout_int : std_ulogic IS MuxSelect(2); VARIABLE Cout_zd : std_ulogic; VARIABLE Dint : std_ulogic; VARIABLE Q1_zd : std_ulogic; VARIABLE Q2_zd : std_ulogic; VARIABLE Q3_zd : std_ulogic; VARIABLE Q4_zd : std_ulogic; VARIABLE Q5_zd : std_ulogic; VARIABLE Q6_zd : std_ulogic; VARIABLE Q7_zd : std_ulogic; VARIABLE Q_zd : std_ulogic; -- Output Glitch Detection Variables VARIABLE Q_GlitchData : VitalGlitchDataType; VARIABLE COUT_GlitchData : VitalGlitchDataType; BEGIN ------------------------------------------------------------------------ -- Timing Check Section ------------------------------------------------------------------------ IF (TimingChecksOn) THEN VitalSetupHoldCheck ( TestSignal => D0_ipd, TestSignalName => "D0_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "000"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D0_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_CLK ); VitalSetupHoldCheck ( TestSignal => D1_ipd, TestSignalName => "D1_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "001"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D1_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D1_CLK ); VitalSetupHoldCheck ( TestSignal => D2_ipd, TestSignalName => "D2_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "010"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D2_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D2_CLK ); VitalSetupHoldCheck ( TestSignal => D3_ipd, TestSignalName => "D3_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "011"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D3_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D3_CLK ); VitalSetupHoldCheck ( TestSignal => D4_ipd, TestSignalName => "D4_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "100"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D4_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D4_CLK ); VitalSetupHoldCheck ( TestSignal => D5_ipd, TestSignalName => "D5_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "101"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D5_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D5_CLK ); VitalSetupHoldCheck ( TestSignal => D6_ipd, TestSignalName => "D6_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "110"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D6_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D6_CLK ); VitalSetupHoldCheck ( TestSignal => D7_ipd, TestSignalName => "D7_ipd", RefSignal => CLKint, RefSignalName => "CLKint", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => (MuxSelect = "111"), RefTransition => '/', HeaderMsg => InstancePath & "/nlb6254", TimingData => TD_D7_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D7_CLK ); VitalPeriodPulseCheck ( TestSignal => CLKint, TestSignalName => "CLKint", Period => tperiod_CLK_posedge, HeaderMsg => InstancePath & "/nlb6254", CheckEnabled => TRUE, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK ); VitalPeriodPulseCheck ( TestSignal => R_ipd, TestSignalName => "R_ipd", PulseWidthHigh => tpw_R_posedge, HeaderMsg => InstancePath & "/nlb6254", CheckEnabled => TRUE, PeriodData => PD_R, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_R ); END IF; ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ ViolationA := Pviol_CLK OR Pviol_R; ViolationB := Pviol_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK OR Tviol_D6_CLK OR Tviol_D7_CLK; -- Cout is delayed one half-clock to match Timing Diagram -- Order is not important since DFFN is active on clk falling edge VitalStateTable ( StateTable => DFFN_tab, DataIn => (Pviol_CLK, CLKint, Cout_int), Result => Cout_zd, PreviousDataIn => PrevDataCOUT ); -- Output f/fs with mux input, order important Dint := VitalMux8 ( data => (D0_ipd, D1_ipd, D2_ipd, D3_ipd, D4_ipd, D5_ipd, D6_ipd, D7_ipd), dselect => MuxSelect ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q7_zd), Result => Q_zd, PreviousDataIn => PrevDataQ8 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q6_zd), Result => Q7_zd, PreviousDataIn => PrevDataQ7 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q5_zd), Result => Q6_zd, PreviousDataIn => PrevDataQ6 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q4_zd), Result => Q5_zd, PreviousDataIn => PrevDataQ5 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q3_zd), Result => Q4_zd, PreviousDataIn => PrevDataQ4 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q2_zd), Result => Q3_zd, PreviousDataIn => PrevDataQ3 ); VitalStateTable ( StateTable => DREG_tab, DataIn => (Pviol_CLK, CLKint, Q1_zd), Result => Q2_zd, PreviousDataIn => PrevDataQ2 ); VitalStateTable ( StateTable => DFF_tab, DataIn => (ViolationB, CLKint, Dint), Result => Q1_zd, PreviousDataIn => PrevDataQ1 ); -- Lastly, do the State change, 0 -> 7 VitalStateTable ( StateTable => st8R_tab, DataIn => (ViolationA, CLKint, R_ipd), NumStates => 3, Result => MuxSelect, --> Cout_int is MuxSelect(2) PreviousDataIn => PrevData ); ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Qint, OutSignalName => "Qint", OutTemp => Q_zd, Mode => VitalTransport, GlitchData => Q_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => COUTint, OutSignalName => "COUTint", OutTemp => COUT_zd, Mode => VitalTransport, GlitchData => COUT_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_COUT, PathCondition => TRUE) ) ); END PROCESS; END vhdl_behavioral;